Cache management method and device for memory access, equipment and storage medium

Abstract

The invention discloses a cache management method and device for memory access, equipment and a storage medium, and relates to the technical field of storage, and the method comprises the following steps: obtaining a data read-write message of a central processing unit; detecting a data popularity type of an access address of the data read-write message; searching cache data corresponding to the access address from a target cache region; if the cache data is not found in the target cache region, sending a corresponding read-write request to a memory so as to find memory data corresponding to the access address from the memory; by setting the preset cache regions corresponding to the cold data and the hot data respectively, the cache can be partitioned according to the heat of the data, so that cache resources are reasonably allocated, the cost is reduced, the memory access efficiency and speed are improved, finer consistency control can be realized, and the cache hit rate and the system performance are improved; therefore, the required data is searched in the corresponding preset cache region according to the heat of the data, and the memory access speed is increased.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a cache management method, device, equipment and storage medium for memory access. Background Art

[0002] Generally, as the performance of the CPU (Central Processing Unit) increases, the CPU speed becomes faster and faster, while the memory read speed is slower than the CPU. The memory close to the CPU has low latency, but is limited in size and has a high implementation cost. It is usually necessary to implement larger memory blocks, but these memory blocks increase latency. In order to optimize overall performance, the memory system can include multiple levels of cache in a hierarchical memory system, thereby making a trade-off between size and latency.

[0003] Cache is a high-speed memory block, usually composed of static random access memory (SRAM), which is faster than main memory (such as DRAM, i.e. memory), but more expensive. Modern computers usually have a multi-level cache structure, such as L1, L2, and L3 cache. The closer to the CPU, such as L1 cache is the fastest, but the capacity is the smallest; L3 cache has the largest capacity and is relatively slow. When the CPU reads and writes memory data, it will first look in the cache. If it hits, the data in the cache is used, otherwise it will go to the main memory to read.

[0004] At present, with the development of artificial intelligence and information industry, the amount of data is growing, and the speed of memory access is required to be higher and higher. In the process of memory access, there are often some data that are frequently read, or the same data is accessed in large quantities in a short period of time. When processing data access, the traditional cache management system does not distinguish the popularity of data, resulting in mixed storage of hot data and cold data, thereby reducing the cache hit rate and system performance, causing a waste of cache resources. As a key technology to alleviate the speed difference between CPU and memory, the design and management of cache directly affect the performance of the entire system. Therefore, how to improve the speed of memory access, cache hit rate and system performance is an urgent problem to be solved today. Summary of the invention

[0005] The purpose of the present invention is to provide a cache management method, device, equipment and computer-readable storage medium for memory access to increase the speed of memory access, improve the cache hit rate and system performance.

[0006] In order to solve the above technical problems, the present invention provides a cache management method for memory access, comprising:

[0007] Get the data read and write messages of the central processor;

[0008] Detecting the data heat type of the access address of the data read / write message; wherein the data heat type includes cold data and hot data;

[0009] Searching for cache data corresponding to the access address from a target cache area; wherein the target cache area is a preset cache area corresponding to the data heat type, the preset cache area corresponding to the hot data includes a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer, the preset cache area corresponding to the cold data includes a cold data area in the first common cache layer and the second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer; the distance between the hot data cache layer and the central processing unit is smaller than the distance between the first common cache layer and the central processing unit, and the distance between the second common cache layer and the central processing unit is smaller than the distance between the second common cache layer and the central processing unit;

[0010] If the cache data is not found in the target cache area, a corresponding read / write request is sent to the memory to search the memory for memory data corresponding to the access address.

[0011] On the other hand, searching the target cache area for a cache block corresponding to the access address includes:

[0012] The cache data corresponding to the access address is searched from each cache layer in the target cache area in order of distance from the central processor from near to far.

[0013] On the other hand, the hot data cache layer includes a first cache layer, the first common cache layer includes a second cache layer, and the second common cache layer includes a third cache layer and a fourth cache layer; searching for cache data corresponding to the access address from each cache layer in the target cache area in order of distance from the central processor from near to far, includes:

[0014] If the data heat type is the hot data, searching the cache data from the first cache layer;

[0015] When the cache data is not found in the first cache layer, searching for the cache data in a hot data area in the second cache layer;

[0016] When the cache data is not found in the hot data area in the second cache layer, searching for the cache data in the third cache layer;

[0017] When the cache data is not found in the third cache layer, searching for the cache data in the fourth cache layer;

[0018] When the cache data is not found in the fourth cache layer, executing the step of sending a corresponding read / write request to the memory to search the memory for the memory data corresponding to the access address;

[0019] If the data heat type is the cold data, searching for the cached data from the cold data area in the second cache layer;

[0020] When the cache data is not found in the cold data area in the second cache layer, searching for the cache data in the third cache layer;

[0021] When the cache data is not found in the third cache layer, searching for the cache data in the fourth cache layer;

[0022] When the cache data is not found in the fourth cache layer, the step of sending a corresponding read / write request to the memory is performed to search the memory for memory data corresponding to the access address.

[0023] In another aspect, the method further comprises:

[0024] Determine the prefetch strategy of each memory data according to the data heat type of each memory data in the memory; wherein the prefetch strategy includes a cold data prefetch strategy and a hot data prefetch strategy; the prefetch trigger condition of the hot data prefetch strategy is lower than the prefetch trigger condition of the cold data prefetch strategy, and / or the prefetch window of the hot data prefetch strategy is larger than the prefetch window of the cold data prefetch strategy;

[0025] According to the pre-fetch strategy, the memory data that triggers the corresponding pre-fetch triggering condition is stored in the corresponding preset cache area.

[0026] On the other hand, the detecting the data heat type of the access address of the data read / write message includes:

[0027] The data heat type is determined according to the data heat value flag of the access address in the preset memory management mapping table; wherein the preset memory management mapping table includes each address information and the respective data heat value flag.

[0028] In another aspect, the method further comprises:

[0029] Monitoring the access frequency of the central processing unit to each historical access address;

[0030] Determine the latest data heat value flag of each of the historical access addresses according to the access frequency;

[0031] According to the latest data heat value flag, the data heat value flag of the corresponding address information in the preset memory management mapping table is updated.

[0032] In another aspect, the method further comprises:

[0033] Determine key hotspot data according to the access frequency;

[0034] The key hotspot data is distributed to each cache layer in a preset cache area corresponding to the hot data for storage and locking.

[0035] The present invention also provides a cache management device for memory access, comprising:

[0036] An acquisition module is used to acquire data read and write messages from the central processor;

[0037] A detection module, used to detect the data heat type of the access address of the data read / write message; wherein the data heat type includes cold data and hot data;

[0038] A pre-fetch search module, configured to search for cache data corresponding to the access address from a target cache area; wherein the target cache area is a preset cache area corresponding to the data heat type, the preset cache area corresponding to the hot data includes a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer, the preset cache area corresponding to the cold data includes a cold data area in the first common cache layer and the second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer; the distance between the hot data cache layer and the central processing unit is smaller than the distance between the first common cache layer and the central processing unit, and the distance between the second common cache layer and the central processing unit is smaller than the distance between the second common cache layer and the central processing unit;

[0039] A memory search module is used to send a corresponding read / write request to the memory if the cache data is not found in the target cache area, so as to search the memory for the memory data corresponding to the access address.

[0040] The present invention also provides a cache management device for memory access, comprising:

[0041] Memory for storing computer programs;

[0042] A processor is used to implement the steps of the cache management method for memory access as described above when executing the computer program.

[0043] In addition, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the cache management method for memory access as described above are implemented.

[0044] A cache management method for memory access provided by the present invention comprises: obtaining a data read / write message of a central processing unit; detecting a data heat type of an access address of the data read / write message; wherein the data heat type comprises cold data and hot data; searching for cache data corresponding to the access address from a target cache area; wherein the target cache area is a preset cache area corresponding to the data heat type, the preset cache area corresponding to the hot data comprises a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer, the preset cache area corresponding to the cold data comprises a cold data area in the first common cache layer, and a second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer; the distance between the hot data cache layer and the central processing unit is smaller than the distance between the first common cache layer and the central processing unit, and is smaller than the distance between the second common cache layer and the central processing unit; if the cache data is not found from the target cache area, sending a corresponding read / write request to the memory to search for the memory data corresponding to the access address from the memory;

[0045] It can be seen that the present invention can partition the cache according to the heat of the data by setting the preset cache areas corresponding to the cold data and the hot data respectively, so as to reasonably allocate cache resources, reduce costs, and improve the efficiency and speed of memory access. By setting the hot data cache layer and hot data area with smaller granularity, it can achieve more refined consistency control, improve cache hit rate and system performance; by searching the cache data corresponding to the access address from the target cache area, it is possible to search the required data in the corresponding preset cache area according to the heat of the data, thereby improving the speed of memory access. In addition, the present invention also provides a cache management device, equipment and computer-readable storage medium for memory access, which also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0047] Figure 1 A flowchart of a cache management method for memory access provided by an embodiment of the present invention;

[0048] Figure 2 A schematic diagram of the system architecture of a cache management method for memory access provided by an embodiment of the present invention;

[0049] Figure 3 A schematic diagram of a mapping table update process of another memory access cache management method provided by an embodiment of the present invention;

[0050] Figure 4 A schematic flow chart of another memory access cache management method provided by an embodiment of the present invention;

[0051] Figure 5 A structural block diagram of a cache management device for memory access provided by an embodiment of the present invention;

[0052] Figure 6 A schematic diagram of the structure of a cache management device for memory access provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] Please refer to Figure 1 , Figure 1 A flow chart of a cache management method for memory access provided by an embodiment of the present invention. The method may include:

[0055] Step 101: Obtain data read and write messages from a central processing unit.

[0056] The data read and write message in this embodiment can be a message for reading and writing data of the CPU, such as a data read message. The method provided in this embodiment can be applied to a processor in a CPU chip (such as Figure 2 The memory management unit in the memory management unit may receive the data read and write message sent by the CPU (ie, the CPU core) in this step.

[0057] Step 102: Detect the data heat type of the access address of the data read / write message; wherein the data heat type includes cold data and hot data.

[0058] It can be understood that the access address of the data read and write message in this step can be the address that the CPU wants to access, such as a virtual address or a physical address; the data heat type in this step can be the heat type of the data stored in the access address, such as hot data with a higher access frequency or cold data with a lower access frequency.

[0059] Correspondingly, the specific number and type division of data heat types in this embodiment can be set by the designer according to the usage scenario and user needs. For example, the data heat types can only include hot data and cold data, or cold data and / or hot data can be further graded to use more types to perform more detailed partitioning of the cache. This embodiment does not impose any restrictions on this.

[0060] It should be noted that this embodiment is demonstrated by taking the processing of a data read and write message of a central processing unit by a processor (such as a memory management unit) as an example. The processing of other data read and write messages of the central processing unit by the processor can be implemented in the same or similar manner as the method provided in this embodiment, and this embodiment does not impose any restrictions on this.

[0061] Accordingly, the specific method for detecting the data heat type of the access address of the data read / write message in this step can be set by the designer according to the practical scenario and user needs. For example, the processor (e.g., the memory management unit) can determine the data heat type of the access address according to the historical access times of the access address in the preset time period; for example, when the historical access times are greater than the heat threshold, the data heat type is determined to be hot data, and when the historical access times are greater than the heat threshold, the data heat type is determined to be cold data. The processor can also determine the data heat type according to the data heat value flag of the access address in the preset memory management mapping table; wherein the preset memory management mapping table includes each address information and each data heat value flag; that is, in this embodiment, the data heat value flag corresponding to each address information in the preset memory management mapping table (i.e., the preset memory management mapping table) can be used (e.g., the default cold data flag) to directly find the data heat value flag corresponding to the access address, thereby determining the data heat type of the access address according to the flag on the data heat value flag (e.g., the hot data flag or the cold data flag).

[0062] Among them, the address information in the preset memory management mapping table may include the mapping relationship between the virtual address and the physical address. For example, in this step, the memory control unit can use the preset memory management mapping table to convert the virtual address to be queried by the CPU (i.e., the access address of the data read and write message) into a physical address, and at the same time query the corresponding data heat value flag recorded in the mapping table to determine the corresponding data heat type.

[0063] Correspondingly, the method provided in this embodiment may also include a configuration update process of the data heat value flag corresponding to each address information in the preset memory management mapping table. For example, the method provided in this embodiment may also include monitoring the access frequency of the central processing unit to each historical access address; determining the latest data heat value flag of each historical access address based on the access frequency; and updating the data heat value flag of the corresponding address information in the preset memory management mapping table based on the latest data heat value flag. For example, in some embodiments, a pre-written script software can be used to dynamically and real-time monitor the memory physical address information (such as Figure 3 The access data in the CPU is used to monitor the access frequency of each access address (i.e., the historical access address), so as to dynamically evaluate the access heat of the address according to the access frequency and determine the current latest data heat value flag of each access address; then Figure 3 As shown, the script software can send a command to the CPU to control the CPU to send a corresponding command (such as a flag update command) to the memory control unit to update the data heat value flag of the corresponding address information of the preset memory management mapping table.

[0064] Accordingly, this embodiment does not limit the specific method of determining the latest data heat value flag of each historical access address based on the access frequency. For example, the heat threshold set according to the system performance requirements and the historical access address can be used to determine whether the number of accesses to the current historical access address within a preset time period reaches the heat threshold; wherein the current historical access address is any historical access address; if so, the latest data heat value flag of the current historical access address is determined to be an identifier of hot data; if not, the latest data heat value flag of the current historical access address is determined to be an identifier of cold data. For example, the number of accesses to a certain address suddenly increases. When the number of accesses to a data item at a certain historical access address within a preset time period exceeds the heat threshold, it can be determined to be hot data.

[0065] Furthermore, in some embodiments, the above-mentioned heat threshold can be adjusted according to the access records of each historical access address, such as determining and updating the heat threshold according to the access records of all historical access addresses at a preset time interval.

[0066] Step 103: Search the target cache area for cache data corresponding to the access address.

[0067] Among them, the target cache area is a preset cache area corresponding to the data heat type, the preset cache area corresponding to the hot data includes the hot data cache layer, the hot data area in the first common cache layer and the second common cache layer, the preset cache area corresponding to the cold data includes the cold data area in the first common cache layer and the second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer; the distance between the hot data cache layer and the central processing unit is smaller than the distance between the first common cache layer and the central processing unit, which is smaller than the distance between the second common cache layer and the central processing unit.

[0068] It can be understood that the target cache area in this embodiment can be a preset cache area corresponding to the data heat type of the access address; that is, in this embodiment, by pre-setting the cache areas corresponding to each data heat type (such as hot data and cold data) (i.e., preset cache areas), the CPU cache can be partitioned according to the heat of the data to reasonably allocate cache resources and reduce costs.

[0069] Correspondingly, the preset cache area corresponding to the hot data in this embodiment may include a hot data cache layer, a hot data area in the first common cache layer, and a second common cache layer; the preset cache area corresponding to the cold data may include a cold data area in the first common cache layer and a second common cache layer. The hot data cache layer may be a cache layer specifically used to store hot data (such as Figure 2 The L0 hot data layer in the memory); the first common cache layer and the second common cache layer may be cache layers for storing hot data and cold data, and the first common cache layer may be divided into a cold data area for storing cold data and a hot data area for storing hot data; the second common cache layer may not be partitioned. That is to say, in this embodiment, a hot data cache layer may be added to the hardware architecture, and a high-speed memory block with better performance, such as a static random access memory (SRAM) or non-volatile memory technology, may be used with fine granularity as a cache area dedicated to storing hot data; the first common cache layer may be divided into a hot data area (such as Figure 2 L1 hot data area) and cold data area (such as Figure 2 The L1 cold data area in the cache is used in the hot data area with fine granularity and the cold data area with coarse granularity; the second common cache layer (such as Figure 2 The L2 cache layer and L3 cache layer in the cache can be unpartitioned and both use coarse granularity; this can reasonably allocate cache resources, make some hot data cache granularity smaller, and achieve more refined consistency control. At the same time, because the control data access frequency is high, the problem of small granularity misses can be reduced, while cold data uses larger granularity, so that more data is loaded each time.

[0070] Correspondingly, the specific method of searching for cache data corresponding to the access address from the target cache area in this embodiment can be set by the designer. For example, the memory management unit can search for cache data corresponding to the access address from each cache layer in the target cache area in order of distance from the central processor from near to far; the memory management unit can also search for cache data corresponding to the access address from the target cache area in parallel at the same time. This embodiment does not impose any restrictions on this.

[0071] Similarly, this embodiment does not limit the specific data of the hot data cache layer, the first common cache layer, and the second common cache layer. For example, the number of the hot data cache layer, the first common cache layer, and the second common cache layer can be 1 or a number greater than 1. Figure 2 As shown, the number of hot data cache layers and the first common cache layer may be 1, and the number of second common cache layers may be 2.

[0072] For example, if Figure 2 As shown, the hot data cache layer includes a first cache layer (L0 cache layer), the first common cache layer includes a second cache layer (L1 cache layer), and the second common cache layer includes a third cache layer (L2 cache layer) and a fourth cache layer (L3 cache layer); the above process of searching for cache data corresponding to the access address from each cache layer in the target cache area in order of distance from the central processor from near to far may include: if the data heat type is hot data, searching for cache data from the first cache layer; when the cache data is not found in the first cache layer (i.e., a miss), searching for cache data from the hot data area in the second cache layer; when the cache data is not found in the hot data area in the second cache layer, searching for cache data from the third cache layer; when the cache data is not found in the third cache layer, searching for cache data from the fourth cache layer; when the cache data is not found in the fourth cache layer, entering step 104 to send a corresponding read and write request to the memory to search for memory data corresponding to the access address from the memory;

[0073] Correspondingly, if the data heat type is cold data, the cache data is searched from the cold data area in the second cache layer; when the cache data is not found in the cold data area in the second cache layer, the cache data is searched from the third cache layer; when the cache data is not found from the third cache layer, the cache data is searched from the fourth cache layer; when the cache data is not found from the fourth cache layer, step 104 is entered to send a corresponding read and write request to the memory to search for memory data corresponding to the access address from the memory.

[0074] like Figure 4As shown, when the CPU sends a message for reading and writing data (i.e., a data read and write message), the memory control unit can query the mapping table of converting virtual addresses to physical addresses, and at the same time obtain the corresponding data heat value flag recorded in the mapping table; if the data to be read and written is hot data, the L0 cache layer is directly checked with an index for the corresponding cache block, and then the cache group in its hot data cache area is checked to see whether each cache group tag (the high-order part of the cache address) is hit, and whether there is a backup in the cache block. If it is hit, the data in the cache is read and written according to the protocol consistency strategy; if it is not hit, the hot data area of ​​the next L1 cache layer is indexed, and if it is hit, the data is read and written; if it is not hit, the L2 cache layer is queried to see if it is hit, and if it is hit, the data in the cache is read and written according to the protocol consistency strategy; if it is not hit, the L3 cache layer is queried to see if it is hit, and if it is hit, the backup data in the read and write cache is read and written, and if it is not hit, the memory (such as Figure 2 The main memory in the cache) sends a request to load data into the cache. If the data to be read or written is cold data, the cold data area of ​​the L1 cache layer uses the index to check the corresponding cache block, and then checks each cache group tag corresponding to the cold data area to see if it hits, and whether there is a backup in the cache block. If it hits, read and write the data backup in the cache; if it misses, query the L2 cache layer to see if it hits. If it hits, read and write the data in the cache according to the protocol consistency strategy; if it misses, query the L3 to see if it hits. If it hits, read and write the backup data in the cache. If it misses, send a request to the memory to load the data into the cache. If it still misses, send a read and write request to the memory, read and write from the memory, and load the data into the cache.

[0075] Correspondingly, the method provided in this embodiment may also include a data pre-fetching process in the cache, that is, a storage process of the corresponding hot data and cold data in the respective preset cache areas of the hot data and the cold data. For example, in order to improve the accuracy and efficiency of pre-fetching, the pre-fetching technology adjusted according to the heat level may be adopted in this embodiment, such as different pre-fetching strategies may be adopted for cold data and hot data; that is, in this embodiment, the pre-fetching strategy of each memory data (that is, the memory data corresponding to each address information) in the memory may be determined according to the data heat type; wherein the pre-fetching strategy includes a cold data pre-fetching strategy and a hot data pre-fetching strategy; according to the pre-fetching strategy, the memory data that triggers the corresponding pre-fetching trigger condition is stored in the corresponding preset cache area.

[0076] Accordingly, to avoid the extra delay caused by prefetching, the prefetching frequency of hot data can be higher because it is expected that the hot data may be accessed frequently. By relatively improving the expected triggering conditions for cold data, the prefetching frequency of cold data can be reduced; that is, in some embodiments, the prefetching triggering conditions of the hot data prefetching strategy are lower than the prefetching triggering conditions of the cold data prefetching strategy. In other embodiments, the prefetching window of the hot data prefetching strategy can be larger than the prefetching window of the cold data prefetching strategy to achieve dynamic adjustment of the prefetching window size.

[0077] Among them, data with a large amount of data access (i.e., hot data) is pre-fetched, and the spatial and temporal locality principle of data is used. If a data item is accessed, then the data items related to it may also be accessed soon, so they can be pre-fetched together. For example, in this embodiment, when the hot data that needs to be pre-fetched is stored in the corresponding preset cache area, the related data of the hot data can be determined as hot data and stored in the preset cache area corresponding to the hot data.

[0078] Furthermore, the method provided in this embodiment can also copy very hot critical data (i.e., key hot data) to multiple cache layers to ensure the cache hit rate, and can temporarily lock the data to prevent it from being replaced during high concurrent access; such as determining the key hot data based on the access frequency; distributing the key hot data to each cache layer in the preset cache area corresponding to the hot data for storage and locking; wherein the access frequency of the key hot data (such as the number of historical accesses within a preset time period) can be greater than the key hot threshold, and the key hot threshold can be greater than the above-mentioned heat threshold.

[0079] Accordingly, based on the multi-level cache structure in this embodiment, the cache priority can be set according to the heat of the data, and the cache replacement strategy based on the cache priority can be set to upgrade the priority of hot data, downgrade the data of cold data, and delete it from the cache layer close to the CPU to improve the efficiency of memory access. For example, the method provided by this embodiment can also include determining the latest cache priority of each historical access address according to the access frequency of each historical access address by the monitored CPU, that is, determining the latest cache priority corresponding to each cached data; adjusting the data in the cache according to the latest cache priority corresponding to each cached data; if the latest cache priority corresponding to the current hot data in the cache is higher than the cache priority corresponding to the cache layer, the current hot data is moved to the cache layer corresponding to the latest cache priority for storage; if the latest cache priority corresponding to the current cold data in the cache is lower than the cache priority corresponding to the cache layer, the current cold data is moved to the cache layer corresponding to the latest cache priority for storage.

[0080] Step 104: If the cache data is not found in the target cache area, a corresponding read / write request is sent to the memory to search for memory data corresponding to the access address from the memory.

[0081] In this step, when the data corresponding to the access address is not found in the cache, a corresponding read / write request may be sent to the memory to search for the corresponding data in the memory.

[0082] In this embodiment, the embodiment of the present invention can partition the cache according to the heat of the data by setting preset cache areas corresponding to cold data and hot data respectively, so as to reasonably allocate cache resources, reduce costs, and improve the efficiency and speed of memory access. By setting up hot data cache layers and hot data areas with smaller granularity, more refined consistency control can be achieved, and the cache hit rate and system performance can be improved. By searching for cache data corresponding to the access address from the target cache area, the required data can be searched in the corresponding preset cache area according to the heat of the data, thereby improving the speed of memory access.

[0083] Corresponding to the above method embodiment, an embodiment of the present invention further provides a cache management device for memory access. The cache management device for memory access described below and the cache management method for memory access described above can refer to each other.

[0084] Please refer to Figure 5 , Figure 5 A structural block diagram of a cache management device for memory access provided by an embodiment of the present invention. The device may include:

[0085] An acquisition module 10 is used to acquire data read and write messages from a central processing unit;

[0086] A detection module 20, used to detect the data heat type of the access address of the data read / write message; wherein the data heat type includes cold data and hot data;

[0087] A pre-fetch search module 30 is used to search for cache data corresponding to an access address from a target cache area; wherein the target cache area is a preset cache area corresponding to a data heat type, the preset cache area corresponding to hot data includes a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer, the preset cache area corresponding to cold data includes a cold data area in a first common cache layer and a second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer; the distance between the hot data cache layer and the central processor is smaller than the distance between the first common cache layer and the central processor, and the distance between the second common cache layer and the central processor is smaller than the distance between the second common cache layer and the central processor;

[0088] The memory search module 40 is used to send a corresponding read / write request to the memory if the cache data is not found in the target cache area, so as to search the memory for the memory data corresponding to the access address.

[0089] In some embodiments, the pre-fetch search module 30 may be specifically configured to search for cache data corresponding to the access address from each cache layer in the target cache area in order of distance from the central processor from near to far.

[0090] In some embodiments, the hot data cache layer includes a first cache layer, the first common cache layer includes a second cache layer, and the second common cache layer includes a third cache layer and a fourth cache layer; the pre-fetch lookup module 30 may include:

[0091] A first heat search submodule, used for searching cache data from a first cache layer if the data heat type is hot data;

[0092] A second hot search submodule, used for searching for cache data from a hot data area in a second cache layer when cache data is not found in the first cache layer;

[0093] A third hot search submodule, configured to search for cache data from a third cache layer when cache data is not found in a hot data area in the second cache layer;

[0094] A fourth hot search submodule, configured to search for cache data from a fourth cache layer when no cache data is found in the third cache layer; and to send a start signal to the memory search module 40 when no cache data is found in the fourth cache layer;

[0095] A first cold search submodule, configured to search for cached data from a cold data area in a second cache layer if the data heat type is cold data;

[0096] A second cold search submodule, configured to search for cache data from a third cache layer when cache data is not found in a cold data area in the second cache layer;

[0097] The third cold search submodule is used to search for cache data from the fourth cache layer when no cache data is found in the third cache layer; and to send a start signal to the memory search module 40 when no cache data is found in the fourth cache layer.

[0098] In some embodiments, the apparatus may further include:

[0099] A strategy determination module is used to determine the prefetch strategy of each memory data according to the data heat type of each memory data in the memory; wherein the prefetch strategy includes a cold data prefetch strategy and a hot data prefetch strategy; the prefetch trigger condition of the hot data prefetch strategy is lower than the prefetch trigger condition of the cold data prefetch strategy, and / or the prefetch window of the hot data prefetch strategy is larger than the prefetch window of the cold data prefetch strategy;

[0100] The pre-fetch module is used to store the memory data that triggers the corresponding pre-fetch triggering condition into the corresponding preset cache area according to the pre-fetching strategy.

[0101] In some embodiments, the detection module 20 can be specifically used to determine the data heat type based on the data heat value flag of the access address in the preset memory management mapping table; wherein the preset memory management mapping table includes each address information and its respective data heat value flag.

[0102] In some embodiments, the apparatus may further include:

[0103] A monitoring module, used for monitoring the access frequency of the central processing unit to each historical access address;

[0104] A heat determination module is used to determine the heat value flag of the latest data of each historical access address according to the access frequency;

[0105] The flag update module is used to update the data heat value flag of the corresponding address information in the preset memory management mapping table according to the latest data heat value flag.

[0106] In some embodiments, the apparatus may further include:

[0107] A data determination module is used to determine key hotspot data based on access frequency;

[0108] The locking module is used to distribute the key hotspot data to each cache layer in the preset cache area corresponding to the hot data for storage and locking.

[0109] In this embodiment, the embodiment of the present invention can partition the cache according to the heat of the data by setting preset cache areas corresponding to cold data and hot data respectively, so as to reasonably allocate cache resources, reduce costs, and improve the efficiency and speed of memory access. By setting up hot data cache layers and hot data areas with smaller granularity, more refined consistency control can be achieved, and the cache hit rate and system performance can be improved. By searching the cache data corresponding to the access address from the target cache area through the pre-fetch search module 30, the required data can be searched in the corresponding preset cache area according to the heat of the data, thereby improving the speed of memory access.

[0110] Corresponding to the above method embodiment, an embodiment of the present invention further provides a cache management device for memory access. The cache management device for memory access described below and the cache management method for memory access described above can refer to each other.

[0111] Please refer to Figure 6 , Figure 6 A schematic diagram of the structure of a cache management device for memory access provided by an embodiment of the present invention. The device may include:

[0112] A memory D1, for storing computer programs;

[0113] The processor D2 is used to implement the steps of the cache management method for memory access provided by the above method embodiment when executing a computer program.

[0114] The memory access cache management device provided in this embodiment may specifically be a CPU chip, or a memory management unit in a CPU chip.

[0115] Corresponding to the above method embodiment, an embodiment of the present invention further provides a computer program product. The computer program product described below and the cache management method for memory access described above can be referred to in correspondence with each other.

[0116] A computer program product includes a computer program / instruction, which, when executed by a processor, implements the steps of the cache management method for memory access provided by the above method embodiment.

[0117] Corresponding to the above method embodiment, an embodiment of the present invention further provides a computer-readable storage medium. The computer-readable storage medium described below and the cache management method for memory access described above can be referred to each other.

[0118] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the cache management method for memory access in the above method embodiment.

[0119] The computer-readable storage medium may be a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., which may store program codes.

[0120] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the devices, equipment, computer program products and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0121] The above is a detailed introduction to a cache management method, device, equipment and storage medium for memory access provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A cache management method for memory access, characterized in that: include: Get the data read and write messages of the central processor; Detecting the data heat type of the access address of the data read / write message; wherein the data heat type includes cold data and hot data; Searching for cache data corresponding to the access address from a target cache area; wherein the target cache area is a preset cache area corresponding to the data heat type, the preset cache area corresponding to the hot data includes a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer, the preset cache area corresponding to the cold data includes a cold data area in the first common cache layer and the second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer; the distance between the hot data cache layer and the central processing unit is smaller than the distance between the first common cache layer and the central processing unit, and the distance between the second common cache layer and the central processing unit is smaller than the distance between the second common cache layer and the central processing unit; If the cache data is not found in the target cache area, a corresponding read / write request is sent to the memory to search the memory for memory data corresponding to the access address.

2. The memory access cache management method according to claim 1, characterized in that: The step of searching the target cache area for a cache block corresponding to the access address includes: The cache data corresponding to the access address is searched from each cache layer in the target cache area in order of distance from the central processor from near to far.

3. The memory access cache management method according to claim 2, characterized in that: The hot data cache layer includes a first cache layer, the first common cache layer includes a second cache layer, and the second common cache layer includes a third cache layer and a fourth cache layer; searching for cache data corresponding to the access address from each cache layer in the target cache area in order of distance from the central processor from near to far, includes: If the data heat type is the hot data, searching the cache data from the first cache layer; When the cache data is not found in the first cache layer, searching for the cache data in a hot data area in the second cache layer; When the cache data is not found in the hot data area in the second cache layer, searching for the cache data in the third cache layer; When the cache data is not found in the third cache layer, searching for the cache data in the fourth cache layer; When the cache data is not found in the fourth cache layer, executing the step of sending a corresponding read / write request to the memory to search the memory for the memory data corresponding to the access address; If the data heat type is the cold data, searching for the cached data from the cold data area in the second cache layer; When the cache data is not found in the cold data area in the second cache layer, searching for the cache data in the third cache layer; When the cache data is not found in the third cache layer, searching for the cache data in the fourth cache layer; When the cache data is not found in the fourth cache layer, the step of sending a corresponding read / write request to the memory is performed to search the memory for memory data corresponding to the access address.

4. The cache management method for memory access according to claim 1, characterized in that: Also includes: Determine the prefetch strategy of each memory data according to the data heat type of each memory data in the memory; wherein the prefetch strategy includes a cold data prefetch strategy and a hot data prefetch strategy; the prefetch trigger condition of the hot data prefetch strategy is lower than the prefetch trigger condition of the cold data prefetch strategy, and / or the prefetch window of the hot data prefetch strategy is larger than the prefetch window of the cold data prefetch strategy; According to the pre-fetch strategy, the memory data that triggers the corresponding pre-fetch triggering condition is stored in the corresponding preset cache area.

5. The cache management method for memory access according to any one of claims 1 to 4, characterized in that: The detecting the data heat type of the access address of the data read / write message includes: The data heat type is determined according to the data heat value flag of the access address in the preset memory management mapping table; wherein the preset memory management mapping table includes each address information and the respective data heat value flag.

6. The memory access cache management method according to claim 5, characterized in that: Also includes: Monitoring the access frequency of the central processing unit to each historical access address; Determine the latest data heat value flag of each of the historical access addresses according to the access frequency; According to the latest data heat value flag, the data heat value flag of the corresponding address information in the preset memory management mapping table is updated.

7. The memory access cache management method according to claim 6, characterized in that: Also includes: Determine key hotspot data according to the access frequency; The key hotspot data is distributed to each cache layer in a preset cache area corresponding to the hot data for storage and locking.

8. A cache management device for memory access, characterized in that: include: An acquisition module is used to acquire data read and write messages from the central processor; A detection module, used to detect the data heat type of the access address of the data read / write message; wherein the data heat type includes cold data and hot data; A pre-fetch search module, configured to search for cache data corresponding to the access address from a target cache area; wherein the target cache area is a preset cache area corresponding to the data heat type, the preset cache area corresponding to the hot data includes a hot data cache layer, a hot data area in a first common cache layer, and a second common cache layer, the preset cache area corresponding to the cold data includes a cold data area in the first common cache layer and the second common cache layer, the granularity of the hot data cache layer and the hot data area is smaller than the granularity of the cold data area and the second common cache layer; the distance between the hot data cache layer and the central processing unit is smaller than the distance between the first common cache layer and the central processing unit, and the distance between the second common cache layer and the central processing unit is smaller than the distance between the second common cache layer and the central processing unit; A memory search module is used to send a corresponding read / write request to the memory if the cache data is not found in the target cache area, so as to search the memory for the memory data corresponding to the access address.

9. A cache management device for memory access, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the cache management method for memory access as claimed in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the cache management method for memory access according to any one of claims 1 to 7 are implemented.

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