Graphic processor interrupt control unit and interrupt control method

Abstract

The invention provides an interrupt control unit and an interrupt control method for a graphics processor. The interrupt control unit comprises a state machine control module and an interrupt register configuration module. When the state machine control module acquires that the interrupt line level of the sub-module is a high level, the interrupt vector number of the sub-module is acquired from the register, and the interrupt request and the interrupt vector number of the sub-module are sent to the upper computer; and when the upper computer receives the interrupt request, the corresponding sub-module is found in a table look-up mode to execute the interrupt operation according to the interrupt vector number in the interrupt request. When the interrupt request is sent to the upper computer, the corresponding interrupt vector number is added, after the upper computer analyzes the interrupt request, the interrupt vector number can be obtained, the submodule needing to be interrupted can be directly found, round-robin searching is not needed, and the interrupt response efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of interrupt control, and more specifically, to a graphics processor interrupt control unit and an interrupt control method. Background Art

[0002] Most modern graphics processors communicate with the host computer through the PCIE bus interface, and the graphics processor serves as a PCIE terminal device of the host computer. In the PCIE architecture, there are two main ways for the PCIE terminal to send an interrupt to the host computer. One is the traditional interrupt line level method, and the other is the MSI interrupt method, that is, the interrupt request is sent to the host computer through the PCIE storage write operation message sending mechanism. Due to the large number of sub-modules in the graphics processor that can initiate host computer interrupts, the traditional interrupt line level method requires a large number of additional lines and bypass logic, so most of them use the MSI interrupt method of the PCIE bus.

[0003] In the graphics processor, due to the complexity of functions, there are many types of host computer interrupts. The conventional PCIE bus MSI interrupt method will have some disadvantages. For example, as long as the interrupt line level is valid, interrupt requests will be continuously sent to the host computer until the host computer responds and clears the interrupt, and then the MSI message will be stopped. This causes a large number of interrupt request signals to accumulate and the memory usage is too large. Summary of the invention

[0004] The present invention aims at the technical problems existing in the prior art and provides a graphics processor interrupt control unit and an interrupt control method, which overcome the problems of slow interrupt request response speed and large memory occupation.

[0005] According to a first aspect of the present invention, there is provided a graphics processor interrupt control unit, the interrupt control unit is located in the graphics processor, and the interrupt control unit includes a state machine control module and an interrupt register configuration module; The state machine control module is used to collect the interrupt line level of each submodule, and when the interrupt line level of the collected submodule is high, obtain the interrupt vector number of the submodule from the interrupt vector register, and send an interrupt request and the interrupt vector number to the host computer; The interrupt register configuration module is used to configure the interrupt vector register, and the interrupt vector register is configured with the interrupt vector number corresponding to each submodule; The host computer is used to find the submodule corresponding to the interrupt vector number from the interrupt vector table according to the interrupt vector number in the received interrupt request, and perform an interrupt operation on the submodule corresponding to the interrupt vector number, wherein the interrupt vector table storing the corresponding relationship between the submodules and the interrupt vector numbers is stored in the host computer.

[0006] On the basis of the above technical solution, the present invention can also make the following improvements.

[0007] Optionally, the interrupt vector register is also configured with a correspondence between the interrupt vector number and the priority. When the state machine control module simultaneously detects that the interrupt line levels of multiple sub-modules are high, the interrupt vector numbers of the multiple sub-modules and the priority of each interrupt vector number are found from the interrupt vector register, and the interrupt request and interrupt vector number are sent to the host computer in the order of the priority of each interrupt vector number.

[0008] Optionally, the interrupt register configuration module is further configured with an interrupt mask register, and the interrupt mask register is used to configure the interrupt mask of each submodule, and the interrupt mask indicates whether to mask the interrupt enable of the submodule; The state machine control module is used to search for the interrupt mask of the submodule when the interrupt line level of the submodule is collected to be high level, and to send an interrupt request and an interrupt vector number to the host computer when the submodule is not masked.

[0009] Optionally, the interrupt register configuration module is further configured with a timed query count register; In the interrupt idle state, when the state machine control module collects that the interrupt line level of one or more sub-modules is enabled and not masked, it jumps to the corresponding interrupt sending state. When the interrupt sending is allowed, the timed query count register enters the timed counting state. When the timed counting state overflows, the state machine control module jumps back to the interrupt idle state, and at the same time reads the interrupt line level and interrupt mask of each module to enter the next interrupt sending state.

[0010] Optionally, when the state machine control module enters the interrupt request sending state of a submodule, it stops sending interrupt requests with the same interrupt vector number to the host computer.

[0011] Optionally, the graphics processor further includes an MSI message sending module; The state machine control module is used to collect the interrupt line level of each submodule, and when the collected interrupt line level of the submodule is high, obtain the interrupt vector number of the submodule from the interrupt vector register, and output the interrupt request and the interrupt vector number to the MSI message sending module; The MSI message sending module is used to send an MSI interrupt request to a host computer in an MSI message data packet format according to the interrupt request and interrupt vector number output by the state machine control module.

[0012] According to a second aspect of the present invention, there is provided a graphics processor interrupt control method, comprising: The interrupt line level of each submodule is collected by the state machine control module. When the interrupt line level of the collected submodule is high, the interrupt vector number of the submodule is obtained from the interrupt vector register, wherein the interrupt vector register is configured with the interrupt vector number corresponding to each submodule; Sending an interrupt request to a host computer according to the interrupt request and the interrupt vector number of the submodule, wherein the interrupt request includes the interrupt vector number; When the host computer receives the interrupt request, it searches the interrupt vector table for the submodule corresponding to the interrupt vector number according to the interrupt vector number in the interrupt request, and performs an interrupt operation on the submodule corresponding to the interrupt vector number, wherein the interrupt vector table storing the correspondence between each submodule and the interrupt vector number is pre-set in the host computer.

[0013] Optionally, the method further includes: The correspondence between the interrupt vector number and the priority is configured in the interrupt vector register. When the state machine control module simultaneously collects the interrupt line levels of multiple sub-modules as high levels, the interrupt vector numbers of the multiple sub-modules and the priority of each interrupt vector number are found through a lookup table, and an interrupt request is sent to the host computer in the priority order of each interrupt vector number.

[0014] Optionally, the method further includes: Configuring the interrupt mask of each submodule in the interrupt mask register, wherein the interrupt mask indicates whether to mask the interrupt enable of the submodule; When the state machine control module detects that the interrupt line level of the submodule is high, it searches for the interrupt mask of the submodule, and sends an interrupt request to the host computer when the submodule is not masked.

[0015] Optionally, the method further includes: Configure the timing query count register; In the interrupt idle state, when the state machine control module collects that the interrupt line level of one or more sub-modules is enabled and not masked, it jumps to the corresponding interrupt request sending state. When the interrupt request sending is allowed, the timed query count register enters the timed counting state. When the timed counting state overflows, the state machine control module jumps back to the interrupt idle state, and at the same time reads the interrupt line level and interrupt mask of each module to enter the next interrupt sending state.

[0016] The present invention provides a graphics processor interrupt control unit and interrupt control method. When the state machine control module collects the interrupt line level of the submodule as a high level, the interrupt vector number of the submodule is obtained from the interrupt vector register, wherein the interrupt vector number corresponding to each submodule is configured in the interrupt vector register; the interrupt request and the interrupt vector number are sent to the host computer; when the host computer receives the interrupt request, according to the interrupt vector number in the interrupt request, the submodule corresponding to the interrupt vector number is found from the preset interrupt vector table, and the interrupt operation is performed on the submodule corresponding to the interrupt vector number. The present invention adds the corresponding interrupt vector number to the interrupt request sent to the host computer. After parsing the interrupt request, the host computer can obtain the interrupt vector number and directly find the submodule that needs to execute the interrupt without round-robin search, thereby improving the interrupt response efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic block diagram of a graphics processor interrupt control unit provided by the present invention; Figure 2 It is a schematic diagram of the state jump of the state machine control module; Figure 3 It is a signal timing diagram of MSI interruption of the prior art solution; Figure 4 It is a timing diagram of the MSI interrupt signal of the solution of the present invention; Figure 5 The present invention provides a flowchart of a graphics processor interrupt control method. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be arbitrarily combined with each other to form a feasible technical solution. This combination is not subject to the constraints of the sequence of steps and / or the structural composition mode, but must be based on the ability of ordinary technicians in this field to achieve. When the combination of technical solutions is contradictory or cannot be achieved, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0019] In the traditional interrupt control scheme, when a submodule generates an interrupt line level, the MSI interrupt controller sends an interrupt request to the host computer. Before the host computer responds to the interrupt request, or another submodule also generates an interrupt line level, the MSI interrupt controller will continue to send interrupt requests to the host computer. When the host computer cannot respond to the interrupt request in time, invalid interrupt requests will continue to accumulate, causing a large amount of host computer memory to be occupied. At the same time, since there is no relevant information about the interrupt vector in the interrupt request, the host computer needs to poll each module after receiving the interrupt request to determine which module has generated the interrupt, resulting in a long interrupt processing time and reduced interrupt response efficiency. Furthermore, since there are many types of interrupts in the graphics processor, if the priority of each interrupt request is the same, it is impossible to give priority to the interrupt request that needs to be processed in time, which affects the smooth operation of the graphics processor.

[0020] Based on this, Figure 1 The invention provides a graphics processor interrupt control unit, which is located in the graphics processor and mainly comprises a state machine control module and an interrupt register configuration module.

[0021] Its working process is as follows: the state machine control module is used to collect the interrupt line level of each sub-module. When the interrupt line level of the collected sub-module is high, the interrupt vector number of the sub-module is obtained from the interrupt vector register, and the interrupt request and interrupt vector number are sent to the upper computer; The interrupt register configuration module is used to configure the interrupt vector register, and the interrupt vector register is configured with the interrupt vector number corresponding to each submodule; The host computer is used to find the submodule corresponding to the interrupt vector number from a preset interrupt vector table according to the interrupt vector number in the received interrupt request, and perform an interrupt operation on the submodule corresponding to the interrupt vector number, wherein the host computer stores an interrupt vector table that shows the corresponding relationship between the submodules and the interrupt vector numbers.

[0022] Specifically, Figure 1 As shown, the state machine control module monitors the interrupt line level enable signal of each interrupt submodule. If the interrupt line level of one or more submodules is detected to be high, it indicates that the submodule needs to execute an interrupt. At this time, the state machine control module obtains the interrupt vector number of the submodule from the interrupt vector register and sends the interrupt request and the interrupt vector number corresponding to the submodule to the host computer.

[0023] When the state machine control module sends an interrupt request to the host computer, the present invention organizes the interrupt request into the form of an MSI message data packet through the MSI message sending module for sending. Specifically, the MSI message sending module receives the interrupt request and the interrupt vector number transmitted by the state machine control module, assembles the interrupt request according to the MSI message data packet format, and the graphics processor communicates with the host computer through the PCIE bus. Therefore, the MSI message sending module sends the organized MSI interrupt request to the host computer through the PCIE sending module.

[0024] When the host computer receives the MSI interrupt request, it responds to the interrupt request of the corresponding submodule according to the interrupt vector number in the interrupt request. The graphics processor receives the interrupt response information of the host computer through the PCIE receiving module.

[0025] Among them, the MSI message sending module, PCIE sending module and PCIE receiving module are all located in the graphics processor. The interrupt register configuration module configures each interrupt register. The interrupt register mainly includes an interrupt vector number register, an interrupt mask register and a timing query count register. The three registers are configured respectively.

[0026] The interrupt vector number register is mainly used to configure the interrupt vector number corresponding to each submodule, and store the interrupt vector table of the correspondence between each submodule and the interrupt vector number in the host computer. When the host computer receives an MSI interrupt request, it directly locates the submodule that needs to execute the interrupt according to the interrupt vector number carried in the MSI interrupt request and the correspondence table between each submodule and the interrupt vector number, and performs the interrupt operation on it, without the need to poll and respond to the interrupt requests of multiple submodules as in the existing control scheme, thus speeding up the interrupt response speed.

[0027] In addition, the priority of each submodule can be dynamically set, specifically, the priority corresponding to each interrupt vector number can be set. When the state machine control module simultaneously collects the interrupt line levels of multiple submodules as high levels, the interrupt vector numbers of multiple submodules and the priority of each interrupt vector number are found from the interrupt vector register, and the interrupt request and interrupt vector number are output to the MSI message sending module according to the priority order of each interrupt vector number, and then the interrupt request is sent to the host computer according to the priority, so that the host computer responds to the interrupt request of each submodule according to the priority.

[0028] Among them, the interrupt mask register is used to configure the interrupt mask of each submodule. When it is not necessary to perform an interrupt operation on a certain submodule, the interrupt mask of the submodule can be set to shield the interrupt task of the submodule. Specifically, when the state machine control module collects the interrupt line level of the submodule as a high level, it searches for the interrupt mask of the submodule. When the submodule is not masked, it outputs the interrupt request and interrupt vector number to the MSI message sending module. That is, only when the state machine control module detects that the interrupt line level of the submodule is high and the submodule is not masked, the state machine control module will send an interrupt request to the host computer through the MSI message sending module; if the submodule is masked, even if the interrupt line level of the submodule is high, it still does not send an interrupt request to the host computer.

[0029] Among them, the timer count register can be configured to send the interrupt request time interval to the host computer. In the interrupt idle state, when the state machine control module collects the interrupt line level of one or more sub-modules and is enabled and not masked, it jumps to the corresponding MSI interrupt sending state. After collecting the MSI interrupt sending permission, the timing query count register enters the timing counting state. When the timing counting state overflows, the state machine control module jumps back to the interrupt idle state, and reads the interrupt line level and interrupt mask of each module to enter the next interrupt sending state. Through the online configurable timing counter jump value, the interrupt sending time interval of each module is dynamically adjusted and optimized according to the execution rate of the host computer program and the complexity of the interrupt service program, reducing invalid and redundant interrupt requests.

[0030] It should be noted that when the graphics processor is initialized, the interrupt mask and interrupt vector number of each submodule can be configured, the MSI interrupt enable can be turned on or off, and the timed query counter jump value can be configured. During the operation of the graphics processor, the register value of the interrupt register configuration module can also be dynamically modified.

[0031] During the operation of the graphics processor, if the performance of a submodule needs to be improved, the interrupt line mask status of other submodules can be reconfigured to shield other interrupts. For example, when the state machine control module enters a certain interrupt request sending state, it stops sending interrupt requests with the same vector number to the host computer; increase the interrupt mask to dynamically shield the interrupt requests of each module. You can also reconfigure the interrupt vector number of the submodule to improve the interrupt response priority.

[0032] The present invention realizes dynamically adjustable MSI interrupt transmission control through configurable interrupt vector numbers, interrupt masks, and interrupt timing counters of each submodule. During a certain interrupt request response period, the interrupt response state is regularly queried, and the timing values ​​of each interrupt are dynamically configured. Within the timing, new or redundant invalid interrupt requests are stopped from being sent to the host computer. The interrupt vector numbers of each submodule are dynamically adjusted to control the interrupt response priority thereof; according to the memory usage of the host computer, the interrupt mask of each module is dynamically configured to shield the interrupt request transmission, thereby reducing the memory occupation of the host computer.

[0033] like Figure 2 The figure shows the state transition diagram of the interrupt state machine. In the interrupt idle state, when one or more interrupt line levels are enabled and not masked, the state machine control module jumps to the corresponding MSI interrupt send state. When the MSI interrupt send permission is collected, it enters the timing count state. When the timing count state overflows, it jumps back to the interrupt idle state, and reads the interrupt line level and mask to enter the next interrupt send state.

[0034] After the host computer receives the MSI interrupt, it enters the interrupt response service program. The host computer reads the interrupt submodule register, clears the interrupt line level state, and executes the interrupt service. After the host computer completes the interrupt service program, it jumps back to the main program to continue execution. Only when the host computer completes the interrupt service program can it respond to other MSI interrupt requests. When the host computer executes the interrupt service program, the MSI message sent by the PCIE bus is invalid redundant data, which occupies the host computer memory and affects the interrupt response efficiency of the host computer.

[0035] in, Figure 3 The MSI interrupt sending timing diagram of the existing control scheme is shown below. Figure 4 This is a timing diagram of the MSI interrupt transmission of the present invention.

[0036] See also Figure 5 , a graphics processor interrupt control method provided by the present invention comprises: Step 1, collecting the interrupt line level of each submodule through the state machine control module, when the collected interrupt line level of the submodule is high, obtaining the interrupt vector number of the submodule from the interrupt vector register, wherein the interrupt vector register is configured with the interrupt vector number corresponding to each submodule; Step 2, sending an interrupt request to a host computer according to the interrupt request and interrupt vector number of the submodule, wherein the interrupt request includes the interrupt vector number; Step 3, when the host computer receives the interrupt request, it searches the interrupt vector table for the submodule corresponding to the interrupt vector number according to the interrupt vector number in the interrupt request, and performs an interrupt operation on the submodule corresponding to the interrupt vector number, wherein the interrupt vector table storing the correspondence between each submodule and the interrupt vector number is pre-set in the host computer.

[0037] It is understandable that the present invention is configured with multiple registers, namely, an interrupt vector register, an interrupt mask register, and a timing query count register. The interrupt vector number of each submodule is configured in the interrupt vector register, and the corresponding relationship between the interrupt vector number and the priority is configured in the interrupt vector register. When the state machine control module simultaneously collects the interrupt line levels of multiple submodules as high levels, the interrupt vector numbers of multiple submodules and the priority of each interrupt vector number are found through a lookup table, and an MSI interrupt request is sent to the host computer according to the priority order of each interrupt vector number.

[0038] And configure the interrupt mask of each submodule in the interrupt mask register, the interrupt mask represents whether to mask the interrupt enable of the submodule; when the state machine control module collects the interrupt line level of the submodule as a high level, it searches for the interrupt mask of the submodule, and when the submodule is not masked, sends an MSI interrupt request to the upper computer.

[0039] And configure the interrupt count value of the timing query count register. In the interrupt idle state, when the state machine control module collects that the interrupt line level of one or more sub-modules is enabled and not masked, it jumps to the corresponding MSI interrupt request sending state. When the MSI interrupt request sending is allowed, the timing query count register enters the timing counting state. When the timing counting state overflows, the state machine control module jumps back to the interrupt idle state, and at the same time reads the interrupt line level and interrupt mask of each module to enter the next interrupt sending state.

[0040] The embodiment of the present invention provides a graphics processor interrupt control unit and control method. During initialization, interrupt vector tables of each module are configured in a host computer and a graphics processor, and corresponding interrupt vector information is added to a sent MSI message. After parsing the message, the host computer can obtain the interrupt vector without obtaining the interrupt type through polling, thereby improving the interrupt response efficiency. The interrupt vector number of each module can be dynamically shielded and configured to control the priority of each interrupt vector, and the interrupt request of the key submodule is processed preferentially. The interrupt vector mask of each module can be dynamically configured. According to the memory occupancy of the host computer, when the memory consumption is too large or the interrupt cannot be processed in time, the interrupt request sending can be shielded to avoid a large number of interrupt requests accumulating. In the interrupt request sending state, the sending time interval of the interrupt request can be dynamically adjusted according to the execution rate of the host computer program and the complexity of the interrupt service program, thereby reducing the number of interrupt requests of the same type and alleviating the memory occupancy.

[0041] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0042] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0043] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A graphics processor interrupt control unit, characterized in that: The interrupt control unit is located in the graphics processor, and the interrupt control unit includes a state machine control module and an interrupt register configuration module; The state machine control module is used to collect the interrupt line level of each submodule, and when the interrupt line level of the collected submodule is high, obtain the interrupt vector number of the submodule from the interrupt vector register, and send an interrupt request and the interrupt vector number to the host computer; The interrupt register configuration module is used to configure the interrupt vector register, and the interrupt vector register is configured with the interrupt vector number corresponding to each submodule; The host computer is used to find the submodule corresponding to the interrupt vector number from the interrupt vector table according to the interrupt vector number in the received interrupt request, and perform an interrupt operation on the submodule corresponding to the interrupt vector number, wherein the interrupt vector table storing the corresponding relationship between the submodules and the interrupt vector numbers is stored in the host computer.

2. The graphics processor interrupt control unit according to claim 1, characterized in that: The interrupt vector register is also configured with a correspondence between the interrupt vector number and the priority. When the state machine control module simultaneously collects that the interrupt line levels of multiple sub-modules are high, the interrupt vector numbers of the multiple sub-modules and the priority of each interrupt vector number are found from the interrupt vector register, and the interrupt request and interrupt vector number are sent to the host computer in the order of the priority of each interrupt vector number.

3. The graphics processor interrupt control unit according to claim 1, characterized in that: The interrupt register configuration module is further configured with an interrupt mask register, which is used to configure the interrupt mask of each submodule, and the interrupt mask indicates whether to mask the interrupt enable of the submodule; The state machine control module is used to search for the interrupt mask of the submodule when the interrupt line level of the submodule is collected to be high level, and to send an interrupt request and an interrupt vector number to the host computer when the submodule is not masked.

4. The graphics processor interrupt control unit according to claim 1, characterized in that: The interrupt register configuration module is also configured with a timing query count register; In the interrupt idle state, when the state machine control module collects that the interrupt line level of one or more sub-modules is enabled and not masked, it jumps to the corresponding interrupt sending state. When the interrupt sending is allowed, the timed query count register enters the timed counting state. When the timed counting state overflows, the state machine control module jumps back to the interrupt idle state, and at the same time reads the interrupt line level and interrupt mask of each module to enter the next interrupt sending state.

5. The graphics processor interrupt control unit according to claim 1, characterized in that: When the state machine control module enters the interrupt request sending state of a submodule, it stops sending the interrupt request with the same interrupt vector number to the host computer.

6. The graphics processor interrupt control unit according to claim 1, characterized in that: The graphics processor also includes an MSI message sending module; The state machine control module is used to collect the interrupt line level of each submodule, and when the interrupt line level of the collected submodule is high, obtain the interrupt vector number of the submodule from the interrupt vector register, and output the interrupt request and the interrupt vector number to the MSI message sending module; The MSI message sending module is used to send an MSI interrupt request to a host computer in an MSI message data packet format according to the interrupt request and interrupt vector number output by the state machine control module.

7. A graphics processor interrupt control method, characterized in that: include: The interrupt line level of each submodule is collected by the state machine control module. When the interrupt line level of the collected submodule is high, the interrupt vector number of the submodule is obtained from the interrupt vector register, wherein the interrupt vector register is configured with the interrupt vector number corresponding to each submodule; Sending an interrupt request to a host computer according to the interrupt request and the interrupt vector number of the submodule, wherein the interrupt request includes the interrupt vector number; When the host computer receives the interrupt request, it searches the interrupt vector table for the submodule corresponding to the interrupt vector number according to the interrupt vector number in the interrupt request, and performs an interrupt operation on the submodule corresponding to the interrupt vector number, wherein the interrupt vector table storing the correspondence between each submodule and the interrupt vector number is pre-set in the host computer.

8. The graphics processor interrupt control method according to claim 7, characterized in that: The method further comprises: The correspondence between the interrupt vector number and the priority is configured in the interrupt vector register. When the state machine control module simultaneously collects the interrupt line levels of multiple sub-modules as high levels, the interrupt vector numbers of the multiple sub-modules and the priority of each interrupt vector number are found through a lookup table, and an interrupt request is sent to the host computer in the priority order of each interrupt vector number.

9. The graphics processor interrupt control method according to claim 7, characterized in that: The method further comprises: Configure the interrupt mask of each submodule in the interrupt mask register, wherein the interrupt mask indicates whether to mask the interrupt enable of the submodule; When the state machine control module detects that the interrupt line level of the submodule is high, it searches for the interrupt mask of the submodule, and sends an interrupt request to the host computer when the submodule is not masked.

10. The graphics processor interrupt control method according to claim 7, characterized in that: The method further comprises: Configure the timing query count register; In the interrupt idle state, when the state machine control module collects that the interrupt line level of one or more sub-modules is enabled and not masked, it jumps to the corresponding interrupt request sending state. When the interrupt request sending is allowed, the timed query count register enters the timed counting state. When the timed counting state overflows, the state machine control module jumps back to the interrupt idle state, and at the same time reads the interrupt line level and interrupt mask of each module to enter the next interrupt sending state.

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