SMI transparent transmission method and device based on SPI interface

Abstract

The invention discloses an SMI transparent transmission method based on an SPI interface, and relates to the technical field of communication, the transparent transmission steps are as follows: S1, the SPI interface is initialized, the overall performance of a system and the electrical characteristics of a connected external device are evaluated, the clock frequency parameter of the SPI interface is determined, and the SPI interface is initialized; s2, directly connecting an SPI interface and an SMI interface by using an FPGA, and establishing a data transmission channel between the SPI interface and the SMI interface; and S3, configuring the FPGA, analyzing characteristics, protocols and time sequence parameters of the SPI and the SMI, creating a project based on a development tool, and planning logic resources and pin setting. The invention further discloses an SMI transparent transmission device based on the SPI interface. Transparent transmission from the SPI interface to the SMI interface is achieved through the FPGA, the FPGA does not need to design an SMIMaster module, internal caching and transferring of the FPGA are not needed, the design is simple, delay does not exist, the SPI interface equivalent to a CPU directly accesses a slave, the SPI interface and SMI transparent transmission are effectively combined, and the data transmission performance and compatibility of a system are improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an SMI transparent transmission method and device based on an SPI interface. Background Art

[0002] As the functions of modern electronic devices become increasingly complex and diversified, the demand for data interaction between different modules is also increasing. SMI, or serial management interface, is a commonly used management interface used in many devices to realize the transmission of control information and status information. However, the traditional SMI interface has low transmission efficiency and limited compatibility in some application scenarios. SPI, or serial peripheral interface, has the advantages of simplicity, high speed and flexibility. Therefore, how to effectively combine the SPI interface with SMI transparent transmission to improve the data transmission performance and compatibility of the system has become a technical problem that needs to be solved urgently. In this regard, we propose an SMI transparent transmission method and device based on SPI interface. Summary of the invention

[0003] In order to solve the above technical problems, a SMI transparent transmission method and device based on SPI interface are provided. This technical solution solves the above problems of low transmission efficiency and limited compatibility.

[0004] To achieve the above purpose, the technical solution adopted by the present invention is: an SMI transparent transmission method based on the SPI interface, the transparent transmission steps are:

[0005] S1, SPI interface initialization, evaluate the overall system performance and the electrical characteristics of the connected external devices, determine the clock frequency parameters of the SPI interface, and initialize the SPI interface;

[0006] S2, using FPGA to directly connect the SPI interface and the SMI interface to establish a data transmission channel between the two;

[0007] S3, configure the FPGA, analyze the characteristics, protocols and timing parameters of the SPI and SMI interfaces, create a project based on the development tool, plan logic resources and pin settings, write code in HDL, and design connection and control logic;

[0008] S4, transmission, when the SPI interface has data input, the FPGA directly transmits the data to the SMI interface according to the timing requirements of the SMI interface; when the SMI interface has data input, the FPGA also directly transmits the data to the SPI interface according to the timing requirements of the SPI interface, and performs transparent transmission from the SPI interface to the SMI interface;

[0009] S5, Error detection, based on hash algorithm data integrity verification, verifies the accuracy of transmitted data from multiple dimensions;

[0010] S6, status feedback processing, receiving the transmission status signal of the target device, and performing data release, error correction and error reporting processing according to the status.

[0011] Preferably, in step S1, the overall performance is evaluated by analyzing the data transmission rate, counting the data generation frequency, data byte length and data urgency of different types of sensors, determining by calculation the minimum data transmission rate required for the system to maintain normal and efficient operation per unit time, and estimating the maximum data transmission demand under the system peak load condition; evaluating the electrical characteristics of the external device, obtaining the technical specifications of the external device through big data, obtaining the maximum SPI clock frequency supported, and determining the SPI data bit width format supported by the external device.

[0012] Preferably, the transmission rate analysis formula is:

[0013]

[0014] Where n is the number of sensors, F i is the frequency of sensor data generated by the i-th type, L i is the byte length of the data generated by the i-th type sensor each time, K i is the urgency weight coefficient of the i-th type of sensor data, and R is the calculated transmission rate;

[0015] The formula for estimating the maximum data transmission under system peak load conditions is: A = αR, where A is the calculated maximum download transmission demand value, α is the peak load factor estimated based on historical data and experience, and R is the calculated transmission rate.

[0016] Preferably, in step S2, based on the characteristics of the SPI interface and the SMI interface and their hardware connection, electrical compatibility and signal integrity are ensured, and an SPI interface controller and an SMI interface controller are respectively constructed inside the FPGA. The SPI interface controller generates the signals required by the SPI and monitors its status, and the SMI interface controller parses the SMI protocol to realize data reception and transmission and control signal processing.

[0017] Preferably, in step S3, the SPI and SMI interface characteristics, protocols and timing parameters are first analyzed, and in the process of creating a project with professional development tools, the internal logic resource allocation of the FPGA is planned to adapt the interface logic design and data processing volume and pin setting, the signal integrity factor is considered, the pin electrical standard and drive strength are determined, the code is written based on HDL, and a SPI interface controller, SMI interface controller and connection and functional modules are constructed.

[0018] Preferably, the logical resource allocation calculation formula is:

[0019] B=C1×DSPI ×E SPI +C2×D SMI ×E SMI

[0020] Where B is the calculated value of logic resource allocation, C1 and C2 are adjustment coefficients determined based on experience and FPGA architecture, and D SPI With D SMI is the interface logic complexity index, E SPI With E SMI is the correlation coefficient of data processing volume; the formula of pin electrical standard and driving strength is: S=g1(h, m, j), O=g2(h, m, j), where h is signal frequency, m is transmission distance, j is line width, S is pin driving strength, O is electrical standard, g1 and g2 are expressed as a complex functional relationship based on signal integrity theory and practical experience. When the signal frequency is high, the transmission distance is long and the line width is narrow, high driving strength S and high-frequency electrical standard O are selected.

[0021] Preferably, in step S4, when the SPI interface has data input, the FPGA receives and caches the data, generates an adaptation clock signal according to the timing requirements of the SMI interface, performs format conversion, and then transmits the data to the SMI interface according to its protocol specifications; wherein the format conversion method uses a binary complement method for conversion, and converts the data bit by bit according to the Gray code and binary complement conversion rules.

[0022] Preferably, in step S5, the misalignment detection is performed by pre-blocking the data to determine the size of the transmitted data. When the amount of data is large, the data is divided into blocks of fixed size. For each data block, a hash value is calculated using a hash algorithm. If the data is not blocked, the hash value of the entire data is calculated, and the obtained hash value is stored. The stored hash value is verified, compared and judged. When a hash value mismatch is detected, the data is erroneous.

[0023] Preferably, in step S6, when the data reaches the target device through the transmission channel, the target device generates a transmission status signal according to its own data reception and processing status, and transmits it back to the sending end. After receiving the transmission status signal, the sending end performs a data release link. If the transmission signal is complete and accurate, the sending end triggers a data release mechanism, and the sending end releases the cache area originally used to temporarily store the batch of data to make room for subsequent new data transmission;

[0024] If the transmission status signal indicates that the data has a correctable error, the error correction program is started, and the Hamming code error correction technology is used. The sender locates the erroneous bit in the data according to the received error information and the check rule of the Hamming code, and automatically corrects it. By analyzing and calculating the Hamming code check bit contained in the data and comparing it with the received error status information, the position of the error bit is determined, the error bit is flipped, and the correctness of the data is restored;

[0025] When the transmission status signal indicates that the data is erroneous and cannot be repaired by the error correction mechanism, the sender generates a detailed error report.

[0026] An SMI transparent transmission device based on an SPI interface comprises an SPI interface, an SMI interface, a data cache memory, an FPGA core processor, an error detector and a feedback center; the SPI interface comprises a four-wire connection port for docking with a device conforming to the SPI protocol, and the SMI interface is connected to the SMI device.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention realizes transparent transmission from SPI interface to SMI interface through FPGA, does not need FPGA to design SMI_Master module, and does not need FPGA internal cache and transfer. The design is simple and has no delay. It is equivalent to the SPI interface of CPU directly accessing the slave, and effectively combines the SPI interface with SMI transparent transmission to improve the data transmission performance and compatibility of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a flow chart of the transparent transmission steps of the present invention. DETAILED DESCRIPTION

[0030] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art may think of other obvious variations.

[0031] Reference Figure 1 As shown, a SMI transparent transmission method based on SPI interface, the transparent transmission steps are:

[0032] S1, SPI interface initialization, evaluate the overall system performance and the electrical characteristics of the connected external devices, determine the clock frequency parameters of the SPI interface, and initialize the SPI interface;

[0033] S2, using FPGA to directly connect the SPI interface and the SMI interface to establish a data transmission channel between the two;

[0034] S3, configure the FPGA, analyze the characteristics, protocols and timing parameters of the SPI and SMI interfaces, create a project based on the development tool, plan logic resources and pin settings, write code in HDL, and design connection and control logic;

[0035] S4, transmission, when the SPI interface has data input, the FPGA directly transmits the data to the SMI interface according to the timing requirements of the SMI interface; when the SMI interface has data input, the FPGA also directly transmits the data to the SPI interface according to the timing requirements of the SPI interface, and performs transparent transmission from the SPI interface to the SMI interface;

[0036] S5, Error detection, based on hash algorithm data integrity verification, verifies the accuracy of transmitted data from multiple dimensions;

[0037] S6, status feedback processing, receiving the transmission status signal of the target device, and performing data release, error correction and error reporting processing according to the status.

[0038] Since the present application does not need to build a complex SMI_Master module and cache unit inside the FPGA, a large amount of FPGA logic resources are saved. These saved resources can be used to expand or optimize other functional modules of the system, thereby improving the resource utilization of the entire system, so that the system can achieve more functions at the same hardware cost or run on a lower-cost hardware platform;

[0039] By evaluating the overall system performance and the electrical characteristics of the connected external devices during the initialization phase, the clock frequency parameters of the SPI interface can be accurately determined, which helps ensure a good electrical match between the SPI interface and the external devices, reduces signal distortion and bit errors caused by electrical mismatch, and improves the reliability of data transmission.

[0040] Transparent transmission from the SPI interface to the SMI interface is realized, and data flows directly between the two interfaces without complicated internal caching and transit processing. This makes the data transmission process more concise and intuitive, reduces errors and data inconsistency problems that may be introduced in the data processing link, and ensures the originality and accuracy of the data.

[0041] In step S1, the overall performance is evaluated by analyzing the data transmission rate, counting the data generation frequency, data byte length and data urgency of different types of sensors, and determining the minimum data transmission rate required for the system to maintain normal and efficient operation per unit time through calculation, and estimating the maximum data transmission demand under the system peak load; the electrical characteristics of external devices are evaluated by obtaining the technical specifications of external devices through big data, obtaining the maximum supported SPI clock frequency, and determining the SPI data bit width format supported by the external device.

[0042] This application calculates the minimum data transmission rate by analyzing the data generation frequency, data byte length and data urgency of different types of sensors, and can accurately determine the network bandwidth and processing power required for the system to operate normally and efficiently. This helps to reasonably select data transmission lines, determine the read and write speeds of data storage devices, and configure the performance parameters of processor core components during the system design phase, avoiding waste caused by over-configuration of resources or system performance bottlenecks caused by insufficient resources.

[0043] The transmission rate analysis formula is:

[0044]

[0045] Where n is the number of sensors, F i is the frequency of sensor data generated by the i-th type, L i is the byte length of the data generated by the i-th type sensor each time, K i is the urgency weight coefficient of the i-th type of sensor data, and R is the calculated transmission rate;

[0046] The formula for estimating the maximum data transmission under system peak load conditions is: A = αR, where A is the calculated maximum download transmission demand value, α is the peak load factor estimated based on historical data and experience, and R is the calculated transmission rate.

[0047] This application can optimize the data processing flow within the system based on the calculation results of the transmission rate formula. If it is found that the data generation frequency of a certain type of sensor is too high, resulting in the transmission rate requirement exceeding the current hardware processing capability, you can consider performing certain data preprocessing close to the sensor end, such as data compression or data screening, to reduce the amount of transmitted data so that the transmission rate meets the system requirements. You can also optimize the system's storage structure based on the formula results to ensure that the read and write speeds of the storage device can meet the data writing and reading requirements.

[0048] In step S2, based on the characteristics of the SPI interface and the SMI interface and their hardware connections, electrical compatibility and signal integrity are ensured. Inside the FPGA, an SPI interface controller and an SMI interface controller are constructed respectively. The SPI interface controller generates the signals required by the SPI and monitors its status. The SMI interface controller parses the SMI protocol to realize data transmission and reception and control signal processing.

[0049] The SPI interface of this application usually has the characteristics of simple and efficient, full-duplex communication, and flexible clock polarity and phase setting, while the SMI interface shows its advantages in specific network management and data interaction scenarios. It can realize convenient device configuration and status monitoring in LAN management applications. Based on the accurate grasp of the characteristics of the two and the hardware connection requirements between them, a series of rigorous measures are taken to ensure electrical compatibility and signal integrity; in terms of hardware connection, electrical specifications are strictly followed, suitable cables and connectors are selected, and reasonable impedance matching design is performed on signal lines to prevent signal reflection and attenuation. At the same time, the power supply line is effectively filtered and stabilized to eliminate In addition to the interference of power supply noise on signal transmission, a solid physical foundation is laid for the stable transmission of data between the two interfaces. Inside the FPGA, the SPI interface controller and the SMI interface controller are constructed. The SPI interface controller accurately generates the clock signal, chip select signal, and data input and output signals required by the SPI according to the communication protocol standard of the SPI interface, and monitors the state changes of these signals in real time. Through precise control of the clock signal, it ensures that the data is transmitted at the correct timing. In addition, during the data transmission process, it can promptly detect abnormal fluctuations or error states of the signal, jitter of the clock signal, and glitches on the data line, and take corresponding error correction or retransmission mechanisms.

[0050] In step S3, we first analyze the SPI and SMI interface characteristics, protocols, and timing parameters. In the process of creating a project with professional development tools, we plan the allocation of FPGA internal logic resources to adapt to the interface logic design, data processing volume, and pin settings. We consider signal integrity factors, determine the pin electrical standards and drive strength, write code based on HDL, and build a SPI interface controller, SMI interface controller, and connection and functional modules.

[0051] The logical resource allocation calculation formula is:

[0052] B=C1×D SPI ×E SPI +C2×D SMI ×E SMI

[0053] Where B is the calculated value of logic resource allocation, C1 and C2 are adjustment coefficients determined based on experience and FPGA architecture, and D SPI With D SMI is the interface logic complexity index, E SPI With E SMIis the correlation coefficient of data processing volume; the formula of pin electrical standard and driving strength is: S=g1(h, m, j), O=g2(h, m, j), where h is signal frequency, m is transmission distance, j is line width, S is pin driving strength, O is electrical standard, g1 and g2 are expressed as a complex functional relationship based on signal integrity theory and practical experience. When the signal frequency is high, the transmission distance is long and the line width is narrow, high driving strength S and high-frequency electrical standard O are selected.

[0054] The reasonable logical resource allocation of this application helps to optimize system performance. When each interface can obtain appropriate logical resources, the delay of data processing and transmission can be effectively controlled. Allocating sufficient logical resources to the SMI interface with a large data processing volume can avoid data congestion at the interface and speed up data processing and forwarding, thereby improving the data transmission efficiency of the entire system.

[0055] In step S4, when the SPI interface has data input, the FPGA receives and caches the data, generates an adaptation clock signal according to the timing requirements of the SMI interface, performs format conversion, and then transmits the data to the SMI interface according to its protocol specifications; the format conversion method uses binary complement method for conversion, and converts the data bit by bit according to the conversion rules between Gray code and binary complement.

[0056] In the present application, when the SPI interface has data input, the FPGA quickly receives the data from the SPI interface with its powerful high-speed data processing capability. At the moment of receiving the data, the cache unit inside the FPGA is immediately started to temporarily store the data to ensure the integrity and stability of the data and avoid data loss or confusion due to differences in data transmission rates or other external interference. The FPGA begins to carefully generate an adaptive clock signal based on the timing requirements of the SMI interface. This process requires an in-depth analysis of the timing characteristics of the SMI interface, including the key parameters of the clock frequency, phase, and duty cycle. The FPGA uses the internal precision clock management module to strictly follow the timing specifications of the SMI interface and accurately generate a clock signal that perfectly matches it, thereby laying a solid timing foundation for subsequent data transmission.

[0057] In step S5, the misalignment detection is performed by pre-blocking the data to determine the size of the transmitted data. If the data volume is large, the data is divided into blocks of fixed size. For each data block, a hash value is calculated using a hash algorithm. If the data is not blocked, the hash value of the entire data is calculated and the obtained hash value is stored. The stored hash value is verified, compared and judged. When a hash value mismatch is detected, the data is erroneous.

[0058] This application can decompose the hash calculation task of large-scale data into multiple relatively small and parallelizable subtasks by pre-judging the size of the data and processing it in blocks. This greatly improves the efficiency of hash calculation and reduces the overall calculation time. Especially when processing massive data transmission, it can quickly complete data integrity verification without affecting the real-time data processing performance of the system.

[0059] In step S6, when the data reaches the target device through the transmission channel, the target device generates a transmission status signal based on its own data reception and processing status, and transmits it back to the sending end. After receiving this transmission status signal, the sending end performs a data release link. If the transmission signal is complete and accurate, the sending end triggers a data release mechanism, and the sending end releases the cache area originally used to temporarily store the batch of data to make room for subsequent new data transmission;

[0060] If the transmission status signal indicates that the data has a correctable error, the error correction program is started, and the Hamming code error correction technology is used. The sender locates the erroneous bit in the data according to the received error information and the check rule of the Hamming code, and automatically corrects it. By analyzing and calculating the Hamming code check bit contained in the data and comparing it with the received error status information, the position of the error bit is determined, the error bit is flipped, and the correctness of the data is restored;

[0061] When the transmission status signal indicates that the data is erroneous and cannot be repaired by the error correction mechanism, the sender generates a detailed error report.

[0062] When the transmission signal is complete and accurate, the data release mechanism is triggered in time to quickly clean up the cache area used to temporarily store data. This allows cache resources to be quickly recovered and reused, improving the cache turnover rate and avoiding delays or even failures in subsequent new data transmission due to lack of cache space. In a network monitoring system with large data flow and continuous transmission, rapid release of the cache can ensure that a steady stream of monitoring data can be smoothly temporarily stored and processed, maintaining efficient operation of the system.

[0063] An SMI transparent transmission device based on an SPI interface comprises an SPI interface, an SMI interface, a data cache memory, an FPGA core processor, an error detector and a feedback center; the SPI interface comprises a four-wire connection port for docking with a device conforming to the SPI protocol, and the SMI interface is connected to the SMI device.

[0064] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions only describe the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention, and these changes and improvements fall within the scope of the present invention claimed.

Claims

1. A SMI transparent transmission method based on SPI interface, characterized in that: The transparent transmission steps are: S1, SPI interface initialization, evaluate the overall system performance and the electrical characteristics of the connected external devices, determine the clock frequency parameters of the SPI interface, and initialize the SPI interface; S2, using FPGA to directly connect the SPI interface and the SMI interface to establish a data transmission channel between the two; S3, configure the FPGA, analyze the characteristics, protocols and timing parameters of the SPI and SMI interfaces, create a project based on the development tool, plan logic resources and pin settings, write code in HDL, and design connection and control logic; S4, when there is data input to the SPI interface, the FPGA directly transmits the data to the SMI interface according to the timing requirements of the SMI interface; When the SMI interface has data input, the FPGA also directly transmits the data to the SPI interface according to the timing requirements of the SPI interface, performing transparent transmission from the SPI interface to the SMI interface; S5, Error detection, based on hash algorithm data integrity verification, verifies the accuracy of transmitted data from multiple dimensions; S6, status feedback processing, receiving the transmission status signal of the target device, and performing data release, error correction and error reporting processing according to the status.

2. A SMI transparent transmission method based on SPI interface according to claim 1, characterized in that: In step S1, the overall performance is evaluated by analyzing the data transmission rate, counting the data generation frequency, data byte length and data urgency of different types of sensors, and determining the minimum data transmission rate required for the system to maintain normal and efficient operation per unit time through calculation, and estimating the maximum data transmission demand under the system peak load; the electrical characteristics of external devices are evaluated by obtaining the technical specifications of external devices through big data, obtaining the maximum supported SPI clock frequency, and determining the SPI data bit width format supported by the external device.

3. A SMI transparent transmission method based on SPI interface according to claim 2, characterized in that, The transmission rate analysis formula is: Where n is the number of sensors, F i is the frequency of sensor data generated by the i-th type, L i is the byte length of the data generated by the i-th type sensor each time, K i is the urgency weight coefficient of the i-th type of sensor data, and R is the calculated transmission rate; The formula for estimating the maximum data transmission under system peak load conditions is: A = αR, where A is the calculated maximum download transmission demand value, α is the peak load factor estimated based on historical data and experience, and R is the calculated transmission rate.

4. A SMI transparent transmission method based on SPI interface according to claim 1, characterized in that: In step S2, based on the characteristics of the SPI interface and the SMI interface and their hardware connections, electrical compatibility and signal integrity are ensured. Inside the FPGA, an SPI interface controller and an SMI interface controller are constructed respectively. The SPI interface controller generates the signals required by the SPI and monitors its status. The SMI interface controller parses the SMI protocol to realize data transmission and reception and control signal processing.

5. A SMI transparent transmission method based on SPI interface according to claim 1, characterized in that: In step S3, we first analyze the SPI and SMI interface characteristics, protocols, and timing parameters. In the process of creating a project with professional development tools, we plan the allocation of FPGA internal logic resources to adapt to the interface logic design, data processing volume, and pin settings. We consider signal integrity factors, determine the pin electrical standards and drive strength, write code based on HDL, and build a SPI interface controller, SMI interface controller, and connection and functional modules.

6. A SMI transparent transmission method based on SPI interface according to claim 5, characterized in that: The logical resource allocation calculation formula is: B=C1×D SPI ×E SPI +C2×D SMI ×E SMI Where B is the calculated value of logic resource allocation, C1 and C2 are adjustment coefficients determined based on experience and FPGA architecture, and D SPI With D SMI is the interface logic complexity index, E SPI With E SMI is the correlation coefficient of data processing volume; the formula of pin electrical standard and driving strength is: S=g1(h, m, j), O=g2(h, m, j), where h is signal frequency, m is transmission distance, j is line width, S is pin driving strength, O is electrical standard, g1 and g2 are expressed as a complex functional relationship based on signal integrity theory and practical experience. When the signal frequency is high, the transmission distance is long and the line width is narrow, high driving strength S and high-frequency electrical standard O are selected.

7. A SMI transparent transmission method based on SPI interface according to claim 1, characterized in that: In step S4, when the SPI interface has data input, the FPGA receives and caches the data, generates an adaptation clock signal according to the timing requirements of the SMI interface, performs format conversion, and then transmits the data to the SMI interface according to its protocol specifications; the format conversion method uses binary complement method for conversion, and converts the data bit by bit according to the conversion rules between Gray code and binary complement.

8. The SMI transparent transmission method based on the SPI interface according to claim 1, characterized in that: In step S5, the misalignment detection is performed by pre-blocking the data to determine the size of the transmitted data. If the data volume is large, the data is divided into blocks of fixed size. For each data block, a hash value is calculated using a hash algorithm. If the data is not blocked, the hash value of the entire data is calculated and the obtained hash value is stored. The stored hash value is verified, compared and judged. When a hash value mismatch is detected, the data is erroneous.

9. The SMI transparent transmission method based on the SPI interface according to claim 1, characterized in that: In step S6, when the data reaches the target device through the transmission channel, the target device generates a transmission status signal based on its own data reception and processing status, and transmits it back to the sending end. After receiving this transmission status signal, the sending end performs a data release link. If the transmission signal is complete and accurate, the sending end triggers a data release mechanism, and the sending end releases the cache area originally used to temporarily store the batch of data to make room for subsequent new data transmission; If the transmission status signal indicates that the data has a correctable error, the error correction program is started, and the Hamming code error correction technology is used. The sender locates the erroneous bit in the data according to the received error information and the check rule of the Hamming code, and automatically corrects it. By analyzing and calculating the Hamming code check bit contained in the data and comparing it with the received error status information, the position of the error bit is determined, the error bit is flipped, and the correctness of the data is restored; When the transmission status signal indicates that the data is erroneous and cannot be repaired by the error correction mechanism, the sender generates a detailed error report.

10. An SMI transparent transmission device based on an SPI interface, applied to the SMI transparent transmission method based on an SPI interface according to any one of claims 1 to 9, characterized in that: The transparent transmission device includes an SPI interface, an SMI interface, a data cache memory, an FPGA core processor, an error detector and a feedback center; the SPI interface includes a four-wire connection port for docking with a device that complies with the SPI protocol, and the SMI interface is connected to an SMI device.

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