Point-to-point access verification method and device, electronic equipment and medium

Abstract

The invention relates to a point-to-point access verification method and device, electronic equipment and a medium. The method comprises the steps of obtaining configuration information of a to-be-verified module; writing the configuration information of the to-be-verified module into a verification document, and storing the verification document as a JSON (JavaScript Object Notation) file; the verification document comprises at least one verification test item; each verification test item comprises a plurality of verification test paths; the JSON file is analyzed, and configuration information of the module to be verified is extracted; generating a plurality of universal verification methodology UVM components and UVM excitation files according to the configuration information based on a preset configuration script; establishing a script based on a UVM environment, and integrating the UVM component and the UVM excitation file to a UVM verification platform; in response to a target verification test command, performing test verification on a plurality of to-be-tested paths of a target verification test item on the UVM verification platform; the number of the target verification test items is greater than or equal to 1.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit verification, and in particular to a point-to-point path verification method, device, electronic equipment and medium. Background Art

[0002] With the rapid development of digital integrated circuits, chip functions are becoming increasingly complex, and the importance of chip verification in the chip design cycle is becoming more and more prominent. In order to ensure the functional correctness and performance of the chip, the comprehensive verification of the internal paths and interfaces of the chip must be completed in a short time. This requires not only efficient verification methods and technologies, but also advanced tools and automated processes to improve verification efficiency, and has high requirements for the automation and reusability of the verification environment.

[0003] In the related art, a test vector is manually written for the signal interface of the module to be verified, and the response of the module to be verified is checked to determine whether the interface path is unobstructed. This method has low reusability and low verification efficiency, resulting in a long verification cycle.

[0004] Therefore, how to improve verification efficiency to avoid a large amount of repetitive verification work caused by duplication of peripheral functions is an issue that needs to be solved urgently. Summary of the invention

[0005] In order to solve the above technical problems, the present disclosure provides a point-to-point path verification method, device, electronic device and medium.

[0006] In a first aspect, the present disclosure provides a point-to-point path verification method, comprising:

[0007] Get the configuration information of the module to be verified;

[0008] Writing the configuration information of the module to be verified into a verification document, and saving the verification document as a JSON file; the verification document includes at least one verification test item; each verification test item includes multiple verification test paths;

[0009] Parse the JSON file to extract the configuration information of the module to be verified;

[0010] Based on a preset configuration script, and according to the configuration information, a plurality of universal verification methodology UVM components and UVM stimulus files are generated;

[0011] Building a script based on the UVM environment, integrating the UVM component and the UVM stimulus file into the UVM verification platform;

[0012] In response to a target verification test command, multiple to-be-tested paths of a target verification test item are tested and verified on the UVM verification platform; the number of the target verification test items is greater than or equal to 1.

[0013] As an optional implementation of the embodiment of the present disclosure, the configuration information includes: a verification module name, a verification test item name, a source signal, a terminal signal, a peripheral base address, a peripheral offset address, configuration data, and a reference clock source.

[0014] As an optional implementation of the embodiment of the present disclosure, based on the preset configuration script, multiple universal verification methodology UVM components and UVM stimulus files are generated according to the configuration information, including:

[0015] Input the configuration information into the configuration script to generate a plurality of UVM components and UVM stimulus files with the configuration information;

[0016] Wherein, the UVM component includes: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM component to perform test verification.

[0017] As an optional implementation of the embodiment of the present disclosure, in response to the target verification test command, the UVM verification platform tests and verifies multiple to-be-tested paths of the target verification test item, including:

[0018] The role of the monitor is to collect input and output data of the device under test;

[0019] In response to the target verification test command, determining at least one path to be tested;

[0020] Acquiring terminal signals of each path to be tested through the monitor component;

[0021] Acquire source end signals of each path to be tested through the reference model component;

[0022] Based on the scoreboard component detecting the source end signal and the terminal end signal of each to-be-tested channel, it is determined whether each to-be-tested channel is successfully verified.

[0023] As an optional implementation of the embodiment of the present disclosure, the step of detecting the source end signal and the terminal end signal of each to-be-tested path based on the scoreboard component to determine whether each to-be-tested path is successfully verified includes:

[0024] If the source end signal of the target path to be tested is consistent with the terminal signal of the target path to be tested, it is determined that the verification of the target path to be tested is successful;

[0025] If the source end signal of the target path to be tested is inconsistent with the terminal end signal of the target path to be tested, it is determined that the verification of the target path to be tested fails.

[0026] In a second aspect, an embodiment of the present disclosure provides a point-to-point path verification device, including:

[0027] An acquisition module is used to obtain configuration information of the module to be verified;

[0028] A configuration module, used to write the configuration information of the module to be verified into a verification document, and save the verification document as a JSON file; the verification document includes at least one verification test item; each verification test item includes multiple verification test paths;

[0029] A parsing module, used to parse the JSON file and extract the configuration information of the module to be verified;

[0030] A generation module is used to generate a plurality of universal verification methodology UVM components and UVM stimulus files based on a preset configuration script and according to the configuration information;

[0031] An integration module is used to build a script based on the UVM environment, and integrate the UVM component and the UVM stimulus file into the UVM verification platform;

[0032] The verification module is used to test and verify multiple to-be-tested paths of the target verification test items on the UVM verification platform in response to the target verification test command; the number of the target verification test items is greater than or equal to 1.

[0033] As an optional implementation of the embodiment of the present disclosure, the configuration information includes: a verification module name, a verification test item name, a source signal, a terminal signal, a peripheral base address, a peripheral offset address, configuration data, and a reference clock source.

[0034] As an optional implementation of the embodiment of the present disclosure, the generating module is specifically used for:

[0035] Input the configuration information into the configuration script to generate a plurality of UVM components and UVM stimulus files with the configuration information;

[0036] Wherein, the UVM component includes: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM component to perform test verification.

[0037] As an optional implementation of the embodiment of the present disclosure, the verification module includes:

[0038] A determination unit, configured to determine at least one path to be tested in response to a target verification test command;

[0039] A first acquisition unit, used for acquiring terminal signals of each to-be-tested channel through the monitor component;

[0040] A second acquisition unit, used for acquiring source end signals of each path to be tested through the reference model component;

[0041] The detection unit is used to detect the source end signal and the terminal end signal of each channel to be tested based on the scoreboard component to determine whether each channel to be tested is successfully verified.

[0042] As an optional implementation of the embodiment of the present disclosure, the detection unit is specifically used to:

[0043] If the source end signal of the target path to be tested is consistent with the terminal signal of the target path to be tested, it is determined that the verification of the target path to be tested is successful;

[0044] If the source end signal of the target path to be tested is inconsistent with the terminal end signal of the target path to be tested, it is determined that the verification of the target path to be tested fails.

[0045] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising: a memory and a processor; the memory stores a computer program, and when the processor executes the computer program, it implements the point-to-point path verification method described in the first aspect or any implementation of the first aspect.

[0046] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the point-to-point path verification method as described in any implementation of the first aspect is implemented.

[0047] The technical solution provided by the embodiment of the present disclosure has the following advantages compared with the prior art: obtaining the configuration information of the module to be verified, writing the configuration information of the module to be verified into the verification document, and saving the verification document as a JSON file, parsing the JSON file, extracting the configuration information of the module to be verified, based on the preset configuration script, generating multiple universal verification methodology UVM components and UVM incentive files according to the configuration information, building a script based on the UVM environment, integrating the UVM components and the UVM incentive files into the UVM verification platform, and responding to the target verification test command, testing and verifying multiple paths to be tested of the target verification test items on the UVM verification platform. Since the verification document includes at least one verification test item, each verification test item includes multiple verification test paths, and the number of target verification test items is greater than or equal to 1, multiple paths to be tested of multiple target verification test items can be tested and verified on the UVM verification platform at the same time, thereby improving the verification efficiency and avoiding a large number of repetitive verifications caused by the repetition of peripheral functions. In addition, since the configuration parameters of the verification document are extracted by the script, each UVM component with configuration information is automatically generated without manual configuration, and the mistakes caused by manual configuration information can be avoided, thereby improving the verification accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0050] Figure 1 It is a flowchart of a point-to-point path verification method provided by an embodiment of the present disclosure;

[0051] Figure 2 It is a schematic diagram of a UVM verification platform architecture provided by an embodiment of the present disclosure;

[0052] Figure 3 is a schematic diagram of the structure of a point-to-point path verification device provided by an embodiment of the present disclosure;

[0053] Figure 4 It is a structural schematic diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0055] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0056] Relational terms such as “first” and “second” in the description and claims of the present disclosure are merely used to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0057] In the embodiments of the present disclosure, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present disclosure should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way. In addition, in the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "multiple" refers to two or more.

[0058] Point-to-point path verification usually involves verifying whether the data transmission between two modules is correct and complete, for example, whether the data transmission between a first peripheral and a second peripheral is correct and complete, wherein the first peripheral may be a USART module and the second peripheral may be a GPIO module. It should be noted that the first peripheral and the second peripheral may also be other communication modules or other modules with specific functions, which are not specifically limited here.

[0059] In some embodiments, Figure 1 As shown, a point-to-point path verification method is provided, comprising the following steps S11-S16:

[0060] S11. Obtain configuration information of the module to be verified.

[0061] Specifically, the configuration information of the module to be verified is obtained according to the test plan.

[0062] Optionally, the configuration information includes: verification module name, verification test item name, source signal, terminal signal, peripheral base address, peripheral offset address, configuration data and reference clock source.

[0063] Specifically, the verification module name is used to describe each module to be verified; the verification test item name is used to describe each test item to be verified; the source signal refers to the original signal sent from the signal source, and the source signal carries the information to be transmitted; the terminal signal refers to the place where the signal is received, which is used to receive the source signal. The base address of the register refers to the starting address of the memory mapping device or the register mapping device in the physical address space, which is the reference point of all register offset addresses. The offset address of the register is an offset relative to the base address, which is used to access a specific register or a register in a memory mapping device. When a specific register needs to be accessed, the base address and the offset address need to be added to generate the physical address of the register to be accessed, and then the read or write operation is performed through the physical address. The peripheral base address is determined based on the verification module name; the peripheral offset address can be set according to the range of the peripheral base address and the register, and the reference clock source is used to ensure that the UVM component works synchronously.

[0064] Access memory-mapped peripheral registers, extract base addresses and offset addresses of peripheral registers, and generate UVM stimulus files.

[0065] The configuration data includes: turning on clock enable, peripheral communication configuration, and IO multiplexing configuration.

[0066] Exemplarily, the clock enable is turned on to allow the peripheral to start working. For example, to enable the clock of a peripheral, the corresponding register bit of RCC needs to be set. The communication configuration of the peripheral usually involves GPIO pin function configuration, initialization of the peripheral (for example, setting the operating mode of the peripheral, clock frequency, etc.), configuration of the communication rate, etc. For example, for serial communications such as UART, it is necessary to configure the baud rate, data bit, stop bit and check bit. For the multi-function multiplexing of the IO interface, multiple test stimuli are constructed to test the different functions of the IO interface to be tested, and each test stimulus corresponds to the state value of a register. The test case loop sets different register state parameters and executes the corresponding test stimulus to implement the verification process of all multiplexed functions of the chip IO interface.

[0067] S12. Write the configuration information of the module to be verified into a verification document, and save the verification document as a JSON file.

[0068] The verification document includes at least one verification test item; each verification test item includes multiple verification test paths.

[0069] Specifically, the verification document contains at least one verification test item, each verification test item includes multiple verification test paths, and after the configuration information of the module to be verified is written into the verification document, the verification document is saved as a JSON file. JSON (JavaScript Object Notation) is a lightweight data exchange format that is easy to read and write, and is also easy to machine parse and generate. It is based on a subset of JavaScript, but JSON is language independent, and many programming languages ​​support data exchange in JSON format.

[0070] For example, assume that the verification test items are USART? _TX? _GPIO? _, where ? represents the number, i.e., 0 to n. For example, tx0 of USART corresponds to PB0 of GPIO; rx0 of USART1 corresponds to PB1 of GPIO; tx1 of USART corresponds to PB2 of GPIO; rx1 of USART1 corresponds to PD0 of GPIO; tx2 of USART corresponds to PD1 of GPIO; rx2 of USART1 corresponds to PD2 of GPIO; the difference between these verification test items is only that the ports are different, but the verification methods are the same. For example, if tx0 is toggled, it is detected that PB0 is also toggled.

[0071] S13. Parse the JSON file to extract configuration information of the module to be verified.

[0072] Specifically, a python script is used to parse the JSON file and extract the configuration information of the module to be verified, that is, the verification module name, the verification test item name, the source signal, the terminal signal, the peripheral base address, the peripheral offset address, the configuration data, and the reference clock source.

[0073] S14, based on a preset configuration script, generating multiple universal verification methodology UVM components and UVM stimulus files according to the configuration information.

[0074] Specifically, based on a pre-written configuration script and the configuration information, a plurality of UVM components and UVM stimulus files with the configuration information are generated.

[0075] Exemplarily, after extracting the configuration information of each verification test item in the verification document, an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component and a test component with the configuration information are generated.

[0076] In some embodiments, the above step S14 (generating multiple universal verification methodology UVM components and UVM stimulus files based on the preset configuration script and the configuration information) can be implemented as follows:

[0077] The configuration information is input into the configuration script to generate a plurality of UVM components and UVM stimulus files with the configuration information.

[0078] Wherein, the UVM component includes: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM component to perform test verification.

[0079] Specifically, UVM components include: driver components, monitor components, reference model components, sequencer components, agent components, scoreboard components, environment components, test components, etc. These components together constitute the structure of the UVM verification platform, making the design verification process more efficient and systematic. Each component has its specific responsibilities and functions. Through the collaborative work of these components, comprehensive verification of integrated circuit design can be achieved.

[0080] The driver component is responsible for obtaining transactions from the sequencer component and driving them to the port of the device under test. The driver component is a parameterized class, and the type of the parameter needs to be declared when defining it.

[0081] The monitor component has the opposite function to the driver component. It is used to receive data from the port of the device under test, convert the received data into transaction-level sequence items, and then send them to the scoreboard for comparison.

[0082] The reference model component is used to simulate the functions of the device under test and send the data generated by the reference model to the scoreboard component for comparison with the data collected by the monitor component to verify the correctness of the device under test.

[0083] The sequencer component, located between the driver component and the monitor component, is used to manage and coordinate the flow of transactions.

[0084] Agent components, typically including one or more drivers, monitors, and sequencers, are used to abstract and encapsulate test behaviors related to a specific protocol or interface.

[0085] The Scoreboard component collects and compares data from the Monitor with the expected results from the Sequencer component to verify that the device under test is behaving correctly.

[0086] The environment component, as a container, holds multiple agent components and other components to implement different configurations of the test.

[0087] The test component is a user-defined top-level structure that inherits from uvm_test. The goals of test include providing different configurations, environment structure configurations, test mode configurations, etc., and then creating the environment, instantiating the test sequence, and mounting the target sequencer component sequencer.

[0088] S15, build a script based on the UVM environment, and integrate the UVM component and the UVM stimulus file into the UVM verification platform.

[0089] Specifically, a script is built based on the UVM environment, and UVM components and UVM stimulus files are integrated into the UVM verification platform.

[0090] S16, in response to the target verification test command, testing and verifying multiple to-be-tested paths of the target verification test item on the UVM verification platform.

[0091] The number of the target verification test items is greater than or equal to 1. The target verification test command is used to verify whether multiple to-be-tested paths of the target verification test items transmit data correctly.

[0092] Specifically, in response to a target verification test command input by a user, a plurality of to-be-tested paths of a target verification test item are tested and verified on a UVM verification platform.

[0093] In some embodiments, the above step S16 (in response to the target verification test command, testing and verifying multiple to-be-tested paths of the target verification test item on the UVM verification platform) can be implemented as follows:

[0094] A. In response to a target verification test command, determining at least one path to be tested.

[0095] B. Acquire the terminal signals of each path to be tested through the monitor component.

[0096] C. Acquire the source end signal of each path to be tested through the reference model component.

[0097] D. Based on the scoreboard component, the source end signal and the terminal end signal of each channel to be tested are detected to determine whether each channel to be tested is successfully verified.

[0098] The above step D can be implemented in the following ways:

[0099] (1) If the source end signal of the target path to be tested is consistent with the terminal end signal of the target path to be tested, it is determined that the verification of the target path to be tested is successful.

[0100] (2) If the source end signal of the target path to be tested is inconsistent with the terminal end signal of the target path to be tested, it is determined that the verification of the target path to be tested has failed.

[0101] Specifically, in response to a target verification test command, at least one channel to be tested is determined, the terminal signal of each channel to be tested is obtained through the monitor component, and the source signal of each channel to be tested is obtained through the reference model component. After the monitor component obtains the terminal signal of each channel to be tested, the terminal signal of each channel to be tested is sent to the scoreboard component. After the reference model component obtains the source signal of each channel to be tested, the source signal of each channel to be tested is sent to the scoreboard component. The source signal and terminal signal of each channel to be tested are detected through the scoreboard component. If the source signal of the target channel to be tested is consistent with the terminal signal of the target channel to be tested, it is determined that the verification of the target channel to be tested is successful. If the source signal of the target channel to be tested is inconsistent with the terminal signal of the target channel to be tested, it is determined that the verification of the target channel to be tested has failed.

[0102] For example, refer to Figure 2 As shown, Figure 2 It is a schematic diagram of the UVM verification platform architecture. Among them, test_cfg is a verification document, which contains configuration information, and the C stimulus file is the UVM stimulus file mentioned above, which stores this information in flash. The module to be verified is the SOC design part to be tested, wherein the source signal of the path to be tested is the interface signal corresponding to the USART module, and the terminal signal of the path to be tested is the interface signal corresponding to the GPIO module. The environment component includes an agent component, a reference model component, a scoreboard component, etc. The agent component includes a driver component and a monitor component. It should be noted that the agent component also includes a sequencer component. Assuming that the source signal of the target path to be tested obtained by the reference model component is the data corresponding to the TX0 interface of the USART module, and the terminal signal of the target path to be tested obtained by the monitor component is the data corresponding to the IO0 interface of the GPIO module, if the data corresponding to the TX0 interface of the USART module is consistent with the data corresponding to the IO0 interface of the GPIO module, then it is determined that the verification of the target path to be tested is successful; if the data corresponding to the TX0 interface of the USART module is inconsistent with the data corresponding to the IO0 interface of the GPIO module, then it is determined that the verification of the target path to be tested fails.

[0103] The point-to-point path verification method provided by the present disclosure obtains the configuration information of the module to be verified, writes the configuration information of the module to be verified into a verification document, and saves the verification document as a JSON file, parses the JSON file, extracts the configuration information of the module to be verified, generates multiple general verification methodology UVM components and UVM incentive files based on a preset configuration script, builds a script based on a UVM environment, integrates the UVM components and the UVM incentive files into a UVM verification platform, and responds to a target verification test command, and tests and verifies multiple paths to be tested of target verification test items on the UVM verification platform. Since the verification document includes at least one verification test item, each verification test item includes multiple verification test paths, and the number of target verification test items is greater than or equal to 1, multiple paths to be tested of multiple target verification test items can be tested and verified on the UVM verification platform at the same time, thereby improving verification efficiency and avoiding a large number of repetitive verifications caused by repeated peripheral functions. Again, since the configuration parameters of the verification document are extracted by a script, each UVM component with configuration information is automatically generated, and manual configuration is not required, and mistakes caused by manual configuration information can be avoided, thereby improving verification accuracy.

[0104] In some embodiments, reference Figure 3 As shown, a point-to-point path verification device 300 is provided, comprising:

[0105] The acquisition module 310 is used to acquire the configuration information of the module to be verified;

[0106] Configuration module 320, used to write the configuration information of the module to be verified into a verification document, and save the verification document as a JSON file; the verification document includes at least one verification test item; each verification test item includes multiple verification test paths;

[0107] A parsing module 330, used to parse the JSON file and extract the configuration information of the module to be verified;

[0108] A generating module 340 is used to generate a plurality of universal verification methodology UVM components and UVM stimulus files based on a preset configuration script and according to the configuration information;

[0109] An integration module 350 is used to build a script based on a UVM environment to integrate the UVM component and the UVM stimulus file into a UVM verification platform;

[0110] The verification module 360 ​​is used to test and verify multiple to-be-tested paths of the target verification test items on the UVM verification platform in response to the target verification test command; the number of the target verification test items is greater than or equal to 1.

[0111] As an optional implementation of the embodiment of the present disclosure, the configuration information includes: a verification module name, a verification test item name, a source signal, a terminal signal, a peripheral base address, a peripheral offset address, configuration data, and a reference clock source.

[0112] As an optional implementation of the embodiment of the present disclosure, the generating module is specifically used for:

[0113] Input the configuration information into the configuration script to generate a plurality of UVM components and UVM stimulus files with the configuration information;

[0114] Wherein, the UVM component includes: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM component to perform test verification.

[0115] As an optional implementation of the embodiment of the present disclosure, the verification module includes:

[0116] A determination unit, configured to determine at least one path to be tested in response to a target verification test command;

[0117] A first acquisition unit, used for acquiring terminal signals of each to-be-tested channel through the monitor component;

[0118] A second acquisition unit, used for acquiring source end signals of each path to be tested through the reference model component;

[0119] The detection unit is used to detect the source end signal and the terminal end signal of each channel to be tested based on the scoreboard component to determine whether each channel to be tested is successfully verified.

[0120] As an optional implementation of the embodiment of the present disclosure, the detection unit is specifically used to:

[0121] If the source end signal of the target path to be tested is consistent with the terminal signal of the target path to be tested, it is determined that the verification of the target path to be tested is successful;

[0122] If the source end signal of the target path to be tested is inconsistent with the terminal end signal of the target path to be tested, it is determined that the verification of the target path to be tested fails.

[0123] The point-to-point path verification device provided by the present disclosure obtains the configuration information of the module to be verified, writes the configuration information of the module to be verified into a verification document, and saves the verification document as a JSON file, parses the JSON file, extracts the configuration information of the module to be verified, generates multiple universal verification methodology UVM components and UVM incentive files based on the preset configuration script and the configuration information, builds a script based on the UVM environment, integrates the UVM components and the UVM incentive files into the UVM verification platform, and responds to the target verification test command, and tests and verifies multiple paths to be tested of the target verification test items on the UVM verification platform. Since the verification document includes at least one verification test item, each verification test item includes multiple verification test paths, and the number of target verification test items is greater than or equal to 1, the UVM verification platform can simultaneously test and verify multiple paths to be tested of multiple target verification test items, improve the verification efficiency, and avoid the repetition of peripheral functions to bring a large number of repetitive verifications. In addition, since the configuration parameters of the verification document are extracted by the script, each UVM component with configuration information is automatically generated, and no manual configuration is required, the mistakes caused by manual configuration information can be avoided, and the verification accuracy is improved.

[0124] The specific definition of the point-to-point path verification device can be found in the definition of the point-to-point path verification method above, which will not be repeated here. Each module in the above-mentioned point-to-point path verification device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor of the electronic device in the form of hardware, or can be stored in the processor of the electronic device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0125] The present disclosure also provides an electronic device, Figure 4 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. Figure 4As shown, the electronic device provided in this embodiment includes: a memory 41 and a processor 42, the memory 41 is used to store a computer program; the processor 42 is used to execute the steps executed in any embodiment of the point-to-point path verification method of the electronic device provided by the above method embodiment when calling the computer program. The electronic device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. When the computer program is executed by the processor, a point-to-point path verification method of an electronic device is implemented. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the housing of the computer device, or an external keyboard, touchpad or mouse.

[0126] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present disclosure, and does not constitute a limitation on the computer device to which the scheme of the present disclosure is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0127] In some embodiments, the point-to-point path verification device provided by the present disclosure can be implemented in the form of a computer program. Figure 4 The computer program composed of various program modules enables the processor to execute the steps of the point-to-point path verification method of various embodiments of the present disclosure described in this specification.

[0128] The embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the point-to-point path verification method of an electronic device provided by the above method embodiment is implemented.

[0129] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0130] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0131] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0132] Computer readable media include permanent and non-permanent, removable and non-removable storage media. Storage media can be implemented by any method or technology to store information, and the information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0133] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0134] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A point-to-point path verification method, characterized in that: The method comprises: Get the configuration information of the module to be verified; Writing the configuration information of the module to be verified into a verification document, and saving the verification document as a JSON file; the verification document includes at least one verification test item; each verification test item includes multiple verification test paths; Parse the JSON file to extract the configuration information of the module to be verified; Based on a preset configuration script, and according to the configuration information, a plurality of universal verification methodology UVM components and UVM stimulus files are generated; Building a script based on the UVM environment, integrating the UVM component and the UVM stimulus file into the UVM verification platform; In response to a target verification test command, multiple to-be-tested paths of a target verification test item are tested and verified on the UVM verification platform; the number of the target verification test items is greater than or equal to 1.

2. The method according to claim 1, characterized in that The configuration information includes: a verification module name, a verification test item name, a source signal, a terminal signal, a peripheral base address, a peripheral offset address, configuration data, and a reference clock source.

3. The method according to claim 2, characterized in that Based on the preset configuration script, according to the configuration information, multiple universal verification methodology UVM components and UVM stimulus files are generated, including: Input the configuration information into the configuration script to generate a plurality of UVM components and UVM stimulus files with the configuration information; Wherein, the UVM component includes: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM component to perform test verification.

4. The method according to claim 3, characterized in that In response to the target verification test command, the UVM verification platform tests and verifies a plurality of paths to be tested of the target verification test item, including: The role of the monitor is to collect input and output data of the device under test; In response to the target verification test command, determining at least one path to be tested; Acquiring terminal signals of each path to be tested through the monitor component; Acquire source end signals of each path to be tested through the reference model component; Based on the scoreboard component detecting the source end signal and the terminal end signal of each to-be-tested channel, it is determined whether each to-be-tested channel is successfully verified.

5. The method according to claim 4, characterized in that The step of detecting source end signals and terminal end signals of each to-be-tested path based on the scoreboard component to determine whether each to-be-tested path is successfully verified includes: If the source end signal of the target path to be tested is consistent with the terminal signal of the target path to be tested, it is determined that the verification of the target path to be tested is successful; If the source end signal of the target path to be tested is inconsistent with the terminal end signal of the target path to be tested, it is determined that the verification of the target path to be tested fails.

6. A point-to-point path verification device, characterized in that: include: An acquisition module is used to obtain configuration information of the module to be verified; A configuration module, used to write the configuration information of the module to be verified into a verification document, and save the verification document as a JSON file; the verification document includes at least one verification test item; each verification test item includes multiple verification test paths; A parsing module, used to parse the JSON file and extract the configuration information of the module to be verified; A generation module is used to generate a plurality of universal verification methodology UVM components and UVM stimulus files based on a preset configuration script and according to the configuration information; An integration module is used to build a script based on the UVM environment, and integrate the UVM component and the UVM stimulus file into the UVM verification platform; The verification module is used to test and verify multiple to-be-tested paths of the target verification test items on the UVM verification platform in response to the target verification test command; the number of the target verification test items is greater than or equal to 1.

7. The device according to claim 6, characterized in that The configuration information includes: a verification module name, a verification test item name, a source signal, a terminal signal, a peripheral base address, a peripheral offset address, configuration data, and a reference clock source.

8. The device according to claim 7, characterized in that Based on the preset configuration script, according to the configuration information, multiple universal verification methodology UVM components and UVM stimulus files are generated, including: Input the configuration information into the configuration script to generate a plurality of UVM components and UVM stimulus files with the configuration information; Wherein, the UVM component includes: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM component to perform test verification.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the point-to-point path verification method according to any one of claims 1 to 5 is implemented.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the point-to-point path verification method described in any one of claims 1 to 5 is implemented.

Images