FPGA chip verification method and device, electronic equipment and storage medium

Abstract

The invention provides an FPGA chip verification method and device, electronic equipment and a storage medium, and belongs to the technical field of integrated circuits. The method comprises the steps of obtaining a test case of the FPGA chip, and obtaining a bit stream file and a comprehensive netlist file based on the test case; based on the bit stream file, performing bit stream simulation on the test case to obtain a bit stream simulation result; based on the comprehensive netlist file, performing function simulation on the test case to obtain a function simulation result; under the condition that the bit stream simulation result is inconsistent with the function simulation result, downloading the bit stream file to the FPGA chip so as to perform board-level test on the test case to obtain a board-level test result; and obtaining a test verification result according to the board-level test result and the bit stream simulation result. Thus, bit stream simulation, case logic function simulation and board level test are combined to perform a more complete test on the FPGA chip, the integrity and effectiveness of the FPGA chip test are improved, and then hidden problems of the chip can be found.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to an FPGA chip verification method, device, electronic equipment and storage medium. Background Art

[0002] The design and manufacture of FPGA chips is a core component of the semiconductor industry. With the continuous advancement of semiconductor technology, the design and manufacture of FPGA chips are becoming increasingly important. In the design and manufacture process of FPGA chips, FPGA chip verification is a key link to ensure that the design can run accurately and efficiently in actual applications.

[0003] It is crucial to verify the correctness of FPGA chip functions. An effective and comprehensive verification method can exhaustively test the logical functions of chip circuits, thereby significantly shortening the development cycle of FPGA chips and helping to discover potential chip circuit problems. However, in the process of related FPGA chip function verification, when the verification deviates, it is difficult to effectively distinguish whether there is a problem with the simulation process or a defect in the hardware logic itself. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide an FPGA chip verification method, device, electronic device and storage medium, which perform more comprehensive testing and verification on the FPGA chip, and effectively determine whether there is a problem with the simulation process or a defect in the hardware logic itself when a problem occurs in the simulation of the FPGA chip.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a method for verifying an FPGA chip, the method comprising:

[0007] Get the bitstream file and integrated netlist file of the test case;

[0008] Based on the bitstream file, performing bitstream simulation on the test case to obtain a bitstream simulation result;

[0009] Based on the comprehensive netlist file, functional simulation is performed on the test case to obtain a functional simulation result;

[0010] In the case where the bitstream simulation result and the functional simulation result are inconsistent, downloading the bitstream file to the FPGA chip to perform board-level testing on the test case to obtain a board-level test result;

[0011] The hardware logic verification result of the test case is obtained according to the board-level test result and the bitstream simulation result.

[0012] In an optional implementation manner, the step of downloading the bitstream file to the FPGA chip to perform board-level testing on the test case to obtain a board-level test result includes:

[0013] Downloading the bitstream file to the FPGA chip so that the FPGA chip adjusts the switch state of each circuit sub-module;

[0014] Inputting an excitation signal to the FPGA chip, and acquiring board-level output data of the FPGA chip after responding to the excitation signal;

[0015] A board-level test result is obtained according to the board-level output data.

[0016] In an optional implementation manner, the step of performing bitstream simulation on the test case based on the bitstream file to obtain a bitstream simulation result includes:

[0017] According to the bit stream file, a circuit assignment file is obtained; wherein the circuit assignment file is a start and stop configuration file of each circuit sub-module of the FPGA chip corresponding to the test case;

[0018] Writing the logic function stimulus file into the circuit assignment file to obtain a bit stream simulation stimulus file;

[0019] The bitstream simulation stimulus file is used as an input signal stimulus, and the complete circuit model netlist file of the FPGA chip is used as a circuit design file, which is input into a simulation tool to obtain a bitstream simulation result output by the simulation tool.

[0020] In an optional implementation, the FPGA chip includes a plurality of circuit sub-modules, and the bitstream file includes a plurality of configuration values ​​corresponding one-to-one to the circuit sub-modules;

[0021] The step of obtaining a circuit assignment file according to the bit stream file comprises:

[0022] Traversing the bitstream file, and taking data with a configuration value of one in the bitstream file as target data;

[0023] For each of the target data, taking the circuit submodule corresponding to the location of the target data as the target submodule;

[0024] The state of each of the target submodules is configured to be open, and the state of each of the remaining circuit submodules is configured to be closed, so as to obtain a circuit assignment file.

[0025] In an optional implementation, the step of performing functional simulation on the test case based on the integrated netlist file to obtain a functional simulation result includes:

[0026] Obtaining a logic function stimulus file and a primitive library file of the test case;

[0027] The logic function stimulus file, the primitive library file and the comprehensive netlist file are used as inputs of functional simulation to obtain functional simulation results.

[0028] In an optional embodiment, the method further comprises:

[0029] When the bit stream simulation result is consistent with the functional simulation result, it is determined that the FPGA chip hardware circuit structure logic corresponding to the test case meets expectations.

[0030] In an optional implementation manner, the step of obtaining the hardware logic verification result of the test case according to the board-level test result and the bitstream simulation result includes:

[0031] According to the board-level test results, a board-level implementation function is obtained;

[0032] According to the bit stream simulation result, a bit stream realization function is obtained;

[0033] Determine whether the board-level implementation function is consistent with the bitstream implementation function;

[0034] If so, it is determined that the FPGA chip hardware circuit structure logic corresponding to the test case meets expectations;

[0035] If not, it is determined that the FPGA chip hardware circuit structure logic corresponding to the test case does not meet expectations.

[0036] In a second aspect, the present invention provides an FPGA chip verification device, including a case acquisition module, a bit stream simulation module, a function simulation module, a board-level test module and;

[0037] The case acquisition module is used to acquire the bitstream file and the comprehensive netlist file of the test case;

[0038] The bitstream simulation module is used to perform bitstream simulation on the test case based on the bitstream file to obtain a bitstream simulation result;

[0039] The functional simulation module is used to perform functional simulation on the test case based on the comprehensive netlist file to obtain a functional simulation result;

[0040] The board-level test module is used to download the bitstream file to the FPGA chip when the bitstream simulation result and the functional simulation result are inconsistent, so as to perform board-level testing on the test case and obtain a board-level test result;

[0041] The verification module is used to obtain the hardware logic verification result of the test case according to the board-level test result and the bit stream simulation result.

[0042] In a third aspect, the present invention provides an electronic device, comprising a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement an FPGA chip verification method as described in any one of the aforementioned embodiments.

[0043] In a fourth aspect, the present invention provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the FPGA chip verification method as described in any one of the aforementioned embodiments.

[0044] The FPGA chip verification method, device, electronic device and storage medium provided by the embodiment of the present invention include: obtaining a test case of the FPGA chip, and obtaining a bitstream file and a comprehensive netlist file based on the test case; performing bitstream simulation on the test case based on the bitstream file to obtain a bitstream simulation result; performing functional simulation on the test case based on the comprehensive netlist file to obtain a functional simulation result; when the bitstream simulation result and the functional simulation result are inconsistent, downloading the bitstream file to the FPGA chip to perform board-level testing on the test case to obtain a board-level test result; and obtaining a test verification result based on the board-level test result and the bitstream simulation result.

[0045] In this way, bitstream simulation, case logic function simulation and board-level testing are combined to perform a more complete test on the FPGA chip, effectively solving the problem of incompleteness of single execution compilation simulation, improving the integrity and effectiveness of FPGA chip testing, and thus being able to discover potential problems with the chip.

[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 A schematic diagram of the system architecture of an FPGA chip verification system provided by an embodiment of the present invention is shown.

[0049] Figure 2A schematic diagram of a module architecture of an electronic device provided by an embodiment of the present invention is shown.

[0050] Figure 3 One of the flow charts of the FPGA chip verification method provided by the embodiment of the present invention is shown.

[0051] Figure 4 Shows Figure 3 Schematic diagram of the process flow of some sub-steps of step 13.

[0052] Figure 5 Shows Figure 4 A flowchart of some sub-steps of step 131 in FIG.

[0053] Figure 6 Shows Figure 3 Schematic diagram of the process of some sub-steps of step 15.

[0054] Figure 7 The second flowchart of the FPGA chip verification method provided by the embodiment of the present invention is shown.

[0055] Figure 8 Shows Figure 3 and Figure 7 Schematic diagram of the process of some sub-steps of step 17.

[0056] Fig. 9 Shows Figure 3 and Figure 7 Schematic diagram of the process of some sub-steps of step 19.

[0057] Fig.10 A schematic diagram of the module architecture of an FPGA chip verification device provided by an embodiment of the present invention is shown.

[0058] Explanation of the accompanying drawings: 10-FPGA chip verification system; 110-verification service equipment; 120-FPGA chip; 20-electronic device; 210-memory; 220-processor; 230-communication module; 30-FPGA chip verification device; 310-case acquisition module; 320-bitstream simulation module; 330-functional simulation module; 340-board-level test module; 350-verification module. DETAILED DESCRIPTION

[0059] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0060] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0061] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0062] The FPGA chip verification method provided by the embodiment of the present invention can be applied to Figure 1 In the FPGA chip verification system 10 shown, the FPGA chip verification system 10 includes a verification service device 110 and a development board, the development board includes an FPGA chip 120 and a communication interface (such as a USB interface, an Ethernet interface, an HDMI interface, etc.), and the verification service device 110 can be connected to the communication interface in a wired or wireless manner to communicate with the FPGA chip 120.

[0063] The verification service device 110 is installed with software tools required for FPGA design and manufacturing, such as synthesis tools, layout tools, routing tools, and simulation functions. The synthesis tools, layout tools, and routing tools may be the same tool, that is, different functions provided for the same software function.

[0064] The FPGA chip 120 is used for performing board-level testing.

[0065] The verification service device 110 is used to implement the FPGA chip verification method provided by the embodiment of the present invention, including: obtaining a test case of the FPGA chip 120, and obtaining a bitstream file and a comprehensive netlist file based on the test case; based on the bitstream file, performing a bitstream simulation on the test case to obtain a bitstream simulation result; based on the comprehensive netlist file, performing a functional simulation on the test case to obtain a functional simulation result; when the bitstream simulation result and the functional simulation result are inconsistent, downloading the bitstream file to the FPGA chip 120 to perform a board-level test on the test case to obtain a board-level test result; and obtaining a test verification result based on the board-level test result and the bitstream simulation result.

[0066] The authentication service device 110 may be, but is not limited to, a personal computer, a laptop computer, a tablet computer, an independent server, a server cluster, etc.

[0067] Please refer to Figure 2 , is a block diagram of an electronic device 20, which may be Figure 1 The verification service device 110 in the FPGA chip verification system 10 is shown. The electronic device 20 includes a memory 210, a processor 220 and a communication module 230. The memory 210, the processor 220 and the communication module 230 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0068] The memory 210 is used to store programs or data and can be, but not limited to, a random access memory, a read-only memory, a programmable read-only memory, an erasable read-only memory, an electrically erasable read-only memory, and the like.

[0069] The processor 220 is used to read / write data or programs stored in the memory 210 and execute corresponding functions. For example, Figure 1 In the FPGA chip verification system 10 shown, the processor 220 of the verification service device 110 executes the computer program stored in the memory 210 to implement the FPGA chip verification method provided by the embodiment of the present invention.

[0070] The communication module 230 is used to establish a communication connection between the electronic device 20 and other communication terminals, and to send and receive data. Figure 1 In the FPGA chip verification system 10 shown, the verification service device 110 is connected to the communication interface on the development board through the communication module 230 to transmit and receive data with the FPGA chip 120 through the communication channel formed by the connection.

[0071] It should be understood that Figure 2The structure shown is only a schematic diagram of the structure of the electronic device 20. The electronic device 20 may also include Figure 2 More or fewer components as shown, or with Figure 2 Different configurations are shown. Figure 2 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0072] In order to improve the problem that when a deviation occurs in the verification process of the relevant FPGA chip 120 function, it is difficult to effectively distinguish whether there is a problem with the simulation process or a defect in the hardware logic itself, the embodiment of the present invention provides an FPGA chip verification method, referring to Figure 3 , including steps 11 to 19. Thus, Figure 1 In the FPGA chip verification system 10 shown in FIG. Figure 2 The structure shown implements steps 11 to 19 when the processor 220 executes the computer program stored in the memory 210.

[0073] Step 11, obtain the test case of the FPGA chip, and obtain the bitstream file and the integrated netlist file based on the test case.

[0074] Step 13: Based on the bitstream file, perform bitstream simulation on the test case to obtain a bitstream simulation result.

[0075] Step 15: Based on the comprehensive netlist file, functional simulation is performed on the test case to obtain functional simulation results.

[0076] Step 17, when the bitstream simulation result and the functional simulation result are inconsistent, the bitstream file is downloaded to the FPGA chip to perform board-level testing on the test case to obtain a board-level test result.

[0077] Step 19, obtaining the test verification result according to the board-level test result and the bitstream simulation result.

[0078] For example, in combination Figure 1 In the FPGA chip verification system 10 shown, the verification service device 110 obtains one or more test cases of the FPGA chip 120 to be tested that are passed in or input by a technician, wherein each test case is an implementation code of at least one function of the FPGA chip 120 to be tested, that is, a circuit design code written in a high-level hardware description language (such as Verilog or VHDL).

[0079] For each test case, the verification service device 110 obtains a bitstream file and a comprehensive netlist file based on the test case. Next, the verification service device 110 uses the simulation function of the simulation tool to perform bitstream simulation on the test case based on the bitstream file to obtain a bitstream simulation result. At the same time, the verification service device 110 uses the simulation function of the simulation tool to perform functional simulation on the test case based on the comprehensive netlist file to obtain a functional simulation result. The verification service device 110 compares the bitstream simulation result with the functional simulation result. If the two are inconsistent, the verification service device 110 opens the communication interface between the development board and the student, and downloads the bitstream file to the FPGA chip 120 on the development board to perform board-level testing on the test case to obtain a board-level test result. Furthermore, the verification service device 110 obtains the test verification result of the test case based on the board-level test result and the bitstream simulation result, that is, obtains the test verification result of a function of the FPGA chip 120.

[0080] Finally, the verification service device 110 combines the test verification results of all test cases of the FPGA chip 120 to be tested to obtain the final test verification result of the FPGA chip 120 .

[0081] In the verification of the related FPGA chip 120, one is to test based on the circuit structure of the chip itself, generate a bitstream file through targeted test cases and burn it into the development board, and use an oscilloscope or the like to determine whether the test result is correct after external input stimulation. The second is to compile the code in the test case, simulate the compiled simulation model file, and determine whether the simulation result is correct by manually analyzing the simulation waveform and the simulation log file.

[0082] In the above two FPGA testing methods, only the design files are compiled, and the chip logic function is manually judged through an oscilloscope, simulation software or other testing equipment to determine whether it is correct, and the testing efficiency is low. In addition, the simulation cannot fully reflect the fuse configuration information of the FPGA chip 120 hardware circuit in the bitstream file. For cases where problems occur in the simulation, no actual board-level test verification is performed, and it is difficult to effectively distinguish whether there is a problem with the simulation process or a defect in the hardware logic itself, resulting in poor accuracy and reliability of the verification results.

[0083] In the FPGA chip verification method provided in the embodiment of the present invention, a comparison is first performed between the bitstream simulation and the functional simulation, and then a board-level test is performed when there is a discrepancy, so as to obtain the final verification test result after comparing the bitstream simulation and the board-level test, that is, the bitstream simulation, the case logic function simulation and the board-level test are combined to perform a more complete test on the FPGA chip 120, which effectively solves the problem of incompleteness of a single execution compilation simulation, improves the integrity and effectiveness of the FPGA chip 120 test, and further enables the discovery of potential problems in the chip.

[0084] The implementation methods of each step from step 11 to step 19 above can be flexibly selected and are not limited.

[0085] For example, for step 11, the test case can be manually compiled to obtain a bitstream file and a comprehensive netlist file. The test case can also be automatically compiled to obtain a bitstream file and a comprehensive netlist file. The above two methods are examples, and their implementation methods are not limited.

[0086] In order to obtain a bitstream file and a synthesis netlist file, in step 11, the test case is input into a design compilation tool to synthesize, place and route the test case, and then the synthesis netlist file and the bitstream file are extracted from a report output by the design compilation tool.

[0087] The synthesis includes at least: converting the test case (i.e., the circuit design code written in the hardware description language) into a gate-level netlist, i.e., a comprehensive netlist file, which is represented by logic gates (AND, OR, NOT, D flip-flop, etc.).

[0088] The layout includes at least: allocating the logic units such as logic gates and triggers obtained after synthesis to specific locations on the FPGA chip. During the layout process, the connection relationship between the logic units and the resource distribution inside the FPGA are considered.

[0089] Routing at least includes: connecting the logic units whose positions are determined after layout through the connection resources (such as wires, switches, etc.) inside the FPGA to realize the connection relationship defined in the logic netlist.

[0090] Through the above process, the bitstream file and the integrated netlist file can be obtained from the report output by the design verification tool. In addition, the above synthesis, layout and routing process can also include optimization and other processes, which will not be repeated here.

[0091] In step 13, the bitstream file may be used directly for testing, or the bitstream file may be processed according to a preset rule and then bitstream simulation may be performed. The above two methods are examples, and the implementation method is not limited.

[0092] In order to fully reflect the fuse configuration information of the FPGA chip hardware circuit in the bitstream file during simulation, the bitstream simulation process in step 13 introduces the idea of ​​obtaining a circuit assignment file from the bitstream file and performing bitstream simulation with a bitstream simulation stimulus file made from the circuit assignment file. Figure 4 The implementation process of step 13 includes steps 131 to 135.

[0093] Step 131, obtaining a circuit assignment file according to the bit stream file.

[0094] Among them, the FPGA chip includes multiple circuit sub-modules in array form, and the circuit assignment file is the start and stop configuration file of each circuit sub-module of the FPGA chip corresponding to the test case.

[0095] Step 133, write the logic function stimulus file into the circuit assignment file to obtain a bit stream simulation stimulus file.

[0096] Step 135, using the bitstream simulation stimulus file as an input signal stimulus and the complete circuit model netlist file of the FPGA chip as a circuit design file, inputting them into a simulation tool to obtain a bitstream simulation result output by the simulation tool.

[0097] For example, the FPGA chip 120 corresponding to the test case has a complete circuit design file written in a hardware description language, that is, a complete circuit model netlist file, represented by av. The circuit assignment file obtained based on the bitstream file is represented by tb_1.v, the logic function stimulus file is represented by tb_2.v, and tb_2.v is written into tb_1.v (it can also be understood as combining tb_1.v and tb_2.v files) to obtain a bitstream simulation stimulus file, represented by tb_3.v. At this time, the bitstream simulation stimulus file tb_3.v contains both the stimulus value of the input signal for this test case and the switch values ​​of some circuit signals of the entire chip after the layout and routing of this test case under the current FPGA chip 120.

[0098] Furthermore, tb_3.v is used as the input signal stimulus, and the complete circuit model netlist file av (i.e., circuit design file) of FPGA chip 120 is used as the circuit design file. tb_3.v and av are input into the simulation tool, and the simulation tool will perform simulation and output the bit stream simulation result.

[0099] The bitstream simulation result includes at least input and output information files, and may also include simulation waveforms.

[0100] The FPGA chip 120 corresponding to each test case includes multiple circuit sub-modules, and the bitstream file of the test case includes multiple configuration values ​​corresponding to the circuit sub-modules of the FPGA chip 120. Therefore, in step 131, the circuit assignment file of the FPGA chip 120 corresponding to the test case can be obtained according to the bitstream file.

[0101] For step 131, the bitstream file and the circuit configuration information of the FPGA chip 120 can be input into a pre-trained parsing model to output a circuit assignment file using the parsing model, or the bitstream file can be processed according to preset rules to obtain the circuit assignment file. The above methods are all examples and their implementation methods are not limited.

[0102] In order to ensure the accuracy of the circuit assignment file and avoid errors in the circuit on / off states between the circuit assignment file and the bitstream file, in step 131, the data in the bitstream file is traversed to obtain the concept of the circuit assignment file. Figure 5 The process of obtaining the circuit assignment file in step 131 includes steps 1311 to 1315.

[0103] Step 1311, traverse the bitstream file, and take the data with a configuration value of 1 in the bitstream file as the target data.

[0104] Step 1313: for each target data, the circuit sub-module corresponding to the location of the target data is used as the target sub-module.

[0105] Step 1315, configure the status of each target submodule to be open, and configure the status of each remaining circuit submodule to be closed, so as to obtain a circuit assignment file.

[0106] The above steps 1311 to 1315 traverse each value in the bitstream file one by one, and obtain the circuit assignment file according to the traversed configuration value of one, so as to ensure the consistency between the circuit assignment file and the bitstream file.

[0107] Through the above steps 131 to 135, a bitstream simulation stimulus file is generated according to the configuration value of the FPGA chip 120 hardware circuit in the bitstream file (i.e., fuse configuration information, representing open or closed), and simulation is performed accordingly, so that the fuse configuration information of the FPGA chip 120 hardware circuit in the bitstream is fully reflected during the simulation, thereby improving the test integrity of the FPGA chip 120, and further helping to improve the accuracy and reliability of the test verification results.

[0108] While executing the above steps 131 to 135, step 15, i.e. logic function simulation, can also be executed. Figure 6 The process of performing functional simulation in step 15 includes steps 151 to 153.

[0109] Step 151, obtaining the logic function stimulus file and primitive library file of the test case.

[0110] Step 153, the logic function stimulus file, the primitive library file and the integrated netlist file are used as inputs of the functional simulation to obtain the functional simulation results.

[0111] Among them, the primitive library file refers to a plurality of pre-defined, basic hardware functional modules, which provide logical building blocks for realizing specific functions.

[0112] After obtaining the logic function stimulus file, primitive library file and integrated netlist file, the integrated netlist file, logic function stimulus file and primitive library file are all used as input files for functional simulation and input into the simulation tool. The simulation tool performs functional simulation of the test case based on the input files and outputs the functional simulation results.

[0113] The functional simulation results at least include input and output information files, and may also include functional simulation waveforms.

[0114] Functional simulation is performed through the above steps 151 to 153 to obtain a functional simulation result.

[0115] After obtaining the functional simulation results and bitstream simulation results using the above method, refer to Figure 7 The FPGA chip verification method provided by the embodiment of the present invention may also include step 16 and step 18.

[0116] Step 16, comparing the bitstream simulation result with the functional simulation result.

[0117] Step 18, when the board-level test results and the bitstream simulation results are consistent, it is determined that the FPGA chip hardware circuit structure logic corresponding to the test case meets expectations.

[0118] For example, the input and output information files in the bitstream simulation results are compared with the input and output information files in the functional simulation results, that is, each information is compared one by one. If they are all consistent, it is determined that the FPGA chip hardware circuit structure logic corresponding to the test case meets the expectations. Otherwise, step 17 is executed to perform board-level testing.

[0119] The input and output information files in the bitstream simulation results can also be compared with the input and output information files in the functional simulation results. The technicians manually compare the simulation waveforms. If they are consistent, it is determined that the FPGA chip hardware circuit structure logic corresponding to the test case meets the expectations. Otherwise, step 17 is executed to perform board-level testing.

[0120] Reference Figure 8The process of performing board-level testing in step 17 includes steps 171 to 175.

[0121] Step 171, downloading the bit stream file to the FPGA chip, so that the FPGA chip adjusts the switch state of each circuit sub-module.

[0122] Step 173, inputting an excitation signal to the FPGA chip, and obtaining board-level output data after the FPGA chip responds to the excitation signal.

[0123] Step 175, obtaining a board-level test result based on the board-level output data.

[0124] The FPGA chip 120 receives and responds to the bitstream file, opens the circuit sub-module with a configuration value of 1 in the bitstream file, and closes the remaining circuit sub-modules to achieve the circuit state required by the bitstream file.

[0125] Furthermore, an online logic analysis tool in an electronic design automation tool (such as EDA software) can be used to send input stimulus signals to the FPGA chip 120 one by one according to a preset stimulus sequence, receive board-level output data after the FPGA chip 120 responds to the stimulus signal, and obtain board-level test results (such as simulation waveforms and input-output information files) based on the board-level output data.

[0126] Alternatively, a manual method may be used to send input stimulus signals to the FPGA chip 120 in sequence, and an online logic analysis tool in an electronic design automation tool (such as EDA software) may be used to receive board-level output data of the FPGA chip 120 after responding to the stimulus signal, and board-level test results (such as simulation waveforms and input-output information files) may be obtained based on the board-level output data.

[0127] In the above steps 171 to 175, the stimulus signal input to the FPGA chip 120 may be consistent with the stimulus value in the logic function stimulus file used in the bit stream simulation and the functional simulation, or may be different, which is not limited here.

[0128] Through the above steps 171 to 175, actual board-level test verification is performed on the test cases where simulation deviations occur based on the bitstream file to obtain board-level test results, which helps to effectively determine whether there is a problem with the simulation process or a defect in the hardware logic itself, thereby helping to improve the accuracy and reliability of test verification.

[0129] After obtaining the board-level test results in the above manner, the method for obtaining the test verification results in step 19 can be flexibly set. For example, the board-level test results and the bitstream simulation results (both including input and output information files) can be compared. If they are consistent, it means that the bitstream simulation results are consistent with the actual hardware architecture design, and the FPGA chip 120 hardware circuit structure logic corresponding to the test case meets expectations, otherwise, it does not meet expectations. It can also be compared according to preset rules. And the implementation method is not limited.

[0130] Considering that the stimulus signal input during board-level testing may be different from the logic function stimulus file used during bitstream simulation due to disordered order, equipment reasons, or limitations of the tools used for board-level testing, the test verification result obtained based on whether the input and output information files are consistent will be inaccurate. Therefore, in order to ensure the accuracy and reliability of the test verification results, the concept of comparison implementation function is introduced in step 19.

[0131] Reference Fig. 9 The process of obtaining the test verification result in step 19 includes steps 191 to 199.

[0132] Step 191, obtaining the board-level implementation function according to the board-level test result.

[0133] Step 193, obtaining the bitstream implementation function according to the bitstream simulation result.

[0134] Step 195, determine whether the board-level implementation function is consistent with the bitstream implementation function. If yes, execute step 197. If not, execute step 199.

[0135] Step 197, determine whether the FPGA chip hardware circuit structure logic corresponding to the test case meets expectations.

[0136] Step 199, determining that the FPGA chip hardware circuit structure logic corresponding to the test case does not meet expectations.

[0137] Among them, the technicians can manually analyze the simulation waveforms and input-output information files in the board-level test results to obtain the board-level implementation functions, and manually analyze the simulation waveforms and input-output information files in the bitstream simulation results to obtain the bitstream implementation functions.

[0138] Alternatively, the complete circuit model netlist file of the FPGA chip 120 and the input-output information file in the board-level test result may be input into the pre-trained functional analysis model, and the board-level implementation function may be output using the functional analysis model. Similarly, the complete circuit model netlist file of the FPGA chip 120 and the input-output information file in the bitstream simulation result may be input into the pre-trained functional analysis model, and the bitstream implementation function may be output using the functional analysis model.

[0139] The above two methods are just examples, and their implementation methods are not limited.

[0140] If the bitstream implementation function is consistent with the board-level implementation function, it means that the hardware circuit structure logic of the FPGA chip 120 meets expectations, but there is a problem with the bitstream simulation. Otherwise, it means that the problem is not with the bitstream simulation, but that the hardware circuit structure logic of the FPGA chip 120 does not meet expectations, that is, the actual hardware architecture design does not meet the requirements.

[0141] Through the above steps 191 to 199, the test verification results are obtained by comparing the implementation functions corresponding to the board-level test results and the bitstream simulation results, thereby avoiding deviations and interference caused by inconsistent excitation signals and ensuring the accuracy and reliability of the test verification results.

[0142] Based on the same inventive concept as the above-mentioned FPGA chip verification method, refer to Fig.10 The embodiment of the present invention further provides an FPGA chip verification device 30, including a case acquisition module 310, a bit stream simulation module 320, a functional simulation module 330, a board-level test module 340 and a verification module 350.

[0143] The case acquisition module 310 is used to acquire the test case of the FPGA chip 120, and obtain a bitstream file and a comprehensive netlist file based on the test case.

[0144] The bitstream simulation module 320 is used to perform bitstream simulation on the test case based on the bitstream file to obtain a bitstream simulation result.

[0145] The functional simulation module 330 is used to perform functional simulation on the test case based on the comprehensive netlist file to obtain a functional simulation result.

[0146] The board-level test module 340 is used to download the bitstream file to the FPGA chip when the bitstream simulation result and the functional simulation result are inconsistent, so as to perform board-level testing on the test case and obtain the board-level test result.

[0147] The verification module 350 is used to obtain a test verification result according to the board-level test result and the bitstream simulation result.

[0148] Optionally, the verification module 350 is also used to determine whether the hardware circuit structure logic of the FPGA chip 120 corresponding to the test case meets expectations when the bit stream simulation result and the functional simulation result are consistent.

[0149] The above-mentioned FPGA chip verification device 30, under the coordinated action of the case acquisition module 310, the bitstream simulation module 320, the functional simulation module 330, the board-level test module 340 and the verification module 350, first compares the bitstream simulation and the functional simulation, and then performs a board-level test when they are inconsistent, to obtain the final verification test result after comparing the bitstream simulation and the board-level test, that is, combining the bitstream simulation, the case logic function simulation and the board-level test to perform a more complete test on the FPGA chip, effectively solving the problem of incompleteness of a single execution compilation simulation, improving the integrity and effectiveness of the FPGA chip test, and thus being able to discover potential problems with the chip.

[0150] For the specific implementation and effect of the FPGA chip verification device 30, please refer to the description of the implementation of the FPGA chip verification method above, such as, for the specific implementation and effect of the case acquisition module 310, please refer to the description of the relevant content of step 11 above, for the specific implementation and effect of the bitstream simulation module 320, please refer to the description of the relevant content of step 13 above, for the specific implementation and effect of the functional simulation module 330, please refer to the description of the relevant content of step 15 above, for the specific implementation and effect of the board-level test module 340, please refer to the description of the relevant content of step 17 above, and for the specific implementation and effect of the board-level test module 340, please refer to the description of the relevant content of step 19 above, which will not be repeated here.

[0151] In addition, each module of the above-mentioned FPGA chip verification device 30 can be implemented in whole or in part by software, hardware, or a combination thereof. The above-mentioned modules can be embedded in or independent of the processor 220 in the electronic device 20 in the form of hardware, or can be stored in the memory 210 of the electronic device 20 in the form of software, so that the processor 220 can call and execute the operations corresponding to the above modules to implement the FPGA chip verification method provided above.

[0152] The embodiment of the present invention also provides an electronic device 20, including a processor 220 and a memory 210, wherein the memory 210 stores a computer program that can be executed by the processor 220, and the processor 220 can execute the computer program to implement the FPGA chip verification method proposed in the embodiment of the present invention.

[0153] The embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by the processor 220, the FPGA chip verification method proposed in the embodiment of the present invention is implemented.

[0154] In summary, the FPGA chip verification method, device, electronic device, and storage medium provided by the embodiments of the present invention have at least the following beneficial effects:

[0155] (1) Combining bitstream simulation, case logic function simulation and board-level testing improves the integrity and effectiveness of the test, effectively solves the problem of incompleteness of single execution compilation simulation, and helps to discover potential problems in the chip;

[0156] (ii) Combining bitstream simulation, case logic function simulation and board-level testing to obtain test verification results makes the test verification results more accurate and reliable.

[0157] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0158] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0159] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling an electronic device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

[0160] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A FPGA chip verification method, characterized in that: The method comprises: Obtaining a test case for the FPGA chip, and obtaining a bitstream file and a comprehensive netlist file based on the test case; Based on the bitstream file, performing bitstream simulation on the test case to obtain a bitstream simulation result; Based on the comprehensive netlist file, functional simulation is performed on the test case to obtain a functional simulation result; In the case where the bitstream simulation result and the functional simulation result are inconsistent, downloading the bitstream file to the FPGA chip to perform board-level testing on the test case to obtain a board-level test result; A test verification result is obtained based on the board-level test result and the bitstream simulation result.

2. The FPGA chip verification method according to claim 1, characterized in that: The step of downloading the bitstream file to the FPGA chip to perform board-level testing on the test case to obtain a board-level test result includes: Downloading the bitstream file to the FPGA chip so that the FPGA chip adjusts the switch state of each circuit sub-module; Inputting an excitation signal to the FPGA chip, and acquiring board-level output data of the FPGA chip after responding to the excitation signal; A board-level test result is obtained according to the board-level output data.

3. The FPGA chip verification method according to claim 1 or 2, characterized in that: The step of performing bitstream simulation on the test case based on the bitstream file to obtain a bitstream simulation result includes: According to the bit stream file, a circuit assignment file is obtained; wherein the circuit assignment file is a start and stop configuration file of each circuit sub-module of the FPGA chip corresponding to the test case; Writing the logic function stimulus file into the circuit assignment file to obtain a bit stream simulation stimulus file; The bitstream simulation stimulus file is used as an input signal stimulus, and the complete circuit model netlist file of the FPGA chip is used as a circuit design file, which is input into a simulation tool to obtain a bitstream simulation result output by the simulation tool.

4. The FPGA chip verification method according to claim 3, characterized in that: The FPGA chip includes a plurality of circuit sub-modules, and the bitstream file includes a plurality of configuration values ​​corresponding to the circuit sub-modules one by one; The step of obtaining a circuit assignment file according to the bit stream file comprises: Traversing the bitstream file, and taking data with a configuration value of one in the bitstream file as target data; For each of the target data, taking the circuit submodule corresponding to the location of the target data as the target submodule; The state of each of the target submodules is configured to be open, and the state of each of the remaining circuit submodules is configured to be closed, so as to obtain a circuit assignment file.

5. The FPGA chip verification method according to claim 1 or 2, characterized in that: The step of performing functional simulation on the test case based on the comprehensive netlist file to obtain a functional simulation result comprises: Obtaining a logic function stimulus file and a primitive library file of the test case; The logic function stimulus file, the primitive library file and the comprehensive netlist file are used as inputs of functional simulation to obtain functional simulation results.

6. The FPGA chip verification method according to claim 1 or 2, characterized in that: The method further comprises: When the bit stream simulation result is consistent with the functional simulation result, it is determined that the FPGA chip hardware circuit structure logic corresponding to the test case meets expectations.

7. The FPGA chip verification method according to claim 1 or 2, characterized in that: The step of obtaining a test verification result according to the board-level test result and the bitstream simulation result comprises: According to the board-level test results, a board-level implementation function is obtained; According to the bit stream simulation result, a bit stream realization function is obtained; Determine whether the board-level implementation function is consistent with the bitstream implementation function; If so, it is determined that the FPGA chip hardware circuit structure logic corresponding to the test case meets expectations; If not, it is determined that the FPGA chip hardware circuit structure logic corresponding to the test case does not meet expectations.

8. An FPGA chip verification device, characterized in that: It includes case acquisition module, bit stream simulation module, functional simulation module, board-level test module and verification module; The case acquisition module is used to acquire the test case of the FPGA chip, and obtain a bit stream file and a comprehensive netlist file based on the test case; The bitstream simulation module is used to perform bitstream simulation on the test case based on the bitstream file to obtain a bitstream simulation result; The functional simulation module is used to perform functional simulation on the test case based on the comprehensive netlist file to obtain a functional simulation result; The board-level test module is used to download the bitstream file to the FPGA chip when the bitstream simulation result and the functional simulation result are inconsistent, so as to perform board-level testing on the test case and obtain a board-level test result; The verification module is used to obtain a test verification result based on the board-level test result and the bit stream simulation result.

9. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the FPGA chip verification method as described in any one of claims 1 to 7.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the FPGA chip verification method according to any one of claims 1 to 7 is implemented.

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