Parameter determination method, preparation method and display panel of thin film transistor

Abstract

The application relates to a parameter determination method of a thin film transistor, a preparation method and a display panel. The parameter determination method comprises the following steps: obtaining design parameters of the thin film transistor, wherein the design parameters comprise at least one of a threshold voltage, a channel width, a channel length, a ratio of the channel width and the channel length and a preparation process coefficient; determining target parameter information according to the design parameters and a design relationship corresponding to the thin film transistor; and the design relationship represents the correlation between the threshold voltage, the channel width, the channel length, the ratio of the channel width and the channel length and the preparation process coefficient. The parameter determination method of the thin film transistor provided by the application can realize the target that each thin film transistor meets the circuit working requirement at the same time.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a method for determining the parameters of a thin-film transistor, a fabrication method, and a display panel. Background Technology

[0002] Thin Film Transistors (TFTs) are attracting increasing attention due to their excellent electrical and mechanical properties. The display matrix driving circuit layer of an Active Matrix Organic Light Emitting Diode (AMOLD) panel is composed of a series of TFTs with different structures and functional requirements.

[0003] To meet the display requirements of AMOLED displays, it is necessary to ensure that different TFTs simultaneously meet the circuit operation requirements. However, traditional technologies, which rely on process and TFT size design adjustments, often struggle to achieve this goal of having all TFT devices simultaneously meet the circuit operation requirements. Summary of the Invention

[0004] Therefore, it is necessary to provide a method for determining the parameters of a thin-film transistor, a method for fabricating it, and a display panel to address the aforementioned technical problems.

[0005] In a first aspect, one embodiment of this application provides a method for determining parameter information of a thin-film transistor, the method comprising:

[0006] Obtain the design parameters of the thin-film transistor; the design parameters include at least one of the following: threshold voltage, channel width, channel length, the ratio of channel width to channel length, and fabrication process factor;

[0007] Based on the design parameters and the corresponding design formulas for thin-film transistors, the target parameter information is determined; the design formulas represent the correlation between threshold voltage, channel width, channel length, the ratio of channel width to channel length, and fabrication process coefficients.

[0008] In one embodiment, the method further includes:

[0009] The design formula is determined based on the type of thin-film transistor; different types of thin-film transistors correspond to different sets of coefficients, and each set of coefficients contains multiple different coefficients.

[0010] Optionally, the design relationship includes a first relationship, a second relationship, and a third relationship. The first relationship is used to represent the correlation between threshold voltage, fabrication process coefficient, channel length, and the ratio of channel width to channel length. The second relationship is used to represent the correlation between channel length and the ratio of channel width to channel length. The third relationship is used to represent the correlation between channel width, channel length, and the ratio of channel width to channel length.

[0011] In one embodiment, the target parameter information is determined based on the design parameters and the design relationship corresponding to the thin-film transistor, including:

[0012] Input the channel width and channel length from the design parameters into the design formula for calculation, and output the change information between the threshold voltage and the fabrication process coefficient;

[0013] Optionally, the fabrication process coefficients in the design parameters can be input into the design formula for calculation, and the variation information between the threshold voltage, channel width and channel length can be output.

[0014] Optionally, the fabrication process coefficients in the design parameters can be input into the design formula for calculation, and the information on the change between the threshold voltage and the ratio of the channel width and the channel length can be output.

[0015] Optionally, target parameter information is determined based on design parameters and the corresponding design formulas for thin-film transistors, including:

[0016] The threshold voltage, the ratio of channel width to channel length, and the fabrication process coefficients in the design parameters are input into the design formula for calculation, and the channel width and channel length are output.

[0017] Secondly, one embodiment of this application provides a method for fabricating a thin-film transistor, the method comprising:

[0018] Thin-film transistors are fabricated based on the channel width and channel length; the channel width and channel length are calculated according to the parameter information determination method for thin-film transistors provided in the first aspect above.

[0019] In one embodiment, the thin-film transistor is fabricated based on the channel width and channel length, including:

[0020] Provide substrate;

[0021] A first metal layer is formed on one side of the substrate; an oxide semiconductor layer is formed on the side of the first metal layer away from the substrate; a second metal layer is formed on the side of the oxide semiconductor layer away from the substrate; the size of the overlapping area between the oxide semiconductor layer and the second metal layer is determined according to the channel width and the channel length.

[0022] Three electrodes of a thin-film transistor are formed on the side of the oxide semiconductor layer away from the substrate;

[0023] Optionally, a first metal layer is formed on one side of the substrate; an oxide semiconductor layer is formed on the side of the first metal layer facing away from the substrate; and a second metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate, comprising:

[0024] A first metal layer is formed on one side of the substrate; a first insulating layer and a second insulating layer are sequentially formed on the side of the first metal layer opposite to the substrate.

[0025] An oxide semiconductor layer is formed on the side of the second insulating layer that is away from the substrate;

[0026] A third insulating layer is formed on the side of the oxide semiconductor layer facing away from the substrate, and a second metal layer is formed on the side of the third insulating layer facing away from the substrate.

[0027] In one embodiment, three electrodes of a thin-film transistor are formed on the side of the oxide semiconductor layer facing away from the substrate, including:

[0028] A first source of a thin-film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the first source and the oxide semiconductor layer are electrically connected to the first metal layer through a via.

[0029] A first drain of a thin-film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the first drain is electrically connected to the oxide semiconductor layer.

[0030] A first gate of a thin-film transistor is formed on the side of the second metal layer away from the substrate, and the first gate is electrically connected to the second metal layer;

[0031] Optionally, the three electrodes of the thin-film transistor are formed on the side of the oxide semiconductor layer facing away from the substrate, and the transistor further includes:

[0032] A fourth insulating layer is formed on the side of the first source, first gate, and first drain near the substrate.

[0033] Optionally, the three electrodes of the thin-film transistor are formed on the side of the oxide semiconductor layer facing away from the substrate, and the transistor further includes:

[0034] A second source of a thin-film transistor is formed on the side of the oxide semiconductor layer away from the substrate. The second source is electrically connected to the oxide semiconductor layer and is electrically connected to the first metal layer through a via.

[0035] A second gate of a thin-film transistor is formed on the side of the second metal layer away from the substrate; the second gate is electrically connected to the second metal layer and to the second source.

[0036] A second drain of a thin-film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the second drain is electrically connected to the oxide semiconductor layer.

[0037] Optionally, a first insulating layer and a second insulating layer are sequentially formed on the side of the first metal layer facing away from the substrate, including:

[0038] A first insulating layer is formed on the side of the first metal layer that faces away from the substrate;

[0039] A third metal layer is formed on the side of the first insulating layer that is away from the substrate;

[0040] A second insulating layer is formed on the side of the third metal layer that is away from the substrate.

[0041] In one embodiment, the thin-film transistor is fabricated based on the channel width and channel length, including:

[0042] Provide substrate;

[0043] A third metal layer is formed on one side of the substrate; an oxide semiconductor layer is formed on the side of the third metal layer away from the substrate; a second metal layer is formed on the side of the oxide semiconductor layer away from the substrate; the size of the overlapping area between the oxide semiconductor layer and the second metal layer is determined according to the channel width and the channel length.

[0044] Three electrodes of a thin-film transistor are formed on the side of the oxide semiconductor layer away from the substrate;

[0045] Optionally, three electrodes of the thin-film transistor are formed on the side of the oxide semiconductor layer facing away from the substrate, including:

[0046] The third source of the thin-film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the third source is electrically connected to the oxide semiconductor layer.

[0047] A third drain of a thin-film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the third drain is electrically connected to the oxide semiconductor layer.

[0048] A third gate of a thin-film transistor is formed on the side of the second metal layer away from the substrate. The third gate is electrically connected to the second metal layer and passes through a via to be electrically connected to the third metal layer.

[0049] Thirdly, one embodiment of this application provides a thin-film transistor, which is fabricated using the thin-film transistor fabrication method provided in the second aspect above.

[0050] Fourthly, one embodiment of this application provides a display panel that includes a plurality of thin-film transistors as described in the third aspect above.

[0051] Fifthly, one embodiment of this application provides a display device including a display panel as described in the fourth aspect above.

[0052] This application provides a method for determining the parameters of a thin-film transistor (TFT), a fabrication method, and a display panel. The method for determining the TFT parameters includes acquiring the TFT's design parameters; these design parameters include at least one of threshold voltage, channel width, channel length, and fabrication process parameters; and determining target parameter information based on the design parameters and the corresponding design formula for the TFT. The design formula represents the correlation between the threshold voltage, channel width, channel length, and fabrication process parameters. Using the method provided in this application, the fabrication process parameters and dimensions of the TFT, i.e., the correlation between the channel width and channel length, can be determined through the corresponding design formula. This allows the TFT size to be adjusted according to different fabrication process parameters to meet circuit operation requirements. Different types of TFTs have corresponding design formulas, and the dimensions of different types of TFTs can be determined based on these formulas to meet circuit operation requirements. This ensures that different types of TFTs can meet circuit operation requirements, thereby enabling the display panel to meet these requirements and improving the display effect. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 A flowchart illustrating the steps of a method for determining parameter information of a thin-film transistor according to one embodiment;

[0055] Figure 2 A flowchart illustrating the steps of a method for determining parameter information of a thin-film transistor according to another embodiment;

[0056] Figure 3 A schematic flowchart illustrating the steps of a method for fabricating a thin-film transistor according to one embodiment;

[0057] Figure 4 A schematic flowchart of a method for fabricating a thin-film transistor according to another embodiment;

[0058] Figure 5 A schematic flowchart of a method for fabricating a thin-film transistor according to another embodiment;

[0059] Figure 6 A schematic flowchart of a method for fabricating a thin-film transistor according to another embodiment;

[0060] Figure 7 A schematic flowchart of a method for fabricating a thin-film transistor according to another embodiment;

[0061] Figure 8 A schematic flowchart of a method for fabricating a thin-film transistor according to another embodiment;

[0062] Figure 9 A schematic flowchart of a method for fabricating a thin-film transistor according to another embodiment;

[0063] Figure 10 A schematic cross-sectional view of a display panel provided in one embodiment;

[0064] Figure 11 This is a schematic diagram showing the dimensions of the overlapping region between the oxide semiconductor layer and the second metal layer, provided in one embodiment. Detailed Implementation

[0065] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0066] The technical solution of this application and how it solves the technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0067] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various objects, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one object from another. For example, without departing from the scope of this application, a first object may be referred to as a second object, and similarly, a second object may be referred to as a first object. Words such as “comprising” or “including” mean that the objects or items preceding the word encompass the objects or items listed following the word and their equivalents, without excluding other objects or items.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0069] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0070] Thin-film transistors (TFTs) are attracting increasing attention due to their superior electrical and mechanical properties. The display matrix driving circuit layer of an Active Matrix Organic Light Emitting Diode (AMOLD) panel consists of a series of TFTs with different structures and functional requirements. To meet the display requirements of AMOLD, it is necessary to ensure that different TFTs simultaneously meet the circuit's operational needs. Different products require different TFT sizes. In traditional technologies, under the same process technology, it is difficult to achieve the goal of simultaneously meeting the circuit's operational needs for each TFT device by simply adjusting the process and TFT size design. Therefore, different combinations of design sizes and process adjustments are needed for different types of TFTs.

[0071] In view of this, embodiments of this application provide a method for determining parameter information of a thin-film transistor (TFT), a fabrication method, and a display panel. The method for determining TFT parameter information includes obtaining design parameters of the TFT; the design parameters include at least one of threshold voltage, channel width, channel length, and fabrication process coefficients; and determining target parameter information based on the design parameters and the corresponding design formula of the TFT; the design formula represents the correlation between threshold voltage, channel width, channel length, and fabrication process coefficients. Using the method provided in this application, the fabrication process coefficients and dimensions of the TFT, i.e., the correlation between channel width and channel length, can be determined through the corresponding design formula. Therefore, the dimensions of the TFT can be adjusted according to different fabrication process coefficients to ensure that the TFT meets the circuit operation requirements. Different types of TFTs have corresponding design formulas, and the dimensions of different types of TFTs can be determined based on these formulas to meet the circuit operation requirements. This allows different types of TFTs to meet the circuit operation requirements, thereby enabling the display panel to meet the circuit operation requirements and improving the display effect of the display panel.

[0072] Please see Figure 1This application provides a method for determining parameter information of a thin-film transistor. This embodiment illustrates the method by applying it to a computer device. In this embodiment, the steps of the method include:

[0073] Step 100: Obtain the design parameters of the thin-film transistor; the design parameters include at least one of the following: threshold voltage, channel width, channel length, the ratio of channel width to channel length, and fabrication process factor.

[0074] The design parameters of a thin-film transistor (TFT) refer to the parameters required to ensure the normal operation of the TFT during its design and fabrication. These parameters may include threshold voltage, channel width, channel length, the ratio of channel width to channel length, and fabrication process factors. Threshold voltage is the voltage required to be applied to the gate when a significant conductive channel begins to form between the source and drain of the TFT. Channel length refers to the actual length of the conductive channel between the source and drain in the TFT structure. Channel width refers to the lateral width occupied by the conductive channel perpendicular to the direction of carrier flow. Fabrication process factors are the conditional coefficients corresponding to the fabrication process used to fabricate the TFT; different process factors represent different fabrication processes.

[0075] The design parameters of a thin-film transistor (TFT) can be preset by the user according to the actual application. Alternatively, the TFT design parameters can be user-inputted, retrieved by the computer device in response to the user's input. The TFT design parameters retrieved by the computer device can be any one of the following: threshold voltage, channel width, channel length, the ratio of channel width to channel length, and fabrication process factors; or any two or three of these parameters. This embodiment does not limit the specific method for obtaining the TFT design parameters, as long as the function can be achieved.

[0076] Step 110: Determine the target parameter information based on the design parameters and the design formula corresponding to the thin-film transistor; the design formula represents the relationship between threshold voltage, channel width, channel length, the ratio of channel width to channel length, and the fabrication process coefficient.

[0077] The design formula for a thin-film transistor (TFT) can be established based on the TFT's threshold voltage, channel width, channel length, the ratio of channel width to channel length, and fabrication process parameters. This formula characterizes the relationship between the TFT's threshold voltage, channel width, channel length, the ratio of channel width to channel length, and fabrication process parameters. The TFT design formula can be pre-set by the user and stored in the computer's memory.

[0078] After acquiring the design parameters of the thin-film transistor, the computer device retrieves the corresponding design formulas from memory. Based on the design parameters and the corresponding design formulas, the target parameter information can be determined. The target parameter information can be the values ​​of other design parameters besides the acquired design parameters, or it can be the correlation between other design parameters besides the acquired design parameters. This embodiment does not limit the determined target parameter information.

[0079] This application provides a method for determining the parameter information of a thin-film transistor (TFT). This method obtains the design parameters of the TFT, including at least one of the following: threshold voltage, channel width, channel length, the ratio of channel width to channel length, and fabrication process coefficients. Based on the design parameters and the corresponding device formulas for the TFT, target parameter information is determined. The design formulas represent the correlation between the threshold voltage, channel width, channel length, the ratio of channel width to channel length, and the fabrication process coefficients. Thus, the fabrication process coefficients and dimensions of the TFT, i.e., the correlation between the channel width and channel length, can be determined through the corresponding design formulas. Therefore, the dimensions of the TFT can be adjusted according to different fabrication process coefficients to ensure that the TFT meets the circuit operation requirements. Different types of TFTs have corresponding design formulas, and the dimensions of different types of TFTs can be determined based on these formulas to meet the circuit operation requirements. This allows different types of TFTs to meet the circuit operation requirements, thereby enabling the display panel to meet the circuit operation requirements and improving the display effect.

[0080] In one embodiment, the design relationship includes a first relationship, a second relationship, and a third relationship. The first relationship is used to represent the correlation between threshold voltage, fabrication process coefficient, channel length, and the ratio of channel width to channel length. The second relationship is used to represent the correlation between channel length and the ratio of channel width to channel length. The third relationship is used to represent the correlation between channel width, channel length, and the ratio of channel width to channel length.

[0081] The design relationships for thin-film transistors include a first relationship based on threshold voltage, fabrication process parameters, channel length, and the ratio of channel width to channel length; a second relationship based on channel length and the ratio of channel width to channel length; and a third relationship based on channel width, channel length, and the ratio of channel width to channel length. In other words, after acquiring the design parameters, the computer inputs these parameters into the first, second, and third relationships. By solving these relationships, the target parameter information can be determined.

[0082] This embodiment describes design relations including a first relation, a second relation, and a third relation. The first relation, the second relation, and the third relation can be used to more accurately determine the target parameter information.

[0083] In one embodiment, the method for determining the parameter information of a thin-film transistor further includes:

[0084] The design formula is determined based on the type of thin-film transistor; different types of thin-film transistors correspond to different sets of coefficients, and each set of coefficients contains multiple different coefficients.

[0085] Different types of thin-film transistors (TFTs) correspond to different design formulas. After obtaining the design parameters of a TFT, the computer device first determines the type of TFT, and then looks up the corresponding design formula based on that type.

[0086] Thin-film transistors (TFTs) can be categorized into top-gate (TG), bottom-gate (BG), and dual-gate (DG) structures. The design equations for TFTs include a set of coefficients, which contains several different coefficients. The coefficient sets differ depending on the type of TFT being designed.

[0087] In an optional embodiment, the design relation for a TG structure thin-film transistor can be expressed as:

[0088]

[0089] in, The threshold voltage of the TG structure thin-film transistor is represented by A, which represents the fabrication process factor of the TG structure thin-film transistor. This indicates the channel length of a thin-film transistor with a TG structure. This indicates the channel width of a thin-film transistor with a TG structure. This represents the ratio of channel width to channel length in a TG-structured thin-film transistor. - This is the coefficient set for a TG-structured thin-film transistor. Specifically, It can be 13.7. It can be 2.336. It can be 0.5. It can be 3.3. It can be -0.025. It can be 4.7. It can be 0.2. It can be 0.8327. It can be 4.0882. It can be 0.8. Due to fluctuations in the actual manufacturing process, the actual channel width W of the TG structure thin-film transistor in the actual product will vary. TG Compared with the actual channel length L TG It can be located in W TG ±0.2um and L TG Within the range of ±0.2um.

[0090] In an optional embodiment, the design relation for a BG structure thin-film transistor can be expressed as:

[0091]

[0092] in, The threshold voltage of the BG structure thin-film transistor is represented by A, where A represents the fabrication process factor of the BG structure thin-film transistor. This indicates the channel length of a BG structure thin-film transistor. This represents the channel width of a BG structure thin-film transistor. This represents the ratio of channel width to channel length in a BG structure thin-film transistor. - This is the coefficient set for a BG structure thin-film transistor. Specifically, It can be 20.9. It can be 2.633. It can be 0.3. It can be 8.7. It can be -0.0075. It can be 6.2. It can be 0.18. It can be 0.2877. It could be 5.7964. It can be 0.8. Due to fluctuations in the actual manufacturing process, the actual channel width W of the BG structure thin-film transistor in the actual product will vary. BG Compared with the actual channel length L BG It can be located in W BG±0.2um and L BG Within the range of ±0.2um.

[0093] In an optional embodiment, the design relation for a DG structure thin-film transistor can be expressed as:

[0094]

[0095] in, The threshold voltage of the DG structure thin-film transistor is represented by A, where A represents the fabrication process factor of the DG structure thin-film transistor. This indicates the channel length of the thin-film transistor with a DG structure. This represents the channel width of a thin-film transistor with a DG structure. This represents the ratio of channel width to channel length in a DG structure thin-film transistor. - This represents the coefficient set of the DG structure thin-film transistor. Specifically, It can be 6.73. It can be 0.9277. It can be 0.5. It can be 5.8. It can be -0.0025. It can be 7.8. It can be 0.04. It could be 1.4708. It can be 6.7063. It can be 0.8. Due to fluctuations in the actual manufacturing process, the actual channel width W of the DG structure thin-film transistor in the actual product will vary. DG Compared with the actual channel length L DG It can be located in W DG ±0.2um and L DG Within the range of ±0.2um.

[0096] In this embodiment, different design formulas are described for different types of thin-film transistors. Thus, for different types of thin-film transistors in a display panel, the corresponding design formulas can be used to determine the size of the different types of thin-film transistors that meet the circuit operation requirements under the same fabrication process. This ensures that the different types of thin-film transistors in the fabricated display panel can meet the circuit operation requirements, thereby improving the display effect of the display panel including the different types of thin-film transistors.

[0097] Please see Figure 2 In one embodiment, an implementation method is provided for determining target parameter information based on design parameters and the design relationship corresponding to the thin-film transistor. This implementation method includes:

[0098] Step 200: Input the channel width and channel length from the design parameters into the design formula for calculation, and output the change information between the threshold voltage and the fabrication process coefficient.

[0099] When the design parameters obtained from the computer equipment are the channel width and channel length of the thin-film transistor, the ratio of the channel width to the channel length can be determined based on the channel length and channel width. By inputting the channel width, channel length, and the ratio of the channel width to the channel length into the design formula for calculation, the variation information between the threshold voltage and the fabrication process coefficient can be obtained. In other words, the threshold voltage of the thin-film transistor under different fabrication processes can be determined.

[0100] In this embodiment, the relationship between the threshold voltage of the thin-film transistor and the fabrication process coefficient can be determined through the corresponding formula. This allows users to set the threshold voltage of the thin-film transistor according to the fabrication process, or select the corresponding fabrication process according to the threshold voltage of the thin-film transistor, thereby ensuring that the thin-film transistor can meet the circuit operation requirements.

[0101] Please continue reading Figure 2 In one embodiment, another implementation method is provided for determining target parameter information based on design parameters and the design relationship corresponding to the thin-film transistor. This implementation method includes the following steps:

[0102] Step 210: Input the fabrication process coefficients from the design parameters into the design formula for calculation, and output the variation information between the threshold voltage, channel width, and channel length.

[0103] When the design parameters obtained by the computer equipment are the fabrication process coefficients of the thin-film transistor, the fabrication process coefficients are input into the design formula for calculation. This allows us to obtain information on the changes between the threshold voltage, channel width, and channel length. In other words, we can determine the correlation between the threshold voltage and the channel width and channel length under the same fabrication process, i.e., the channel width and channel length corresponding to different threshold voltages.

[0104] In this embodiment, the relationship between the threshold voltage and the channel width and channel length of the thin-film transistor can be determined by the corresponding formula. This allows the user to set the channel length and channel width of the thin-film transistor according to the threshold voltage, or to determine the corresponding threshold voltage according to the channel length and channel width of the thin-film transistor, thereby ensuring that the thin-film transistor can meet the circuit operation requirements.

[0105] Please continue reading Figure 2 In one embodiment, another implementation method is provided for determining target parameter information based on design parameters and the design relationship corresponding to the thin-film transistor. This implementation method includes the following steps:

[0106] Step 220: Input the fabrication process coefficients from the design parameters into the design formula for calculation, and output the change information between the threshold voltage and the ratio of the channel width to the channel length.

[0107] When the design parameters obtained by the computer equipment are the fabrication process coefficients of the thin-film transistor, the fabrication process coefficients are input into the design formula for calculation. This allows us to obtain information on the change between the threshold voltage and the ratio of the channel width and channel length. In other words, we can determine the correlation between the threshold voltage and the ratio of the channel width and channel length under the same fabrication process, i.e., the ratio of the channel width and channel length corresponding to different threshold voltages.

[0108] In this embodiment, the relationship between the threshold voltage and the ratio of the channel width to the channel length in the thin-film transistor can be determined by the corresponding formula. This allows the user to set the ratio of the channel length to the channel width of the thin-film transistor based on the threshold voltage, or to determine the corresponding threshold voltage based on the ratio of the channel length to the channel width of the thin-film transistor, thereby ensuring that the thin-film transistor can meet the circuit operation requirements.

[0109] Please continue reading Figure 2 In one embodiment, another implementation method is provided for determining target parameter information based on design parameters and the design relationship corresponding to the thin-film transistor. This implementation method includes:

[0110] Step 230: Input the threshold voltage, the ratio of channel width to channel length, and the fabrication process coefficient from the design parameters into the design formula for calculation, and output the channel width and channel length.

[0111] Given the design parameters of a thin-film transistor (TFT) obtained from a computer device, including the threshold voltage, the ratio of channel width to channel length, and fabrication process parameters, the channel width and channel length of the TFT can be calculated by inputting these parameters into the design formula. In other words, the channel width and channel length of the TFT can be determined for a given threshold voltage, fabrication process parameters, and channel width and length.

[0112] In this embodiment, the channel width and channel length can be calculated using the design formula corresponding to the thin-film transistor. For different types of thin-film transistors, the channel width and channel length can be determined under the same fabrication process to achieve the threshold voltage, thereby ensuring that different types of thin-film transistors can meet the circuit operation requirements.

[0113] In an optional embodiment, the values ​​of the design parameters corresponding to the design relationships based on different types of thin-film transistors can be shown in the following table:

[0114]

[0115]

[0116]

[0117]

[0118] In an optional embodiment, the design parameters of the thin-film transistors in the display panel can be determined experimentally as shown in the table below:

[0119]

[0120] As can be seen from the table above, the threshold voltages of the two types of TFTs with DG structure in the display panel differ significantly under the same manufacturing process. If the threshold voltages of the two types of TFTs are required to be the same, it will cause one of the TFTs to exceed the circuit's operating requirements.

[0121]

[0122] After determining the target parameter information using the design formula corresponding to the thin-film transistor provided in this application, the threshold voltage of the two DG structure TFTs is pulled to the same level, so that the two DG structure TFTs can meet the circuit operation requirements at the same time under the same fabrication process.

[0123] This application provides a method for fabricating a thin-film transistor, the method comprising:

[0124] Thin-film transistors are fabricated based on the channel width and channel length; the channel width and channel length are calculated according to the parameter information determination method for thin-film transistors provided in the above embodiments.

[0125] When fabricating thin-film transistors (TFTs) in a display panel, different types of TFTs can be fabricated based on the channel width and channel length calculated in the above embodiments. This embodiment does not limit the specific fabrication method of the TFT, as long as its function can be achieved.

[0126] The channel width and channel length in the thin-film transistor fabrication method provided in this embodiment are calculated using the parameter determination method for thin-film transistors provided in the above embodiment. Therefore, this fabrication method has all the beneficial effects of the parameter determination method for thin-film transistors provided in the above embodiment, which will not be repeated here.

[0127] Please see Figure 3In one embodiment, an implementation of fabricating a thin-film transistor based on a channel width and a channel length includes the following steps:

[0128] Step 300: Provide a substrate.

[0129] The substrate can be an inorganic material substrate, an organic material substrate, or a composite substrate formed by stacking inorganic and organic material substrates.

[0130] Step 310: Form a first metal layer on one side of the substrate; form an oxide semiconductor layer on the side of the first metal layer away from the substrate; form a second metal layer on the side of the oxide semiconductor layer away from the substrate; determine the size of the overlapping area between the oxide semiconductor layer and the second metal layer according to the channel width and channel length.

[0131] A first metal layer is formed on one side of the substrate. The first metal layer can be patterned by a photolithography process. The material of the first metal layer can be molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu). The first metal layer can be a single layer or multiple layers made of any one or more alloys containing the above materials. This embodiment does not limit the material and number of layers of the first metal layer.

[0132] An oxide semiconductor layer is formed on the side of the first metal layer facing away from the substrate. The oxide semiconductor layer can be formed by depositing an oxide semiconductor material and then patterning it. The material of the oxide semiconductor layer can be an oxide containing at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), or hafnium (Hf). Specifically, the oxide semiconductor layer can include zinc tin oxide (TZO), gallium tin oxide (TGO), indium tin zinc oxide (ITZO), indium tin gallium oxide (TZO), indium tin gallium oxide (ITGO), or indium tin tin zinc gallium oxide (ITZGO). This embodiment does not limit the material of the oxide semiconductor layer.

[0133] A second metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate. The second metal layer may be the same as or different from the first metal layer. The description of the second metal layer can be found in the detailed description of the first metal layer described above, and will not be repeated here.

[0134] During the fabrication of the oxide semiconductor layer and the second metal layer, the size of the overlapping region between the oxide semiconductor layer and the second metal layer is determined based on the calculated channel width and channel length. The length of the overlapping region in the first direction is the channel length, and the width in the second direction is the channel width. The first direction and the second direction are perpendicular to each other.

[0135] Step 320: Form three electrodes of a thin-film transistor on the side of the oxide semiconductor layer away from the substrate.

[0136] The three electrodes of a thin-film transistor, namely the gate, drain, and source, are formed on the side of the oxide semiconductor layer facing away from the substrate. A thin-film transistor can be formed by fabricating a first metal layer, an oxide semiconductor layer, a second metal layer, and the three electrodes of the thin-film transistor.

[0137] In an optional embodiment, a fourth metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate, and etching the fourth metal layer can form the three electrodes of the thin-film transistor.

[0138] In this embodiment, a first metal layer is formed on one side of the substrate; an oxide semiconductor layer is formed on the side of the first metal layer facing away from the substrate; a second metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate; the size of the overlapping area of ​​the oxide semiconductor layer and the second metal layer is determined according to the channel width and channel length; and three electrodes of the thin-film transistor are formed on the side of the oxide semiconductor layer facing away from the substrate. The thin-film transistor fabricated using the calculated channel width and channel length ensures that it meets the circuit operation requirements, thereby ensuring that different types of thin-film transistors all meet the circuit operation requirements, and ultimately improving the display effect of the display panel containing different types of thin-film transistors.

[0139] In one embodiment, such as Figure 4 As shown, an implementation involves forming a first metal layer on one side of a substrate; forming an oxide semiconductor layer on the side of the first metal layer facing away from the substrate; and forming a second metal layer on the side of the oxide semiconductor layer facing away from the substrate. The implementation includes the following steps:

[0140] Step 400: A first metal layer is formed on one side of the substrate; a first insulating layer and a second insulating layer are sequentially formed on the side of the first metal layer opposite to the substrate.

[0141] After forming a first metal layer on one side of the substrate, two insulating layers are sequentially formed on the side of the first metal layer facing away from the substrate, namely a first insulating layer and a second insulating layer. The first insulating layer can be one or more inorganic layers. The first insulating layer can be one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) layers formed using chemical vapor deposition (CVD) technology. The second insulating layer can be the same as or different from the first insulating layer; the description of the second insulating layer can refer to the specific description of the first insulating layer. The first insulating layer can be a capacitor insulating layer, and the second insulating layer can be a gate insulating layer. Specifically, the thickness of the capacitor insulating layer can be 1300 Å, and the thickness of the gate insulating layer can be 1400 Å or 3000 Å.

[0142] Step 410: An oxide semiconductor layer is formed on the side of the second insulating layer away from the substrate.

[0143] Step 420: A third insulating layer is formed on the side of the oxide semiconductor layer away from the substrate, and a second metal layer is formed on the side of the third insulating layer away from the substrate.

[0144] An oxide semiconductor layer is sequentially formed on the side of the second insulating layer away from the substrate. A third insulating layer is then formed on the side of the oxide semiconductor layer away from the substrate using CVD technology. A second metal layer is then patterned on the side of the third insulating layer away from the substrate using photolithography. The third insulating layer and the first insulating layer may be the same or different. The third insulating layer is a gate insulating layer. A description of the third insulating layer can be found in the detailed description of the first insulating layer in the above embodiments, and will not be repeated here.

[0145] In this embodiment, a first metal layer is formed on one side of the substrate; a first insulating layer and a second insulating layer are formed on the side of the first metal layer facing away from the substrate; an oxide semiconductor layer is formed on the side of the second insulating layer facing away from the substrate; a third insulating layer is formed on the side of the oxide semiconductor layer facing away from the substrate; and a second metal layer is formed on the side of the third insulating layer facing away from the substrate. In this embodiment, the first insulating layer and the second insulating layer are formed between the first metal layer and the oxide semiconductor layer, and the third insulating layer is formed between the oxide semiconductor layer and the second metal layer. This ensures the normal operation of the fabricated thin-film transistor.

[0146] In one embodiment, such as Figure 5 As shown, one implementation involves forming three electrodes of a thin-film transistor on the side of an oxide semiconductor layer away from the substrate. The implementation includes the following steps:

[0147] Step 500: A first source of a thin film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the first source and the oxide semiconductor layer are electrically connected to the first metal layer through a via.

[0148] A first source of a thin-film transistor is formed on the side of the oxide semiconductor layer and the second metal layer away from the substrate. The first source is electrically connected to the first metal layer through a via. That is, the first source is connected to the oxide semiconductor layer through a via disposed on the third insulating layer, and the first source is electrically connected to the first metal layer through the vias on the third insulating layer, the first insulating layer, and the second insulating layer, so that the first source and the first metal layer are at the same potential.

[0149] Step 510: A first drain of a thin-film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the first drain is electrically connected to the oxide semiconductor layer.

[0150] A first drain of a thin-film transistor is formed on the side of the oxide semiconductor layer and the second metal layer away from the substrate. The first drain is electrically connected to the oxide semiconductor layer through a via in the third insulating layer. The first drain and the first source are located on the same layer.

[0151] Step 520: A first gate of a thin-film transistor is formed on the side of the second metal layer away from the substrate, and the first gate is electrically connected to the second metal layer.

[0152] A first gate of a thin-film transistor is formed on the side of the second metal layer facing away from the substrate, and the first gate is electrically connected to the second metal layer. The first gate, the first source, and the first drain are located on the same layer.

[0153] In one embodiment, after forming a second metal layer on the oxide semiconductor layer facing away from the substrate, a fourth insulating layer is formed on the side of the second metal layer facing away from the substrate. In other words, a fourth insulating layer is formed on the side of the first source, first gate, and first drain near the substrate. The fourth insulating layer can be an interlayer insulating layer. Specifically, the thickness of the interlayer insulating layer can be 5500 Å. In this case, the first source of the thin-film transistor is formed on the side of the fourth insulating layer facing away from the substrate. Vias are provided on the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer. The first source is electrically connected to the first metal layer through the vias provided on the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer. The first drain is electrically connected to the oxide semiconductor layer through the vias on the fourth insulating layer and the third insulating layer. The first gate is electrically connected to the second metal layer through the vias through the fourth insulating layer.

[0154] In this embodiment, a first source of a thin-film transistor is formed on the oxide semiconductor layer away from the substrate, and the first source and the oxide semiconductor layer are electrically connected to a first metal layer through a via; a first drain of the thin-film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the first drain is electrically connected to the oxide semiconductor layer; a first gate of the thin-film transistor is formed on the side of the second metal layer away from the substrate, and the first gate is electrically connected to the second metal layer. This forms a TG structure thin-film transistor, and the switching on and off of the thin-film transistor is controlled by applying different potential electric fields to the first gate of the TG structure thin-film transistor.

[0155] In one embodiment, such as Figure 6 As shown, one implementation involves forming three electrodes of a thin-film transistor on the side of an oxide semiconductor layer away from the substrate. The implementation includes the following steps:

[0156] Step 600: A second source of a thin-film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the second source is electrically connected to the oxide semiconductor layer.

[0157] A second source of a thin-film transistor is formed on the side of the oxide semiconductor layer and the second metal layer opposite to the base. The second source is electrically connected to the oxide semiconductor layer through a via disposed on the third insulating layer, and the second source is electrically connected to the first metal layer through a via disposed on the third insulating layer, the second insulating layer and the first insulating layer.

[0158] Step 610: A second gate of a thin-film transistor is formed on the side of the second metal layer away from the substrate; the second source is electrically connected to the first metal layer through a via and to the second metal layer through the second gate.

[0159] A second gate of a thin-film transistor is formed on the side of the second metal layer facing away from the substrate. The second gate is electrically connected to the second metal layer and also electrically connected to the second source, thereby making the second source, the first metal layer, and the second metal layer at the same potential. The second gate and the second source are located in the same layer.

[0160] Step 620: Form the second drain of the thin film transistor on the side of the oxide semiconductor layer away from the substrate.

[0161] A second drain of a thin-film transistor is formed on the side of the oxide semiconductor layer facing away from the substrate. The second drain is electrically connected to the oxide semiconductor layer through a via in the third insulating layer. The second drain and the second source are located in the same layer.

[0162] In one embodiment, after forming a second metal layer on the oxide semiconductor layer facing away from the substrate, a fourth insulating layer is formed on the side of the second metal layer facing away from the substrate. In other words, a fourth insulating layer is formed on the side of the first source, first gate, and first drain closest to the substrate. In this case, a second source of the thin-film transistor is formed on the side of the fourth insulating layer facing away from the substrate. Vias are provided on the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer. The second source is electrically connected to the first metal layer through the vias provided on the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer. The second drain is electrically connected to the oxide semiconductor layer through the vias on the fourth insulating layer and the third insulating layer. The second gate is electrically connected to the second metal layer through a via through the fourth insulating layer.

[0163] In this embodiment, a second source of the thin-film transistor is formed on the side of the oxide semiconductor layer facing away from the substrate. The second source is electrically connected to the oxide semiconductor layer and passes through a via to be electrically connected to the first metal layer. A second gate of the thin-film transistor is formed on the side of the second metal layer facing away from the substrate. The second gate is electrically connected to the second metal layer and is electrically connected to the second source. A second drain of the thin-film transistor is formed on the side of the oxide semiconductor layer facing away from the substrate and is electrically connected to the oxide semiconductor layer. This forms a BG structure thin-film transistor, and the switching on and off of the thin-film transistor can be controlled by applying different potential electric fields to the second gate of the BG structure thin-film transistor.

[0164] In one embodiment, such as Figure 7 As shown, one implementation involves sequentially forming a first insulating layer and a second insulating layer on the side of the first metal layer facing away from the substrate. The steps of this implementation include:

[0165] Step 700: Form a first insulating layer on the side of the first metal layer away from the substrate.

[0166] Step 710: Form a third metal layer on the side of the first insulating layer away from the substrate.

[0167] Step 720: Form a second insulating layer on the side of the third metal layer away from the substrate.

[0168] The third metal layer may be the same as or different from the first metal layer. The description of the material and structure of the third insulating layer can be found in the specific description of the material and structure of the first metal layer in the above embodiments, and will not be repeated here. After forming the first insulating layer on the side of the first metal layer facing away from the substrate, the third metal layer is patterned and formed on the side of the first insulating layer facing away from the substrate using a photolithography process. After forming the third metal layer, a second insulating layer is formed on the side of the third metal layer facing away from the substrate.

[0169] In this embodiment, a first insulating layer is formed on the side of the first metal layer away from the substrate, and a third metal layer is formed on the side of the first insulating layer away from the substrate; a second insulating layer is formed on the side of the third metal layer away from the substrate. In this way, the first metal layer, the second metal layer, and the oxide can be isolated from the semiconductor layer through the first insulating layer and the second insulating layer, thereby ensuring the normal operation of the fabricated thin-film transistor.

[0170] In one embodiment, such as Figure 8 As shown, another implementation of a thin-film transistor is described, based on the channel width and channel length, the steps of which include:

[0171] Step 800: Provide a substrate.

[0172] Step 810: Form a third metal layer on one side of the substrate; form an oxide semiconductor layer on the side of the third metal layer away from the substrate; form a second metal layer on the side of the oxide semiconductor layer away from the substrate; determine the size of the overlapping area between the oxide semiconductor layer and the second metal layer according to the channel width and channel length.

[0173] The description of the materials and structures of the substrate, the third metal layer, the oxide semiconductor layer, and the second metal layer can be found in the detailed description of the above embodiments, and will not be repeated here.

[0174] A third metal layer is formed on one side of the substrate by photolithography. An oxide semiconductor layer is formed on the side of the third metal layer facing away from the substrate. A second metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate. The dimensions of the overlapping region between the oxide semiconductor layer and the second metal layer can be determined based on the channel width and channel length calculated according to the above embodiment. The length of this overlapping region in the first direction is the channel length, and the width in the second direction is the channel width.

[0175] In an optional embodiment, a second insulating layer is formed between the third metal layer and the oxide semiconductor layer, and a third insulating layer is formed between the oxide semiconductor layer and the second metal layer.

[0176] Step 820: Form three electrodes of a thin-film transistor on the side of the oxide semiconductor layer away from the substrate.

[0177] The three electrodes of a thin-film transistor, namely the gate, drain, and source, are formed on the side of the oxide semiconductor layer facing away from the substrate. A thin-film transistor can be formed by fabricating a third metal layer, an oxide semiconductor layer, a second metal layer, and the three electrodes of the thin-film transistor.

[0178] In an optional embodiment, a fourth metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate, and etching the fourth metal layer can form the three electrodes of the thin-film transistor.

[0179] In this embodiment, a third metal layer is formed on one side of the substrate; an oxide semiconductor layer is formed on the side of the third metal layer facing away from the substrate; a second metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate; the size of the overlapping area between the oxide semiconductor layer and the second metal layer is determined according to the channel width and channel length; and three electrodes of the thin-film transistor are formed on the side of the oxide semiconductor layer facing away from the substrate. The thin-film transistor fabricated using the calculated channel width and channel length ensures that it meets the circuit operation requirements, thereby ensuring that different types of thin-film transistors all meet the circuit operation requirements, and ultimately improving the display effect of the display panel containing different types of thin-film transistors.

[0180] In one embodiment, such as Figure 9 As shown, one implementation involves forming three electrodes of a thin-film transistor on the side of an oxide semiconductor layer away from the substrate. The implementation includes the following steps:

[0181] Step 900: A third source of a thin film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the third source is electrically connected to the oxide semiconductor layer.

[0182] A fourth metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate. Etching the fourth metal layer forms the third source of the thin-film transistor. The third source is electrically connected to the oxide semiconductor layer.

[0183] In an optional embodiment, a second insulating layer is formed between the third metal layer and the oxide semiconductor layer, a third insulating layer is formed between the oxide semiconductor layer and the second metal layer, and a fourth insulating layer is formed on the side of the second metal layer facing away from the substrate. The third source electrode is electrically connected to the oxide semiconductor layer through a via in the fourth insulating layer and the third insulating layer.

[0184] Step 910: A third drain of a thin-film transistor is formed on the side of the oxide semiconductor layer away from the substrate, and the third drain is electrically connected to the oxide semiconductor layer.

[0185] A fourth metal layer is formed on the side of the oxide semiconductor layer away from the substrate. Etching the fourth metal layer can form the third drain of the thin film transistor. The third drain is electrically connected to the oxide semiconductor layer.

[0186] In an optional embodiment, a second insulating layer is formed between the third metal layer and the oxide semiconductor layer, a third insulating layer is formed between the oxide semiconductor layer and the second metal layer, and a fourth insulating layer is formed on the side of the second metal layer facing away from the substrate. The third drain is electrically connected to the oxide semiconductor layer through the fourth insulating layer and vias in the third insulating layer.

[0187] Step 920: A third gate of a thin-film transistor is formed on the side of the second metal layer away from the substrate. The third gate is electrically connected to the second metal layer and passes through a via to be electrically connected to the third metal layer.

[0188] A fourth metal layer is formed on the side of the second metal layer away from the substrate, and etching the fourth metal layer can form the third gate of the thin-film transistor.

[0189] In an optional embodiment, a second insulating layer is formed between the third metal layer and the oxide semiconductor layer, a third insulating layer is formed between the oxide semiconductor layer and the second metal layer, and a fourth insulating layer is formed on the side of the second metal layer facing away from the substrate. The third gate is electrically connected to the second metal layer through a via in the fourth insulating layer, and the third gate is electrically connected to the third metal layer through vias in the fourth insulating layer, the third insulating layer, and the second insulating layer.

[0190] In this embodiment, a third source of the thin-film transistor is formed on the side of the oxide semiconductor layer facing away from the substrate, and the third source is electrically connected to the oxide semiconductor layer; a third drain of the thin-film transistor is formed on the side of the oxide semiconductor layer facing away from the substrate, and the third drain is electrically connected to the oxide semiconductor layer; a third gate of the thin-film transistor is formed on the side of the second metal layer facing away from the substrate, and the third gate is electrically connected to the second metal layer, and the third gate passes through a via and is electrically connected to the third metal layer. This forms a DG structure thin-film transistor, and the switching on and off of the thin-film transistor can be controlled by applying different potential electric fields to the third gate of the DG structure thin-film transistor.

[0191] In an optional embodiment, one or more inorganic layers, namely the first inorganic layer, consisting of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), and silicon oxynitride (SiON), are formed between the substrate and the first metal layer. At least one buffer layer and at least one protective layer made of polyimide material are formed between the substrate and the first inorganic layer.

[0192] It should be understood that although the steps in the flowchart are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0193] One embodiment of this application provides a thin-film transistor, which is fabricated using the thin-film transistor fabrication method provided in the above embodiment.

[0194] The thin-film transistor provided in this embodiment is fabricated using the method for fabricating thin-film transistors as described in the above embodiments. This thin-film transistor has all the beneficial effects of the method for fabricating thin-film transistors, which will not be repeated here.

[0195] One embodiment of this application provides a display panel, which includes a plurality of thin-film transistors as provided in the above embodiments.

[0196] The display panel provided in this embodiment includes a plurality of thin-film transistors as provided in the above embodiments. Therefore, the display panel has all the beneficial effects of thin-film transistors, which will not be repeated here.

[0197] In an optional embodiment, the display panel includes thin-film transistors with TG structure, BG structure, and DG structure. A schematic cross-sectional view of the display panel is shown below. Figure 10 As shown.

[0198] The display panel includes a substrate 1, a buffer layer 2 disposed on one side of the substrate 1, a first metal layer 7a formed on the side of the buffer layer 2 opposite to the substrate 1, a first insulating layer 3 formed on the side of the first metal layer 7a opposite to the substrate 1, a third metal layer 7b formed on the side of the first insulating layer 3 opposite to the substrate 1, a second insulating layer 4 formed on the side of the third metal layer 7b opposite to the substrate 1, an oxide semiconductor layer 5 formed on the side of the second insulating layer 4 opposite to the substrate 1, a third insulating layer 6 formed on the side of the oxide semiconductor layer 5 opposite to the substrate 1, and a third insulating layer 6 formed on the side of the third insulating layer 6 opposite to the substrate 1. A second metal layer 7c is formed on one side, a fourth insulating layer 11 is formed on the side of the second metal layer 7c away from the substrate 1, a first source 9a, a first gate 9b and a first drain 9c of a TG structure thin film transistor is formed on the side of the fourth insulating layer 11 away from the substrate 1, a second source 8a, a second gate 8b and a second drain 8c of a BG structure thin film transistor is formed on the side of the fourth insulating layer 11 away from the substrate 1, and a third source 10a, a third gate 10b and a third drain 10c of a DG structure thin film transistor is formed on the side of the fourth insulating layer 11 away from the substrate 1.

[0199] The dimensions of the overlapping region between the oxide semiconductor layer and the second metal layer in the thin-film transistor of the display panel are as follows: Figure 11 As shown. The length in the first direction X of the overlapping region is the channel length of the thin-film transistor, and the length in the second direction Y is the channel width of the thin-film transistor.

[0200] One embodiment of this application provides a display device including a display panel as described in the above embodiments. The display device can be a laptop computer, mobile phone, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display), navigator, cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, etc.

[0201] The display device provided in this application includes a display panel, and the display device has all the beneficial effects of the display panel, which will not be repeated here.

[0202] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0203] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for determining parameter information of a thin-film transistor, characterized in that, The method includes: Obtain the design parameters of the thin-film transistor; the design parameters include at least one of threshold voltage, channel width, channel length, the ratio of channel width to channel length, and fabrication process factor; Based on the design parameters and the design formula corresponding to the thin-film transistor, the target parameter information is determined; the design formula represents the correlation between threshold voltage, channel width, channel length, the ratio of channel width to channel length, and fabrication process coefficients. The design formula is determined according to the type of the thin-film transistor; the design formulas corresponding to different types of thin-film transistors include different sets of coefficients, and the sets of coefficients include multiple different coefficients; The design relationship includes a first relationship, a second relationship, and a third relationship. The first relationship represents the correlation between the threshold voltage, the fabrication process coefficient, the channel length, and the ratio of the channel width to the channel length. The second relationship represents the correlation between the channel length and the ratio of the channel width to the channel length. The third relationship represents the correlation between the channel width, the channel length, and the ratio of the channel width to the channel length.

2. The method according to claim 1, characterized in that, The step of determining the target parameter information based on the design parameters and the design relationship corresponding to the thin-film transistor includes: The channel width and channel length in the design parameters are input into the design formula for calculation, and the change information between the threshold voltage and the fabrication process coefficient is output. Alternatively, the manufacturing process coefficients in the design parameters can be input into the design formula for calculation, and the variation information between the threshold voltage, the channel width, and the channel length can be output. Alternatively, the fabrication process coefficients in the design parameters can be input into the design formula for calculation, and the change information between the threshold voltage and the ratio of the channel width to the channel length can be output.

3. The method according to claim 1, characterized in that, The step of determining the target parameter information based on the design parameters and the design relationship corresponding to the thin-film transistor includes: The threshold voltage, the ratio of the channel width to the channel length, and the fabrication process coefficient from the design parameters are input into the design formula for calculation, and the channel width and channel length are output.

4. A method for fabricating a thin-film transistor, characterized in that, The method includes: Thin-film transistors are fabricated based on the channel width and channel length; the channel width and channel length are calculated using the parameter information determination method for thin-film transistors according to any one of claims 1-3.

5. The method according to claim 4, characterized in that, The process of fabricating a thin-film transistor based on the channel width and channel length includes: Provide substrate; A first metal layer is formed on one side of the substrate; an oxide semiconductor layer is formed on the side of the first metal layer opposite to the substrate; a second metal layer is formed on the side of the oxide semiconductor layer opposite to the substrate; the size of the overlapping area between the oxide semiconductor layer and the second metal layer is determined according to the channel width and the channel length. The three electrodes of the thin-film transistor are formed on the side of the oxide semiconductor layer opposite to the substrate.

6. The method according to claim 5, characterized in that, A first metal layer is formed on one side of the substrate; An oxide semiconductor layer is formed on the side of the first metal layer facing away from the substrate; a second metal layer is formed on the side of the oxide semiconductor layer facing away from the substrate, comprising: A first metal layer is formed on one side of the substrate; a first insulating layer and a second insulating layer are sequentially formed on the side of the first metal layer opposite to the substrate. The oxide semiconductor layer is formed on the side of the second insulating layer opposite to the substrate; A third insulating layer is formed on the side of the oxide semiconductor layer opposite to the substrate, and a second metal layer is formed on the side of the third insulating layer opposite to the substrate.

7. The method according to claim 5, characterized in that, The three electrodes of the thin-film transistor formed on the side of the oxide semiconductor layer opposite to the substrate include: The first source of the thin-film transistor is formed on the side of the oxide semiconductor layer opposite to the substrate, and the first source and the oxide semiconductor layer are electrically connected to the first metal layer through a via. The first drain of the thin-film transistor is formed on the side of the oxide semiconductor layer opposite to the substrate, and the first drain is electrically connected to the oxide semiconductor layer; A first gate of the thin-film transistor is formed on the side of the second metal layer opposite to the substrate, and the first gate is electrically connected to the second metal layer.

8. The method according to claim 7, characterized in that, The oxide semiconductor layer forms the three electrodes of the thin-film transistor on the side opposite to the substrate, and further includes: A fourth insulating layer is formed on the side of the first source, the first gate, and the first drain near the substrate.

9. The method according to claim 5, characterized in that, The three electrodes of the thin-film transistor formed on the side of the oxide semiconductor layer opposite to the substrate further include: The second source of the thin-film transistor is formed on the side of the oxide semiconductor layer opposite to the substrate. The second source is electrically connected to the oxide semiconductor layer and is electrically connected to the first metal layer through a via. A second gate of the thin-film transistor is formed on the side of the second metal layer opposite to the substrate; the second gate is electrically connected to the second metal layer and to the second source. The second drain of the thin-film transistor is formed on the side of the oxide semiconductor layer opposite to the substrate, and the second drain is electrically connected to the oxide semiconductor layer.

10. The method according to claim 6, characterized in that, The step of sequentially forming a first insulating layer and a second insulating layer on the side of the first metal layer opposite to the substrate includes: The first insulating layer is formed on the side of the first metal layer opposite to the substrate; A third metal layer is formed on the side of the first insulating layer that is away from the substrate; The second insulating layer is formed on the side of the third metal layer opposite to the substrate.

11. The method according to claim 4, characterized in that, The process of fabricating a thin-film transistor based on the channel width and channel length includes: Provide substrate; A third metal layer is formed on one side of the substrate; an oxide semiconductor layer is formed on the side of the third metal layer opposite to the substrate; a second metal layer is formed on the side of the oxide semiconductor layer opposite to the substrate; the size of the overlapping area between the oxide semiconductor layer and the second metal layer is determined according to the channel width and the channel length. The three electrodes of the thin-film transistor are formed on the side of the oxide semiconductor layer opposite to the substrate.

12. The method according to claim 11, characterized in that, The three electrodes of the thin-film transistor formed on the side of the oxide semiconductor layer opposite to the substrate include: The third source of the thin-film transistor is formed on the side of the oxide semiconductor layer opposite to the substrate, and the third source is electrically connected to the oxide semiconductor layer; The third drain of the thin-film transistor is formed on the side of the oxide semiconductor layer opposite to the substrate, and the third drain is electrically connected to the oxide semiconductor layer; A third gate of the thin-film transistor is formed on the side of the second metal layer opposite to the substrate. The third gate is electrically connected to the second metal layer and is electrically connected to the third metal layer through a via.

13. A thin-film transistor, characterized in that, The thin-film transistor is fabricated using the method described in any one of claims 4-12.

14. A display panel, characterized in that, The display panel includes a plurality of thin-film transistors as described in claim 13.

15. A display device, characterized in that, Includes the display panel as described in claim 14.

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