Integrated circuit layout design method and system, readable storage medium and electronic equipment

Abstract

The invention provides an integrated circuit layout design method and system, a readable storage medium and electronic equipment, and relates to the technical field of layout design. Comprises: generating a corresponding instance according to a parameter of a target structure; generating an automatic parasitic parameter extraction script according to the target variable; embedding the automatically extracted parasitic parameter script into the instance and setting an association mechanism; when the target instance is created or updated in the integrated circuit layout, calling an automatic parasitic parameter extraction script through an association mechanism to automatically extract a real-time variable when the target instance is created or updated in the integrated circuit layout, and calculating to obtain a corresponding real-time parasitic parameter; and finally, the real-time parasitic parameters are fed back, and a next target instance is created or the target instance is updated again according to a feedback result. According to the method, the parasitic parameters are accurately extracted and calculated, technical support is provided for accurately and rapidly extracting and calculating the parasitic parameters, the real-time performance and accuracy of the parasitic parameters are ensured, and the problem that the integrated circuit layout design efficiency and precision are low is effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of layout design technology, and in particular to an integrated circuit layout design method, an integrated circuit layout design system, a readable storage medium and an electronic device. Background Art

[0002] As integrated circuits, especially analog integrated circuits, continue to develop towards high precision, high speed and high integration, the requirements for their layout design are increasing.

[0003] In traditional integrated circuit layout design, especially analog integrated circuit layout design, each component needs to be drawn manually, which is not only inefficient but also prone to errors. Although there are technical solutions that make some simple components into parameterized units or instances, which have improved the efficiency of integrated circuit layout design to a certain extent, the parasitic parameters of complex structures, especially the extraction and calculation of parasitic parameters in integrated circuit layouts, still rely on manual or simple tools. It is difficult to accurately and quickly extract and calculate the corresponding parasitic parameters in complex integrated circuit layouts, resulting in low efficiency and accuracy of traditional design methods in integrated circuit design. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide an integrated circuit layout design method, an integrated circuit layout design system, a readable storage medium and an electronic device that solve the above problems or partially solve the above problems.

[0005] A first aspect of an embodiment of the present invention provides an integrated circuit layout design method, the integrated circuit layout design method comprising: Generate corresponding instances according to the parameters of the target structure; Generate an automatic parasitic parameter extraction script according to the target variable; wherein the target variable is all parameters that affect the parasitic parameters when the target structure is created or updated in the integrated circuit layout; Embedding the automatic parasitic parameter extraction script into the instance and setting an association mechanism; When the target instance is created or updated in the integrated circuit layout, the automatic parasitic parameter extraction script is called through the association mechanism to automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout and calculate the corresponding real-time parasitic parameters; Feedback the real-time parasitic parameters, and create the next target instance or update the target instance again according to the feedback result, and execute the steps: call the automatic parasitic parameter extraction script through the association mechanism, automatically extract the real-time variables when the next target instance is created or the target instance is updated in the integrated circuit layout, and calculate the corresponding real-time parasitic parameters.

[0006] Optionally, generate a corresponding instance according to the parameters of the target structure, including: Based on the parameter information of the main device in the target structure and in combination with the preset layout design rules, determine the parameter information of the auxiliary device in the target structure; An instance corresponding to the target structure is generated according to the parameter information of the primary component and the parameter information of the secondary component.

[0007] Optionally, a script for automatically extracting parasitic parameters is generated according to the target variable, including: Determining the target variable in the parameter information of the main device and the parameter information of the auxiliary device based on respective operation modes of the parasitic parameters; By using a preset tool or a preset language, the operation mode is defined in the automatic parasitic parameter extraction script and an operation mechanism is set; The trigger mechanism of the target variable when each instance is created or updated in the integrated circuit layout is set through the preset tool or the preset language.

[0008] Optionally, set an association mechanism, including: The operation mechanism is combined with the trigger mechanism through the preset tool or the preset language to form the association mechanism.

[0009] Optionally, setting a trigger mechanism for the target variable when each instance is created or updated in the integrated circuit layout includes: By means of the preset tool or the preset language, an initialization function and an update function are set in each of the instances; Registering an event listener in the initialization function and the update function respectively through the preset tool or the preset language; Wherein, the initialization function is used for initialization of each instance when it is created in the integrated circuit layout; The update function is used to update the parameters of each instance after it is created in the integrated circuit layout; The event listener is used to monitor whether the target variable is created or updated when each instance is created or updated, and trigger the association mechanism when it is determined that the target variable is created or updated.

[0010] Optionally, the operation mechanism is combined with the trigger mechanism to form the association mechanism, including: By means of the preset tool or the preset language, after the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the created or updated variables from the created or updated instance; Through the preset tool or the preset language, it is arranged that after extracting the created or updated variables, the operation is performed using the operation mechanism.

[0011] Optionally, when the target instance is created or updated in the integrated circuit layout, the automatic parasitic parameter extraction script is called through the association mechanism to automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout and calculate the corresponding real-time parasitic parameters, including: When the target instance is created or updated in the integrated circuit layout, the event listener triggers the association mechanism; After the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the created or updated real-time variables from the created or updated target instance; After extracting the created or updated real-time variables, the automatic parasitic parameter extraction script uses the calculation mechanism to perform calculations through calculation formulas corresponding to the created or updated real-time variables to obtain corresponding real-time parasitic parameters.

[0012] Optionally, the real-time parasitic parameter is fed back, and a next target instance is created or the target instance is updated again according to the feedback result, including: Feedback the real-time parasitic parameters, and automatically determine whether the real-time parasitic parameters meet the design requirements in combination with the design rules, or manually determine whether the real-time parasitic parameters meet the design requirements; If the real-time parasitic parameters meet the design requirements, creating a next target instance; If the real-time parasitic parameters do not meet the design requirements, the target instance is updated again.

[0013] Optionally, a script for automatically extracting parasitic parameters is generated according to the target variable, including: By using a preset tool or a preset language, constraints are set for each of the target variables in the automatic parasitic parameter extraction script.

[0014] Optionally, when the target instance is created or updated in the integrated circuit layout, the automatic parasitic parameter extraction script is called through the association mechanism to automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout and calculate the corresponding real-time parasitic parameters, including: When the target instance is updated in the integrated circuit layout, the event listener triggers the association mechanism; After the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract updated real-time variables from the updated target instance; After extracting the updated real-time variables, the automatic parasitic parameter extraction script uses the constraint conditions to determine the updated real-time variables; If the updated real-time variable satisfies the constraint condition, the automatic parasitic parameter extraction script uses the calculation mechanism to calculate the corresponding real-time parasitic parameter through the calculation formula corresponding to the updated real-time variable; If the updated real-time variables do not satisfy the constraint conditions, the automatic parasitic parameter extraction script feeds back an error alarm and displays the erroneous real-time variables.

[0015] A second aspect of an embodiment of the present invention provides an integrated circuit layout design system, the integrated circuit layout design system comprising: Generate instance module, used to generate corresponding instance according to the parameters of target structure; A script generation module is used to generate an automatic parasitic parameter extraction script according to a target variable; wherein the target variable is all parameters that affect the parasitic parameters when the target structure is created or updated in the integrated circuit layout; An embedding association module, used for embedding the automatic parasitic parameter extraction script into the instance and setting an association mechanism; An extraction calculation module, used for calling the automatic parasitic parameter extraction script through the association mechanism when the target instance is created or updated in the integrated circuit layout, automatically extracting the real-time variables when the target instance is created or updated in the integrated circuit layout and calculating the corresponding real-time parasitic parameters; A feedback execution module is used to feed back the real-time parasitic parameters, and create a next target instance or update the target instance again according to the feedback result, and execute the steps of: calling the automatic parasitic parameter extraction script through the association mechanism, automatically extracting the real-time variables when the next target instance is created or the target instance is updated in the integrated circuit layout, and calculating the corresponding real-time parasitic parameters.

[0016] Optionally, the instance generation module is specifically used for: Based on the parameter information of the main device in the target structure and in combination with the preset layout design rules, determine the parameter information of the auxiliary device in the target structure; An instance corresponding to the target structure is generated according to the parameter information of the primary component and the parameter information of the secondary component.

[0017] Optionally, the script generation module includes: A variable determination submodule, configured to determine the target variable in the parameter information of the main device and the parameter information of the auxiliary device based on respective operation modes of respective parasitic parameters; A submodule for defining an operation mechanism is used to define the operation mode into the automatic parasitic parameter extraction script and set the operation mechanism through a preset tool or a preset language; The trigger mechanism setting submodule is used to set the trigger mechanism of the target variable when each instance is created or updated in the integrated circuit layout through the preset tool or the preset language.

[0018] Optionally, the embedding association module is specifically used for: By using the preset tool or the preset language, the operation mechanism is combined with the trigger mechanism to form the association mechanism; specifically including: By means of the preset tool or the preset language, after the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the created or updated variables from the created or updated instance; Through the preset tool or the preset language, it is arranged that after extracting the created or updated variable, the operation is performed using the operation mechanism. .

[0019] Optionally, the trigger mechanism setting submodule is specifically used for: By means of the preset tool or the preset language, an initialization function and an update function are set in each of the instances; Registering an event listener in the initialization function and the update function respectively through the preset tool or the preset language; Wherein, the initialization function is used for initialization of each instance when it is created in the integrated circuit layout; The update function is used to update the parameters of each instance after it is created in the integrated circuit layout; The event listener is used to monitor whether the target variable is created or updated when each instance is created or updated, and trigger the association mechanism when it is determined that the target variable is created or updated.

[0020] Optionally, the extraction calculation module is specifically used for: When the target instance is created or updated in the integrated circuit layout, the event listener triggers the association mechanism; After the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the created or updated real-time variables from the created or updated target instance; After extracting the created or updated real-time variables, the automatic parasitic parameter extraction script uses the calculation mechanism to perform calculations through calculation formulas corresponding to the created or updated real-time variables to obtain corresponding real-time parasitic parameters.

[0021] Optionally, the feedback execution module is specifically used to: Feedback the real-time parasitic parameters, and automatically determine whether the real-time parasitic parameters meet the design requirements in combination with the design rules, or manually determine whether the real-time parasitic parameters meet the design requirements; If the real-time parasitic parameters meet the design requirements, creating a next target instance; If the real-time parasitic parameters do not meet the design requirements, the target instance is updated again.

[0022] Optionally, the script generation module is further specifically used for: By using a preset tool or a preset language, constraints are set for each of the target variables in the automatic parasitic parameter extraction script.

[0023] Optionally, the extraction calculation module is further specifically used for: When the target instance is updated in the integrated circuit layout, the event listener triggers the association mechanism; After the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract updated real-time variables from the updated target instance; After extracting the updated real-time variables, the automatic parasitic parameter extraction script uses the constraint conditions to determine the updated real-time variables; If the updated real-time variable satisfies the constraint condition, the automatic parasitic parameter extraction script uses the calculation mechanism to calculate the corresponding real-time parasitic parameter through the calculation formula corresponding to the updated real-time variable; If the updated real-time variables do not satisfy the constraint conditions, the automatic parasitic parameter extraction script feeds back an error alarm and displays the erroneous real-time variables.

[0024] A third aspect of an embodiment of the present invention provides a readable storage medium having a program stored thereon, which, when executed by a processor, implements the integrated circuit layout design method as described in any one of the first aspects.

[0025] A fourth aspect of an embodiment of the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a program; the processor is used to execute the program stored in the memory, and when the program is run, the processor executes any integrated circuit layout design method described in the first aspect.

[0026] The integrated circuit layout design method provided by the present invention comprises: firstly generating a corresponding instance according to the parameters of the target structure; then generating an automatic parasitic parameter extraction script according to the target variable; wherein the target variable is all parameters that affect the parasitic parameters when the target structure is created or updated in the integrated circuit layout. That is, the automatic parasitic parameter extraction script includes all parameters in the target structure that may affect the parasitic parameters.

[0027] Then, the automatic parasitic parameter extraction script is embedded in the instance and an association mechanism is set; when the target instance is created or updated in the integrated circuit layout, the automatic parasitic parameter extraction script is called through the association mechanism to automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout and calculate the corresponding real-time parasitic parameters; finally, the real-time parasitic parameters are fed back, and the next target instance is created or updated again according to the feedback result, and the execution steps are: calling the automatic parasitic parameter extraction script through the association mechanism to automatically extract the real-time variables when the next target instance is created in the integrated circuit layout, or automatically extract the real-time variables when the original target instance is updated in the integrated circuit layout, and calculate the corresponding real-time parasitic parameters.

[0028] The integrated circuit layout design method proposed in the present invention creatively proposes an automatic parasitic parameter extraction script, and incorporates all parameters in the target structure that may affect the parasitic parameters into the automatic parasitic parameter extraction script. Using the automatic parasitic parameter extraction script, when each instance is created in the integrated circuit layout, or when the created instance is updated in the integrated circuit layout, the target variable is automatically extracted and the target variable is calculated by the association mechanism to obtain the corresponding parasitic parameters. Finally, according to the result of the parasitic parameter feedback, subsequent operations are performed: whether to continue to create the next new target instance or to update the original target instance, until all instances are created and the parasitic parameters meet the standards, and the entire integrated circuit layout design is completed. The entire design method can automatically and accurately extract and calculate parasitic parameters, so that more physical effects and layout details can be considered, and technical support is provided for the accurate and rapid extraction and calculation of parasitic parameters, ensuring the real-time and accuracy of the parasitic parameters of the integrated circuit layout, effectively solving the problems of low efficiency and precision in the integrated circuit layout design, and having high practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0030] Figure 1It is an exemplary differential pair and an integrated circuit layout design layout diagram with DUMMY devices placed on both sides in the traditional technology; Figure 2 It is an exemplary current mirror in the conventional technology and an integrated circuit layout design diagram with DUMMY devices placed on both sides thereof; Figure 3 is a flow chart of an integrated circuit layout design method in an embodiment of the present invention; Figure 4 The invention is a block diagram of an integrated circuit layout design system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, are only part of the embodiments of the present invention, not all of the embodiments, and are not used to limit the present invention.

[0032] Integrated circuits, also known as ICs (Intergrated Circuits), can be divided into three categories according to their functions and structures: analog integrated circuits, digital integrated circuits, and mixed analog and digital integrated circuits. Among them, mixed analog and digital integrated circuit design can be divided into two methods: digital package analog design and analog package digital design. Analog package digital design refers to the design method in which the analog layout is used as the whole chip level design, and the digital layout is integrated into the full chip level layout in a modular form. In the layout design of mixed analog and digital integrated circuits, due to the different design tools used in the digital layout and the analog layout, when completing the digital-analog mixing, it is necessary to provide information interaction between the digital layout and the analog layout to complete the integration of both digital and analog.

[0033] At present, digital integrated circuit design has basically approached automation, while the automation of analog integrated circuit design and mixed-analog integrated circuit design is still a challenge. Analog integrated circuit design or mixed-analog integrated circuit design mainly includes two parts: circuit design and layout design. Among them, layout design work is more manual "empiricism" due to its high flexibility and "artistic" characteristics. In this situation, if the relevant tools of layout design can generate high-quality layouts, it can greatly reduce the number of loop iterations of analog circuit engineers and other designers in design and simulation projects, and can also speed up product iteration, improve design efficiency, and increase the probability of successful tape-out.

[0034] Generally speaking, the so-called analog integrated circuit layout design is the design of CMOS analog integrated circuit layout. The so-called CMOS (Complementary Metal Oxide Semiconductor) refers to a technology used to manufacture large-scale integrated circuits or devices manufactured using this technology. It is composed of insulated field effect transistors. Since there is only one type of carrier, it is a unipolar transistor integrated circuit. Its basic structure is an N-channel MOS tube and a P-channel MOS tube.

[0035] MOS tubes (Metal-Oxide-Semiconductor, Metal-Oxide Semiconductor Field Effect Transistor) are generally divided into PMOS tubes and NMOS tubes. The integrated circuit composed of MOS tubes is called MOS integrated circuit, and the complementary MOS integrated circuit composed of PMOS tubes and NMOS tubes is CMOS analog integrated circuit.

[0036] CMOS analog integrated circuit layout design is a process of accurately physically describing the created circuit netlist. This process must simultaneously meet the common constraints of design rules, manufacturing processes, and circuit performance indicators. Compared with digital integrated circuits, CMOS analog integrated circuits are more sensitive to parasitic parameters. Therefore, if the pre-simulation meets the design requirements, the post-simulation may not be able to meet the design requirements. Especially in the deep submicron stage, the impact of parasitic effects on circuits is more obvious. In the process of analog integrated circuit or digital-analog hybrid integrated circuit layout design, there are many application scenarios for various components and their combined structures. The design of these components and their combined structures in the layout, especially the value of parasitic parameters, directly affects the overall performance of the circuit.

[0037] Based on the above-mentioned analog integrated circuit layout design or digital-analog hybrid integrated circuit layout design process, the inventors found in the long-term design process that in traditional integrated circuit layout design, especially analog integrated circuit layout design, each component needs to be drawn manually, which is not only inefficient but also prone to errors.

[0038] At present, there are some technical solutions to solve the problems of traditional manual drawing and design of integrated circuit layout by making some simple components and their combined structures into parameterized units or instances, which improves the efficiency of integrated circuit layout design to a certain extent.

[0039] For example: different types of MOS tubes and their combination structures commonly used in analog integrated circuit layout design or digital-analog mixed integrated circuit layout design can be made into multiple parameterized units or instances using relevant tools. In this way, these parameterized units or instances can be directly called during the integrated circuit layout design process without having to design differential pairs from scratch each time, saving a lot of time and energy and improving the efficiency of integrated circuit layout design to a certain extent.

[0040] Take the differential pair structure as an example: differential input is the basic pre-stage input for almost all general-purpose analog integrated circuits due to its extremely high common-mode rejection capability, and is also the basis of modern signal transmission theory. In analog integrated circuits or mixed analog and digital integrated circuits, differential input is generally implemented in the form of a differential pair formed by a combination of MOS tubes.

[0041] The simplest MOS tube differential pair is composed of two completely matched MOS tubes. For example, the current mirror structure is a typical differential pair. For any differential pair, the key parameters of the differential pair can be clearly defined, such as the type, size, spacing, wiring rules, etc. of the MOS tubes in the differential pair. At the same time, the type, size and layout rules of DUMMY devices (a special structure used to fill unused areas in integrated circuits to ensure that the structure and performance of other parts can be maintained. These fillers are usually made of the same material as MOS tubes, but they are not used for any circuit or logic function) are analyzed to meet the process requirements for density and symmetry.

[0042] By defining the parameters of MOS tubes and DUMMY devices, differential pairs can be used as parameterized units or instances for flexible use in different design scenarios. In the design of integrated circuit layouts, various characteristics of differential pairs are controlled by defining parameter variables during the creation process, such as MOS tube length, width, gate connection method, spacing, etc. At the same time, in order to achieve automatic addition of DUMMY devices, the density of the area where the differential pairs are located in the integrated circuit layout is monitored in real time. When the density is lower than the set threshold, DUMMY devices are automatically generated at appropriate locations according to pre-set rules. This rule may include: DUMMY devices and effective devices, that is, the spacing between MOS tubes in the differential pair, arrangement direction and quantity, their own size, etc., to ensure the symmetry of the integrated circuit layout and the stability of the process. A large number of tests can also be performed after completing the preliminary development of differential pairs and automatic addition of DUMMY devices. Test the performance of differential pairs under different parameter combinations, as well as the accuracy and effectiveness of adding DUMMY devices. According to the test results, optimize and adjust the parameter settings of parameterized units or instances and the algorithm for automatically adding DUMMY devices.

[0043] Reference Figure 1An exemplary differential pair and an integrated circuit layout design layout diagram with DUMMY devices placed on both sides thereof are shown. Figure 1 The differential pairs are arranged in the form of ABBABAAB, D represents the DUMMY device, X represents the horizontal parameter setting of the DUMMY device and the effective MOS tube, which can be placed according to actual needs and can be set to 0 to merge one end with the effective MOS tube, Y is the vertical spacing parameter between the differential pair MOS tubes, W and L are the width and length of the MOS tube respectively, which are determined according to the circuit parameters.

[0044] Reference Figure 2 An exemplary current mirror and an integrated circuit layout design diagram with DUMMY devices placed on both sides thereof are shown, Figure 2 The current mirror is arranged in an ABAB form, D represents the DUMMY device, X represents the setting of the horizontal parameters of the DUMMY device and the effective MOS tube, which can be placed according to actual needs and can be set to 0 to merge one end with the effective MOS tube, Y is the vertical spacing parameter between the differential pair MOS tubes, W and L are the width and length of the MOS tube respectively, which are determined according to the circuit parameters.

[0045] Above Figure 1 ABBABAAB differential pair shown, and Figure 2 The current mirrors shown can each be defined as a parameterized unit or instance. In the process of integrated circuit layout design, they can be directly called. Combined with the addition rules of DUMMY devices, the differential pair can be effectively made into a callable parameterized unit or instance and DUMMY devices can be automatically added, thus improving the efficiency and quality of analog integrated circuit layout design.

[0046] In addition, parameters can also be updated after calling. For example, the width of the MOS tube in the differential pair as a parameterized unit or instance is initially defined as 20 microns. If it is not updated, then if it is called directly, the width of the MOS tube on the designed integrated circuit layout will be 20 microns, while the actual required MOS tube width is 50 microns. Therefore, the width parameter of the MOS tube can be updated to 50 microns, thus meeting the actual needs.

[0047] The inventors further studied and found that, although the above technical solution has improved the efficiency of integrated circuit layout design to a certain extent, the parasitic parameters of complex structures, especially the extraction and calculation of parasitic parameters in integrated circuit layout, are still realized by manual or simple tools in the prior art. It is difficult to accurately and quickly extract and calculate the corresponding parasitic parameters in complex integrated circuit layouts, resulting in low efficiency and accuracy of traditional design methods in integrated circuit design.

[0048] Based on the above problems, the inventor creatively proposed an integrated circuit layout design method, an integrated circuit layout design system, a readable storage medium and an electronic device of the present invention. The technical solution of the present invention is explained and illustrated in detail below.

[0049] The integrated circuit layout design method of the embodiment of the present invention refers to Figure 3 The integrated circuit layout design method flow chart shown in FIG. 1 includes: Step 301: Generate a corresponding instance according to the parameters of the target structure.

[0050] To achieve the purpose of the present invention, it is first necessary to generate corresponding instances according to the parameters of the target structure. The so-called target structure can be the devices and their combination structures commonly used in integrated circuit layout design, such as the MOS tube, differential pair, current mirror, etc. described above, and relatively complex amplifiers, comparators, etc., which can all be target structures. Based on these target structures, corresponding instances are generated, which can be directly called in the subsequent integrated circuit layout design process without manual drawing one by one. If there are different needs, the parameters can be simply updated according to the actual needs.

[0051] In one embodiment of the present invention, there are multiple ways to generate corresponding instances, wherein a preferred way to generate corresponding instances according to the parameters of the target structure includes: First, based on the parameter information of the main device in the target structure and combined with the preset layout design rules, determine the parameter information of the auxiliary device in the target structure. The main device is the effective device, and the auxiliary device is the auxiliary device, which does not realize the corresponding function. For example, the MOS tube in the differential pair described above can be regarded as the main device, and the DUMMY device can be regarded as the auxiliary device. Generally, the parameter information of the auxiliary device needs to be determined based on the parameter information of the main device and combined with the integrated circuit layout design rules. Of course, it is understandable that in some special cases, the parameter information of the auxiliary device may not only be obtained in this way, but in either case, it is necessary to obtain the parameter information of the main device and the auxiliary device.

[0052] After obtaining the parameter information of the main device and the parameter information of the auxiliary device, an instance corresponding to the target structure can be generated according to the parameter information of the main device and the parameter information of the auxiliary device. Figure 1 , Figure 2 The corresponding instances of the ABBABAAB differential pair and the ABAB current mirror are generated in a corresponding manner.

[0053] Step 302: Generate an automatic parasitic parameter extraction script based on the target variable; wherein the target variable is all parameters that affect the parasitic parameters when the target structure is created or updated in the integrated circuit layout.

[0054] After generating the instance corresponding to the target structure, it is necessary to generate the automatic parasitic parameter extraction script based on the target variables. The so-called target variables refer to all the parameters that affect the parasitic parameters when the target structure is created or updated in the integrated circuit layout.

[0055] Parasitic parameters: refers to non-essential elements present in electronic components or circuits, which will have an adverse effect on the normal operation of the components or circuits. It usually manifests itself as problems such as consuming power energy, limiting signal transmission rate or affecting signal quality. The generation of parasitic parameters needs to be reduced or avoided as much as possible. They generally include: parasitic capacitance, parasitic resistance, and parasitic inductance. Parasitic capacitance is generally composed of planar capacitance between wires (same layer or different layers), between wires and substrates, and edge capacitance from upper wires to lower wires, and from lower wires to substrates. Generally, due to the small size of the wires, the value of parasitic capacitance is also small. However, as long as high frequency is involved (most of the current integrated circuits involve high frequency), parasitic capacitance will become one of the main factors affecting the performance of integrated circuits.

[0056] Parasitic resistance is generally generated by wires. The wire width can be selected by the current density, and the current size will affect the wiring scheme between units. Since each layer of metal wire can carry different currents, the required metal layer width can be calculated by the current density parameter. For example, if a signal line needs to carry 1 mA of current, and each micron of the signal line can carry 0.5 mA of current, then the width of this signal line must be at least 2 microns.

[0057] Based on the basic IR drop principle, we know that: Assuming that the square resistance Rsqu of the wire is 0.0522 and the length is 2mm, then: R= Rsqu*L / W=0.052*(2mm / 2um)=50Ω.

[0058] And V=IR= 50Ω*1mA= 50 mV.

[0059] So the voltage is calculated to be 50 millivolts. It will have a great impact on a circuit that is very sensitive to voltage. If the voltage drop of this wire cannot exceed 10 millivolts, then the design is obviously a failure. So this means that the wire width must be increased to meet this design requirement.

[0060] As for parasitic inductance, when the circuit is working at a really high frequency, the wire also begins to have an inductance effect, which will produce parasitic capacitance.

[0061] As for MOS tubes, they also have parasitic capacitance: gate capacitance and diffusion capacitance, etc. No matter which parasitic parameters, they may introduce additional delays, causing the signal to propagate slower in the circuit, thus affecting the overall performance of the circuit. Noise may also be introduced, such as switching noise caused by inductive coupling, which will reduce the reliability of the circuit and may even cause circuit failure. It may also change the energy consumption and power distribution in the circuit, causing excessive power consumption in some parts, affecting the efficiency and stability of the circuit.

[0062] At present, the methods for extracting and calculating parasitic parameters in integrated circuit layout include: 1) Direct calculation: For some simple parasitic parameters, such as capacitors and inductors, they can be directly calculated using physical formulas. For example, capacitance can be calculated using the relationship between dielectric constant, area, and distance, while inductance can be calculated using parameters such as wire length, diameter, and number of turns.

[0063] 2) Simulation software extraction: Using professional circuit simulation software, such as SPICE, you can simulate and analyze the circuit and extract parasitic parameters.

[0064] 3) Measurement method: The values ​​of parasitic parameters can be obtained through actual circuit measurement.

[0065] Some of the above-mentioned parasitic parameter extraction and calculation methods are concise and direct, but they are not suitable for integrated circuit layout. Some may also require special measurement equipment and techniques, and it may be difficult to accurately extract and calculate some tiny parasitic parameters.

[0066] To this end, the inventor creatively proposed to generate an automatic parasitic parameter extraction script based on the target variable. The so-called target variable is all the parameters in the target structure that may affect the parasitic parameters. For example, for a differential pair, the width and length of each MOS tube will affect the parasitic parameters, so the width and length of each MOS tube will be used as the target variable; for a metal line, its length and width will also affect the parasitic parameters, so the width and length of the metal line will also be used as the target variable.

[0067] At the same time, since the automatic parasitic parameter extraction script also needs to have the ability to calculate parasitic parameters, and the calculation methods of parasitic parameters corresponding to different devices are different, the calculation ability of the automatic parasitic parameter extraction script also needs to be considered.

[0068] In one embodiment of the present invention, a preferred method for generating an automatic parasitic parameter extraction script according to a target variable includes: Based on the calculation methods of each parasitic parameter, the target variable is determined in the parameter information of the main device and the parameter information of the auxiliary device. For example, for the parasitic capacitance of the metal plate, it is related to the metal line area, spacing and dielectric constant: parasitic capacitance C = εS / d, ε is the dielectric constant, S is the relative effective area of ​​the two metal plates, and d is the distance between the two metal plates. Then the dielectric constant ε, the relative effective area S of the two metal plates, and the distance d between the two metal plates are the target variables.

[0069] Among the target variables corresponding to the parasitic capacitance of the above metal plates, the effective area S and distance d may not be directly extracted by the automatic parasitic parameter extraction script in the integrated circuit layout, but are obtained indirectly. Therefore, the automatic parasitic parameter extraction script also has the function of extracting indirect variables and obtaining target variables through indirect variables. For example: the effective area S can be obtained based on the relative length and width of the two metal plates. Therefore, the relative length and width of the two metal plates are indirect variables. Multiplying the two together can obtain the target variable: effective area.

[0070] After determining the target variable, the operation mode is defined in the automatic parasitic parameter extraction script and the operation mechanism is set through the preset tool or preset language. In the embodiment of the present invention, the so-called preset tool or preset language refers to the relevant tools or languages ​​involved in the integrated circuit layout design. For example: EDA (Electronic Design Automation, Chinese called electronic design automation) tool, which is a technical field covering the entire process of electronic design, simulation, verification, and manufacturing. EDA technology includes system design and simulation, circuit design and simulation, printed circuit board (PCB) design and verification, integrated circuit (IC) layout design, verification and testing, digital logic circuit design, analog circuit design, digital-analog hybrid design, embedded system design, software and hardware collaborative design, system on chip (SoC) design, programmable logic device (PLD) and programmable system chip (SOPC) design, application-specific integrated circuit (ASIC) and application-specific standard product (ASSP) design technology, etc. For example: SKILL language, which is an advanced, interactive programming language, is a key tool for the Cadence software platform for secondary development and automated design processes. SKILL is based on the LISP (List Processing) language and is used to develop custom scripts and macros in the EDA tool suite of Cadence Design Systems. It is a powerful scripting language used to automate and extend the functionality of EDA tools, including Virtuoso, Encounter, Allegro, etc.

[0071] Therefore, by using the above-mentioned preset tools or preset languages, the operation methods corresponding to the parasitic parameters can be defined in the automatic parasitic parameter extraction script and the operation mechanism can be set; at the same time, having only the operation mechanism is not enough, considering that there will be corresponding parasitic parameters when the target variable is created or updated, it is also necessary to set the trigger mechanism of the target variable when each instance is created or updated in the integrated circuit layout through the preset tools or preset languages.

[0072] Step 303: embed the automatic parasitic parameter extraction script into the instance and set the association mechanism.

[0073] After the above-mentioned automatic parasitic parameter extraction script is generated, it is also necessary to embed the automatic parasitic parameter extraction script into the instance and set the association mechanism. Since the automatic parasitic parameter extraction script only has an operation mechanism, it is not enough. It also needs to have the function of automatically extracting when the target variable is created or updated before it can perform operations. Therefore, through a preset tool or a preset language, a trigger mechanism is set when the target variable is created or updated in the integrated circuit layout at each instance. In this way, the operation mechanism is combined with the trigger mechanism through a preset tool or a preset language to form an association mechanism. The combination of the two can realize the predetermined function of the automatic parasitic parameter extraction script.

[0074] In one embodiment of the present invention, a preferred method for setting a trigger mechanism for a target variable when each instance is created or updated in an integrated circuit layout includes: An initialization function and an update function are set in each instance through a preset tool or a preset language; an event listener is registered in the initialization function and the update function respectively through a preset tool or a preset language; that is, an event listener is registered in the initialization function, and an event listener is also registered in the update function.

[0075] Among them, the so-called initialization function is used to initialize each instance when it is created in the integrated circuit layout. That is, when each instance is created in the integrated circuit layout design, it is created in the integrated circuit layout according to the corresponding parameters when the instance is generated. For example: for a differential pair, assuming that the width-to-length ratio of a certain MOS tube is 6:1, which is a commonly used size in a differential pair, then the corresponding differential pair instance is generated with the width-to-length ratio of 6:1. In the process of integrated circuit layout design, the differential pair instance can be directly called to obtain a differential pair with a width-to-length ratio of 6:1.

[0076] The update function is used to update the parameters of each instance after it is created in the integrated circuit layout. The update function is generally used to update parameters. Since the parameters corresponding to different target structures may be different, it is impossible to generate corresponding instances for each target structure with different parameters. That would be a huge number of instances, and it would not be convenient to search and call during the integrated circuit layout design process. Therefore, the corresponding instances are generally generated with commonly used parameters. When the parameters of the instance do not meet the current design requirements and need to be modified, only the parameters that need to be modified need to be updated. For example: a metal wire is generated as an instance of 1 micron wide and 1 mm long, and the current design requires a metal wire of 0.5 micron wide and 1 mm long. After the metal wire is created, only the parameter of its line width needs to be updated.

[0077] The event listener is used to monitor whether the target variable is created or updated when each instance is created or updated, and trigger the association mechanism when the target variable is determined to be created or updated. Whether the instance is created or updated, the association mechanism needs to be triggered in time. Of course, this requires the creation or update of the target variable. If it does not involve the creation or update of the target variable, there is no need to trigger the association mechanism. For example: the position of a port, but even if the position of the port changes, it will not affect the parasitic parameters, that is, the position of the port is not the target variable, so when the port is created at a certain position or its position changes, the event listener will not trigger the association mechanism.

[0078] In one embodiment of the present invention, a method of combining the operation mechanism with the trigger mechanism to form an association mechanism includes: Through a preset tool or a preset language, it is set that after the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the created or updated variables from the created or updated instance; and through a preset tool or a preset language, it is set that after the created or updated variables are extracted, calculations are performed using the calculation mechanism.

[0079] Step 304: When the target instance is created or updated in the integrated circuit layout, the automatic parasitic parameter extraction script is called through the association mechanism to automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout and calculate the corresponding real-time parasitic parameters.

[0080] After the above steps 301 to 303 are followed to generate an instance, automatically extract a parasitic parameter script, and establish an association mechanism, when the target instance is created or updated in the integrated circuit layout, the automatic parasitic parameter extraction script can be called through the association mechanism to automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout and calculate the corresponding real-time parasitic parameters. Specifically: When the target instance is created or updated in the integrated circuit layout, the event listener triggers the association mechanism; after the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the created real-time variables or updated real-time variables from the created or updated target instance.

[0081] After extracting the created real-time variables or extracting the updated real-time variables, the automatic parasitic parameter extraction script uses the calculation mechanism to calculate the corresponding real-time parasitic parameters through the calculation formula corresponding to the created real-time variables or the updated real-time variables.

[0082] Step 305: Feedback the real-time parasitic parameters, and create the next target instance or update the target instance again according to the feedback results, and execute the steps: call the automatic parasitic parameter extraction script through the association mechanism, automatically extract the real-time variables when the next target instance is created or the target instance is updated in the integrated circuit layout, and calculate the corresponding real-time parasitic parameters.

[0083] After obtaining the real-time parasitic parameters using the automatic parasitic parameter extraction script, the real-time parasitic parameters need to be fed back to determine whether the real-time parameters meet the design requirements, and then create the next target instance or update the target instance again based on the feedback results, and execute the steps: call the automatic parasitic parameter extraction script through the association mechanism, automatically extract the real-time variables when the next target instance is created or updated in the integrated circuit layout, and calculate the corresponding real-time parasitic parameters. This process is repeated until the entire integrated circuit layout design is completed.

[0084] In one embodiment of the present invention, a preferred method for feeding back real-time parasitic parameters and creating a next target instance or updating the target instance again according to the feedback result includes: Feedback the real-time parasitic parameters, and automatically determine whether the real-time parasitic parameters meet the design requirements in combination with the design rules, or manually determine whether the real-time parasitic parameters meet the design requirements. That is, after the real-time parasitic parameters are fed back, there are two ways to determine whether the real-time parasitic parameters meet the design requirements. One is to use the design rules to automatically determine whether the real-time parasitic parameters meet the design requirements by the intelligent device. This method can write the design rules into the intelligent device. The advantages are convenience and speed, and the disadvantages are that the initial workload is large, and the accuracy of the judgment result is relatively poor compared to manual judgment; the other is for professional technicians to manually determine whether the real-time parasitic parameters meet the design requirements. The advantage is that no initial work is required, and the accuracy of the judgment result is better than automatic judgment, but the disadvantage is that the manual workload is large and the efficiency is relatively low.

[0085] The feedback result of the real-time parasitic parameters may meet the design requirements or may not meet the design requirements.

[0086] If the real-time parasitic parameters meet the design requirements, the next target instance is created, that is, the new target instance is continued to be created; if the real-time parasitic parameters do not meet the design requirements, the target instance is updated again, that is, the parameters of the created target instance are updated. Whether creating the next target instance or updating the parameters of the created target instance, step 304 and step 305 need to be performed again.

[0087] In one embodiment of the present invention, considering that some target structure parameters have their own restrictions, such as MOS tube size restrictions, minimum spacing requirements, etc., in order to prevent unreasonable parameter values ​​from being input when updating parameters, another preferred method for generating an automatic parasitic parameter extraction script based on target variables includes: By using preset tools or preset languages, set constraints for each target variable in the automatic parasitic parameter extraction script. That is, the parameter constraints of the target structure itself are used as constraints to prevent incorrect parameter values ​​from being entered when updating the parameters.

[0088] Therefore, when the target instance is updated in the integrated circuit layout, the event listener triggers the association mechanism; after the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the updated real-time variables from the updated target instance; after extracting the updated real-time variables, the automatic parasitic parameter extraction script first uses the constraint conditions to judge the updated real-time variables.

[0089] If the updated real-time variables meet the constraints, the automatic parasitic parameter extraction script uses the calculation mechanism to perform calculations through the calculation formulas corresponding to the updated real-time variables to obtain the corresponding real-time parasitic parameters; if the updated real-time variables do not meet the constraints, the automatic parasitic parameter extraction script will not perform subsequent calculations, but will directly feedback an error alarm and display the erroneous real-time variables to remind the integrated circuit layout designer that the updated parameter values ​​are incorrect and to re-update the target instance.

[0090] Based on the above integrated circuit layout design method, the embodiment of the present invention also provides an integrated circuit layout design system, referring to Figure 4 The block diagram of the integrated circuit layout design system shown in FIG. 1 includes: Generate instance module 410, used to generate corresponding instance according to the parameters of target structure; A script generation module 420 is used to generate an automatic parasitic parameter extraction script according to a target variable; wherein the target variable is all parameters that affect the parasitic parameters when the target structure is created or updated in the integrated circuit layout; An embedding association module 430, used to embed the automatic parasitic parameter extraction script into the instance and set an association mechanism; An extraction calculation module 440 is used to call the automatic parasitic parameter extraction script through the association mechanism when the target instance is created or updated in the integrated circuit layout, automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout, and calculate the corresponding real-time parasitic parameters; The feedback execution module 450 is used to feed back the real-time parasitic parameters, and create the next target instance or update the target instance again according to the feedback result, and execute the steps of: calling the automatic parasitic parameter extraction script through the association mechanism, automatically extracting the real-time variables when the next target instance is created or the target instance is updated in the integrated circuit layout, and calculating the corresponding real-time parasitic parameters.

[0091] Optionally, the instance generation module 410 is specifically used for: Based on the parameter information of the main device in the target structure and in combination with the preset layout design rules, determine the parameter information of the auxiliary device in the target structure; An instance corresponding to the target structure is generated according to the parameter information of the primary component and the parameter information of the secondary component.

[0092] Optionally, the script generation module 420 includes: A variable determination submodule, configured to determine the target variable in the parameter information of the main device and the parameter information of the auxiliary device based on respective operation modes of respective parasitic parameters; A submodule for defining an operation mechanism is used to define the operation mode into the automatic parasitic parameter extraction script and set the operation mechanism through a preset tool or a preset language; The trigger mechanism setting submodule is used to set the trigger mechanism of the target variable when each instance is created or updated in the integrated circuit layout through the preset tool or the preset language.

[0093] Optionally, the embedding association module 430 is specifically used for: By using the preset tool or the preset language, the operation mechanism is combined with the trigger mechanism to form the association mechanism; specifically including: By means of the preset tool or the preset language, after the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the created or updated variables from the created or updated instance; Through the preset tool or the preset language, it is arranged that after extracting the created or updated variable, the operation is performed using the operation mechanism. .

[0094] Optionally, the trigger mechanism setting submodule is specifically used for: By means of the preset tool or the preset language, an initialization function and an update function are set in each of the instances; Registering an event listener in the initialization function and the update function respectively through the preset tool or the preset language; Wherein, the initialization function is used for initialization of each instance when it is created in the integrated circuit layout; The update function is used to update the parameters of each instance after it is created in the integrated circuit layout; The event listener is used to monitor whether the target variable is created or updated when each instance is created or updated, and trigger the association mechanism when it is determined that the target variable is created or updated.

[0095] Optionally, the extraction calculation module 440 is specifically used for: When the target instance is created or updated in the integrated circuit layout, the event listener triggers the association mechanism; After the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the created or updated real-time variables from the created or updated target instance; After extracting the created or updated real-time variables, the automatic parasitic parameter extraction script uses the calculation mechanism to perform calculations through calculation formulas corresponding to the created or updated real-time variables to obtain corresponding real-time parasitic parameters.

[0096] Optionally, the feedback execution module 450 is specifically used to: Feedback the real-time parasitic parameters, and automatically determine whether the real-time parasitic parameters meet the design requirements in combination with the design rules, or manually determine whether the real-time parasitic parameters meet the design requirements; If the real-time parasitic parameters meet the design requirements, creating a next target instance; If the real-time parasitic parameters do not meet the design requirements, the target instance is updated again.

[0097] Optionally, the script generation module 420 is further specifically used for: By using a preset tool or a preset language, constraint conditions are set for each of the target variables in the automatic parasitic parameter extraction script.

[0098] Optionally, the extraction calculation module 430 is further specifically used for: When the target instance is updated in the integrated circuit layout, the event listener triggers the association mechanism; After the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract updated real-time variables from the updated target instance; After extracting the updated real-time variables, the automatic parasitic parameter extraction script uses the constraint conditions to determine the updated real-time variables; If the updated real-time variable satisfies the constraint condition, the automatic parasitic parameter extraction script uses the calculation mechanism to calculate the corresponding real-time parasitic parameter through the calculation formula corresponding to the updated real-time variable; If the updated real-time variables do not satisfy the constraint conditions, the automatic parasitic parameter extraction script feeds back an error alarm and displays the erroneous real-time variables.

[0099] Based on the above integrated circuit layout design method, an embodiment of the present invention further provides a readable storage medium on which a program is stored. When the program is executed by a processor, the integrated circuit layout design method as described in any one of steps 301 to 305 is implemented.

[0100] Based on the above integrated circuit layout design method, an embodiment of the present invention further provides an electronic device, the electronic device comprising a memory and a processor. The memory stores a program; The processor is used to execute the program stored in the memory, and when the program is running, the processor executes any one of the integrated circuit layout design methods described in step 301 to step 305.

[0101] In summary, the integrated circuit layout design method provided by the present invention includes: firstly, generating a corresponding instance according to the parameters of the target structure; then generating an automatic parasitic parameter extraction script according to the target variable; wherein the target variable is all parameters that affect the parasitic parameters when the target structure is created or updated in the integrated circuit layout. That is, the automatic parasitic parameter extraction script includes all parameters in the target structure that may affect the parasitic parameters.

[0102] Then, the automatic parasitic parameter extraction script is embedded in the instance and an association mechanism is set; when the target instance is created or updated in the integrated circuit layout, the automatic parasitic parameter extraction script is called through the association mechanism to automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout and calculate the corresponding real-time parasitic parameters; finally, the real-time parasitic parameters are fed back, and the next target instance is created or updated again according to the feedback result, and the execution steps are: calling the automatic parasitic parameter extraction script through the association mechanism to automatically extract the real-time variables when the next target instance is created in the integrated circuit layout, or automatically extract the real-time variables when the original target instance is updated in the integrated circuit layout, and calculate the corresponding real-time parasitic parameters.

[0103] The integrated circuit layout design method proposed in the present invention creatively proposes an automatic parasitic parameter extraction script, and incorporates all parameters in the target structure that may affect the parasitic parameters into the automatic parasitic parameter extraction script. Using the automatic parasitic parameter extraction script, when each instance is created in the integrated circuit layout, or when the created instance is updated in the integrated circuit layout, the target variable is automatically extracted and the target variable is calculated by the association mechanism to obtain the corresponding parasitic parameters. Finally, according to the result of the parasitic parameter feedback, subsequent operations are performed: whether to continue to create the next new target instance or to update the original target instance, until all instances are created and the parasitic parameters meet the standards, and the entire integrated circuit layout design is completed. The entire design method can automatically and accurately extract and calculate parasitic parameters, so that more physical effects and layout details can be considered, and technical support is provided for the accurate and rapid extraction and calculation of parasitic parameters, ensuring the real-time and accuracy of the parasitic parameters of the integrated circuit layout, effectively solving the problems of low efficiency and precision in the integrated circuit layout design, and having high practical value.

[0104] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0105] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0106] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A method for designing an integrated circuit layout, characterized in that: The integrated circuit layout design method comprises: Generate corresponding instances according to the parameters of the target structure; Generate an automatic parasitic parameter extraction script according to the target variable; wherein the target variable is all parameters that affect the parasitic parameters when the target structure is created or updated in the integrated circuit layout; Embedding the automatic parasitic parameter extraction script into the instance and setting an association mechanism; When the target instance is created or updated in the integrated circuit layout, the automatic parasitic parameter extraction script is called through the association mechanism to automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout and calculate the corresponding real-time parasitic parameters; Feedback the real-time parasitic parameters, and create the next target instance or update the target instance again according to the feedback result, and execute the steps: call the automatic parasitic parameter extraction script through the association mechanism, automatically extract the real-time variables when the next target instance is created or the target instance is updated in the integrated circuit layout, and calculate the corresponding real-time parasitic parameters.

2. The integrated circuit layout design method according to claim 1, characterized in that: Generate corresponding instances according to the parameters of the target structure, including: Based on the parameter information of the main device in the target structure and in combination with the preset layout design rules, determine the parameter information of the auxiliary device in the target structure; An instance corresponding to the target structure is generated according to the parameter information of the primary component and the parameter information of the secondary component.

3. The integrated circuit layout design method according to claim 2, characterized in that: Generate an automatic parasitic parameter extraction script based on the target variable, including: Based on respective operation modes of respective parasitic parameters, determining the target variable in the parameter information of the main device and the parameter information of the auxiliary device; By using a preset tool or a preset language, the operation mode is defined in the automatic parasitic parameter extraction script and an operation mechanism is set; The trigger mechanism of the target variable when each instance is created or updated in the integrated circuit layout is set by the preset tool or the preset language.

4. The integrated circuit layout design method according to claim 3, characterized in that: Set up the association mechanism, including: The operation mechanism is combined with the trigger mechanism through the preset tool or the preset language to form the association mechanism.

5. The integrated circuit layout design method according to claim 3, characterized in that: Setting a trigger mechanism for the target variable when each instance is created or updated in the integrated circuit layout includes: By means of the preset tool or the preset language, an initialization function and an update function are set in each of the instances; Registering an event listener in the initialization function and the update function respectively through the preset tool or the preset language; Wherein, the initialization function is used for initialization of each instance when it is created in the integrated circuit layout; The update function is used to update the parameters of each instance after it is created in the integrated circuit layout; The event listener is used to monitor whether the target variable is created or updated when each instance is created or updated, and trigger the association mechanism when it is determined that the target variable is created or updated.

6. The integrated circuit layout design method according to claim 4, characterized in that: Combining the operation mechanism with the trigger mechanism to form the association mechanism includes: By means of the preset tool or the preset language, after the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the created or updated variables from the created or updated instance; Through the preset tool or the preset language, it is arranged that after extracting the created or updated variables, the operation is performed using the operation mechanism.

7. The integrated circuit layout design method according to claim 5, characterized in that: When the target instance is created or updated in the integrated circuit layout, the automatic parasitic parameter extraction script is called through the association mechanism to automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout and calculate the corresponding real-time parasitic parameters, including: When the target instance is created or updated in the integrated circuit layout, the event listener triggers the association mechanism; After the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract the created or updated real-time variables from the created or updated target instance; After extracting the created or updated real-time variables, the automatic parasitic parameter extraction script uses the calculation mechanism to perform calculations through calculation formulas corresponding to the created or updated real-time variables to obtain corresponding real-time parasitic parameters.

8. The integrated circuit layout design method according to claim 1, characterized in that: Feedback of the real-time parasitic parameters is performed, and a next target instance is created or the target instance is updated again according to the feedback result, including: Feedback the real-time parasitic parameters, and automatically determine whether the real-time parasitic parameters meet the design requirements in combination with the design rules, or manually determine whether the real-time parasitic parameters meet the design requirements; If the real-time parasitic parameters meet the design requirements, creating a next target instance; If the real-time parasitic parameters do not meet the design requirements, the target instance is updated again.

9. The integrated circuit layout design method according to claim 5, characterized in that: Generate an automatic parasitic parameter extraction script based on the target variable, including: By using a preset tool or a preset language, constraint conditions are set for each of the target variables in the automatic parasitic parameter extraction script.

10. The integrated circuit layout design method according to claim 9, characterized in that: When the target instance is created or updated in the integrated circuit layout, the automatic parasitic parameter extraction script is called through the association mechanism to automatically extract the real-time variables when the target instance is created or updated in the integrated circuit layout and calculate the corresponding real-time parasitic parameters, including: When the target instance is updated in the integrated circuit layout, the event listener triggers the association mechanism; After the association mechanism is triggered, the automatic parasitic parameter extraction script is called to extract updated real-time variables from the updated target instance; After extracting the updated real-time variables, the automatic parasitic parameter extraction script uses the constraint conditions to determine the updated real-time variables; If the updated real-time variable satisfies the constraint condition, the automatic parasitic parameter extraction script uses the calculation mechanism to calculate the corresponding real-time parasitic parameter through the calculation formula corresponding to the updated real-time variable; If the updated real-time variables do not satisfy the constraint conditions, the automatic parasitic parameter extraction script feeds back an error alarm and displays the erroneous real-time variables.

11. An integrated circuit layout design system, characterized in that: The integrated circuit layout design system comprises: Generate instance module, used to generate corresponding instance according to the parameters of target structure; A script generation module is used to generate an automatic parasitic parameter extraction script according to a target variable; wherein the target variable is all parameters that affect the parasitic parameters when the target structure is created or updated in the integrated circuit layout; An embedding association module, used for embedding the automatic parasitic parameter extraction script into the instance and setting an association mechanism; An extraction calculation module, used for calling the automatic parasitic parameter extraction script through the association mechanism when the target instance is created or updated in the integrated circuit layout, automatically extracting the real-time variables when the target instance is created or updated in the integrated circuit layout and calculating the corresponding real-time parasitic parameters; A feedback execution module is used to feed back the real-time parasitic parameters, and create a next target instance or update the target instance again according to the feedback result, and execute the steps of: calling the automatic parasitic parameter extraction script through the association mechanism, automatically extracting the real-time variables when the next target instance is created or the target instance is updated in the integrated circuit layout, and calculating the corresponding real-time parasitic parameters.

12. A readable storage medium having a program stored thereon, characterized in that: When the program is executed by a processor, the integrated circuit layout design method as described in any one of claims 1 to 10 is implemented.

13. An electronic device, characterized in that: The electronic device comprises a memory and a processor, The memory stores a program; The processor is used to execute the program stored in the memory, and when the program is run, the processor executes the integrated circuit layout design method according to any one of claims 1 to 10.

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