Multi-die Testing Method, Electronic Device and Storage Medium Based on Simulation Platform

Abstract

The present invention relates to the technical field of chip design, and particularly to a multi-die testing method, an electronic device, and a storage medium based on a simulation platform. The method includes obtaining a test template, where the test template includes a basic template in which the interconnection interfaces between dies are configured as full interconnections and a topology structure table. Each topology structure in the topology structure table is configured with an identity identifier topo_id, and corresponding identity identifiers socket_id are configured for multiple interconnection structures in each topology structure; a compiler compiles the test template to obtain a template database; a user specifies a target interconnection structure to be tested according to topo_id and socket_id, and a simulator tests the interconnection relationship in the target interconnection structure. Compared with the prior art, the solution provided by the present invention only needs to generate a template database through a compilation step and does not need to be recompiled when testing various different interconnection structures, greatly shortening the verification cycle.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and particularly to a multi-die testing method, an electronic device, and a storage medium based on a simulation platform. Background Art

[0002] In the complex process of chip design and verification, it is crucial to ensure that the connection relationships between all dies (bare chips) within a topology are fully verified. However, the current emulation platform can only test the interface connectivity between two dies at a time. To comprehensively verify the entire topology, multiple compilation and testing cycles must be executed.

[0003] During this process, different parts of the toolchain undertake specific tasks: The synthesis tool is used to convert the hardware description language code into a netlist. The compiler for emulation is used to compile the netlist and other design files into a database (DB) that can run on the emulation platform. The emulator is used to apply excitation signals using the compiled database, simulate actual working conditions, and collect test data for analysis. Due to the diversity of interfaces between different dies, recompilation is indeed required when changing the test object, which may cause each compilation to take up to dozens of hours or even longer, significantly extending the overall verification cycle. Therefore, there is an urgent need for a testing method that can reduce the compilation time. Summary of the Invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is: A multi-die testing method based on a simulation platform, the method comprising the following steps:

[0005] Obtain a test template, the test template including a basic template consisting of N interconnected dies forming a single interconnected structure and template configuration information; all interfaces between any two of the dies in the basic template are configured as fully interconnected; the target configuration information includes a topology table, and each topology in the topology table includes an identity identifier topo_id of the current topology and all interconnected structures; each interconnected structure includes an identity identifier socket_id of the interconnected structure and the interconnection relationship between the interconnection interfaces of the N dies.

[0006] Compile the test template through a compiler to generate a template database.

[0007] Obtain the target topology structure to be measured, where the target topology structure includes M target interconnect structures to be measured. When simulating the i-th target interconnect structure, configure the topo_id of the target topology structure for the template database i and the socket_id of the i-th target interconnect structure i . The template database obtains the target database according to the topo_id i and socket_id i and the interconnected relationships they are bound to. The value range of i is from 1 to M.

[0008] Test all the interconnected relationships bound to the socket_id i in the target database through the simulator.

[0009] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one segment of program is stored, and the at least one instruction or the at least one segment of program is loaded and executed by a processor to implement the above method.

[0010] In addition, the present invention also provides an electronic device, including a processor and the above non-transitory computer-readable storage medium.

[0011] The present invention has at least the following beneficial effects:

[0012] The present invention provides a multi-die testing method, an electronic device and a storage medium based on a simulation platform. By configuring the inter-die interface included in the test template as a full interconnection and configuring the template configuration information; compiling the test template into a template database; when a user tests a target interconnect structure, only need to specify the topology structure and the identity information of the interconnect structure to obtain the target interconnect structure, and then achieve the purpose of testing the interconnected relationships in the target interconnect structure. Compared with the prior art, the time-consuming compilation step only needs to be executed when generating the template database, and when testing various different interconnect structures, the compilation step does not need to be executed again, greatly shortening the verification cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0014] Figure 1 It is a flowchart of a multi-die testing method based on a simulation platform provided by an embodiment of the present invention;

[0015] Figure 2 A schematic diagram showing the visualization of the content stored in the test template provided by the embodiment of the present invention;

[0016] Figure 3 A schematic diagram of a topological structure. Detailed implementation manners

[0017] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0018] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meaning as commonly understood by those skilled in the art.

[0019] Please refer to Figure 1 , which shows a multi-die test method based on a simulation platform. The method includes the following steps:

[0020] S100, obtain a test template, where the test template includes a basic template composed of N interconnected dies forming a single interconnected structure and template configuration information; all interfaces between any two of the dies in the basic template are configured as full interconnections; the target configuration information includes a topology structure table, and each topology structure in the topology structure table includes the identity identifier topo_id of the current topology structure and all interconnected structures; each interconnected structure includes the identity identifier socket_id of the interconnected structure and the interconnection relationship between the interconnection interfaces of the N dies.

[0021] Among them, the emulation platform includes a compiler and an emulator.

[0022] Among them, the basic template is a netlist of N interconnected dies, and all interfaces between any two of the dies in the netlist are fully interconnected.

[0023] In one implementation manner, the value of N is equal to the maximum number of simulations that the simulation platform can perform at one time. Configuring N as the maximum number of simulations at one time can make full use of the resources of the simulation platform and at the same time can save the time of a single simulation test to the greatest extent.

[0024] In one embodiment, N equals 2. It can be when the maximum number of single simulations on the simulation platform is 2, then N equals 2. It can also be that the minimum test unit specified by the user is 2. In this case, the flexibility is better, and the test templates for interconnecting two dies can more flexibly adapt to all different types of interconnect topologies, whether symmetric or asymmetric interconnect topologies.

[0025] Among them, the topo_id bound to each topology structure is unique. The number of dies included in each interconnect structure is equal to the number of dies in the basic template.

[0026] In one embodiment, in different topology structures, there is no interconnect path between the same two dies. Through reasonable allocation, the number of compilations is reduced, and the verification cycle is shortened. If the same path is allocated to different interconnect structures, it will cause the same path to be repeatedly compiled and tested, increasing the compilation time and verification cycle. As an example, please refer to Figure 3 , taking N = 2 as an example, this interconnect topology includes 4 dies: die0, die1, die2, and die3. Among them, die0 is interconnected with die1, die2, and die3 respectively, then the interconnect structures composed of die0 and die1, die0 and die2, and die0 and die3 are obtained; die1 is also interconnected with die2 and die3 respectively, then the interconnect structures composed of die1 and die2, and die1 and die3 are obtained; die2 and die3 are also interconnected, then the interconnect structure composed of die2 and die3 is obtained. A total of 6 interconnect structures are obtained, and there is no same two interconnect paths between these interconnect structures. Similarly, when N = 3 or N = 4, or when N takes other values, there is also no same two interconnect paths between two interconnect structures.

[0027] In one embodiment, the interface connection between the two dies is a point-to-point interconnection between two interfaces.

[0028] In one embodiment, full interconnect includes all interconnect relationships of all interconnect structures in all target topology structures to be tested.

[0029] As an example, for the convenience of understanding, refer to Figure 2 , Figure 2 A visual schematic diagram of the content saved in the test template is shown to help understanding. Taking N = 2 and each die including M1 - M3 and E0 interfaces as an example, in the test template, where die x includes M1 - M3 interfaces and E0 interface. Similarly, die y also includes M1 - M3 interfaces and E0 interface, die x and die yThe corresponding interfaces are interconnected to achieve full interconnection. Among them, M1-M3 are high-speed interconnection interfaces, and E0 is a network interface. In an actual topology structure, for example, in Figure 3 In the topology structure of, die0 and die1 are interconnected through M3, die0 and die2 are interconnected through M1, and die0 and die3 are interconnected through M2. The interconnection relationships of other topology structures are also included in this test template. That is, the interconnection relationships of all the interconnection structures in the target topology structure to be tested are included in this test template.

[0030] It should be noted that the die in the test template, the interfaces of each die, and the connection relationships between the interfaces of the dies are all saved in the netlist. The template configuration information includes all the topology structures to be tested and all the interconnection structures included in each topology structure. Each topology structure has a unique topo_id, and each interconnection structure in each topology structure has a unique socket_id. Users can uniquely determine the interconnection structure to be tested by specifying the topo_id and socket_id.

[0031] In one implementation manner, the identity identifier of each topology structure in the topology structure table is globally unique, and the identity identifier of each interconnection structure is locally unique in the current topology structure. The local uniqueness of the identity identifier of the interconnection structure can greatly reduce the data volume.

[0032] In another implementation manner, the identity identifier of each topology structure in the topology structure table is globally unique, and the identity identifier of each interconnection structure is globally unique in the topology structure table. The global uniqueness of the identity identifier of the interconnection structure can enable the search for matching during configuration without having to search according to the hierarchical structure, and the search speed is greatly improved.

[0033] S200, compile the test template through a compiler to generate a template database.

[0034] It should be noted that since all the interfaces between N interconnected dies in the test template are configured for full interconnection, a template database storing the full interconnection relationships between these dies is obtained after compilation by the compiler. This template database describes how the interfaces between the dies are interconnected at the logical level, contains the connection mapping situations between the ports of each die, provides basic information for subsequent simulation based on this, and facilitates further simulation of these interconnection relationships.

[0035] S300, obtain the target topology structure to be tested. The target topology structure includes M target interconnection structures to be tested. When simulating the i-th target interconnection structure, configure the topo_id of the target topology structure for the template database iand the socket_id of the i-th target interconnection structure i , the template database is based on the topo_id i and socket_id i and the obtained target database according to the bound interconnection relationship, where the value range of i is from 1 to M.

[0036] Among them, after compilation, the template database has been generated, and users can obtain the target interconnection structure to be tested by configuring the corresponding topo_id and socket_id.

[0037] In one implementation manner, the obtaining step of the target database includes: the template database includes a target selection interface. When the target selection interface receives the topo_id i and socket_id i , the target selection interface searches for the same topo_id as the topo_id i to obtain the target topology structure, and searches for the same socket_id as the socket_id i in the target topology structure to obtain the target interconnection structure and its bound interconnection relationship.

[0038] In one implementation manner, the method for configuring the topo_id i of the target topology structure and the socket_id i of the i-th target interconnection structure in the template database is: obtain a to-be-tested configuration file, and the to-be-tested configuration file includes the topo_id i of the target topology structure and the socket_id i of the i-th target interconnection structure; parse the to-be-tested configuration file, and use the topo_id i and socket_id i in the to-be-tested configuration file to establish a database connection.

[0039] In another implementation manner, it is also possible to directly configure the topo_id i and socket_id i through the emulator.

[0040] S400, test all the interconnection relationships bound to the socket_id i in the target database through the emulator.

[0041] It should be noted that even if the interconnect structure to be tested of the user includes the interconnects between multiple different dies, the user can directly perform simulation after obtaining various different interconnect structures to be tested by configuring the corresponding topo_id and socket_id. Before the simulation, only the hardware description language code of the test template needs to be written and synthesized to obtain the test template, and then the test template is compiled to obtain the template database. That is, the processes of code writing, synthesis, and compilation only need to be executed once. In the traditional simulation method, the hardware description language code, synthesis, compilation, and simulation need to be separately performed for each different interconnect structure to be tested. For example Figure 3 For the topology structure shown, using the traditional method, the netlists of the 6 interconnect structures in this topology structure need to be separately compiled and simulated. However, when using the present invention for simulation, only one compilation is required to generate the template database, and then the 6 interconnect structures to be tested are obtained by sequentially configuring topo_id and socket_id, and each interconnect structure is separately tested. Compared with the traditional solution, the method provided by the embodiment of the present invention greatly reduces the time consumed by compilation and greatly compresses the verification cycle. In addition, since the present invention only needs to compile the test template and does not need to separately compile each interconnect structure, the present invention also greatly reduces the time consumed for collecting the verification coverage rate compared with the traditional method.

[0042] In one implementation manner, the interconnect relationship includes the interconnect relationship interconnected through a high-speed interconnect interface and the interconnect relationship interconnected through a network interface. The types of other interconnect relationships also fall within the protection scope of the present invention.

[0043] In one implementation manner, the high-speed interconnect interface uses a bus interconnect that complies with the MetaX Link, NVLink, InfinityFabric, or UCIe standard.

[0044] In summary, the present invention provides a multi-die test method based on a simulation platform. By configuring the die-to-die interconnect interfaces included in the test template as fully interconnected and configuring the template configuration information; compiling the test template into a template database; when the user tests the target interconnect structure, only by specifying the topology structure and the identity information of the interconnect structure, the target interconnect structure can be obtained, and then the purpose of testing the interconnect relationship in the target interconnect structure is achieved. Compared with the prior art, the time-consuming compilation step only needs to be executed when generating the template database, and when testing various different interconnect structures, the compilation step does not need to be executed again, greatly shortening the verification cycle.

[0045] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be disposed in an electronic device to store at least one instruction or at least one segment of a program related to a method in the method embodiment. The at least one instruction or the at least one segment of the program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0046] An embodiment of the present invention also provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0047] An embodiment of the present invention also provides a computer program product, which includes program code. When the program product runs on an electronic device, the program code is used to cause the electronic device to execute the steps in the method according to various exemplary embodiments of the present invention described above in this specification.

[0048] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0049] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope disclosed by the present invention is defined by the appended claims.

Claims

1. A multi-die testing method based on a simulation platform, characterized in that, The method comprises the following steps: Obtain a test template, where the test template includes a basic template in which N interconnected dies form a single interconnected structure and template configuration information; all interfaces between any two dies in the basic template are configured for full interconnection; the template configuration information includes a topology structure table, and each topology structure in the topology structure table includes an identity identifier topo_id of the current topology structure and all interconnected structures; each interconnected structure includes an identity identifier socket_id of the interconnected structure and the interconnection relationship between the interconnection interfaces of N dies; Compile the test template through a compiler to generate a template database; Obtain the target topology structure to be measured, where the target topology structure includes M target interconnect structures to be measured. When simulating the i-th target interconnect structure, configure the topo_id of the target topology structure for the template database i and the socket_id of the i-th target interconnect structure i , and the template database obtains the target database according to the topo_id i and socket_id i and the interconnect relationship bound thereto, where the value range of i is from 1 to M; Test all the interconnection relationships bound to the socket_id in the target database through the emulator i ​ 2. The method according to claim 1, characterized in that, The value of N is equal to the maximum number of simulations that can be performed in a single simulation on the simulation platform.

3. The method according to claim 1, characterized in that, N is equal to 2.

4. The method according to claim 1, characterized in that, The steps for obtaining the target database include: the template database includes a target selection interface. When the target selection interface receives the topo_id i and the socket_id i , the target selection interface searches for the topo_id identical to the topo_id i to obtain the target topology structure, and searches for the socket_id identical to the socket_id i in the target topology structure to obtain the target interconnection structure and its bound interconnection relationship.

5. The method according to claim 1, characterized in that, Configure the topo_id of the target topology structure for the template database i and the socket_id of the i-th target interconnect structure i in the following way: Obtain the configuration file to be tested, where the configuration file to be tested includes the topo_id of the target topology structure i and the socket_id of the i-th target interconnect structure i ; Parse the configuration file to be tested and use the topo_id i and socket_id in the configuration file to be tested i to establish a database connection.

6. The method according to claim 1, wherein The interconnection relationship includes an interconnection relationship through a high-speed interconnection interface and an interconnection relationship through a network interface.

7. The method according to claim 1, wherein The identity identifier of each topology structure in the topology structure table is globally unique, and the identity identifier of each interconnected structure is locally unique in the current topology structure.

8. The method according to claim 1, wherein The identity identifier of each topology structure in the topology structure table is globally unique, and the identity identifier of each interconnected structure is globally unique in the topology structure table.

9. A non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by a processor to implement the method according to any one of claims 1-8.

10. An electronic device, characterized in that, Comprising a processor and the non-transitory computer-readable storage medium according to claim 9.

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