Square circuit, self-regulation method of square circuit and control module

Abstract

Embodiments of the present disclosure provide an adjustable square circuit, an auto-adjustment method for a square circuit, and a control module. The square circuit includes: a square unit that outputs a first signal; a mirror square unit that outputs a second signal; a current adjustment module configured to receive a target control signal, generate a compensation current, the magnitude of the compensation current being related to the target control signal, and an output end of the current adjustment module is connected to an output end of the square unit or the mirror square unit to compensate for the difference between the first signal and the second signal; wherein the target control signal is generated by the control module based on the voltage difference collected by the voltage acquisition module; the voltage acquisition module is configured to collect the output voltage of the square unit and the output voltage of the mirror square unit; the control module is configured to obtain the voltage difference between the output ends of the square unit and the mirror square unit, and the voltage difference is used to obtain the target control signal. Embodiments of the present disclosure can improve circuit mismatch and expand the dynamic range.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technologies, and in particular, to a squaring circuit, a self-adjustment method for the squaring circuit, and a control module. Background Art

[0002] Detectors, which are usually used to measure the amplitude or power of signals, are widely used in wireless systems. They can be simply divided into two categories: logarithmic amplifying detectors (or envelope detectors) and root mean square (RMS) detectors. For RMS detectors, three operations of taking the root, averaging, and squaring on the signal need to be performed. Among them, since the squaring unit has its own DC operating current / voltage, this part of the current / voltage needs to be subtracted. Therefore, an additional mirror squaring unit is used to provide the same bias for accurately subtracting the corresponding DC voltage / current. However, there may be a mismatch problem between the squaring unit and the mirror squaring unit, and the mismatch may vary with temperature, resulting in the inability to accurately subtract the corresponding DC voltage / current, thus the output result is inaccurate. Summary of the Invention

[0003] Embodiments of the present disclosure provide a squaring circuit, a self-adjustment method for the squaring circuit, and a control module.

[0004] In a first aspect, embodiments of the present disclosure provide an adjustable squaring circuit, including:

[0005] A squaring unit for squaring the received AC signal. The squaring unit receives a bias voltage and the AC signal, and the output end of the squaring unit outputs a first signal;

[0006] A mirror squaring unit for receiving the bias voltage. The structure of the mirror squaring unit is the same as that of the squaring unit, and the output end of the mirror squaring unit outputs a second signal;

[0007] A current adjustment module for receiving a target control signal, generating a compensation current. The magnitude of the compensation current is related to the target control signal. The output end of the current adjustment module is connected to the output end of the squaring unit or the mirror squaring unit for compensating the difference between the first signal and the second signal; wherein, the target control signal is generated by the control module based on the voltage difference collected by the voltage acquisition module; the voltage acquisition module is used to collect the output voltage of the squaring unit and the output voltage of the mirror squaring unit; the control module is used to obtain the voltage difference between the output ends of the squaring unit and the mirror squaring unit, and the voltage difference is used to obtain the target control signal.

[0008] Second aspect, embodiments of the present disclosure provide a self - adjustment method for a square circuit, which is applied to the square circuit as in the first aspect. The method includes:

[0009] Obtain the voltage difference;

[0010] Determine a target control signal according to the voltage difference and output it to the current adjustment module.

[0011] Third aspect, embodiments of the present disclosure provide a control module, including a processor and a memory;

[0012] The processor is configured to execute the instructions stored in the memory, so that the control module executes the self - adjustment method as in the second aspect.

[0013] The beneficial effects of the present disclosure are as follows:

[0014] If there is a process mismatch between the square unit and the mirror square unit, the first signal and the second signal output by the square unit and the mirror square unit are different. The voltage acquisition module acquires the voltage difference between the output voltage of the square unit and the output voltage of the mirror square unit. The magnitude of the voltage difference can reflect the difference between the first signal and the second signal. The control module can determine a target control signal for compensating the mismatch according to the voltage difference; the current adjustment module receives the target control signal and generates a compensation current, and the compensation current can compensate for the difference between the first signal and the second signal, eliminating (or at least partially eliminating) the inaccuracy problem caused by the mismatch between the square unit and the mirror square unit.

[0015] The square circuit further includes a storage module for storing the correspondence between the output voltage difference of the square unit and the mirror square unit and the target control signal. In this way, during calibration, only the corresponding target control signal needs to be found according to the voltage difference, without traversing different control signals, saving calibration time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of input and output of signal envelope detection provided by an embodiment of the present disclosure;

[0017] Figure 2 It is a schematic diagram of the architecture of an RMS detector provided by an embodiment of the present disclosure;

[0018] Figure 3 It is a schematic diagram of a circuit structure of a square circuit provided by an embodiment of the present disclosure;

[0019] Figure 4 It is an equivalent circuit schematic diagram of a square circuit provided by an embodiment of the present disclosure;

[0020] Figure 5Schematic diagram of the structure of the self-adjustable square circuit provided in the embodiment of the present disclosure Figure 1 ;

[0021] Figure 6 Schematic diagram of the structure of the self-adjustable square circuit provided in the embodiment of the present disclosure Figure 2 ;

[0022] Figure 7 Schematic diagram of the structure of the self-adjustable square circuit provided in the embodiment of the present disclosure Figure 3 ;

[0023] Figure 8 Schematic diagram of the structure of the self-adjustable square circuit provided in the embodiment of the present disclosure Figure 4 ;

[0024] Figure 9 Schematic diagram of the structure of the self-adjustable square circuit provided in the embodiment of the present disclosure Figure 5 ;

[0025] Figure 10 Schematic diagram of the structure of the self-adjustable square circuit provided in the embodiment of the present disclosure Figure 6 ;

[0026] Figure 11 Schematic diagram of the structure of the current adjustment module provided in the embodiment of the present disclosure Figure 1 ;

[0027] Figure 12 Schematic diagram of the structure of the current adjustment module provided in the embodiment of the present disclosure Figure 2 ;

[0028] Figure 13 Schematic diagram of the structure of the current adjustment module provided in the embodiment of the present disclosure Figure 3 ;

[0029] Figure 14 Schematic diagram of the structure of the self-adjustable square circuit provided in the embodiment of the present disclosure Figure 7 ;

[0030] Figure 15 Schematic diagram of the structure of the self-adjustable square circuit provided in the embodiment of the present disclosure Figure 8 ;

[0031] Figure 16 Schematic diagram of the self-adjustment process provided by the embodiment of the present disclosure Figure 1 ;

[0032] Figure 17 Schematic diagram of the self-adjustment process provided by the embodiment of the present disclosure Figure 2 ;

[0033] Figure 18Schematic diagram of the composition structure of the self - adjustable square circuit provided by the embodiments of the present disclosure Figure 9 ;

[0034] Figure 19 Schematic diagram of the self - adjustment process provided by the embodiments of the present disclosure Figure 3 ;

[0035] Figure 20 Schematic diagram of the composition structure of the self - adjustable square circuit provided by the embodiments of the present disclosure Figure 10 ;

[0036] Figure 21 Schematic diagram of the self - adjustment process provided by the embodiments of the present disclosure Figure 4 。 Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than limiting the disclosure. Additionally, it should be noted that for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0039] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0040] It should be noted that the terms "first / second / third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0041] Detectors can be divided into envelope detectors and RMS detectors. Figure 1 shows the detection results of the envelope detector and the RMS detector for the same radio frequency signal. As Figure 1As shown, the radio frequency signal is a high-frequency sine wave whose amplitude / phase changes with time. Envelope detection will detect and output the envelope of the input signal, usually its logarithmic value, i.e., the output result 1 in the figure; the RMS detector will detect and output the root mean square value (or power value) of the input signal, i.e., the output result 2 in the figure. Its output voltage does not change with the shape of the signal or the peak-to-average power ratio, where the peak-to-average power ratio refers to the Peak to Average Power Ratio (PAPR). As Figure 1 shown, for the signal value of the radio frequency input signal, the amplitude of the high-frequency sine wave oscillation is not fixed, and the ratio of the power corresponding to its peak value to the power corresponding to its mean value is the peak-to-average power ratio.

[0042] For the RMS detector, its implementation usually performs three operations of Root-Mean-Square on the signal, that is, the output voltage or current is:

[0043] Equation (1)

[0044] where Y is the output voltage or current, X is the input voltage or current, and s is the slope.

[0045] Since the absolute value of the input signal may be small, usually in dBm units, for Equation (1), the absolute value of its output signal Y is also small. When the power of the input signal changes from -40 dBm to -20 dBm and s = 1, the voltage corresponding to the output signal Y only changes from 2.24 mV to 22.4 mV, and the absolute value and dynamic range are extremely small, which is not conducive to subsequent detection. Therefore, the RMS detector usually processes the result Y into a logarithmic value before outputting:

[0046] Equation (2)

[0047] where Z is the actual output current or voltage of the converted detector, k is the logarithmic slope, b is the logarithmic intercept, k` is the logarithmic slope after combining the square root operation, and b` is the logarithmic intercept after combining the linear slope s. The logarithm in the equation can also be of other bases, as long as there is a logarithmic relationship.

[0048] When the function of converting to logarithm is added at the subsequent stage, the square root Root operation in the RMS can be directly moved outside the logarithm and become part of the slope, without the need to be implemented by hardware anymore. The slope s in the previous text will be added to the logarithmic intercept here to form a new logarithmic intercept, which no longer affects the slope of the output signal Z. The following narrative is based on this.

[0049] Since the RMS detector will perform an averaging operation on the input signal, no matter how high the frequency of the input signal is, after averaging over a certain time window, the output signal will be close to direct current and will only change slowly with the change of the mean value of the input signal.

[0050] Common RMS detector architectures are shown in (a) or (b) of Figure 2 and include a square unit, a mirror square unit, an operation module, an averaging capacitor, a logarithmic converter, and a driver. The structures of the square unit and the mirror square unit are exactly the same. The square unit receives a bias voltage DC Bias (used to drive the square unit to work) and a radio frequency input signal RF IN to form a mixed signal. The mirror square unit receives the bias voltage DC Bias or the bias voltage DC Bias + feedback voltage (Feedback, FD), and the feedback voltage Feedback can be generated by the operation module or the driver. The output signals of the square unit and the mirror square unit are subtracted by the operation module, then the averaging operation is achieved through the averaging capacitor, then the logarithmic conversion is achieved through the logarithmic converter, and finally the driving enhancement is performed by the driver, and finally the detected result signal OUT is output, which is equivalent to Figure 1 the output of the root mean square value (or power value) in logarithmic form in Figure 2 . Among them, the position of the averaging capacitor can be placed at the output end of the operation module as shown in (a) of Figure 2 , or it can be placed at the output end of the square unit as shown in (b) of

[0051] That is to say, in the RMS detector shown in Figure 2 , the averaging capacitor is used to average the signal. Since the square unit has a direct current (Direct Current, DC) operating current / voltage itself, this part of the current / voltage needs to be subtracted, so an additional square unit (i.e., the mirror square unit) is used to provide the same bias for accurately subtracting the corresponding DC voltage / current. Its input can also be a feedback voltage for square root operation. The averaging position can be adjusted as needed.

[0052] In the RMS detector, usually the square and averaging operations are implemented together. Figure 3 is an example of a method for implementing a square unit. Inside the dashed box are two identical square units. The square unit 1 includes bipolar junction transistors (BJT, or triodes) Q11~Q14 for receiving radio frequency input, and the square unit 2 is a mirror square unit including BJT Q15~Q18 for receiving a reference voltage (or the same bias voltage as the radio frequency branch). Its main function is to subtract the DC output voltage of the square unit and sometimes can also achieve the square root function.

[0053] Two square units require a certain static DC current to operate properly. Ideally, when there is no RF input and the bias voltages of the two square units are the same, their DC bias currents will also be the same, that is, the output current I11 of square unit 1 and the output current I12 of square unit 2 are the same. The same voltage is generated across the same resistors R11 and R12 ( Figure 3 nodes 1 and 2 in

[0054] ), and the difference between them is zero when subtracted. When an RF signal is input, additional square currents will be generated in the branch where current I11 is located. These currents are averaged by capacitors C11 and C12, and an additional averaged square voltage is generated on top of the DC voltage across resistor R11. Since the DC currents are exactly the same and are completely subtracted, the differential voltage output by the two square units is the exact square voltage.

[0055] Equation (3)

[0056] Vos will enter the logarithm and be added to the square average term, and cannot be factored out of the logarithm. When the input power is small, its square average term is also small, and may even be smaller than Vos, then the useful signal will be covered by the mismatch voltage Vos and cannot be detected. If the mismatch voltage / current is high, it will significantly affect the lower limit of the input dynamic range, resulting in dynamic range loss.

[0057] The mismatch voltage / current is also at DC, and the mismatch current of square units implemented by devices such as BJTs / Heterojunction Bipolar Transistors (HBTs) may vary with temperature.

[0058] Due to the principle limitations of the square unit, the dynamic range of its output signal is strongly correlated with the dynamic range of the input signal. If an input signal in the range of 60 dBm needs to be detected, the output voltage / current will also change by 120 dB, that is, a million times. If the upper limit of the output dynamic range is set to 1 V, its lower limit will reach 1 μV. If no additional processing is done for the mismatch, it may reach several mV, which is much larger than the lower limit of the output voltage. If one wants to increase the lower limit voltage above the mismatch of the square unit during design, such as increasing it to 10 mV, the upper limit will increase correspondingly to 10000 V, which is obviously not achievable.

[0059] The mismatch voltage Vos or mismatch current Ios is at DC, and the useful signal is also at direct current (DC) or very low frequencies, so the mismatch voltage / current cannot be suppressed using methods such as feedback of traditional DC offset elimination circuits (DCOC), capacitive DC blocking, etc., because these methods will also suppress the useful signal at the same time.

[0060] Currently, there are the following techniques for dealing with the mismatch problem of the square unit:

[0061] A front-end radio frequency (RF) analog variable gain amplifier (VGA). By feeding back the output of the square unit to the control terminal of the VGA, on the one hand, the VGA converts to logarithm, and on the other hand, it compresses the input power range of the square unit, thereby reducing the demand for the dynamic range of the square unit. This solution does not reduce the mismatch, but only adjusts the input range of the square unit to the linear interval of the square unit. However, due to the need to use an RF VGA, the power consumption is extremely high, and the overall linear range of the system will be limited by the RF VGA.

[0062] A chopper. The mismatch voltage or current is chopped to a high frequency through switches before and after the square unit, and the mismatch at the high frequency is filtered out together during the averaging of the subsequent stage, thereby achieving automatic mismatch suppression. However, since the chopper usually uses Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs, MOS) or BJT switches, the switch parasitic capacitance may, on the one hand, cause input RF leakage, affecting the input matching, and on the other hand, cause the drive clock of the chopper switch to feed through to the RF path, forming background noise, which instead limits the dynamic range of the square unit. And the drive clock of the chopper also requires additional power consumption.

[0063] For the convenience of understanding, the square circuit is abstracted as Figure 4 , as Figure 4 shown. The input impedance of the device within the bold solid line box in (a) of Figure 4 is equivalent to the resistor RL1 and the resistor RL2 + capacitor CM shown in (b) of Figure 4 . Among them, the two square units have the same bias Bias. Among them, the first end of the resistor RL1, the first end of the resistor RL2, and the first end of the capacitor CM are all connected to the power supply; the second end of the resistor RL1 and the second end of the capacitor CM are both connected to the output end of the square unit; the second end of the resistor RL2 is connected to the output end of the mirror square unit. The square unit inputs the RF signal RF IN, the mirror square unit inputs an optional feedback signal FB (for square root operation). Both have the same load, abstracted as resistors RL1 and RL2, and input the radio frequency signal RF IN The square unit of IN also has a capacitive load CM for filtering, that is, taking the average value. Due to the resistors RL1 and RL2, the current outputs of the two square units are converted into voltage VOUT outputs. When there is no radio frequency signal input, ideally VOUT = 0. But actually due to manufacturing errors, VOUT may not be zero, that is, there is a mismatch.

[0064] Based on this, the embodiments of the present disclosure provide an adjustable square circuit. The voltage acquisition module acquires the output voltage of the square unit and the output voltage of the mirror square unit. When there is a mismatch between the first signal and the second signal output by the square unit and the mirror square unit, it can be reflected by the voltage difference between the output terminals of the square unit and the mirror square unit; the control module can determine the target control signal for compensating the mismatch according to the voltage difference; the current adjustment module receives the target control signal and generates a compensation current, eliminating (or at least partially eliminating) the inaccurate problem caused by the mismatch between the square unit and the mirror square unit, effectively expanding the dynamic range of the square circuit.

[0065] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0066] In an embodiment of the present disclosure, as Figure 5 (or Figure 6 or Figure 7 ) shown, the adjustable square circuit 10 (hereinafter simply referred to as the square circuit 10) includes a square unit 101, a mirror square unit 102, a current adjustment module 103, a voltage acquisition module 104, and a control module 105 (or called a controller).

[0067] It should be noted that in the embodiments of the present disclosure, the voltage acquisition module 104 and / or the control module 105 can be a part of the square circuit 10 or an off-chip device independent of the square circuit 10, and no specific limitation is made thereto. In the accompanying drawings, the voltage acquisition module 104 and the control module 105 are included inside the square circuit 10 as an example.

[0068] Among them, the square unit 101 is used to square the received AC signal. The square unit 101 receives a bias voltage and an AC signal, and the output terminal of the square unit 101 outputs a first signal;

[0069] The mirror square unit 102 is used to receive a bias voltage. The structure of the mirror square unit 102 is the same as that of the square unit 101, and the output terminal of the mirror square unit 102 outputs a second signal;

[0070] The current adjustment module 103 is configured to receive a target control signal, generate a compensation current, the magnitude of the compensation current being related to the target control signal, and the output end of the current adjustment module 103 is connected to the output end of the square unit 101 or the mirror square unit 102 for compensating the difference between the first signal and the second signal; wherein, the target control signal is generated by the control module 105 based on the voltage collected by the voltage acquisition module 104;

[0071] The voltage acquisition module 104 is respectively connected to the output ends of the square unit 101 and the mirror square unit 102, and is configured to acquire the output voltage of the output end of the square unit 101 and the output voltage of the output end of the mirror square unit 102;

[0072] The control module 105 is connected to the output end of the voltage acquisition module 104, and is configured to obtain the voltage difference between the output ends of the square unit 101 and the mirror square unit 102, the voltage difference being used to obtain the target control signal, and the target control signal being used to control the degree of current compensation for the output of the square unit 101 and / or the mirror square unit 102.

[0073] It should be noted that, as Figure 5 shown, the signal at the output end of the square unit 101 is denoted as the first signal, and the signal at the output end of the mirror square unit 102 is denoted as the second signal. The square unit 101 and the mirror square unit 102 usually output current signals. Here, after being converted by the equivalent input impedance into voltage signals, the first signal minus the second signal is the output signal. In the description of the embodiments of the present disclosure, only the first signal and the second signal are used to represent the output signals of the square unit 101 and the mirror square unit 102, and the voltage values and current values corresponding to the first signal and the second signal will be involved later. The voltage acquisition module 104 can acquire the voltage values corresponding to the first signal and the second signal, and the current adjustment module 103 performs current compensation on the output of the square unit 101 and / or the mirror square unit 102 (i.e., the first signal and the second signal) based on the control signal.

[0074] The mirror square unit 102 may also receive a feedback signal ( Figures 5 to 7 not shown in the figure).

[0075] It should also be noted that the square unit 101 and the mirror square unit 102 have exactly the same circuit structure (which can be referred to the foregoing Figure 3 , but not limited to the foregoing Figure 3In the structure shown, in the absence of a radio frequency input (i.e., no AC signal input), if there is no mismatch, the voltages corresponding to the first signal and the second signal have exactly the same voltage value (at this time, the voltage value of the output signal is 0). Due to the existence of mismatch, there will be a voltage difference between the voltages corresponding to the first signal and the second signal (i.e., the voltage value of the output signal), and this voltage difference characterizes the degree of mismatch. Based on this voltage difference, a control signal can be determined, and then under the control of the control signal, a compensation current is generated to compensate for the mismatch.

[0076] It should also be noted that, as Figure 5 shown, the output end of the current adjustment module 103 is connected to the output end of the mirror square unit 102, that is, only the second signal is compensated for current; or, as Figure 6 shown, the output end of the current adjustment module 103 is connected to the output end of the square unit 101, that is, only the first signal is compensated for current; or, as Figure 7 shown, the current adjustment module 103 includes two output ends, which are respectively connected to the output ends of the square unit 101 and the mirror square unit 102. The corresponding compensation currents include a first compensation current and a second compensation current, and the first signal and the second signal are compensated for current simultaneously. Finally, in the absence of an AC signal input, the voltage values corresponding to the first signal and the second signal are basically the same (allowing a certain error range).

[0077] Next, the components and working processes in the square circuit 10 will be described in more detail in combination with specific circuit structures respectively.

[0078] In some embodiments, as Figure 8 shown, the current adjustment module 103 includes:

[0079] A digital-to-analog converter 1031, which is used to receive a control signal, perform digital-to-analog conversion on the control signal, and obtain a current control signal; wherein, the control signal can be a digital signal, and the current control signal can be an analog signal. For example, the current control signal is a voltage analog signal; there is a corresponding relationship between the control signal and the current control signal. When the control signal is different, the current control signal is different;

[0080] A first current source I1, which is used to receive the current control signal and generate a compensation current based on the current control signal. Among them, there is a corresponding relationship between the compensation current and the current control signal. When the current control signal is different, the compensation current is different.

[0081] It should be noted that the control signal is a target control signal or an initial control signal used when determining the target control signal. In the relevant descriptions and drawings (including Figures 5 - 7 ) of the embodiments of the present disclosure, it is all described as a control signal.

[0082] It should also be noted that in the embodiments of the present disclosure, the digital-to-analog converter is sometimes also written as DAC (Digital to Analog Converter). As Figure 8 shown, taking the current compensation for the output of the mirror squaring unit 102 as an example, the output terminal of the first current source I1 is connected to the output terminal of the mirror squaring unit 102 to supply the compensation current to the output terminal of the mirror squaring unit 102, so as to realize the current compensation for the second signal; or, if the current compensation is for the output of the squaring unit 101, the output terminal of the first current source I1 is connected to the output terminal of the squaring unit 101 to supply the compensation current to the output terminal of the squaring unit 101, so as to realize the current compensation for the first signal.

[0083] Furthermore, as Figure 9 shown, in some embodiments, the squaring circuit 10 may further include a third current source I3; the output terminal of the current adjustment module 103 is connected to the output terminal of the mirror squaring unit 102, and the output terminal of the third current source I3 is connected to the output terminal of the squaring unit 101;

[0084] The third current source I3 is used to provide a fixed current to supply a fixed current to the output terminal of the squaring unit 101.

[0085] It should be noted that in other examples, it may also be that the first current source I1 is connected to the output terminal of the squaring unit 101 and the third current source I3 is connected to the output terminal of the mirror squaring unit 102.

[0086] It should also be noted that the third current source I3 is an optional fixed current source, and the current it provides is a fixed current (that is, the current value is fixed) and is not controlled by the control signal output by the control module 105. The magnitude of the fixed current can be the current magnitude of the first current source I1 under the default control signal (that is, the control signal is the uncalibrated default value). That is to say, the fixed current of the third current source I3 provides a reference, so that the compensation current can be increased or decreased based on it, thereby realizing the ability of "two-way" adjustment. For example, when there is no deviation between the currents output by the squaring unit 101 and the mirror squaring unit 102, the first current source I1 is under the default control signal, and at this time, the currents output by the first current source I1 and the third current source I3 are equal; when the current output by the squaring unit 101 is greater than the current output by the mirror squaring unit 102, the compensation current output by the first current source I1 can be increased through the control signal; when the current output by the squaring unit 101 is less than the current output by the mirror squaring unit 102, the compensation current output by the first current source I1 can be decreased through the control signal; therefore, compared with the compensation current under the default control signal, the control signal can control the increase or decrease of the compensation current magnitude to achieve two-way compensation.

[0087] In some embodiments, asFigure 10 As shown, taking the square circuit 10 including two current adjustment modules 103 as an example, the two current adjustment modules 103 are respectively: a current adjustment module 103-1 connected to the output end of the square unit 101 and a current adjustment module 103-2 connected to the output end of the mirror square unit 102. Correspondingly, the control signals output by the control module 105 include a first control signal and a second control signal. The current adjustment module 103-1 receives the first control signal, and based on the control of the first control signal, generates a first compensation current to perform current compensation on the output of the square unit 101. The current adjustment module 103-2 receives the second control signal, and based on the control of the second control signal, generates a second compensation current to perform current compensation on the output of the mirror square unit 102.

[0088] Here, both the current adjustment module 103-1 and the current adjustment module 103-2 may include a digital-to-analog converter 1031 and a first current source I1. If there is a mismatch, the magnitudes of the compensation currents generated by the two current sources are different, that is, the degrees of compensation for both are different, thereby improving the mismatch.

[0089] It should also be noted that different connection positions of the first current source I1 result in different compensation methods. For example, the mismatch of the circuit is: in the case of no AC signal input, the voltage value corresponding to the first signal is greater than the voltage value corresponding to the second signal, and the voltage division of the resistor RL1 is less than the voltage division of the resistor RL2, that is, the current flowing through the resistor RL1 is less than the current flowing through the resistor RL2. Therefore, the compensation method can be: reducing Figure 10 the magnitude of the second compensation current to reduce the voltage division of the resistor RL2, thereby increasing the voltage value of the second signal; or increasing Figure 10 the magnitude of the first compensation current to increase the voltage division of the resistor RL1, thereby reducing the voltage value of the first signal; the ultimate goal is to make the voltage value corresponding to the first signal tend to be consistent with the voltage value corresponding to the second signal, thereby achieving compensation.

[0090] In some embodiments, as Figure 11 shown, the first current source I1 includes an operational amplifier P1, a transistor Q1, and a resistor R1; wherein, the non-inverting input terminal (+) of the operational amplifier P1 is connected to the output terminal of the digital-to-analog converter 1031 for receiving a current control signal, the output terminal of the operational amplifier P1 is connected to the base of the transistor Q1, the emitter of the transistor Q1, the inverting input terminal (-) of the operational amplifier P1, and the first end of the resistor R1 are connected, the second end of the resistor R1 is grounded, and the collector of the transistor Q1 outputs a compensation current. Here, the transistor Q1 may specifically be a BJT or an NMOS transistor, and no specific limitation is made thereto.

[0091] It should be noted that the control signal can be a multi-bit digital signal, and after Figure 11The shown structure can convert the analog voltage (i.e., the current control signal) output by the digital-to-analog converter 1031 into a compensation current, and the current value of the compensation current is the ratio of the voltage value of the current control signal to the resistance value of the resistor R1.

[0092] In some embodiments, as Figure 12 shown, the current adjustment module 103 includes:

[0093] A voltage providing unit 1032 for providing a first voltage V1, and the voltage value of the first voltage V1 can be a fixed value;

[0094] A resistor adjusting unit 1033 is connected to the first voltage V1 and receives a control signal, changes the resistance value based on the control signal, and outputs a compensation current, and the compensation current changes with the control signal.

[0095] It should be noted that, as Figure 12 shown, the voltage providing unit 1032 may include an operational amplifier P2 and a transistor Q2, the resistor adjusting unit 1033 includes a plurality of resistors connected in series, and the plurality of resistors form a resistor string, and a switching transistor M1 is further connected in parallel at both ends of the other resistors except the resistor R1. The plurality of switching transistors M1 are connected in series, the control signal is a multi-bit digital signal, and the control end of each switching transistor M1 receives one-bit control signal. Among them, the transistor Q2 can be a BJT, and the switching transistor M1 can be a MOS transistor. The non-inverting input terminal (+) of the operational amplifier P2 receives a fixed voltage VB, and the fixed voltage VB does not change with temperature and power supply; the output terminal of the operational amplifier P2 is connected to the base of the transistor Q2; the emitter of the transistor Q2 and the first end of the resistor string are connected and connected to the inverting input terminal (-) of the operational amplifier P2, and the voltage at the connection node is the first voltage V1; the second end of the resistor string is grounded.

[0096] In Figure 12 , taking the four resistors R2<1> to R2<4> whose two ends are respectively connected in parallel with the switching transistors M1<1> to M1<4> as an example, when the parallel switching transistor M1 is turned on, the corresponding resistor R2 is not connected to the resistor string for voltage division, so that by controlling the conduction of each switching transistor M1 based on the control signal, the resistance value of the resistor string can be changed, the voltage division can be adjusted, and finally the magnitude of the compensation current at the collector output terminal of the transistor Q2 can be adjusted. It can be understood that compared with Figure 11 , in Figure 12 , the digital-to-analog converter is combined with the circuit generating the compensation current, and there is no longer an independent digital-to-analog converter. Among them, the compensation current = VB / (R1 + the resistor not short-circuited by the switching transistor). The BJT among them can also be replaced by an NMOS transistor, and each switching transistor can be an NMOS transistor as Figure 12 shown, or can be a CMOS transmission gate, etc., and the control signal is correspondingly set.

[0097] For the third current source I3 (fixed current source), the digital-to-analog converter 1031 in Figure 11 can be removed, and a fixed control signal can be directly input. The value of this control signal is fixed to make its output a fixed current; or the switching transistor M1 in Figure 12 can be removed, and a fixed resistor R1 can be directly designed to achieve a fixed current.

[0098] It should also be noted that the resistor adjustment unit 1033 can also be multiple resistors connected in parallel. Some or all of the resistors are connected in series with a switching transistor between the first voltage V1 to achieve controllable resistance values. Alternatively, the resistor adjustment unit can also be a voltage-controlled MOS, and the resistance value is controlled based on the voltage. No specific limitation is made in this regard.

[0099] Here, Figure 11 and Figure 12 The circuits shown can both achieve current extraction. That is to say, the direction of the compensation current flows from the collector of the transistor Q1 / Q2 to the ground, and the collector of the transistor Q1 / Q2 is connected to the output end of the mirror square unit 102. Therefore, it is equivalent to current extraction. In the embodiments of the present disclosure, the input end of a PMOS current mirror can also be connected to the collector of the transistor Q1 / Q2, and the output end of the PMOS current mirror is connected to the output end of the mirror square unit 102. Through the current mirroring of the PMOS current mirror, the output current flows out of the PMOS current mirror, which is equivalent to current injection. For current injection, as shown in Figure 13 In some embodiments, the current adjustment module 103 includes:

[0100] A second current source I2 that receives a second voltage and generates a first current, where the second voltage can be a fixed voltage and the first current can be a fixed current;

[0101] A current control circuit 1034 that receives the first current and outputs a compensation current; the current control circuit 1034 adjusts the magnitude of the compensation current based on a control signal.

[0102] It should be noted that as shown in Figure 13As shown, the second current source I2 may include an operational amplifier P3, a transistor Q3, and may further include a resistor R3; the current control circuit 1034 includes a current mirror structure and multiple transistors. The current mirror structure includes an input transistor M21 and an output transistor M22. The input transistor M21 receives a first current, and the output transistor M22 is used to proportionally copy the first current to output a compensation current; multiple transistors M23 to M2n, the control terminals of the transistors M23 to M2n are respectively connected to a switch, and the control terminal of the switch is used to receive a control signal, and the control signal can control the control terminals of the transistors M23 to M2n to be connected to the power supply VDD or to the control terminal of the transistor M22, so as to turn on or off the transistors M23 to M2n, adjust the equivalent size of the output transistor M22, and adjust the magnitude of the compensation current, where n is a positive integer greater than 2.

[0103] The non-inverting input terminal (+) of the operational amplifier P3 receives a second voltage, the output terminal of the operational amplifier P3 is connected to the base of the transistor Q3, the emitter of the transistor Q3 is connected to the inverting input terminal (-) of the operational amplifier P3; the emitter of the transistor Q3 is grounded through the resistor R3; the collector of the transistor Q3 is connected to the first terminal (e.g., drain) and the control terminal (gate) of the transistor M21, and is connected to the control terminal of the transistor M22, and outputs a first current; the second terminals (e.g., sources) of the transistors M21 to M2n are all connected to the power supply VDD; the first terminals of the transistors M22 to M2n are all connected together for outputting a compensation current.

[0104] The control signal is a multi-bit signal, each bit corresponds to one of the transistors M23 to M2n respectively, and is used to control the control terminal of the corresponding transistor to selectively connect to the power supply VDD or the control terminal of the transistor M21 ( Figure 13 the control signal is not shown). For example, when the control signal of the corresponding bit is a high-level logic 1, it is connected to the power supply VDD, and when the control signal of the corresponding bit is a low-level logic 0, it is connected to the control terminal of the transistor M21; or vice versa, which is not specifically limited. Among them, the transistors M21 to M2n may all be PMOS transistors, their control terminals are gates, and one of the first terminal and the second terminal is a source and the other is a drain; the transistor Q3 may be a BJT.

[0105] In this way, by controlling the connection position of the control terminals of the transistors M23 to M2n through the control signal, the magnitude of the output compensation current is controlled, thereby improving the mismatch of the square circuit 10.

[0106] For the voltage acquisition module 104:

[0107] In some embodiments, as Figure 14 shown, the voltage acquisition module 104 includes a first analog-to-digital converter 1041 and a switch unit SW;

[0108] One end of the switch unit SW is connected to the first analog-to-digital converter 1041, and the other end is selectively connected to the output end of the square unit 101 or the output end of the mirror square unit 102;

[0109] The first analog-to-digital converter 1041 is used to perform analog-to-digital conversion on the voltage at the output end of the square unit 101 or the mirror square unit 102, and then output the converted digital signal to the control module 105.

[0110] It should be noted that, as Figure 14 shown, the voltage acquisition module 104 can collect the voltage values corresponding to the first signal and the second signal through an analog-to-digital converter (ADC), that is, the first analog-to-digital converter 1041, also denoted as ADC1. Specifically, the switch unit SW can be a single-pole double-throw switch, which includes three ports: A, B, and C. Among them, port A is connected to the output end of the square unit 101, port B is connected to the output end of the mirror square unit 102, and port C is connected to the input end of the first analog-to-digital converter 1041.

[0111] The control module 105 can also control the connection state of the switch unit SW. When the voltage difference does not need to be collected, port C is not connected to either port A or port B; when the voltage difference needs to be collected, the control module 105 controls port C to be connected to one of port A and port B respectively; for example, the control module 105 first controls port C and port A to be connected, so that the first analog-to-digital converter 1041 collects the analog voltage of the first signal, converts it into a digital signal and sends it to the control module 105, and then the control module 105 controls port C and port B to be connected, so that the first analog-to-digital converter 1041 collects the analog voltage of the second signal, converts it into a digital signal and sends it to the control module 105, and the control module 105 calculates the difference between the two received voltage values to obtain the voltage difference.

[0112] In some embodiments, as Figure 15 shown, the voltage acquisition module 104 includes a second analog-to-digital converter 1042 and a third analog-to-digital converter 1043;

[0113] The second analog-to-digital converter 1042 is connected to the output end of the square unit 101, performs analog-to-digital conversion on the voltage at the output end of the square unit 101, and then outputs it to the control module 105;

[0114] The third analog-to-digital converter 1043 is connected to the output end of the mirror square unit 102, performs analog-to-digital conversion on the voltage at the output end of the mirror square unit 102, and then outputs it to the control module 105.

[0115] It should be noted that in the embodiments of the present disclosure, the switch unit SW may not be provided, and instead, two analog-to-digital converters are used to respectively collect the voltage values corresponding to the first signal and the second signal. As Figure 15 shown, the second analog-to-digital converter 1042 (which may also be denoted as ADC2) collects the voltage value of the first signal and sends it to the control module 105. The third analog-to-digital converter 1043 (which may also be denoted as ADC3) collects the voltage value of the second signal and sends it to the control module 105. The control module 105 calculates the difference between the two received voltage values to obtain the voltage difference.

[0116] Combined with the foregoing drawings and related descriptions, it can be seen that in the embodiments provided by the present disclosure, the voltage acquisition module 104 is used to collect the voltage values corresponding to the first signal and the second signal and send them to the control module 105. The control module 105 is used to output a control signal to the current adjustment module 103. The current adjustment module 103 performs current compensation on the first signal and / or the second signal based on the control signal to improve the mismatch. Each time the square circuit 10 is powered on, the control module 105 controls the circuit to perform a calibration operation to determine the specific value (or state) of the target control signal currently output.

[0117] In the embodiments of the present disclosure, when the current adjustment module 103 outputs a compensation current based on the target control signal, the difference between the first signal and the second signal is minimized, zero, or substantially zero.

[0118] It should be noted that the difference between the first signal and the second signal here represents the difference in the corresponding current or voltage. As described above, in the ideal case, in the absence of an AC signal input, the first signal and the second signal are exactly the same without any difference. Here, in the absence of an AC signal input, after the current adjustment module 103 outputs a compensation current based on the target control signal to perform current compensation on the first signal and / or the second signal, the difference between the first signal and the second signal is minimized (i.e., reaching the lowest achievable difference), zero (the ideal case, completely eliminating the difference), or substantially zero (it is difficult to completely eliminate the difference in practice. Substantially zero can be considered to meet a certain error range. For example, the voltage difference between the first signal and the second signal is less than a threshold, for example, less than 1% - 5% of the swing of the AC signal, or the absolute value of the voltage difference between the first signal and the second signal is less than 1 mV - 10 mV. Meeting this requirement, the voltage difference / current difference can be ignored).

[0119] In this solution, a self-adjustment method for the square circuit 10 is also provided, including:

[0120] Obtaining a voltage difference, where the voltage difference can be collected by the voltage acquisition module 104;

[0121] Based on the voltage difference, a target control signal is determined and output to the current adjustment module 103 to compensate for the difference between the first signal and the second signal, eliminating (or at least partially eliminating) the inaccuracy problem caused by the mismatch between the square unit 101 and the mirror square unit 102.

[0122] This self-regulation method can be executed by the control module 105, which can be implemented by software or hardware. In some embodiments, the control module 105 includes a processor and a memory; the processor is used to execute the instructions stored in the memory so that the control module 105 executes the aforementioned self-regulation method. It should be noted that the control module 105 can be a digital circuit or composed of logic circuits, and no specific limitation is made thereto.

[0123] It should also be noted that the process of determining the target control signal based on the voltage difference can be referred to as the operation of determining the target control signal or the self-regulation operation (the operation of automatically adjusting the compensation current). Specifically, it can include the following two types:

[0124] The first self-regulation operation:

[0125] When there is no AC signal input, an initial control signal is output to the current adjustment module 103;

[0126] The voltage difference is obtained;

[0127] By traversing different initial control signals, the initial control signal corresponding to the minimum voltage difference is determined as the target control signal;

[0128] The target control signal is output to the current adjustment module 103.

[0129] The second self-regulation operation: The control module 105 obtains the target control signal by looking up a table based on the voltage difference. It includes:

[0130] The voltage difference is obtained;

[0131] According to the voltage difference, a search is performed in the storage module 106 to determine the target control signal, and the corresponding target control signal is output to the current adjustment module 103.

[0132] In the embodiments of the present disclosure, both the above first self-regulation operation and the second self-regulation operation can be executed by the control module 105, and the embodiments of the present disclosure also provide corresponding specific operation methods (or self-regulation methods). The following will be described separately.

[0133] For the first self-regulation operation, the control module 105 is connected to the output terminal of the voltage acquisition module 104; the operation of determining the target control signal executed by the control module 105 includes:

[0134] When there is no AC signal input, the control module 105 outputs an initial control signal to the current adjustment module 103. The initial control signal is a preset control signal. The initial control signal is output to the current adjustment module 103. The current adjustment module 103 outputs a compensation current based on the initial control signal. The voltage acquisition module 104 acquires the output voltage of the square unit 101 and the output voltage of the mirror square unit 102. The control module 105 obtains the voltage difference between the outputs of the square unit 101 and the mirror square unit 102. In this way, the voltage difference corresponding to the first signal and the second signal under the control of a certain initial control signal is obtained.

[0135] The control module 105 traverses different initial control signals and obtains all voltage differences. That is, in the case of no AC signal input, current compensation is performed once for each initial control signal, and the voltage difference corresponding to each initial control signal is obtained.

[0136] The control module 105 compares all the voltage differences. The smaller the voltage difference, the closer the first signal output by the square unit 101 and the second signal output by the mirror square unit 102 are, and the better the process deviation can be compensated. The control module 105 determines the initial control signal corresponding to the smallest voltage difference as the target control signal.

[0137] The control module 105 outputs the target control signal to the current adjustment module 103. The current adjustment module 103 can generate a compensation current with a suitable magnitude. At this time, the compensation current can well compensate the process deviation. When a subsequent AC signal is input, the current adjustment module 103 can continuously provide a compensation current with a suitable magnitude.

[0138] It should be noted that the initial control signal is used to traverse the control signals that the control module 105 can output to find the most suitable control signal in the current state as the target control signal. Under the control of the target control signal, the compensation current output by the current adjustment module 103 can make the voltage difference between the first signal and the second signal as small as possible (approaching 0) in the case of no AC signal input. Suppose the control module 105 can output 100 different initial control signals (the control signals that have not been determined as the target control signal are denoted as the initial control signal). When there is no AC signal input, the current adjustment module 103 is controlled by these 100 initial control signals respectively, and the compensation current is output to compensate the first signal and / or the second signal. The voltage acquisition module 104 acquires the voltage values corresponding to the compensated first signal and the second signal and sends them to the control module 105. Thus, the control module 105 will calculate 100 voltage differences (taking the absolute value), and determine the initial control signal corresponding to the smallest voltage difference as the target control signal.

[0139] For the specific implementation process of the first self-regulation operation, takeFigure 14 Taking the calibration of the circuit shown as an example, such as Figure 16 shown, the first self-adjustment operation may specifically include:

[0140] S601: The control module 105 controls the switch unit SW to connect port C to port A.

[0141] It should be noted that before step S601, it may also include the step of resetting the initial control signal and outputting an initial control signal to the current adjustment module 103. The initial control signal is output to the current adjustment module 103 for testing to obtain the target control signal.

[0142] It should be noted that the control signal can be a multi-bit signal. At the start of the test, the initial control signal needs to be reset, which is equivalent to initialization. The reset initial control signals can all be default initial values as the basis for comparison.

[0143] Alternatively, the reset initial control signal is the first initial control signal in the traversal. For example, assuming that the control module 105 can output 100 initial control signals, C1, C2, C3,..., C100, during the test, these 100 initial control signals need to be traversed, and the initial control signal that makes the voltage difference between the output terminals of the square unit 101 and the mirror square unit 102 the smallest when there is no AC signal input is determined as the target control signal. Any one of these 100 initial control signals can be determined as the reset initial control signal. For example, the traversal can be carried out in the order of C1 to C100, and C1 can be determined as the reset initial control signal in this step first, or in other orders, which is not limited here.

[0144] S602: The control module 105 controls ADC1 to sample, reads the sampling result, and records it as VA.

[0145] S603: The control module 105 controls the switch unit SW to connect port C to port B.

[0146] S604: The control module 105 controls ADC1 to sample, reads the sampling result, and records it as VB.

[0147] S605: The control module 105 calculates the voltage difference |VA - VB|.

[0148] S606: The control module 105 determines whether the voltage difference is less than the optimal voltage difference.

[0149] Among them, the optimal voltage difference is the currently recorded minimum voltage difference; if the optimal voltage difference has not been recorded before, the voltage difference calculated in step S605 is used as the optimal voltage difference.

[0150] If the judgment result is yes, then step S607 is executed; otherwise, step S608 is executed.

[0151] S607: The control module 105 records the current initial control signal and voltage difference as the target control signal and the optimal voltage difference respectively.

[0152] S608: The control module 105 steps the initial control signal output to the DAC.

[0153] It should be noted that here, the example of step - by - step increase is taken, but it is not limited to this.

[0154] S609: The control module 105 determines whether the initial control signal exceeds the maximum value.

[0155] If the judgment result is yes, then step S6010 is executed; otherwise, step S601 is executed.

[0156] S6010: The control module 105 latches the target control signal to the DAC.

[0157] After the DAC latches the target control signal, within the power - on duration, the current adjustment module 103 can continuously provide an appropriate compensation current to compensate for the mismatch between the square unit 101 and the mirror square unit 102.

[0158] In short, the control module 105 searches for the target control signal (or the optimal compensation control code) when the voltage difference is closest to 0 by scanning the initial control signal (or the compensation circuit control code). The initial control signal starts scanning and increasing from 0. At each initial control signal, the control module 105 first controls the switch unit SW (single - pole double - throw switch) and the analog - to - digital converter 1031 (ADC) to sample the voltages of port A and port B respectively, and calculates the absolute value of the voltage difference under the current initial control signal. If the absolute value of the current voltage difference is less than the optimal voltage difference, then the absolute value of the current voltage difference is recorded as the optimal voltage difference, and the current initial control signal is recorded as the target control signal. Then, the initial control signal is changed, and the above process is repeated until the initial control signal reaches the upper limit. The finally obtained target control signal is latched to the DAC, and even after the process of the control module 105 ends, this value will not change until power - off.

[0159] After the control module 105 is reset, it will return to the starting state and execute this process again. In some embodiments, the control module 105 is reset when powered on, such as Figure 14 or Figure 15 As shown, the square circuit 10 may further include:

[0160] The trigger module 108 is configured to receive a reset signal and / or an external sampling signal, and output a trigger signal to the control module 105 when any one of the reset signal and the external sampling signal is in an enabled state; the trigger signal is used to trigger the control module 105 to perform a first self-regulation operation (i.e., the operation of determining a target control signal).

[0161] It should be noted that, in the embodiments of the present disclosure, the first self-regulation operation can be triggered by a trigger signal. For example, the trigger signal can be a reset signal or an external sampling signal. As Figure 14 Or Figure 15 shown, the reset signal can be provided by a power-on reset circuit 109 (Power on Reset, POR), that is, when powering on, the power-on reset circuit 109 will generate a pulse signal to reset the control module 105 and trigger the control module 105 to perform a calibration; alternatively, an external sampling signal can be provided by the user to actively initiate a calibration operation. This power-on trigger or user-initiated self-regulation operation is usually the first self-regulation operation. In this way, after each power-on, a calibration is performed to ensure that the square circuit 10 can work in the minimum mismatch state after each power-on. As Figure 14 Or Figure 15 shown, the trigger module 108 can be implemented by an OR gate 1081, and the OR gate 1081 is used to combine two high-level pulses. If other types of reset signals are used, the combinational logic here can also be modified as needed. This process can be implemented by hardware or software. For software implementation, additional execution units and memories are required to execute and store the code. It can be understood that when the self-regulation process is executed, there should be no AC signal input.

[0162] For the specific implementation process of the first self-regulation operation, taking the calibration of the circuit shown in Figure 15 as an example, as Figure 17 shown, the first self-regulation operation can specifically include:

[0163] S701: The control module 105 controls the ADC2 to sample, reads the sampling result, and records it as VA.

[0164] It should be noted that, before step S701, there may also be a step of resetting the initial control signal and outputting an initial control signal to the current adjustment module 103.

[0165] S702: The control module 105 controls the ADC3 to sample, reads the sampling result, and records it as VB.

[0166] S703: The control module 105 calculates the voltage difference |VA - VB|.

[0167] S704: The control module 105 determines whether the voltage difference is less than the optimal voltage difference.

[0168] If the judgment result is yes, then execute step S705; otherwise, execute step S706.

[0169] S705: The control module 105 records the current initial control signal and voltage difference as the target control signal and the optimal voltage difference respectively.

[0170] S706: The control module 105 steps the initial control signal output to the DAC.

[0171] It should be noted that here, the example of increasing in steps is still used, but it is not limited to this.

[0172] S707: The control module 105 determines whether the initial control signal exceeds the maximum value.

[0173] If the judgment result is yes, then execute step S708; otherwise, execute step S701.

[0174] S707: The control module 105 latches the target control signal to the DAC.

[0175] After the DAC latches the target control signal, within the power-on duration, the current adjustment module 103 can continuously provide a compensation current with a suitable magnitude to compensate for the mismatch between the square unit 101 and the mirror square unit 102.

[0176] Figure 17 The circuit corresponding to the described implementation method ( Figure 15 ) compared with The circuit corresponding to the described implementation method ( Figure 16 ) only has one less single-pole double-throw switch, and uses two ADCs to collect the voltages at port A and port B respectively. Compared with Figure 14 The control module 105 of the described implementation method is simple to implement, but due to adding an ADC, the chip area and power consumption increase, and the controller logic is correspondingly simplified.

[0177] In some embodiments, when the chip temperature changes greatly after power-on, a calibration is triggered to avoid the mismatch changing with temperature. For this purpose, as Figure (16 shown, in some embodiments, the square circuit 10 may further include a temperature sensor 107 for determining the current temperature; the trigger module 108 is also connected to the temperature sensor 107 for generating a trigger signal when the difference between the current temperature and the previously detected temperature is greater than a preset temperature threshold.

[0178] It should be noted that if the self - regulation operation is triggered only once when powering on, then as the working time extends, the device heats up severely, resulting in a temperature increase, and the ambient temperature outside the chip will also change. At different temperatures, the circuit mismatch may also change. Therefore, in the embodiments of the present disclosure, the first self - regulation operation can also be performed only when the temperature changes greatly to ensure that even if the mismatch changes, effective current compensation can be carried out in a timely manner.

[0179] Exemplarily, as Figure 18 shown, the trigger module 108 may further include a trigger signal generation module 1082, which is respectively connected to the temperature sensor 107 and the OR gate 1081. The temperature sensor 107 collects the current temperature in real - time or periodically and sends it to the trigger signal generation module 1082. The trigger signal generation module 1082 compares the current temperature value with the previous temperature value. If the difference (taking the absolute value) between the two is greater than a preset temperature threshold, it means that the temperature difference between the two times is large and self - regulation needs to be performed again. Then it outputs a trigger signal to trigger the control module 105 to perform the first self - regulation operation to ensure that the target control signal meets the current temperature requirement. At the same time, the trigger signal generation module 1082 can also receive the signal output by the OR gate 1081 and perform a trigger operation when either the reset signal or the external sampling signal is enabled.

[0180] In some embodiments, the trigger module 108 is not limited to Figure 18 the structure shown. For example, the OR gate 1081 may include three input terminals, which respectively receive the reset signal, the external sampling signal, and the temperature reset signal sent by the trigger signal generation module 1082. The temperature reset signal is used to indicate that the difference between the current temperature and the temperature detected last time is greater than a preset temperature threshold.

[0181] The above - mentioned ways of triggering self - regulation operations by temperature, reset signal, and external sampling signal can adopt only one of them, or two of them, or all three of them, and no specific limitation is made in this regard.

[0182] In some embodiments, as Figure 18As shown, a first switch S1 may be connected between the input terminal of the square unit 101 and the input terminal of the AC signal, and a second switch S2 may be connected between the input terminal of the mirror square unit 102 and the input terminal of the feedback signal. During the first self - adjustment operation, the control module 105 generates an input control signal in a non - enabled state, disconnects both the first switch S1 and the second switch S2. At this time, the AC signal (radio frequency signal) is not sent to the square unit 101, which can avoid affecting the calibration, and the feedback signal is not sent to the mirror square unit 102 either. After the calibration is completed, the control module 105 outputs an input control signal in an enabled state to re - conduct the first switch S1 and the second switch S2, so as to perform square calculation on the AC signal (radio frequency signal).

[0183] In some embodiments, as Figure 18 shown, the control module 105 is further configured to generate and output a calibration status indication signal during the operation of determining the target control signal (self - adjustment operation), and the calibration status indication signal is used to indicate that the output of the square circuit 10 is invalid.

[0184] To Figure 18 take the calibration of the square circuit 10 shown as an example, as Figure 18 shown, this working process also corresponds to the aforementioned first self - adjustment operation, including:

[0185] S801: The control module 105 outputs a calibration status indication signal in the first state (such as high level).

[0186] The calibration status indication signal is used to indicate that the current is in the calibration state. The calibration status indication signal can be sent to the host computer (such as the baseband), and the host computer knows that the current is in the calibration state according to the first state of the calibration status indication signal.

[0187] S802: The control module 105 controls the switches S1 and S2 at the AC signal and the feedback signal to be disconnected, and the AC signal and the feedback signal are not input into the square unit 101 and the mirror square unit 102.

[0188] It should be noted that before step S803, there may also be a step of resetting the initial control signal and outputting an initial control signal to the current adjustment module 103.

[0189] S803: The control module 105 controls ADC2 to sample, reads the sampling result, and records it as VA.

[0190] S804: The control module 105 controls ADC3 to sample, reads the sampling result, and records it as VB.

[0191] S805: The control module 105 calculates the voltage difference |VA - VB|.

[0192] S806: The control module 105 determines whether the voltage difference is less than the optimal voltage difference.

[0193] If the determination result is yes, step S807 is executed; otherwise, step S808 is executed.

[0194] S807: The control module 105 records the current initial control signal and voltage difference as the target control signal and the optimal voltage difference respectively.

[0195] S808: The control module 105 steps the initial control signal output to the DAC.

[0196] It should be noted that here, taking the step - by - step increase method as an example, but not limited to this.

[0197] S809: The control module 105 determines whether the initial control signal exceeds the maximum value.

[0198] If the determination result is yes, step S8010 is executed; otherwise, step S801 is executed.

[0199] S8010: The control module 105 latches the target control signal to the DAC. After the DAC latches the target control signal, within the power - on duration, the current adjustment module 103 can continuously provide an appropriate compensation current to compensate for the mismatch between the square unit 101 and the mirror square unit 102.

[0200] S8011: The control module 105 controls the switches S1 and S2 at the AC signal and the feedback signal to close, and the AC signal and the feedback signal can be input into the square unit 101 and the mirror square unit 102.

[0201] S8012: The control module 105 outputs a calibration status indication signal in the first state (such as low level) to notify the host computer that the calibration is completed.

[0202] In short, since calibration needs to ensure no RF signal input, to avoid frequently interrupting the normal working process, in Figure 19 the described circuit, an additional temperature sensor 107 is added, and calibration is only performed once when the temperature changes significantly. At the same time, a trigger signal generation module 1082 is also added. The trigger signal (or denoted as the RST signal) of the control module 105 is generated in two cases:

[0203] 1. External input, which is generated by the power-on reset circuit 109 when power is applied, or manually generated externally. When the trigger signal generation module 1082 receives such a signal, it will immediately output a trigger signal to the control module 105 to perform a first self-regulation operation. That is, this triggering method is to automatically generate a reset signal by the power-on reset circuit 109 when power is applied to trigger the execution of a self-regulation, or an external sampling signal requests the execution of a self-regulation. Under this condition, the trigger signal generation module 1082 will query the current temperature output by the temperature sensor 107 once and record it.

[0204] 2. Generated internally by the trigger signal generation module 1082: The trigger signal generation module 1082 will periodically check the current temperature output by the temperature sensor 107. When there is a large difference between the current temperature and the previously recorded temperature, that is, when the temperature has changed significantly, the trigger signal generation module 1082 will generate a trigger signal to the control module 105 to make it perform a self-regulation again. At the same time, the trigger signal generation module 1082 will record the current temperature.

[0205] In this way, in addition to power-on and external triggering, this method will only perform a self-regulation when the temperature changes significantly, and the number of interruptions to the normal working process is less.

[0206] At the same time, when the calibration process starts, the control module 105 will disconnect the switches of the internal radio frequency input and the optional feedback loop of the chip, so as to ensure that there is no radio frequency signal input and avoid the influence of radio frequency signals on calibration. At the same time, as Figure 18 shown, the control module 105 will also provide an external calibration status indication signal, indicating that the current is in the calibration process and the output of the detector is invalid.

[0207] Since the first self-regulation operation needs to be performed without an AC signal input, in this way, it is possible to accurately judge the compensation effect based on the voltage difference. Therefore, in some embodiments, the control module 105 is further configured to disconnect the AC signal input of the square unit 101 during the execution of the first self-regulation operation to ensure a state without an AC signal input. At the same time, in the case of the presence of a feedback signal input, the feedback signal input of the mirror square unit 102 is also disconnected.

[0208] It should be noted that during the first self-regulation operation, there is no AC signal input to the square circuit 10, so its output signal is invalid. In order to avoid incorrect interference with the operation of the subsequent circuit, a calibration status indication signal is output externally during self-regulation to indicate that the output of the square circuit 10 is invalid. For example, if the subsequent stage is a recording module, it can not record the output voltage at this moment according to this calibration status indication signal.

[0209] In some embodiments, as Figure 18As shown, the squaring circuit 10 may further include a storage module 106 for storing the correspondence between the voltage difference and the target control signal. The voltage difference is the voltage difference between the output terminals of the squaring unit 101 and the mirror squaring unit 102 in the case of no AC signal input. Since the storage module 106 stores the correspondence between the voltage difference and the target control signal, during calibration, only the voltage difference needs to be obtained, and the corresponding target control signal can be found according to the voltage difference (which can be understood as looking up a table), without traversing the initial control signals during calibration, which can save the calibration time.

[0210] It should be noted that in the case where the squaring circuit 10 includes two current adjustment modules 103, correspondingly, the storage module 106 stores two correspondences: the correspondence between the voltage difference and the first control signal, and the correspondence between the voltage difference and the second control signal. The control signals output by the control module 105 based on the voltage difference include the first control signal and the second control signal.

[0211] In other examples, the storage module 106 may also be independent outside the squaring circuit 10 or integrated inside the control module 105, and no specific limitation is made thereto. Among them, the storage module 106 can have various implementation manners, such as one-time programmable memory EFUSE, on-chip read-only memory (ROM), off-chip ROM connected through protocols such as Serial Peripheral Interface (SPI), display look-up table (LUT), and so on.

[0212] The embodiment of the present disclosure also provides a second self-adjustment operation. The second self-adjustment operation is based on the correspondence between the voltage difference and the target control signal stored in the storage module 106, and does not need to interrupt the normal operation of the squaring circuit 10 for a long time. Specifically, the control module 105 can be connected to the storage module 106, and the second self-adjustment operation executed by the control module 105 includes:

[0213] The control module 105 obtains the voltage difference, where the voltage difference is the voltage difference between the output terminals of the squaring unit 101 and the mirror squaring unit 102; for example, the control module 105 can obtain the voltage difference from the voltage acquisition module 104;

[0214] The control module 105 searches in the storage module 106 according to the voltage difference to determine the target control signal, and outputs the target control signal corresponding to the voltage difference to the current adjustment module 103. The target control signal is used to control the current adjustment module 103 to output a compensation current with a suitable magnitude.

[0215] It should also be noted that the control signals stored in the storage module 106 are denoted as target control signals, and each value or range of voltage differences corresponds to a target control signal. For example, 100 different voltage differences and the corresponding target control signals are preset, and these 100 voltage differences and the corresponding target control signals are stored in the storage module 106. Then, when performing the second self-regulation operation, the inputs of the square unit 101 and the mirror square unit 102 are first cut off, and at the same time, a calibration status indication signal can be output to the outside. The current voltage difference is determined according to the voltage value collected by the voltage acquisition module 104, and then the current voltage difference is compared with the 100 voltage differences stored in the storage module 106 to determine which voltage difference the current voltage difference matches, that is, which voltage difference the current voltage difference is closest to (equal, or the difference between the two is less than a certain voltage difference error threshold). Then, the target control signal corresponding to the matched voltage difference is output to the current adjustment module 103, and the current adjustment module 103 outputs a compensation current accordingly.

[0216] It should be noted that the voltage difference to be collected here is in the case of no AC signal input, and the AC signal input also needs to be temporarily cut off. However, since the target control signal is searched in the storage module 106, compared with the method of traversing multiple initial control signals to determine a target control signal (i.e., the first self-regulation operation), the interference to the normal operation of the square circuit 10 is relatively small.

[0217] In some embodiments, determining the corresponding relationship between different voltage differences and target control signals may include: under different voltage differences, the control module 105 tests different initial control signals and selects the initial control signal that makes the voltage difference the smallest as the target control signal corresponding to the voltage difference;

[0218] The control module 105 traverses different voltage differences, obtains the corresponding relationship between all voltage differences and target control signals, and stores it in the storage module 106.

[0219] Among them, the control module 105 is also used to perform the operation of obtaining the corresponding relationship when receiving an indication signal for obtaining the corresponding relationship.

[0220] Exemplarily, the target control signal corresponding to each voltage difference can be determined by a test operation. Therefore, the indication signal for obtaining the corresponding relationship can be a test status indication signal, and the operation of obtaining the corresponding relationship can be a test operation. The control module 105 performs the test operation when receiving the test status indication signal.

[0221] The test operation is usually performed in advance. At this time, the test operation can be triggered by a test status indication signal. In this case, after the test operation, the target control signal corresponding to the voltage difference is stored in the storage module 106. When the voltage difference changes or periodically in combination with the current voltage difference, the corresponding target control signal is searched in the storage module 106 (i.e., the second self-regulation operation is performed) to determine the compensation current, and the self-regulation operation can be triggered without a trigger signal, that is, the trigger module 108 can be dispensed with. Alternatively, it can also be combined with the trigger module 108 to trigger calibration when the chip is powered on or manually, so as to avoid the change of mismatch and the poor effect of the stored target control signal after working for a certain period of time.

[0222] In some embodiments, the control module 105 is configured to perform a test operation (i.e., an operation to obtain the correspondence), and the operation to obtain the correspondence includes:

[0223] When there is no AC signal input, at each voltage difference:

[0224] The control module 105 outputs an initial control signal, and the initial control signal is a preset control signal; the initial control signal is output to the current adjustment module 103, and the current adjustment module 103 outputs a compensation current based on the initial control signal; the voltage acquisition module 104 acquires the output voltage of the square unit 101 and the output voltage of the mirror square unit 102; the control module 105 obtains the voltage difference between the output terminals of the square unit 101 and the mirror square unit 102; in this way, the corresponding voltage difference under the control of this initial control signal is obtained;

[0225] The control module 105 traverses different initial control signals and obtains all voltage differences;

[0226] The control module 105 determines the initial control signal corresponding to the minimum voltage difference as the target control signal corresponding to this voltage difference;

[0227] The control module 105 stores the correspondence between different voltage differences and the target control signal in the storage module 106.

[0228] It should be noted that the operation to obtain the correspondence is equivalent to performing the first self-regulation operation for each voltage difference, and then saving the determined target control signal and the corresponding voltage difference. The specific execution process will not be elaborated here.

[0229] In this way, the target control signal is the one that has the best mismatch improvement effect under the corresponding voltage difference, and can minimize this voltage difference. Moreover, since the target control signal is pre-stored in the storage module 106, it is not necessary to interrupt the normal processing of the AC signal by the squaring circuit 10 for a long time, thus avoiding affecting the operation of the circuit. In the embodiment of the present disclosure, the second self-adjustment operation can also be triggered by a trigger signal.

[0230] Taking the test operation and the second self-adjustment operation on the Figure 20 shown circuit as an example, as Figure 20 shown, this process includes:

[0231] S401: The control module 105 determines whether it is in the test state according to the test status indication signal.

[0232] If the determination result is yes, steps S402 to S4013 (i.e., the test operation) are executed; otherwise, steps S4014 to S4017 (i.e., the second self-adjustment operation) are executed.

[0233] Before step S402, the squaring circuit 10 can be first placed at a first preset temperature so that there is a first initial voltage difference between the first signal and the second signal.

[0234] S402: The control module 105 controls the second analog-to-digital converter 1042 (ADC2) to sample the voltage value of the first signal, and the read result is recorded as VA1.

[0235] S403: The control module 105 controls the third analog-to-digital converter 1043 (ADC3) to sample the voltage value of the second signal, and the read result is recorded as VB1.

[0236] S404: The control module 105 calculates the voltage difference |VA1 - VB1|, and records this voltage difference |VA1 - VB1| as the initial voltage difference.

[0237] It should be noted that the absolute value of VA1 and VB1 is taken for the voltage difference here.

[0238] S405: The control module 105 resets the initial control signal and the optimal voltage difference.

[0239] It should be noted that the control signal can be a multi-bit signal. At the start of the test, it is necessary to reset the initial control signal and the optimal voltage difference, which is equivalent to initialization. The reset initial control signal and the optimal voltage difference can both be default values. Or, the reset initial control signal is the first initial control signal for traversal.

[0240] Among them, the optimal voltage difference represents the minimum voltage difference between the output terminals of the square unit 101 and the mirror square unit 102 when there is no AC signal input among the initial control signals that have been traversed. Before entering the test state and before starting to adjust based on the initial control signal, the reset optimal voltage difference can be the default value or the voltage difference detected before the adjustment.

[0241] It should be noted that after resetting the initial control signal, the control module 105 will send the reset initial control signal to the current adjustment module 103, and the current adjustment module 103 will perform current compensation based on the initial control signal.

[0242] S406: The control module 105 controls the ADC2 to sample, and the read result is recorded as VA2.

[0243] S407: The control module 105 controls the ADC3 to sample, and the read result is recorded as VB2.

[0244] S408: The control module 105 calculates the voltage difference |VA2 - VB2|.

[0245] It should be noted that the voltage difference here takes the absolute value of VA2 and VB2.

[0246] S409: The control module 105 determines whether the voltage difference |VA2 - VB2| is less than the optimal voltage difference.

[0247] If the judgment result is yes, it means that the compensation effect of the current initial control signal is better than that of the previously tested control signals, then step S4010 is executed; otherwise, it means that the compensation effect of the current initial control signal is not as good as that of the previously tested control signals, and step S4011 is executed.

[0248] S4010: The control module 105 records the current initial control signal and the voltage difference as the target control signal and the optimal voltage difference respectively.

[0249] S4011: The control module 105 steps the initial control signal output to the DAC.

[0250] It should be noted that if the initial control signals are output one by one in ascending order, the next initial control signal is output with a step increase according to the corresponding step value; if the initial control signals are output one by one in descending order, the next initial control signal is output with a step decrease according to the corresponding step value; or, the initial control signals can also be output in other preset orders or any order, and no specific limitation is made here. Here, taking a step increase as an example, for example, the 100 initial control signals C1 to C100 that increase in sequence, the difference between two adjacent initial control signals is the step value, then after traversing C1, the next one to traverse is C2.

[0251] S4012: The control module 105 determines whether the initial control signal exceeds the maximum value.

[0252] If the judgment result is yes, step S4013 is executed, indicating that the target control signal corresponding to the initial voltage difference is found; otherwise, return to execute step S406.

[0253] For example, for the 100 initial control signals C1 to C100 that increase in sequence as described above, the maximum value of the initial control signal is C100. If the issued initial control signal is C101, it exceeds the maximum value.

[0254] S4013: The control module 105 writes the initial voltage difference and the target control signal into the storage module 106.

[0255] After that, the square circuit 10 can be placed at the second preset temperature so that there is a second initial voltage difference between the first signal and the second signal; then steps S402 to S4013 are executed to find the target control signal corresponding to the second initial voltage difference. And so on, the square circuit 10 is placed at all preset temperatures to find the target control signals corresponding to all initial voltage differences, and the corresponding relationship between the voltage difference and the target control signal is obtained.

[0256] S4014: The control module 105 reads all the voltage differences and target control signals in the storage module 106.

[0257] S4015: The control module 105 obtains the current voltage difference.

[0258] It should be noted that when obtaining the current voltage difference here, the AC signal input needs to be cut off to obtain the voltage difference in the case of no AC signal input.

[0259] S4016: The control module 105 calculates the target control signal corresponding to the current voltage difference.

[0260] S4017: The control module 105 latches and outputs the calculated target control signal to the DAC (digital-to-analog converter 1031), so as to obtain the target control signal corresponding to the current voltage difference, and send it to the current adjustment module 103 to control the current adjustment module 103 to output a compensation current to compensate for the mismatch between the square unit 101 and the mirror square unit 102.

[0261] Briefly, during the pre - shipment test of the chip, the test status indication signal is pulled high to enter the test state. At this time, the external sampling signal is no longer for the reset function, but can still be a pulse. With the cooperation of the host computer of the test system, for each voltage difference, an external sampling signal is sent to the chip once. When the chip receives the sampling signal, it will perform a self - adjustment operation process to determine the corresponding target control signal, and record both the voltage difference and the target control signal in the storage module 106.

[0262] The host computer can perform self - adjustment according to a certain voltage step. After calibration is completed, when the chip is in normal use, the test status indication signal is pulled low to exit the test state and enter the normal working state. The control module 105 will read all the voltage differences and target control signals in the storage module 106. Then, it will cyclically obtain the current voltage difference at a certain frequency, and according to the previous records, confirm the compensation circuit control code required for the current voltage difference through methods such as interpolation, and latch and output it to the DAC. Thus, mismatch compensation under different voltage differences is achieved.

[0263] Figure 21 Figure 21 The corresponding implementation method moves the self - adjustment operation to the test process before the chip leaves the factory. By additionally adding a storage module 106 to record calibration data. During the calibration process, no radio frequency signal (i.e., alternating current signal) is input. This method does not need to interrupt the normal working process.

[0264] As described above, it is only a preferred embodiment of the present disclosure and is not used to limit the protection scope of the present disclosure.

[0265] It should be noted that in the present disclosure, the term "comprising", "including" or any other variation thereof is intended to cover a non - exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0266] The serial numbers of the above - mentioned embodiments of the present disclosure are only for description and do not represent the superiority or inferiority of the embodiments.

[0267] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0268] The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0269] The features disclosed in several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0270] As mentioned above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure.

Claims

1. An adjustable square circuit, characterized in that, Comprising: A squaring unit for squaring the received AC signal. The squaring unit receives a bias voltage and the AC signal, and the output end of the squaring unit outputs a first signal; A mirror squaring unit for receiving the bias voltage. The structure of the mirror squaring unit is the same as that of the squaring unit, and the output end of the mirror squaring unit outputs a second signal; A current adjustment module for receiving a target control signal and generating a compensation current. The magnitude of the compensation current is related to the target control signal. The output end of the current adjustment module is connected to the output end of the squaring unit and / or the output end of the mirror squaring unit, and is used to compensate the current at the output end of the squaring unit and / or compensate the current at the output end of the mirror squaring unit, so as to compensate for the difference between the first signal and the second signal; wherein, the target control signal is generated by a control module based on the voltage difference collected by a voltage collection module; the voltage collection module is used to collect the output voltage of the squaring unit and the output voltage of the mirror squaring unit; the control module is used to obtain the voltage difference between the output ends of the squaring unit and the mirror squaring unit, and the voltage difference is used to obtain the target control signal.

2. The square circuit according to claim 1, characterized in that, The difference between the first signal and the second signal is minimized, zero or substantially zero.

3. The square circuit according to claim 1, wherein The squaring circuit further includes: The control module, connected to the output end of the voltage collection module; the control module is configured to perform an operation of determining the target control signal: [[ID= ​ ​ ​ 4. The squaring circuit according to claim 1, characterized in that, ​ ​ ​ ​ ​ 5. The square circuit according to claim 4, characterized in that, ​ ​ ​ ​ 6. The square circuit according to claim 1, wherein ​ ​ 7. The square circuit according to any one of claims 1 to 6, characterized in that, ​ ​ 8. The square circuit according to claim 7, wherein ​ The temperature sensor is used to determine the current temperature; The trigger module is further configured to generate the trigger signal when the difference between the current temperature and the temperature detected last time is greater than a temperature threshold.

9. The squaring circuit according to any one of claims 1 to 6, characterized in that, The squaring circuit further includes a first switch and a second switch. The first switch is located between the input end of the squaring unit and the input end of the AC signal. The second switch is located between the input end of the mirror squaring unit and the input end of the feedback signal; The control module is further configured to disconnect the first switch and the second switch during the operation of determining the target control signal.

10. The squaring circuit according to any one of claims 1 to 6, characterized in that, The control module is further configured to generate and output a calibration status indication signal during the operation of determining the target control signal. The calibration status indication signal is used to indicate that the output of the squaring circuit is invalid.

11. The squaring circuit according to claim 1, characterized in that, The current adjustment module includes: A digital-to-analog converter, configured to receive the target control signal, perform digital-to-analog conversion on the target control signal, and obtain a current control signal; A first current source, configured to receive the current control signal, generate the compensation current based on the current control signal, and the output end of the first current source is connected to the output end of the squaring unit or the mirror squaring unit.

12. The square circuit according to claim 1, characterized in that, The current adjustment module includes: A voltage providing unit, configured to provide a first voltage; A resistance adjusting unit, connected to the first voltage, receiving the target control signal, changing the resistance value based on the target control signal, and outputting the compensation current.

13. The square circuit according to claim 1, wherein The current adjustment module includes: A second current source, receiving a second voltage, generating a first current; A current control circuit, receiving the first current, and outputting the compensation current; the current control circuit adjusts the magnitude of the compensation current based on the target control signal.

14. The squaring circuit according to any one of claims 1-6, 8, 11-13, characterized in that The squaring circuit further includes a third current source; the output end of the current adjustment module is connected to the output end of one of the squaring unit and the mirror squaring unit, and the output end of the third current source is connected to the output end of the other of the squaring unit and the mirror squaring unit; The third current source is configured to provide a fixed current.

15. The squaring circuit according to any one of claims 3-5, characterized in that, The squaring circuit includes at least two current adjustment modules for generating at least two compensation currents; the control module obtains at least two target control signals based on the voltage difference; the output end of one current adjustment module is connected to the output end of one of the squaring unit and the mirror squaring unit, and the output end of the other current adjustment module is connected to the output end of the other of the squaring unit and the mirror squaring unit.

16. The squaring circuit according to any one of claims 1-6, 8, 11-13, characterized in that The voltage acquisition module includes a first analog-to-digital converter and a switch unit; One end of the switch unit is connected to the first analog-to-digital converter, and the other end is selectively connected to the output end of the squaring unit or the output end of the mirror squaring unit; The first analog-to-digital converter is configured to perform analog-to-digital conversion on the voltage at the output end of the squaring unit or the mirror squaring unit, and output the converted digital signal to the control module.

17. The squaring circuit according to any one of claims 1-6, 8, 11-13, characterized in that, The voltage acquisition module includes a second analog-to-digital converter and a third analog-to-digital converter; The second analog-to-digital converter is connected to the output end of the squaring unit. After performing analog-to-digital conversion on the voltage at the output end of the squaring unit, it outputs to the control module; The third analog-to-digital converter is connected to the output end of the mirror squaring unit. After performing analog-to-digital conversion on the voltage at the output end of the mirror squaring unit, it outputs to the control module.

18. A self - regulating method for a squaring circuit, characterized in that, Applied to the squaring circuit as claimed in claim 1, the method includes: Obtain the voltage difference; Determine a target control signal according to the voltage difference and output it to the current adjustment module.

19. The method according to claim 18, wherein It further includes: When there is no input of the AC signal, output an initial control signal to the current adjustment module; Obtain the voltage difference; By traversing different initial control signals, determine the initial control signal corresponding to the minimum voltage difference as the target control signal; Output the target control signal to the current adjustment module.

20. The method according to claim 18, characterized in that It further includes: Obtain the voltage difference; Search in the storage module according to the voltage difference to determine the target control signal, and output the corresponding target control signal to the current adjustment module. The storage module stores the corresponding relationship between the voltage difference and the target control signal.

21. The method according to claim 20, characterized in that, It further includes: When there is no input of the AC signal, at each voltage difference: Output an initial control signal to the current adjustment module; By traversing different initial control signals, determine the initial control signal corresponding to the minimum voltage difference as the target control signal.

22. A control module, characterized in that, It includes a processor and a memory; The processor is configured to execute the instructions stored in the memory so that the control module executes the self-adjustment method as claimed in any one of claims 18 to 21.

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