Display panel

Abstract

Embodiments of the present application disclose a display panel. The display panel of the embodiments of the present application adds a first capacitor between a first initial signal line of a first reset circuit and a second initial signal line of a second reset circuit, so that the capacitance of the second initial signal line is increased, the anti-coupling capability is improved, and when a fourth node is reset, the influence of the second initial signal line on the data line coupling is reduced, thereby reducing the risk of appearing bright and dark lines.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel driving circuit and a display panel. BACKGROUND

[0002] In the existing Low Temperature Poly-Oxide (LTPO) thin film transistor driven product, the product adopting an 8T (8 thin film transistors) pixel driving circuit is more popular in the market. However, in the low gray scale of the 8T LTPO product, a bright and dark line appears in the middle of the screen, which affects the display effect. SUMMARY

[0003] Embodiments of the present application provide a display panel, which can reduce the risk of bright and dark lines appearing in the display panel.

[0004] Embodiments of the present application provide a pixel driving circuit, which comprises:

[0005] A first transistor, the first transistor being a driving transistor, a gate of the first transistor being connected to a first node, a first pole of the first transistor being connected to a second node, and a second pole of the first transistor being connected to a third node;

[0006] A data writing circuit, the data writing circuit being connected to the second node, and the data writing circuit being configured to write a data signal into the second node in response to a first gate driving signal;

[0007] A threshold compensation circuit, the threshold compensation circuit being connected to the first node and the third node, and the threshold compensation circuit being configured to connect the first node and the third node in response to a second gate driving signal;

[0008] A first reset circuit, the first reset circuit being connected to the first node and a first initial signal line, and the first reset circuit being configured to transmit a signal of the first initial signal line to the first node in response to a first reset signal;

[0009] A control circuit, the control circuit being connected to the second node, the third node and a fourth node, and the control circuit being configured to transmit a signal of the first power supply end to the second node in response to an enable signal, and the control circuit being configured to connect the third node and the fourth node in response to the enable signal;

[0010] A second reset circuit, the second reset circuit being connected to the fourth node and a second initial signal line, and the second reset circuit being configured to transmit a signal of the second initial signal line to the fourth node in response to a second reset signal;

[0011] A first capacitor, one end of the first capacitor being connected to the first initial signal line, and the other end of the first capacitor being connected to the second initial signal line.

[0012] a light emitting device, an anode of the light emitting device being connected to the fourth node.

[0013] Optionally, in some embodiments of the present application, the pixel driving circuit further comprises a second capacitor, a third capacitor and a third reset circuit, one end of the second capacitor being connected to the first node, the other end of the second capacitor being connected to a control end of the data writing circuit;

[0014] one end of the third capacitor being connected to the first node, the other end of the third capacitor being connected to the first power supply end;

[0015] the third reset circuit being connected to the second node and a second power supply end, the third reset circuit being configured to input a signal of the second power supply end to the second node in response to the second reset signal.

[0016] Optionally, in some embodiments of the present application, the data writing circuit comprises a second transistor, a gate of the second transistor being connected to the second capacitor and configured to access the first gate driving signal, a first pole of the second transistor being configured to access the data signal, a second pole of the second transistor being connected to the second node;

[0017] the threshold compensation circuit comprises a third transistor, a gate of the third transistor being configured to access the second gate driving signal, a first pole of the third transistor being connected to the first node, a second pole of the third transistor being connected to the third node;

[0018] the first reset circuit comprises a fourth transistor, a gate of the fourth transistor being configured to access the first reset signal, a first pole of the fourth transistor being connected to the first initial signal line, a second pole of the fourth transistor being connected to the first node;

[0019] the control circuit comprises a fifth transistor and a sixth transistor, a gate of the fifth transistor being configured to access the enable signal, a first pole of the fifth transistor being connected to the first power supply end, a second pole of the fifth transistor being connected to the second node, a gate of the sixth transistor being configured to access the enable signal, a first pole of the sixth transistor being connected to the third node, a second pole of the sixth transistor being connected to the fourth node;

[0020] the second reset circuit comprises a seventh transistor, a gate of the seventh transistor being configured to access the second reset signal, a first pole of the seventh transistor being connected to the second initial signal line, a second pole of the seventh transistor being connected to the fourth node;

[0021] The third reset circuit includes an eighth transistor, a gate of the eighth transistor is connected to the second reset signal, a first electrode of the eighth transistor is connected to the second power supply end, and a second electrode of the eighth transistor is connected to the second node.

[0022] Optionally, in some embodiments of the present application, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are P-type low-temperature polysilicon transistors, and the third transistor and the fourth transistor are N-type oxide transistors.

[0023] Optionally, in some embodiments of the present application, the first capacitor has a capacitance greater than or equal to 14.4 fF.

[0024] Correspondingly, the present application also provides a display panel including the pixel driving circuit according to any one of the above embodiments.

[0025] Optionally, in some embodiments of the present application, the display panel includes a substrate, a first insulating layer and a second insulating layer, the first initial signal line includes a first segment, and the first capacitor includes a first electrode plate and a second electrode plate, the first segment is arranged on the substrate, the first insulating layer covers the first segment, the first electrode plate is arranged on a side of the first insulating layer away from the substrate, the first segment is connected to the first electrode plate, and the second insulating layer covers the first electrode plate.

[0026] The second initial signal line includes a second segment, the second segment is connected to the second electrode plate and arranged on a side of the second insulating layer away from the substrate in the same layer as the second electrode plate, and the first electrode plate and the second electrode plate are arranged in an overlapping manner in a direction perpendicular to a panel surface of the display panel.

[0027] Optionally, in some embodiments of the present application, the display panel further includes a data line for connecting to the data signal, the data line is arranged on a side of the second insulating layer away from the substrate, the data line and the second segment are arranged in a partially overlapping manner in a direction perpendicular to a panel surface of the display panel, the data line and the second segment form a parasitic capacitor, and the first capacitor is greater than the parasitic capacitor.

[0028] Optionally, in some embodiments of the present application, the first capacitor further includes a compensation electrode plate formed by the first segment extending in the direction of the first electrode plate, the compensation electrode plate includes a first part and a second part connected in sequence, in a front projection pattern of the display panel, the first part is arranged in an overlapping manner with the first electrode plate and the second electrode plate respectively, the second part is located outside the first electrode plate, and the second part is arranged in a partially overlapping manner with the second electrode plate.

[0029] Optionally, in some embodiments of the present application, the resistivity of the compensation electrode plate is less than the resistivity of the first electrode plate.

[0030] Optionally, in some embodiments of the present application, the first initial signal line further comprises a transition segment, a connection segment and a first input segment, the transition segment is arranged on the second insulating layer in the same layer and spaced apart from the second segment, the connection segment, the first input segment, the first electrode plate are arranged on the first insulating layer in the same layer, the connection segment is connected to the first electrode plate and the first input segment, the first input segment is connected to the first reset circuit, the second insulating layer is provided with a first via hole and a second via hole, the first via hole further penetrates the first insulating layer and exposes the first segment, the second via hole exposes the connection segment, one end of the transition segment is connected to the first segment through the first via hole, the other end of the transition segment is connected to the connection segment through the second via hole.

[0031] Optionally, in some embodiments of the present application, the connection segment, the first input segment, the first electrode plate and the active layer of the fourth transistor of the first reset circuit are arranged in the same layer and the materials of the four are all metal oxide semiconductor.

[0032] The pixel driving circuit and the display panel provided by the embodiments of the present application add a first capacitor between the first initial signal line of the first reset circuit and the second initial signal line of the second reset circuit, so that the capacitance of the second initial signal line is increased, the anti-coupling capability is improved, and when the fourth node is reset, the influence of the data line coupling on the second initial signal line is reduced, thereby reducing the risk of bright and dark lines. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is an equivalent circuit diagram of the pixel driving circuit provided by the embodiments of the present application;

[0034] Figure 2 is a timing diagram of the pixel driving circuit provided by the embodiments of the present application;

[0035] Figure 3 is a structure schematic diagram of a local orthographic projection of the display panel provided by the embodiments of the present application;

[0036] Figure 4 is a cross-sectional structure schematic diagram of the display panel provided by the embodiments of the present application;

[0037] Figure 5 is Figure 3 is a structure schematic diagram of an orthographic projection of a film layer in which the first segment of the first initial signal line is located;

[0038] Figure 6 is Figure 3A schematic diagram of a normal projection structure of a film layer in which a first plate is located;

[0039] Figure 7 is Figure 3 A schematic diagram of a normal projection structure of a film layer in which a second segment of a second initial signal line is located. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower of the device in the actual use or working state, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the contour of the device; the words "first", "second", "third" and the like are only used as labels, and do not impose numerical requirements or establish sequences.

[0041] Those skilled in the art can understand that all the transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the present specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using transistors with opposite polarities or changing the current direction in the working of the circuit, the functions of "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in the present specification, "source electrode" and "drain electrode" can be interchanged.

[0042] The embodiments of the present application provide a pixel driving circuit and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0043] Please refer to Figure 1 The embodiments of the present application provide a pixel driving circuit, which comprises a first transistor T1, a data writing circuit D1, a threshold compensation circuit D2, a first reset circuit D3, a control circuit D4, a second reset circuit D5, a first capacitor C1 and a light emitting device EL.

[0044] The first transistor T1 is a driving transistor. The gate of the first transistor T1 is connected to a first node Q, the first electrode of the first transistor T1 is connected to a second node A, and the second electrode of the first transistor T1 is connected to a third node B.

[0045] The data write circuit D1 is connected to the second node A. The data write circuit D1 is configured to write a data signal Data into the second node A in response to a first gate drive signal Pscan.

[0046] The threshold compensation circuit D2 is connected to the first node Q and the third node B. The threshold compensation circuit D2 is configured to connect the first node Q and the third node B in response to a second gate drive signal Nscan1.

[0047] The first reset circuit D3 is connected to the first node Q and a first initial signal line. The first reset circuit D3 is configured to transmit a signal Vi1 of the first initial signal line to the first node Q in response to a first reset signal Nscan2.

[0048] The control circuit D4 is connected to a first power supply terminal, the second node A, the third node B and a fourth node C. The control circuit D4 is configured to transmit a signal VDD of the first power supply terminal to the second node A in response to an enable signal EM, and configured to connect the third node B and the fourth node C in response to the enable signal EM.

[0049] The second reset circuit D5 is connected to the fourth node C and a second initial signal line. The second reset circuit D5 is configured to transmit a signal Vi2 of the second initial signal line to the fourth node C in response to a second reset signal Pscan2.

[0050] One end of the first capacitor C1 is connected to the first initial signal line, and the other end of the first capacitor C1 is connected to the second initial signal line. An anode of the light emitting device EL is connected to the fourth node C. A cathode of the light emitting device EL is connected to a third power supply signal VSS.

[0051] In the pixel driving circuit of the prior art, there is a parasitic capacitance between the data line and the second initial signal line. When the data signal of the data line jumps, the second initial signal line is coupled, the fourth node reset changes, and the bright-dark line problem occurs. In the pixel driving circuit of the embodiment of the present application, the first capacitor C1 is additionally arranged between the first initial signal line of the first reset circuit D3 and the second initial signal line of the second reset circuit D5. The capacitance of the second initial signal line is increased, the anti-coupling capability is improved, and when the fourth node C is reset, the influence of the second initial signal line caused by the coupling of the data line is reduced, thereby reducing the risk of the bright-dark line.

[0052] Optionally, the light emitting device EL can be a light emitting diode. Writing the second initial signal Vi2 into the fourth node C can eliminate the carriers that do not recombine on the light emitting interface inside the light emitting diode, and alleviate the aging of the light emitting diode.

[0053] Optionally, the pixel driving circuit further comprises a second capacitor Cboost, a third capacitor Cst and a third reset circuit D6.

[0054] One end of the second capacitor Cboost is connected to the first node Q, and the other end of the second capacitor Cboost is connected to the control end of the data write circuit D1. One end of the third capacitor Cst is connected to the first node Q, and the other end of the third capacitor Cst is connected to the first power supply end.

[0055] The third reset circuit D6 is connected to the second node A and the second power supply end. The third reset circuit D6 is configured to input a signal Vi3 of the second power supply end to the second node A in response to a second reset signal Pscan2.

[0056] Optionally, in some embodiments of the present application, the data write circuit D1 comprises a second transistor T2, a gate of the second transistor T2 is connected to the second capacitor Cboost and is configured to access a first gate drive signal Pscan, a first electrode of the second transistor T2 is configured to access a data signal Data, and a second electrode of the second transistor T2 is connected to the second node A.

[0057] The threshold compensation circuit D2 comprises a third transistor T3, a gate of the third transistor T3 is configured to access a second gate drive signal Nscan1, a first electrode of the third transistor T3 is connected to the first node Q, and a second electrode of the third transistor T3 is connected to the third node B.

[0058] The first reset circuit D3 comprises a fourth transistor T4, a gate of the fourth transistor T4 is configured to access a first reset signal Nscan2, a first electrode of the fourth transistor T4 is connected to the first initial signal line, and a second electrode of the fourth transistor T4 is connected to the first node Q.

[0059] The control circuit D4 comprises a fifth transistor T5 and a sixth transistor T6, a gate of the fifth transistor T5 is configured to access an enable signal EM, a first electrode of the fifth transistor T5 is connected to the first power supply end, and a second electrode of the fifth transistor T5 is connected to the second node A. A gate of the sixth transistor T6 is configured to access the enable signal EM, a first electrode of the sixth transistor T6 is connected to the third node B, and a second electrode of the sixth transistor T6 is connected to the fourth node C.

[0060] The second reset circuit D5 comprises a seventh transistor T7, a gate of the seventh transistor T7 is configured to access a second reset signal Pscan2, a first electrode of the seventh transistor T7 is connected to the second initial signal line, and a second electrode of the seventh transistor T7 is connected to the fourth node C.

[0061] The third reset circuit D6 comprises an eighth transistor T8, a gate of the eighth transistor T8 is configured to access the second reset signal Pscan2, a first electrode of the eighth transistor T8 is connected to the second power supply end, and a second electrode of the eighth transistor T8 is connected to the second node A.

[0062] Optionally, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are P-type low-temperature polysilicon transistors, and the third transistor T3 and the fourth transistor T4 are N-type oxide transistors.

[0063] The N-type metal oxide transistor has a small leakage current, so that the light-emitting stage can be avoided, and the third node B leaks through the third transistor T3 and the fourth transistor T4. The low-temperature polysilicon transistor has a high carrier mobility, so that a high-resolution, high-speed, high-pixel-density, high-aperture-ratio display panel can be realized.

[0064] Optionally, in some embodiments, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can also be N-type transistors, and the third transistor T3 and the fourth transistor T4 can also be P-type transistors, which are not limited in the embodiments of the present application.

[0065] Optionally, in the pixel driving circuit in the embodiments of the present application, the capacitance of the first capacitor C1 is greater than or equal to 14.4 fF (femtofarad). It can be understood that the greater the capacitance of the first capacitor C1, the better the anti-coupling effect of the second initial signal line, and the lower the risk of appearing bright and dark lines.

[0066] According to the following table, when the first capacitor C1 reaches 14.4 fF, it can be fully optimized, and the influence of the data line coupling on the second initial signal line is improved from 9.3% to 3%, and the product does not appear bright and dark lines.

[0067]

[0068] Optionally, the first capacitor C1 can be 14.4 fF, 14.5 fF, 14.6 fF, 14.7 fF, 14.8 fF, 14.9 fF, 15 fF, 15.1 fF, 15.2 fF, 15.3 fF, 15.4 fF, 15.5 fF, 15.6 fF, 15.7 fF, 15.8 fF, 15.9 fF, 16 fF, 16.1 fF, 16.2 fF, 16.3 fF, 16.4 fF, 16.5 fF, 16.6 fF, 16.7 fF, 16.8 fF, 16.9 fF, 17 fF, 17.5 fF, 18 fF, 18.5 fF, 19 fF, 19.5 fF, 20 fF, 21 fF, 22 fF, 23 fF, 24 fF, 25 fF, 26 fF, 27 fF, 28 fF, 29 fF or 30 fF.

[0069] In some embodiments, the first capacitance C1 can also be less than 14.4fF, such as 14fF, 13fF, 12fF, 11fF, 10fF, 9fF, 8fF, 7fF, 6fF, 5fF, 4fF, 3fF, 2fF or 1fF.

[0070] It can be understood that as long as the first capacitance C1 is added, the total capacitance of the second initial signal line can be increased, and the anti-coupling effect can be improved. When the capacitance of the first capacitance C1 reaches 14.4fF, the effect of no bright and dark lines appears.

[0071] Optionally, the first capacitance C1 is greater than 0.64fF, so that the second initial signal line can better resist the coupling effect of the data line.

[0072] Please refer to Figure 2 The pixel driving circuit of the embodiment includes six stages: a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5 and a sixth stage t6.

[0073] In the first stage t1, the enable signal EM, the first gate drive signal Pscan and the second gate drive signal Nscan1 output high level signals, the first reset signal Nscan2 and the second reset signal Pscan2 output low level signals, the first transistor T1, the third transistor T3, the seventh transistor T7 and the eighth transistor T8 are turned on, and other transistors are turned off. The first power supply end charges the signal Vi3 of the second power supply end to the second node A, the third node B and the first node Q. The second initial signal line resets the signal Vi2 of the second initial signal line to the fourth node C.

[0074] In the second stage t2, the enable signal EM, the first reset signal Nscan2, the second reset signal Pscan2 and the first gate drive signal Pscan output high level signals, the second gate drive signal Nscan1 outputs a low level signal, the fourth transistor T4 is turned on, and other transistors are turned off. The first initial signal line resets the signal Vi1 of the first initial signal line to the first node Q.

[0075] In the third stage t3, the enable signal EM, the second gate drive signal Nscan1, the first reset signal Nscan2, the second reset signal Pscan2 and the first gate drive signal Pscan output high level signals, the first transistor T1, the third transistor T3 and the fourth transistor T4 are turned on, and other transistors are turned off. The first initial signal line writes the signal Vi1 of the first initial signal line to the first node Q, the second node A and the third node B for resetting.

[0076] In the fourth stage t4, the enable signal EM, the second gate driving signal Nscan1 and the second reset signal Pscan2 output high level signals, the first gate driving signal Pscan and the first reset signal Nscan2 output low level signals, the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, and other transistors are turned off, and the data line writes the data signal Data to the first node Q.

[0077] In the fifth stage t5, the enable signal EM and the first gate driving signal Pscan output high level signals, the first reset signal Nscan2, the second gate driving signal Nscan1 and the second reset signal Pscan2 output low level signals, the first transistor T1, the second transistor T2 and the seventh transistor T7 are turned on. The first power supply end charges the signal Vi3 of the second power supply end to the second node A and the third node B. The second initial signal line resets the signal Vi2 of the second initial signal line to the fourth node C.

[0078] In the sixth stage t6, the first gate driving signal Pscan and the second reset signal Pscan2 output high level signals, the enable signal EM, the second gate driving signal Nscan1 and the first reset signal Nscan2 output low level signals, the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned on, and other transistors are turned off, and the light emitting device EL emits light.

[0079] Correspondingly, the embodiment of the present application also provides a display panel 100, which comprises the pixel driving circuit of any one of the above embodiments. That is, the structure of the pixel driving circuit of the display panel 100 of the embodiment of the present application is similar or identical to the structure of the pixel driving circuit of the above embodiment.

[0080] In the display panel of the 8T product of the prior art, there is a parasitic capacitance between the data line and the second initial signal line, which couples the second initial signal line when the data signal of the data line jumps, causes the reset of the fourth node to change, and causes the problem of bright and dark lines. The display panel 100 of the embodiment of the present application adds the first capacitor C1 between the first initial signal line of the first reset circuit D3 and the second initial signal line of the second reset circuit D5 of the pixel driving circuit, so that the capacitance of the second initial signal line is increased, the anti-coupling capability is improved, and when the fourth node C is reset, the influence of the second initial signal line on the data line coupling is reduced, thereby reducing the risk of bright and dark lines.

[0081] Optionally, please refer to Figure 3 and Figure 4The display panel 100 comprises a substrate 11, a first insulating layer 12 and a second insulating layer 13. The first initial signal line R1 comprises a first segment r11. The first capacitor C1 comprises a first plate c11 and a second plate c12. The first segment r11 is disposed on the substrate 11. The first insulating layer 12 covers the first segment r11. The first plate c11 is disposed on a side of the first insulating layer 12 away from the substrate 11. The first segment r11 is connected to the first plate c11. The second insulating layer 13 covers the first plate c11.

[0082] The second initial signal line R2 comprises a second segment r21, which is connected to the second plate c12 and disposed on a side of the second insulating layer 13 away from the substrate 11 in the same layer as the second plate c12. The first plate c11 and the second plate c12 are disposed in an overlapping manner in a direction perpendicular to a plane of the display panel 100.

[0083] The display panel 100 further comprises a data line Dt for accessing a data signal Data. The data line Dt is disposed on a side of the second insulating layer 13 away from the substrate 11. The data line Dt and the second segment r21 are partially disposed in an overlapping manner in a direction perpendicular to a plane of the display panel 100. The data line Dt and the second segment r21 form a parasitic capacitor, and the first capacitor C1 is greater than the parasitic capacitor.

[0084] The first capacitor C1 being greater than the parasitic capacitor enables the second initial signal line R2 to better resist the coupling effect of the data line Dt.

[0085] Optionally, the data line Dt is connected to a first electrode of the second transistor T2.

[0086] Optionally, the first segment r11, the second segment r21 and the second plate c12 can be formed of a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, an alloy comprising any of the above metal elements or an alloy combining any of the above metal elements, etc. In addition, the first segment r11, the second segment r21 and the second plate c12 can have a single-layer structure or a laminated structure of two or more layers, such as titanium / aluminum / titanium.

[0087] Optionally, please refer to Figure 5 The first capacitor C1 further comprises a compensation plate c13 extending from the first segment r11 to the first plate c11. The compensation plate c13 comprises a first part c131 and a second part c132 connected to each other. In a front projection pattern of the display panel 100, the first part c131 is disposed in an overlapping manner with the first plate c11 and the second plate c12 respectively, the second part c132 is disposed outside the first plate c11, and the second part c132 is partially disposed in an overlapping manner with the second plate c12.

[0088] The compensation electrode plate c13 and the first electrode plate c11 are connected to form a lower electrode plate, and the second electrode plate c12 is an upper electrode plate.

[0089] It can be understood that the compensation electrode plate c13 can improve the capacitance of the first capacitor C1.

[0090] Secondly, the distance between the compensation electrode plate c13 and the second electrode plate c12 is greater than the distance between the first electrode plate c11 and the second electrode plate c12, so that the capacitance of the second part c132 of the compensation electrode plate c13 and the second electrode plate c12 is smaller than the capacitance of the first electrode plate c11 and the second electrode plate c12 in a unit area. That is, by setting the second part c132 of the compensation electrode plate c13, the capacitance of the first capacitor C1 can be better adjusted and the idle space can be fully utilized.

[0091] Optionally, the resistivity of the compensation electrode plate c13 is smaller than the resistivity of the first electrode plate c11. That is, the resistivity of the first electrode plate c11 is higher, the conductive performance is poorer, and the potential difference is larger, so that the electric field intensity formed by the first electrode plate c11 and the second electrode plate c12 is stronger, and the capacitance is larger.

[0092] In combination with the overlapping area of the first electrode plate c11 and the second electrode plate c12 being greater than the overlapping area of the second part c132 of the compensation electrode plate c13 and the second electrode plate c12, the first capacitor C1 with large capacitance can be formed in limited space.

[0093] Optionally, in combination with Figure 6 and Figure 7 The first initial signal line R1 further includes a transition segment r12, a connecting segment r13, and a first input segment r14. The transition segment r12 is arranged on the second insulating layer 13 in the same layer as the second segment r21 and is spaced apart. The connecting segment r13, the first input segment r14, and the first electrode plate c11 are arranged on the first insulating layer 12 in the same layer. The connecting segment r13 is connected to the first electrode plate c11 and the first input segment r14. The first input segment r14 is connected to the first reset circuit D3. The first via hole k1 and the second via hole k2 are arranged on the second insulating layer 13, the first via hole k1 further penetrates the first insulating layer 12 and exposes the first segment r11, and the second via hole k2 exposes the connecting segment r13. One end of the transition segment r12 is connected to the first segment r11 through the first via hole k1, and the other end of the transition segment r12 is connected to the connecting segment r13 through the second via hole k2.

[0094] The first segment r11 and the connecting segment r13 are connected through the transition segment r12 in different layers, which can save the horizontal wiring space.

[0095] Optionally, the active layer yy of the connecting segment r13, the first input segment r14, the first plate c11 and the fourth transistor T4 of the first reset circuit D3 are arranged in the same layer and the materials of the four are all metal oxide semiconductor.

[0096] The active layer of the connecting segment r13, the first input segment r14, the first plate c11 and the fourth transistor T4 of the first reset circuit D3 can be formed by the same mask process, so that the capacitance of the first capacitor C1 can be improved under the condition of saving the process.

[0097] Optionally, the fourth transistor T4 further includes a gate g, and the gate g is connected to the first reset signal line R3 through the third via hole k3. The first reset signal line R3 is arranged in the same layer as the second segment r21 of the second initial signal line R2. The gate g is arranged in a different layer from the first reset signal line R3. The first pole and the second pole of the fourth transistor T4 are integrally formed with the active layer yy.

[0098] The gate g and the first reset signal line R3 are provided with a third insulating layer 14, the gate g is arranged on the side of the second insulating layer 13 away from the substrate 11, and the third insulating layer 14 covers the gate g and the second insulating layer 13. The first reset signal line R3 is arranged on the third insulating layer 14.

[0099] Optionally, the second segment r21, the connecting segment r13, the second plate c12 and the first reset signal line R3 can be formed by the same mask process, and the materials of the four are the same.

[0100] Optionally, the second initial signal line R2 further includes a second input segment r22. The second input segment r22 is arranged on the substrate 11. The second segment r21 is connected to the second input segment r22 through the fourth via hole k4. The second input segment r22 is linked to the first pole of the seventh transistor T7.

[0101] The second input segment r22 is arranged in the same layer as the active layer of the seventh transistor T7. The material of the second input segment r22 is polysilicon.

[0102] The fourth insulating layer 15 is arranged between the second input segment r22 and the first segment r11. The second input segment r22 is arranged on the substrate 11. The fourth insulating layer 15 covers the second input segment r22 and the substrate 11. The first segment r11 and the compensation plate c13 are arranged on the side of the fourth insulating layer 15 away from the substrate 11.

[0103] Optionally, the second input segment r22 and the active layer of the seventh transistor T7 are formed by the same mask process, and the materials of the two are the same.

[0104] The pixel driving circuit and the display panel provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed, and the above description of the embodiments should not be understood as a limitation on the present application.

Claims

1. A display panel comprising a pixel driving circuit, characterized by, The display panel comprises a substrate, a first initial signal line, a second initial signal line, a first insulating layer and a second insulating layer, the first initial signal line is configured to input a first initial signal to a first reset circuit of the pixel driving circuit, the first initial signal line comprises a first segment, the first segment is arranged on the substrate, the first insulating layer covers the first segment, a first plate is arranged on a side of the first insulating layer away from the substrate, the first segment is connected to the first plate, and the second insulating layer covers the first plate. The second initial signal line is configured to input a second initial signal to a second reset circuit of the pixel driving circuit, the second initial signal line comprises a second segment, the second segment is arranged on a side of the second insulating layer away from the substrate, and a second plate is connected to the second segment, wherein an extension direction of the second plate intersects an extension direction of the second segment. In a direction perpendicular to a panel surface of the display panel, the first plate and the second plate are arranged in different layers and overlap to form a first capacitor, and the second plate has a single-layer structure or a laminated structure with two or more layers.

2. The display panel of claim 1, wherein, The display panel further comprises a data line for accessing a data signal, the data line is arranged on a side of the second insulating layer away from the substrate, and in a direction perpendicular to a panel surface of the display panel, the data line and the second segment are partially overlapped and arranged, the data line and the second segment form a parasitic capacitor, and the first capacitor is greater than the parasitic capacitor.

3. The display panel of claim 2, wherein, The first capacitor further comprises a compensation plate formed by the first segment extending in the direction of the first plate, the compensation plate comprises a first part and a second part connected to each other, wherein in a front projection pattern of the display panel, the first part is arranged to overlap the first plate and the second plate respectively, the second part is located outside the first plate, and the second part is partially overlapped and arranged with the second plate.

4. The display panel of claim 3, wherein, The resistivity of the compensation plate is less than the resistivity of the first plate.

5. The display panel of claim 3 or 4, wherein, The first initial signal line further comprises a transfer segment, a connection segment and a first input segment, the transfer segment is arranged on the second insulating layer in the same layer as the second segment and is spaced apart, the connection segment, the first input segment and the first plate are arranged on the first insulating layer in the same layer, the connection segment is connected to the first plate and the first input segment, the first input segment is connected to the first reset circuit, the second insulating layer is provided with a first via and a second via, the first via further penetrates the first insulating layer and exposes the first segment, the second via exposes the connection segment, one end of the transfer segment is connected to the first segment through the first via, and the other end of the transfer segment is connected to the connection segment through the second via.

6. The display panel of claim 5, wherein, The connection segment, the first input segment, the first plate and an active layer of a fourth transistor of the first reset circuit are arranged in the same layer and the materials of the four are all metal oxide semiconductor.

7. The display panel according to any one of claims 1-4, wherein, The pixel driving circuit comprises: a first transistor, the first transistor being a driving transistor, a gate of the first transistor being connected to a first node, a first electrode of the first transistor being connected to a second node, and a second electrode of the first transistor being connected to a third node; a data writing circuit, the data writing circuit being connected to the second node, the data writing circuit being configured to write a data signal into the second node in response to a first gate driving signal; a threshold compensation circuit, the threshold compensation circuit being connected to the first node and the third node, the threshold compensation circuit being configured to connect the first node and the third node in response to a second gate driving signal; the first reset circuit, the first reset circuit being connected to the first node and a first initial signal line, the first reset circuit being configured to transmit a signal of the first initial signal line to the first node in response to a first reset signal; a control circuit, the control circuit being connected to a first power supply terminal, the second node, the third node and a fourth node, the control circuit being configured to transmit a signal of the first power supply terminal to the second node in response to an enable signal, and configured to connect the third node and the fourth node in response to the enable signal; the second reset circuit, the second reset circuit being connected to the fourth node and a second initial signal line, the second reset circuit being configured to transmit a signal of the second initial signal line to the fourth node in response to a second reset signal; the first capacitor, one end of the first capacitor being connected to the first initial signal line, and the other end of the first capacitor being connected to the second initial signal line; and a light emitting device, an anode of the light emitting device being connected to the fourth node.

8. The display panel of claim 7, wherein, the pixel driving circuit further comprises a second capacitor, a third capacitor and a third reset circuit, one end of the second capacitor being connected to the first node, and the other end of the second capacitor being connected to a control terminal of the data writing circuit; one end of the third capacitor being connected to the first node, and the other end of the third capacitor being connected to the first power supply terminal; the third reset circuit being connected to the second node and a second power supply terminal, the third reset circuit being configured to input a signal of the second power supply terminal to the second node in response to the second reset signal.

9. The display panel of claim 8, wherein, the data writing circuit comprises a second transistor, a gate of the second transistor being connected to the second capacitor and configured to access the first gate driving signal, a first electrode of the second transistor being configured to access the data signal, and a second electrode of the second transistor being connected to the second node; the threshold compensation circuit comprises a third transistor, a gate of the third transistor being configured to access the second gate driving signal, a first electrode of the third transistor being connected to the first node, and a second electrode of the third transistor being connected to the third node; the first reset circuit comprises a fourth transistor, a gate of the fourth transistor being configured to access the first reset signal, a first electrode of the fourth transistor being connected to the first initial signal line, and a second electrode of the fourth transistor being connected to the first node; The control circuit comprises a fifth transistor and a sixth transistor, a gate of the fifth transistor is connected to the enable signal, a first electrode of the fifth transistor is connected to the first power supply end, and a second electrode of the fifth transistor is connected to the second node; a gate of the sixth transistor is connected to the enable signal, a first electrode of the sixth transistor is connected to the third node, and a second electrode of the sixth transistor is connected to the fourth node. The second reset circuit comprises a seventh transistor, a gate of the seventh transistor is connected to the second reset signal, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode of the seventh transistor is connected to the fourth node. The third reset circuit comprises an eighth transistor, a gate of the eighth transistor is connected to the second reset signal, a first electrode of the eighth transistor is connected to the second power supply end, and a second electrode of the eighth transistor is connected to the second node.

10. The display panel of claim 9, wherein, The first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are P-type low-temperature polysilicon transistors, and the third transistor and the fourth transistor are N-type oxide transistors.

11. The display panel of claim 7, wherein, The capacitance of the first capacitor is greater than or equal to 14.4 fF.

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