Display driving circuit, display module and electronic device

Abstract

The application provides a display driving circuit, a display module and an electronic device. The display driving circuit comprises a signal control module, an output switch circuit and a source output circuit. When the current frame display data and the last frame display data corresponding to the same display position in the display screen are different, the signal control module compares the current frame display data and the last frame display data, outputs a first switch signal and provides the first switch signal to the switch control end of the output switch circuit. The output switch circuit controls the first switch branch to be turned off and the second switch branch to be turned on according to the first switch signal, so that the output switch circuit outputs a negative voltage signal, and the negative voltage signal is processed by the source output circuit and then output. It can be seen that for the display pixels that need to be updated, the output switch circuit of the DDIC outputs a preset negative voltage, and the source output circuit amplifies the driving capability of the preset negative voltage signal and then outputs, that is, source output. The voltage range of the DDIC output source output includes the preset negative voltage signal, so that the DDIC is suitable for the OLED local refresh scene, and the application range of the DDIC is expanded.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to display driver circuits, display modules and electronic devices. Background Technology

[0002] The display driver integration chip (DDIC) is one of the main control components of a display panel. It sends drive signals and data to the display panel in the form of electrical signals, enabling the display panel to display the corresponding content.

[0003] Currently, the source output voltage range of the driver IC for Organic Light-Emitting Diode (OLED) to control the grayscale display of pixels is a positive voltage. However, in some special applications (such as partial refresh), OLED requires the DDIC to output a set negative voltage at specific times. The fact that the source output voltage range of the OLED driver IC does not include negative voltage limits the use of OLED in special scenarios. Summary of the Invention

[0004] In view of this, this application provides a display driver circuit, a display module, and electronic equipment to solve the problem that DDIC cannot output a negative voltage. The disclosed technical solution is as follows:

[0005] In a first aspect, this application provides a display driving circuit for controlling the display pixels of an OLED. The display driving circuit includes a signal control module, an output switching circuit, and a source output circuit. The output switching circuit includes an input terminal, a switch control terminal, an output terminal, a first switch branch, and a second switch branch. The first switch branch is connected between the input terminal and the output terminal, and the second switch branch is connected between the output terminal and a negative reference voltage source. The switch control terminal is connected to the control terminals of the first switch branch and the second switch branch, respectively. When the signal control module compares the current frame display data and the previous frame display data corresponding to the same display position on the display screen and finds them different, it outputs a first switch signal and provides it to the switch control terminal of the output switching circuit. According to the first switch signal, the output switching circuit controls the first switch branch to turn off and the second switch branch to turn on, so that the output switching circuit outputs a negative voltage signal. The negative voltage signal is processed by the source output circuit and then output. Therefore, for display pixels whose display content needs to be updated, the switch control terminal of the DDIC's output switching circuit receives the first switch signal. At this time, the output switching circuit outputs a preset negative voltage and transmits it to the source output circuit. The source output circuit, after adjusting the driving capability of the received preset negative voltage signal, outputs a write data trigger signal (i.e., the preset negative voltage after increasing the driving capability), thereby triggering the OLED to receive the data signal. In other words, the voltage range of the DDIC's source output includes the preset negative voltage signal, thus making the DDIC suitable for OLED partial refresh scenarios and expanding its applicability.

[0006] In one possible implementation, when the signal control module compares the current frame display data corresponding to the same display position on the screen with the previous frame display data, it outputs a second switch signal and provides it to the switch control terminal of the output switch circuit. Based on the second switch signal, the output switch circuit controls the first switch branch to be turned on and the second switch branch to be turned off, causing the output terminal of the output switch circuit to output the signal input to the input terminal. The level of the second switch signal is opposite to that of the first switch signal. Therefore, for display pixels whose display content does not need to be updated, when the switch control terminal of the output switch circuit receives the second switch signal, the output terminal of the output switch circuit follows the input terminal; that is, the output signal of the output switch circuit is the signal input to the input terminal. DDIC will not output a write data trigger signal, and therefore will not trigger the OLED to receive data signals.

[0007] In one possible implementation, the signal control module includes a digital signal control circuit and a signal-to-analog converter circuit; the digital signal control circuit compares whether the current frame display data and the previous frame display data corresponding to the same display position on the display screen are the same, generates a switch signal corresponding to the comparison result and transmits it to the signal-to-analog converter circuit; the signal-to-analog converter circuit converts the switch signal into an analog signal and transmits it to the output switch circuit.

[0008] In one possible implementation, an output switch circuit is configured for each column of display pixels on the OLED screen.

[0009] In one possible implementation, the output switching circuit includes a first switching transistor, a second switching transistor, and a third switching transistor. The first terminal of the first switching transistor is connected to the input terminal of the output switching circuit, and its second terminal is connected to the output terminal of the output switching circuit. A control terminal is connected to the second terminal of the second switching transistor, and the control terminal also receives a first voltage, which is a high-level voltage. The first terminal of the second switching transistor receives a second voltage, and its control terminal is connected to the switch control terminal of the output switching circuit. The second voltage is a low-level voltage or a negative voltage. The first terminal of the third switching transistor is connected to the output terminal of the output switching circuit, its second terminal receives a preset negative voltage, and its control terminal is connected to the switch control terminal. Therefore, the output switching circuit in this implementation exhibits high stability, thereby improving the stability of the DDIC.

[0010] In one possible implementation, the first, second, and third switching transistors are all NMOS transistors, with the first terminal being the drain, the second terminal being the source, and the control terminal being the gate.

[0011] In one possible implementation, the output switching circuit includes a fourth switch, a fifth switch, and a sixth switch; the first terminal of the fourth switch is connected to the input terminal of the output switching circuit, the second terminal is connected to the output terminal of the output switching circuit, and the control terminal is connected to the switch control terminal of the output switching circuit; the first terminal of the fifth switch receives a second voltage, and the second terminal receives a first voltage, wherein the first voltage is a high-level voltage, and the second voltage is a low-level voltage or a negative voltage; the first terminal of the sixth switch is connected to the output terminal of the output switching circuit, the second terminal receives a preset negative voltage, and the control terminal receives the first voltage.

[0012] In one possible implementation, the fourth, fifth, and sixth switches are all NMOS transistors, with the first terminal being the drain, the second terminal being the source, and the control terminal being the gate.

[0013] In one possible implementation, the first switching signal is a high-level signal.

[0014] In one possible implementation, the output switching circuit includes a seventh switch and an eighth switch. The first terminal of the seventh switch is the input terminal of the output switching circuit, the second terminal is the output terminal of the output switching circuit, and the control terminal is the switch control terminal of the output switching circuit. The first terminal of the eighth switch is connected to the output terminal of the output switching circuit, the second terminal receives a preset negative voltage, and the control terminal is connected to the switch control terminal. It is evident that the output switching circuit in this implementation has a simple structure, is easy to control, and has low hardware cost.

[0015] In one possible implementation, the seventh switch is an NMOS transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate; the eighth switch is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate.

[0016] In one possible implementation, the first switching signal is a low-level signal.

[0017] Secondly, this application also provides a display module, including: a display screen and a display driving circuit according to any one of the first aspects.

[0018] Thirdly, this application also provides an electronic device, which includes: one or more processors, a memory, a touch screen, and a display driver circuit according to any one of the first aspects; the memory is used to store program code; the processor is used to run the program code, causing the display driver circuit to drive the touch screen to update the displayed content.

[0019] It should be understood that the descriptions of technical features, technical solutions, beneficial effects, or similar language in this application do not imply that all features and advantages can be achieved in any single embodiment. Rather, it is understood that the description of a feature or beneficial effect means that a specific technical feature, technical solution, or beneficial effect is included in at least one embodiment. Therefore, the descriptions of technical features, technical solutions, or beneficial effects in this specification do not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions, and beneficial effects described in this embodiment can be combined in any suitable manner. Those skilled in the art will understand that embodiments can be implemented without one or more specific technical features, technical solutions, or beneficial effects of a particular embodiment. In other embodiments, additional technical features and beneficial effects may be identified in specific embodiments that do not embody all embodiments. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of a pixel array for a display screen;

[0023] Figure 3This is a schematic diagram of the structure of a display driver chip provided in an embodiment of this application;

[0024] Figure 4 This is a circuit diagram of an output switch circuit provided in an embodiment of this application;

[0025] Figure 5 This is provided by the embodiments of this application. Figure 3 The waveform diagram of each signal in the output switching circuit shown;

[0026] Figure 6 This is a circuit diagram of another output switch circuit provided in an embodiment of this application;

[0027] Figure 7 This is a circuit diagram of another output switch circuit provided in the embodiments of this application;

[0028] Figure 8 This is provided by the embodiments of this application. Figure 6 The diagram shows the voltage signal waveform corresponding to the output switching circuit. Detailed Implementation

[0029] The terms "first," "second," and "third," etc., used in this application specification, claims, and drawings are used to distinguish different objects, not to limit a specific order.

[0030] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0031] Please see Figure 1 This illustration shows a structural schematic diagram of an electronic device provided in an embodiment of this application. The electronic device can be any form of device including a display screen, such as a mobile phone, tablet computer, desktop computer, laptop computer, notebook computer, ultra-mobile personal computer (UMPC), handheld computer, netbook, personal digital assistant (PDA), wearable electronic device, smartwatch, etc.

[0032] This electronic device includes a processor, memory, a display driver chip (DDIC), and a display screen. The processor is also known as a system-on-a-chip (SoC).

[0033] It is understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device. In other embodiments, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0034] like Figure 1 As shown, the processor is connected to the DDIC and memory. The processor may include one or more processing units. Different processing units may be independent devices or integrated into one or more processors.

[0035] The processor may also include memory for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. This memory can store instructions or data that the processor has just used or that are used repeatedly. If the processor needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces processor waiting time, and thus improves system efficiency.

[0036] The processor may also include memory for storing instructions and data. In some embodiments, the memory in the processor is a cache memory.

[0037] like Figure 1 As shown, the TE pin of the DDIC is connected to the processor. Both the processor and the DDIC are equipped with a Display Serial Interface (DSI). The DSI of the processor and the DSI of the DDIC are connected through the Mobile Industry Processor Interface (MIPI) bus.

[0038] Memory can be used to store executable program code for a computer, which includes instructions. The processor executes various functional applications and data processing of the electronic device by running the instructions stored in memory.

[0039] The memory may include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function (such as sound playback, image playback, etc.), etc. The data storage area may store data created during the use of the electronic device (such as audio data, etc.). The processor executes various functional applications and data processing of the mobile terminal by running instructions stored in the memory and / or instructions stored in the memory located within the processor.

[0040] The display driver chip (DDIC) is connected to the display screen. For example, the DDIC and display screen can be integrated into a single device, such as being fixed to the back of the display screen. When the display screen is turned on, the DDIC notifies the processor of the refresh rate via the TE pin. The processor generates image data in real time based on the received refresh rate (e.g., 60Hz) and sends it to the DDIC via the MIPI bus. The DDIC then controls the display screen to show the corresponding image based on the image data. For example, the processor generates image data representing the system desktop and sends it to the DDIC, which then controls the display screen to show the system desktop based on the image data.

[0041] Please see Figure 2 The diagram shows a schematic of the pixel array of the display screen.

[0042] like Figure 2 As shown, an OLED screen includes a pixel array, which is the effective display area of ​​the display screen used to display content. A typical distribution of the pixel array is a 1920*1080 pixel array. Figure 2 The illustration is based on a 10×7 pixel array only.

[0043] OLED screens also include pixel driving circuits and array driving circuits. The array driving circuits include row scan driving circuits and column driving circuits. The row scan driving circuit provides row scan signals to the pixel driving circuits, while the column driving circuit provides data signals. The row scan signal converts the serial bus clock signal output from the DDIC into sequential write pulses with driving capability. Driven by the row scan signal, the data signal is linearly written to the pixel circuits, thereby refreshing the content of the entire screen.

[0044] Each pixel in the pixel array comprises three types of organic light-emitting diodes: red, green, and blue, namely RedOLED, GreenOLED, and BlueOLED. Each OLED is coupled to a pixel driving circuit. Each pixel driving circuit receives a line scan signal and a data signal as inputs. The pixel driving circuit drives the OLED to emit light and adjust its brightness based on the line scan signal and the data signal.

[0045] The DDIC drives the OLED screen to display corresponding content based on the display data and update instructions output by the processor (also known as the SOC).

[0046] Please see Figure 3 The diagram shows a schematic of the structure of a display driver chip provided in an embodiment of this application.

[0047] like Figure 3As shown, the display driver chip includes a data / instruction interface, a data control module, an instruction decoding module, an update address management module, a data storage module, a digital signal control circuit, a data latch circuit, a data digital-to-analog converter circuit, a signal digital-to-analog converter circuit, an output switch circuit, and a source output circuit.

[0048] Understandable Figure 3 The structure illustrated in this embodiment does not constitute a specific limitation on the DDIC. In other embodiments, the DDIC may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0049] like Figure 3 As shown, the input terminal of the data / instruction interface is connected to the processor via the MIPI bus, the data output terminal of the data / instruction interface is connected to the data control module, and the signal output terminal of the data / instruction interface is connected to the input terminal of the instruction decoding module. The data / instruction interface receives display data and / or refresh instructions sent by the processor. Further, the data / instruction interface transmits the received display data to the data control module and simultaneously transmits the received update instructions to the instruction decoding module.

[0050] The output of the data control module is connected to the data input of the data storage module. The data control module processes the received display data and then transmits it to the data storage module for storage. For example, the data storage module (also known as display RAM) can be random access memory (RAM), and the received display data is stored in the corresponding storage space within the RAM.

[0051] The first output of the instruction decoding module is connected to the input of the update address management module, and the second output is connected to the digital signal control circuit. The instruction decoding module decodes the received update instruction and transmits it to the digital signal control circuit. Simultaneously, it transmits the content update address obtained from parsing the update instruction to the update address management module for management. The content update address is the coordinate of the position on the display screen where the displayed content needs to be updated.

[0052] The output of the data control module is connected to the first input of the data storage module, the output of the update address management module is connected to the second input of the data storage module, and the output of the data storage module is connected to the first input of the digital signal control circuit. The data storage module is used to store display data and content update addresses.

[0053] The second input terminal of the digital signal control circuit is connected to the instruction decoding module, the first output terminal is connected to the input terminal of the data latch circuit, and the second output terminal is connected to the input terminal of the signal digital-to-analog converter circuit. The digital signal control circuit compares the current frame display data at the same position on the display screen with the previous frame display data. If they are the same, it indicates that the display content at that position does not need to be updated, and a second switch signal is output and transmitted to the signal digital-to-analog converter circuit. If they are different, it indicates that the display content at that position needs to be updated, and the current frame display data at that position is output to the data latch circuit, while simultaneously outputting a first switch signal and transmitting it to the signal digital-to-analog converter circuit.

[0054] In one possible implementation, a digital signal control circuit is configured for each column of pixels in the pixel array. The digital signal control circuit for each column is used to compare whether the display data of the two frames corresponding to that column and the current scan row are the same. For example, Figure 2 The pixel array shown includes 7 columns, so the DDIC is equipped with 7 digital signal control circuits. That is, each column of display pixels corresponds to one digital signal control circuit, and each digital signal control circuit compares one by one whether the display content of each row of display pixels in that column has changed.

[0055] For example, such as Figure 2 Taking the first column of display pixels as an example, the digital signal control circuit corresponding to this column compares the current frame data and the previous frame data of the first row of the first column at the first moment. If they are different, the current frame data of the first row of the first column is transmitted to the data latch circuit corresponding to that column, and a first switch signal is output. The same digital signal control circuit compares the current frame data and the previous frame data of the second row of the first column at the second moment. If they are different, the current frame data of the second row of the first column is transmitted to the data latch circuit corresponding to that column, and a first switch signal is output. Similarly, at the Nth moment, the digital control circuit compares the current frame data and the previous frame data of the Nth row of the first column. If they are different, the current frame data of that display pixel is latched and a first switch signal is output; if they are the same, a second switch signal is output.

[0056] In one possible implementation, the data storage module also stores the display data of the previous frame. Therefore, the digital signal control circuit can read the display data of the previous frame corresponding to the current pixel position from the data storage module and further compare the display data of the previous frame with the data of the current frame.

[0057] In one scenario, the update instruction carries a flag indicating a partial update. In this scenario, after each digital signal control circuit receives the update instruction carrying the partial update flag from the instruction decoding module, it needs to compare the current frame data and the previous frame data of each display pixel corresponding to each row of the current column until all display pixels in the entire column have been compared to obtain the display position that needs to be updated in that column.

[0058] In another scenario, the update instruction carries a partial update flag and the update position. In this scenario, after receiving the update instruction transmitted by the instruction decoding module, the digital signal control circuit obtains the update position. Further, the digital signal control circuit corresponding to this update position compares the current frame data with the previous frame data. If the two frames of display data corresponding to this position are indeed different, the current frame display data corresponding to this position is transmitted to the data latch circuit for latching, and simultaneously a first switching signal is transmitted to the output switching circuit.

[0059] In one possible implementation, the digital signal control circuit can read the previous frame display data corresponding to the updated position from the display RAM, and further compare whether the previous frame display data corresponding to the updated position is the same as the current frame display data.

[0060] In another scenario, the update instruction does not carry a local update flag. The processing procedure of the digital signal control circuit in this scenario is the same as that in the scenario where the update instruction carries an update flag but does not include the update position, and will not be described again here.

[0061] The output of the data latch circuit is connected to the input of the digital-to-analog converter circuit. The data latch circuit receives the current frame display data (digital signal) transmitted by the digital signal control circuit and then transmits it to the digital-to-analog converter circuit. In this embodiment, the data latch circuit includes multiple data latches, each corresponding to a column of display pixels on the screen. Each data latch is used to latch the display data corresponding to that position at the current moment. When the display data for that position at the next moment is received, the data in the data latch is updated to the newly received display data.

[0062] The output terminal of the digital-to-analog converter circuit is connected to the input terminal of the output switch circuit. The digital-to-analog converter circuit converts the current frame display data from digital signals to analog signals and transmits them to the input terminal of the output switch circuit.

[0063] The output of the digital-to-analog converter circuit is connected to the switch control terminal of the output switch circuit. The digital-to-analog converter circuit is used to convert the digital switch signals transmitted by the digital signal control circuit into analog switch signals and transmit them to the switch control terminal of the output switch circuit.

[0064] The output switching circuit controls the output terminal to output a corresponding signal based on the switch signal (also known as the switch signal) input to the switch control terminal. If the switch signal is the first switch signal, a preset negative voltage is output. If the switch signal is the second switch signal, the output signal is the same as the input signal, meaning the output of the output switching circuit follows the input.

[0065] In one possible implementation, an output switch circuit is provided for each column of pixels in the pixel array, meaning one output switch circuit corresponds to one column of display pixels. The pixel array includes N columns of pixels, and the corresponding DDIC is configured with N output switch circuits. Each output switch circuit is responsible for controlling the output of the data signal or a preset negative voltage signal (i.e., negative reference voltage Vref) for that column of pixels. For example, when there are display pixels in that column that require partial refresh, the output switch circuit first outputs the preset negative voltage signal and then outputs the data signal corresponding to that display pixel.

[0066] The input terminal of the source output circuit is connected to the output terminal of the output switch circuit. The output terminal of the source output circuit is the source output of the DDIC. The source output is used to control the grayscale of the display pixels, that is, the voltage signal used to control the grayscale of the display.

[0067] Grayscale refers to the number of gray levels represented by each pixel in an image. Specifically, each pixel on a display screen is composed of OLEDs using the three primary colors: red, green, and blue. The light source behind each primary color can display different brightness levels. Grayscale represents the different levels of brightness from the darkest to the brightest. The changes in each of the three primary colors as it gradually darkens from pure color to black are defined as the grayscale levels of the color.

[0068] In one embodiment, the source output circuit can be a voltage follower, that is, the output voltage of the source output circuit is the same as the input voltage, but the output current is greater than the input current. In other words, the source output circuit is used to improve the driving capability of the output signal.

[0069] When the output switch circuit outputs a preset negative voltage, the source output circuit amplifies the current of the preset negative voltage signal, thereby improving the driving capability of the signal. When the output switch circuit outputs a display data analog signal, the output terminal of the source output circuit outputs a display data analog signal with amplified driving capability.

[0070] The display driver chip provided in this application, in scenarios where partial content of the display screen needs to be updated (i.e., partial update), for display pixels whose content needs updating, the switch control terminal of the DDIC's output switch circuit receives a first switch signal. At this time, the output switch circuit outputs a preset negative voltage, which is transmitted to the source output circuit. The source output circuit, after adjusting the driving capability of the received preset negative voltage signal, outputs a write data trigger signal (i.e., the preset negative voltage after increasing the driving capability), thereby triggering the OLED to receive data signals. For display pixels whose content does not need to be updated, the switch control terminal of the output switch circuit receives a second switch signal. At this time, the output terminal of the output switch circuit follows the input terminal; that is, the output signal of the output switch circuit is the signal input to the input terminal. The DDIC will not output a write data trigger signal, therefore, it will not trigger the OLED to receive data signals. It can be seen that the voltage range of the source output of the DDIC provided in this application includes the preset negative voltage signal, thus making the DDIC suitable for OLED partial refresh scenarios and expanding the applicability of the DDIC.

[0071] Please see Figures 4-5 , Figure 4 A circuit diagram of an output switch circuit provided in an embodiment of this application is shown; Figure 5 It shows Figure 4 The waveform diagram of each signal in the output switching circuit is shown.

[0072] like Figure 4 As shown, the output switching circuit includes a first switch transistor T1, a second switch transistor T2, and a third switch transistor T3. In this embodiment, T1 to T3 are all NMOS transistors. In other embodiments, T1 to T3 can be other types of switch transistors; this application does not limit the type of switch transistors. Furthermore, each switch transistor can be replaced by a structure of at least two switches of the same type connected in series or in parallel, which will not be elaborated further in this application.

[0073] The drain of T1 is the input terminal of the output switch circuit, and the source of T1 is the output terminal of the output switch circuit. The gate of T1 is connected to the source of T2, and the drain of T2 is connected to VSS, which is a low-level signal or a negative voltage signal. The gate of T2 is connected to the gate of T3 and serves as the switch control terminal of the output switch circuit.

[0074] The gate of T1 is connected to the voltage source VDD through resistor R1. In this embodiment, VDD is a high-level voltage. The function of resistor R1 is to limit current. In this embodiment, the resistance value of resistor R1 can be determined according to the actual circuit parameters.

[0075] The source of T3 is connected to the output terminal of the output switching circuit, and the drain of T3 is connected to the reference voltage Vref, which is negative.

[0076] The following is combined Figure 4 and Figure 5 Introducing the working process of the output switching circuit:

[0077] During the t0-t1 phase: The switch signal is low, meaning the gate inputs of T2 and T3 are low, T2 and T3 are disconnected, and the gate input of T1 is high (VDD), turning T1 on. Since T1 is connected between the input and output terminals, when T1 is on, the signal input at the input terminal is directly transmitted to the output terminal; that is, the output terminal directly outputs the signal input at the input terminal. In other words, when the switch signal is low, the output terminal outputs the signal from the input terminal. Figure 5 As shown, during the t0-t1 stage, the output signal waveform is consistent with the input signal waveform, that is, the output terminal follows the input terminal during this stage.

[0078] During the t1-t2 phase: The switch signal is high, meaning the gate inputs of T2 and T3 are high, and T2 and T3 are turned on. T2's conduction transmits VSS to the gate of T1. VSS is a low-level voltage or a negative voltage, therefore T1 is turned off. T3's conduction transmits the negative voltage Vref to the output terminal; that is, when the switch is high, the output terminal outputs Vref, i.e., a negative voltage. Figure 5 As shown, during the t1-t2 stage, the output signal waveform is a negative voltage.

[0079] During the t2-t4 phase: the switch is low, and the input is high during the t2-t3 phase and low during the t3-t4 phase. As previously mentioned, when the switch is low, the output follows the input. Figure 5 As shown, the voltage waveform of the output during the t2-t4 stage is consistent with the voltage waveform of the input.

[0080] For example, suppose the time period t1-t4 is Figure 2 In the pixel array shown, the write data cycle corresponding to the display pixel in the first row of the first column outputs a preset negative voltage signal (Vref) during the t1-t2 time period of the write data cycle, and outputs the data signal corresponding to the display pixel during the t2-t4 time period. Simultaneously, t4 is the start time of the next write data cycle, which is used to output the data signal corresponding to the display pixel in the second row of the first column. Similarly, the preset negative voltage signal (Vref) is output during the t4-t5 time period of this cycle, and the data signal corresponding to the display pixel is output from t5 to the end of the cycle.

[0081] Furthermore, for ease of illustration, this application uses a pulse signal waveform to represent the input signal waveform. In practical applications, the voltage range of the input signal is [Vgmp, Vgsp]. Different voltage values ​​correspond to different brightness values ​​of the displayed pixels; the higher the voltage value, the higher the pixel brightness. The values ​​of Vgmp and Vgsp can be determined based on the actual pixels of the display panel, and this application does not impose any limitations on them.

[0082] The output switching circuit provided in this application, when the switch control terminal (switch) input is high, closes the transmission branch between the input and output terminals, while simultaneously opening the transmission branch between the negative voltage Vref and the output terminal, causing the output switching circuit to output a negative voltage Vref. Conversely, when the switch control terminal (switch) input is low, it opens the transmission branch between the input and output terminals, while simultaneously closing the transmission branch between the negative voltage Vref and the output terminal, causing the output terminal of the output switching circuit to follow the input terminal, i.e., output the signal input at the input terminal. It can be seen that this output switching circuit is placed before the source output circuit of the DDIC. The negative voltage output by the output switching circuit is amplified by the source output circuit before being output, ultimately ensuring that the source output voltage range of the DDIC includes negative voltages. This makes the DDIC suitable for OLED partial refresh scenarios, thus expanding the applicable scenarios of the DDIC.

[0083] Please see Figure 6 The diagram shows a circuit diagram of another output switch circuit provided in an embodiment of this application.

[0084] like Figure 6 As shown, the output switching circuit includes a fourth switch T4, a fifth switch T5, and a sixth switch T6. In this embodiment, T4-T6 are all NMOS transistors. In other embodiments, T4-T6 can be other types of switch transistors; this application does not limit the type of switch transistors. Furthermore, each switch transistor can be replaced by a structure of at least two switches of the same type connected in series or in parallel, which will not be elaborated further in this application.

[0085] The drain of T4 is the input terminal of the output switch circuit, where the display data is input. The source of T4 is the output terminal of the output switch circuit, and the gate of T1 is the switch control terminal of the output switch circuit, where the switch signal is input.

[0086] The switch control terminal is also connected to the gate of T5, the drain of T5 is connected to the voltage source VDD via resistor R2, and the source of T5 is connected to the voltage source VSS.

[0087] In one embodiment of this application, VDD is a high-level voltage source, and VSS is a low-level or negative voltage source. The function of resistor R2 is to limit current and prevent excessive current flowing through T5 from burning it out. The resistance value of R2 can be determined according to the actual circuit parameters.

[0088] The output terminal is also connected to the source of T6. The gate of T6 is connected to the voltage source VDD via R2. The drain of T6 is connected to the reference voltage Vref, which is a negative voltage.

[0089] The following will provide a detailed introduction. Figure 6 The working process of the output switch circuit shown is as follows:

[0090] When the switch signal is high, both T4 and T5 are turned on. T4 being on means the transmission branch between the input and output terminals is open. When T5 is on, the voltage at point A is pulled low to VSS, meaning the gate voltage of T6 is low or negative. Therefore, T6 is turned off, and the transmission branch between the reference voltage Vref and the output is closed. In other words, when the switch input is high, the output follows the input, meaning the output outputs the signal input to the input terminal.

[0091] When the switch signal is low, both T4 and T5 are off. T4 shuts down the transmission branch between the input and output terminals. The shutdown of T5 makes the gate voltage of T6 VDD, meaning T6 receives a high-level gate input signal. At this time, T6 is turned on, thus opening the transmission branch between the reference voltage Vref and the output terminal. In other words, when the switch input is low, the output terminal outputs a negative voltage Vref.

[0092] Based on the above Figure 6 As can be seen from the working process of the output switching circuit shown, the waveforms of each signal voltage in the output switching circuit are as follows: Figure 5 The waveform diagram shown is not described in detail here.

[0093] Please see Figure 7 and Figure 8 , Figure 7 A circuit diagram of yet another output switch circuit provided in an embodiment of this application is shown; Figure 8 It shows Figure 7 The diagram shows the voltage signal waveform corresponding to the output switching circuit.

[0094] like Figure 7 As shown, the output switching circuit includes a seventh switch transistor T7 and an eighth switch transistor T8.

[0095] In this embodiment, T7 is an NMOS transistor and T8 is a PMOS transistor. In other embodiments, T7 and T8 can be other types of switching transistors; this application does not limit the type of switching transistors. Furthermore, each switching transistor can be replaced by a structure of at least two switches of the same type connected in series or parallel, which will not be elaborated further in this application.

[0096] The drain of T7 is the input terminal of the output switch circuit, the source of T7 is the output terminal of the output switch circuit, and the gate of T7 is the switch control terminal. The drain of T8 is connected to the reference voltage Vref, which is a negative voltage. The source of T8 is connected to the output terminal, and the gate of T8 is connected to the switch control terminal.

[0097] The following is combined Figure 7 and Figure 8 The working process of the output switching circuit provided in this embodiment is described below:

[0098] During the t0-t1 phase: The switch input is high, meaning both transistors T7 and T8 have high-level gate inputs. T7 is an NMOS transistor, which conducts when its gate is high. T8 is a PMOS transistor, which turns off when its gate is high. T7's conduction connects the input and output transmission paths, while T8's deactivation disconnects the transmission path between the reference voltage Vref and the output. In other words, when the switch input is high, the output follows the input. Figure 8 As shown, the waveform of the output is consistent with that of the input during the time period t0-t1.

[0099] During the t1-t2 phase: The switch signal is low, meaning both gates of T7 and T8 receive low-level inputs. Therefore, T7 is off and T8 is on. T7 is connected between the input and output terminals, so when T7 is off, the transmission path between the input and output terminals is closed. T8 is connected between Vref and the output terminal, so when T8 is on, the transmission path between Vref and the output terminal is open. In other words, when the switch signal is low, the output outputs the reference voltage Vref, and Vref is a negative voltage. Figure 8 As shown, the output terminal outputs the reference voltage Vref during the time period t1-t2.

[0100] During the t2-t4 phase: the switch signal is high, and this phase is the same as the t0-t1 phase. The output follows the input, such as... Figure 8 As shown, the voltage waveform of the output during the t2-t4 stage is consistent with that of the input.

[0101] In this embodiment, it is assumed that the time period t1-t4 is Figure 2 In the pixel array shown, the write data cycle corresponding to the display pixel in the first row of the first column outputs a preset negative voltage signal, Vref, during the time interval t1-t2 of this cycle. The data signal corresponding to this display pixel is output during the time interval t2-t4. Simultaneously, t4 marks the start of the next write cycle, which is used to output the data signal corresponding to the display pixel in the second row of the first column. Similarly, the preset negative voltage signal, Vref, is output during the time interval t4-t5 of this cycle, and the data signal corresponding to this display pixel is output from t5 to the end of the cycle.

[0102] like Figure 7 As shown, the output switch circuit provided in this embodiment is placed before the source output circuit of the DDIC. The negative voltage output by the output switch circuit is amplified by the source output circuit before being output, ultimately making the output voltage range of the DDIC include negative voltages. This makes the DDIC suitable for OLED partial refresh scenarios, thus expanding the applicable scenarios of the DDIC. Moreover, this output switch circuit contains fewer switching transistors and does not require voltage sources such as VDD and VSS. It can be seen that the circuit structure and control process of this output switch circuit are simpler. In addition, the fewer components in the circuit reduce the hardware cost of the output switch circuit.

[0103] Through the above description of the embodiments, those skilled in the art will clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device, and unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0104] In the several embodiments provided in this example, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0105] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] Furthermore, in each embodiment of this invention, the functional units can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0107] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments. The aforementioned storage medium includes various media capable of storing program code, such as flash memory, portable hard disk, read-only memory, random access memory, magnetic disk, or optical disk.

[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display driving circuit, characterized in that, The display driving circuit for controlling the display pixels of an OLED includes: a signal control module, an output switching circuit, and a source output circuit; The output switch circuit includes an input terminal, a switch control terminal, an output terminal, a first switch branch, and a second switch branch. The first switch branch is connected between the input terminal and the output terminal, and the second switch branch is connected between the output terminal and the negative reference voltage source. The switch control terminal is connected to the control terminals of the first switch branch and the second switch branch, respectively. When the signal control module compares the current frame display data and the previous frame display data at the same display position on the display screen and finds them to be different, it outputs a first switch signal and provides it to the switch control terminal of the output switch circuit. The output switch circuit controls the first switch branch to turn off and the second switch branch to turn on according to the first switch signal, so that the output switch circuit outputs a negative voltage signal, which is then processed by the source output circuit and output.

2. The display driving circuit according to claim 1, characterized in that, When the signal control module compares the current frame display data corresponding to the same display position on the display screen with the previous frame display data, it outputs a second switch signal and provides it to the switch control terminal of the output switch circuit. The output switch circuit controls the first switch branch to be turned on and the second switch branch to be turned off according to the second switch signal, so that the output terminal of the output switch circuit outputs the signal input to the input terminal, and the level of the second switch signal is opposite to that of the first switch signal.

3. The display driving circuit according to claim 1 or 2, characterized in that, The signal control module includes a digital signal control circuit and a signal-to-analog converter circuit; The digital signal control circuit compares whether the current frame display data and the previous frame display data corresponding to the same display position in the display screen are the same, generates a switch signal corresponding to the comparison result, and transmits it to the signal digital-to-analog conversion circuit. The signal digital-to-analog converter circuit converts the switching signal into an analog signal and then transmits it to the output switching circuit.

4. The display driving circuit according to claim 1 or 2, characterized in that, One output switch circuit is configured for each column of display pixels on the OLED screen.

5. The display driving circuit according to claim 1 or 2, characterized in that, The output switching circuit includes a first switching transistor, a second switching transistor, and a third switching transistor; The first terminal of the first switching transistor is connected to the input terminal of the output switching circuit, the second terminal is connected to the output terminal of the output switching circuit, the control terminal is connected to the second terminal of the second switching transistor, and the control terminal is also input with a first voltage, which is a high-level voltage. The first terminal of the second switching transistor is input with a second voltage, and the control terminal is connected to the switch control terminal of the output switching circuit. The second voltage is a low-level voltage or a negative voltage. The first terminal of the third switching transistor is connected to the output terminal of the output switching circuit, the second terminal is input with a preset negative voltage, and the control terminal is connected to the switch control terminal.

6. The display driving circuit according to claim 5, characterized in that, The first switch, the second switch, and the third switch are all NMOS transistors, with the first terminal being the drain, the second terminal being the source, and the control terminal being the gate.

7. The display driving circuit according to claim 1 or 2, characterized in that, The output switching circuit includes a fourth switching transistor, a fifth switching transistor, and a sixth switching transistor; The first terminal of the fourth switching transistor is connected to the input terminal of the output switching circuit, the second terminal is connected to the output terminal of the output switching circuit, and the control terminal is connected to the switch control terminal of the output switching circuit. The first terminal of the fifth switch is input with a second voltage, and the second terminal is input with a first voltage. The first voltage is a high-level voltage, and the second voltage is a low-level voltage or a negative voltage. The first terminal of the sixth switching transistor is connected to the output terminal of the output switching circuit, the second terminal is input with a preset negative voltage, and the control terminal is input with the first voltage.

8. The display driving circuit according to claim 7, characterized in that, The fourth, fifth, and sixth switching transistors are all NMOS transistors, with the first terminal being the drain, the second terminal being the source, and the control terminal being the gate.

9. The display driving circuit according to claim 5, characterized in that, The first switch signal is a high-level signal.

10. The display driving circuit according to claim 1, characterized in that, The output switching circuit includes a seventh switching transistor and an eighth switching transistor; The first terminal of the seventh switch is the input terminal of the output switch circuit, the second terminal is the output terminal of the output switch circuit, and the control terminal is the switch control terminal of the output switch circuit. The first terminal of the eighth switch is connected to the output terminal of the output switch circuit, the second terminal is input with a preset negative voltage, and the control terminal is connected to the switch control terminal.

11. The display driving circuit according to claim 10, characterized in that, The seventh switch is an NMOS transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate. The eighth switch is a PMOS transistor, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate.

12. The display driving circuit according to claim 10 or 11, characterized in that, The first switch signal is a low-level signal.

13. A display module, characterized in that, include: The display screen and the display driving circuit according to any one of claims 1-12.

14. An electronic device, characterized in that, The electronic device includes: one or more processors, a memory, a touch screen, and a display driving circuit according to any one of claims 1-12; the memory is used to store program code; the processor is used to run the program code, causing the display driving circuit to drive the touch screen to update the displayed content.

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