Voltage control in memory devices

Abstract

Example memory devices, circuits, and methods for voltage control in memory devices are disclosed. One example method includes adjusting a rate of change of a reference voltage based on a step voltage and a step time duration, wherein adjusting the rate of change of the reference voltage includes changing the reference voltage for a period of time equal to the step time duration by an amount of the step voltage. An output voltage from one or more charge pumps is generated using a reference voltage, where a ratio between the output voltage and the reference voltage is locked.

Description

Technical Field

[0001] The present disclosure relates to a memory device, a circuit and a method for voltage control in a memory device Background Art

[0002] A voltage generator, such as a charge pump, can provide voltage to support operations in a memory device. An example of a memory device is a flash memory. Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memories include NOR flash memories and NAND flash memories. Flash memories can perform various operations, such as read, program (write), and erase operations. Summary of the invention

[0003] The present disclosure relates to a memory device, a circuit, and a method for voltage control in a memory device.

[0004] Certain aspects of the subject matter described herein can be implemented as a circuit. The circuit includes: one or more charge pumps; and a reference voltage generation circuit. The reference voltage generation circuit includes an adder, the adder is configured to adjust the rate of change of the output voltage of the one or more charge pumps, wherein the input of the adder includes a step size and a step frequency, and the output of the adder changes within a time period equal to the inverse of the step frequency and the amount of change is the step size to adjust the rate of change of the output voltage.

[0005] The circuit may include one or more of the following features.

[0006] In some embodiments, the reference voltage generating circuit further comprises a first comparator coupled to the adder, an input of the first comparator comprising a threshold and the output of the adder, and an output of the first comparator controls a first operating mode of the adder based on a comparison between the threshold and the output of the adder.

[0007] In some implementations, the reference voltage generation circuit further includes a decoder configured to generate an output for decoding the output of the adder.

[0008] In some embodiments, the reference voltage generating circuit further comprises a digital-to-analog converter coupled to the output of the decoder, wherein the digital-to-analog converter is configured to convert the decoded output of the adder into a reference voltage as the output of the reference voltage generating circuit.

[0009] In some embodiments, the reference voltage generating circuit is configured to output a reference voltage based on the output of the adder during a charge pump operation period, and the charge pump operation period includes one or more time periods, during which the ratio between the output voltage of the one or more charge pumps and the reference voltage is locked.

[0010] In some embodiments, the reference voltage in the charge pump operation period includes three consecutive segments, the three consecutive segments include a first segment, a second segment and a third segment, the reference voltage in the first segment is a first constant, and the reference voltage in the third segment is a second constant greater than the first constant.

[0011] In some implementations, the second segment includes two or more consecutive subsegments corresponding to two or more rates of change of the reference voltage.

[0012] In some embodiments, the circuit further includes a charge pump output feedback circuit, which is configured to output a feedback voltage during the charge pump operation period, and during the charge pump operation period, a ratio of the feedback voltage to the output voltage of the one or more charge pumps is predetermined.

[0013] In some implementations, the charge pump output feedback circuit includes a plurality of resistors.

[0014] In some embodiments, the circuit further includes a second comparator, the input of the second comparator including the feedback voltage and the reference voltage, and the output of the second comparator controls a second operating mode of the one or more charge pumps based on a comparison between the feedback voltage and the reference voltage.

[0015] In some embodiments, the circuit further includes one or more clock drivers, the input of the one or more clock drivers being the output of the second comparator, and the one or more clock drivers being configured to provide one or more clock signals to the one or more charge pumps based on the output of the second comparator.

[0016] In some implementations, the configuration of the one or more charge pumps includes a series connection of the one or more charge pumps or a parallel connection of the one or more charge pumps.

[0017] In some implementations, when the output voltage of the one or more charge pumps is greater than a switching threshold, the configuration of the one or more charge pumps is switched from the parallel connection to the series connection.

[0018] Certain aspects of the subject matter described herein can be implemented as a method. The method includes: adjusting a rate of change of a reference voltage based on a step voltage and a step time duration, wherein adjusting the rate of change of the reference voltage includes changing the reference voltage within a time period equal to the step time duration, and the amount of change is the step voltage. Using the reference voltage, an output voltage is generated from one or more charge pumps, wherein a ratio between the output voltage and the reference voltage is locked.

[0019] The method may include one or more of the following features.

[0020] In some embodiments, the configuration of the one or more charge pumps includes a series connection of the one or more charge pumps or a parallel connection of the one or more charge pumps. The method further includes: determining that an output voltage of the one or more charge pumps is greater than a switching threshold; and in response to determining that the output voltage of the one or more charge pumps is greater than the switching threshold, switching the configuration of the one or more charge pumps from the parallel connection to the series connection.

[0021] In some implementations, adjusting the rate of change of the reference voltage further includes: determining that the reference voltage is greater than or equal to a voltage threshold; and in response to determining that the reference voltage is greater than or equal to the voltage threshold, setting the rate of change of the reference voltage to zero.

[0022] In some implementations, adjusting the rate of change of the reference voltage further includes changing the step voltage or changing the step time duration.

[0023] In some implementations, the length of the step time duration is the inverse of a step frequency, and adjusting the rate of change of the reference voltage based on the step voltage and the step time duration includes adjusting the rate of change of the reference voltage based on the step voltage and the step frequency.

[0024] In some embodiments, generating the output voltage from the one or more charge pumps based on the reference voltage includes comparing the reference voltage with a feedback voltage to determine an operating mode of the one or more charge pumps, and a ratio of the feedback voltage to the output voltage of the one or more charge pumps is predetermined.

[0025] Certain aspects of the subject matter described herein may be implemented as a memory device. The memory device comprises: a memory cell array and a circuit. The memory cell array comprises memory cells. The circuit comprises: one or more charge pumps operable to provide an output voltage to a word line of one of the memory cells coupled to the memory cell array; and a reference voltage generating circuit, wherein the reference voltage generating circuit comprises an adder configured to adjust the rate of change of the output voltage of the one or more charge pumps, wherein the input of the adder comprises a step size and a step frequency, and wherein the output of the adder changes within a time period equal to the inverse of the step frequency and the amount of change is the step size to adjust the rate of change of the output voltage.

[0026] Details of these and other aspects and embodiments of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 An example of a schematic circuit diagram of a memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0028] Figure 2 An example of a side view of a cross section of a memory cell array including NAND memory strings according to some aspects of the present disclosure is shown.

[0029] Figure 3 An example of a transaction between a host and a device according to some aspects of the present disclosure is shown.

[0030] Figure 4 An example circuit for charge pump voltage control according to some aspects of the present disclosure is shown.

[0031] Figure 5A An example of parallel-connected charge pumps according to some aspects of the present disclosure is shown.

[0032] Figure 5B An example of a series-connected charge pump is shown in accordance with some aspects of the present disclosure.

[0033] Figure 6 An example of a reference voltage generating circuit according to some aspects of the present disclosure is shown.

[0034] Figure 7 An example of a pump output 410 is shown in accordance with some aspects of the present disclosure.

[0035] Figure 8 An example of simulation results of charge pump output voltage and corresponding peak input current according to some aspects of the present disclosure is shown.

[0036] Fig. 9 An example of a flow chart of a method for controlling a charge pump voltage in a memory device according to some aspects of the present disclosure is shown.

[0037] Fig.10 A block diagram of an example system having a memory device according to some aspects of the present disclosure is shown.

[0038] Fig.11A A diagram showing a memory card having a storage device according to some aspects of the present disclosure is shown.

[0039] Fig. 11B A diagram showing a solid-state drive (SSD) having a storage device according to some aspects of the present disclosure.

[0040] Like reference numbers and designations in different drawings indicate like elements. DETAILED DESCRIPTION

[0041] The present specification relates to memory devices, circuits, and methods for voltage control in memory devices. In some cases, a charge pump can provide different voltages to support operations in a three-dimensional (3D) NAND flash memory. For example, a charge pump group in a 3D NAND flash memory can provide a bias voltage to a word line that is not selected for programming during a programming operation of a memory cell in the 3D NAND flash memory. During a programming operation of a memory cell in the 3D NAND flash memory, the bias voltage provided by the charge pump group to the unselected word line can be increased from a relatively low value (e.g., 1.8V) to a relatively high value (e.g., 10V). The above increase in the bias voltage to the unselected word line can result in a large peak input current to the charge pump group. In order to reduce the peak input current without significantly reducing the rate at which the bias voltage increases during the programming operation of the 3D NAND flash memory, a reference voltage generation circuit can be used. The reference voltage generation circuit can control the rate of increase of the reference voltage, which in turn controls the rate of increase of the bias voltage from the charge pump group. In this way, when the peak input current is relatively high, the reference voltage generation circuit can increase the bias voltage at a slower rate. When the peak input current is relatively low, the reference voltage generation circuit may increase the bias voltage at a higher rate.

[0042] Embodiments of the present disclosure may provide one or more of the following technical advantages. For example, a reference voltage generating circuit may use a reference voltage to adjust the rate of change of a bias voltage from a charge pump. In this way, the peak input current to the charge pump may be reduced without significantly reducing the rate at which the bias voltage increases during a programming operation of a 3D NAND flash memory. In addition, different rates of change of the voltage from the charge pump may be preset for different operations of the NAND flash memory, so that the charge pump may more effectively support different operations in the NAND flash memory.

[0043] Figure 1 An example of a schematic circuit diagram of a memory device 100 including peripheral circuits according to some aspects of the present disclosure is shown. The memory device 100 may include a memory cell array 101 and a peripheral circuit 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, in which memory cells 106 are provided in the form of an array of NAND memory strings 108, each NAND memory string 108 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as a voltage or charge that depends on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

[0044] In some embodiments, each memory cell 106 is a single-level cell (SLC) having two possible storage states, and thus can store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 106 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to adopt a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to adopt one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. The fourth nominal storage value can be used for the erased state.

[0045] like Figure 1 As shown, each NAND memory string 108 may include a source select gate (SSG) 110 at its source end and a drain select gate (DSG) 112 at its drain end. SSG 110 and DSG 112 may be configured to activate a selected NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 108 in the same block 104 are coupled by the same source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the DSG 112 of each NAND memory string 108 is coupled to a corresponding bit line 116, from which data may be read or written via an output bus (not shown). In some embodiments, each NAND memory string 108 is configured to be selected or deselected by applying a select voltage or a deselect voltage (e.g., 0 V) ​​to the corresponding DSG 112 via one or more DSG lines 113, and / or by applying a select voltage or a deselect voltage (e.g., 0 V) ​​to the corresponding SSG 110 via one or more SSG lines 115.

[0046] like Figure 1 As shown, the NAND memory string 108 can be organized into a plurality of blocks 104, each block 104 can have a common source line 114, for example, the common source line 114 is coupled to the ACS. In some embodiments, each block 104 is a basic data unit for an erase operation, that is, all memory cells 106 on the same block 104 are erased simultaneously. In order to erase the memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and the unselected blocks 104 in the same plane as the selected block 104 can be biased with an erase voltage (erase voltage, Vers), and the erase voltage (Vers) is a high positive voltage (e.g., 20V or higher). In some examples, the erase operation can be performed at a half-block level, a quarter-block level, or a level with any suitable number of blocks or any suitable fraction of blocks. The memory cells 106 of adjacent NAND memory strings can be coupled by word lines 118, which select which row of memory cells 106 is affected by read and program operations. Each word line 118 may include a plurality of control gates (gate electrodes) at each memory cell 106 and a gate line coupling the control gates. Figure 1The example word lines (WL) shown in FIG. 1 include dummy WLs, WL1 , WL2 , WL3 , WL4 , and WL5 , located between one or more DSG lines 113 and one or more SSG lines 115 .

[0047] Figure 2 An example of a side view of a cross section of a memory cell array 101 including NAND memory strings 108 is shown in accordance with some aspects of the present disclosure. Figure 2 As shown, the NAND memory strings 108 may extend vertically through a memory stack 204 above a substrate 202. The substrate 202 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0048] The memory stack 204 may include interlaced gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 may determine the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 106, DSG 112, or SSG 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between the DSG line 113 and the SSG line 115.

[0049] Peripheral circuit 102 may be coupled to memory cell array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuit 102 may include any suitable analog, digital, and mixed signal circuits for facilitating operation of memory cell array 101 by applying and sensing voltage and / or current signals to and from each target memory cell in memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuit 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some example peripheral circuits according to some aspects of the present disclosure are shown. The example peripheral circuits include page buffers / sense amplifiers 304, column decoders / bit line drivers 306, row decoders / word line drivers 308, voltage generators 310, control logic 312, registers 314, interfaces 316, and data buses. In some examples, the peripheral circuits may also include Figure 3 Additional peripheral circuits not shown.

[0050] The page buffer / sense amplifier 304 may be configured to read data from the memory cell array 101 and program (write) data to the memory cell array 101 according to a control signal from the control logic 312. In one example, the page buffer / sense amplifier 304 may store a page of programming data (write data) to be programmed into one page of the memory cell array 101. In another example, the page buffer / sense amplifier 304 may perform a program verification operation to ensure that the data has been properly programmed into the memory cell 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 may also sense a low-power signal from the bit line 116 representing a data bit stored in the memory cell 106, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 306 may be configured to be controlled by the control logic 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated from the voltage generator 310.

[0051] The row decoder / word line driver 308 may be configured to be controlled by the control logic 312 and to select / deselect the block 104 of the memory cell array 101 and to select / deselect the word line 118 of the block 104. The row decoder / word line driver 308 may also be configured to drive the word line 118 using the word line voltage generated from the voltage generator 310. In some embodiments, the row decoder / word line driver 308 may also select / deselect and drive the SSG line 115 and the DSG line 113. The row decoder / word line driver 308 may be configured to apply a read voltage to the selected word line 118 in a read operation of the memory cell 106 coupled to the selected word line 118.

[0052] The voltage generator 310 may be configured to be controlled by the control logic 312 and generate word line voltages (eg, read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 101 .

[0053] The control logic 312 may be coupled to each of the above-mentioned peripheral circuits and configured to control the operation of each peripheral circuit. The register 314 may be coupled to the control logic 312 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The status register of the register 314 may include one or more registers, and the register is configured to store open block information indicating the open blocks (single or multiple) in all blocks 104 in the memory cell array 101, such as an auto dynamic start voltage (ADSV) list. In some embodiments, the open block information also indicates the last programming page of each open block.

[0054] The interface 316 may be coupled to the control logic 312 and act as a control buffer to buffer and relay control commands received from a host (not shown) to the control logic 312 and to buffer and relay status information received from the control logic 312 to the host. The interface 316 may also be coupled to the column decoder / bit line driver 306 via a data bus and act as a data input / output (I / O) interface and a data buffer to buffer and relay data to and from the memory cell array 101.

[0055] Figure 4 An example circuit 400 for charge pump voltage control is shown. In some implementations, the circuit 400 can be an example of a voltage generator 310 in the peripheral circuit 102. The circuit 400 can generate voltages for the memory cell array 101, such as word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verification voltages, etc.).

[0056] In some embodiments, circuit 400 includes a charge pump 402, a charge pump output feedback circuit including multiple resistors (e.g., resistors Ra412 and Rb414), a reference voltage generating circuit DAC 420, a comparator 422 (e.g., a second comparator), and a charge pump clock control circuit (e.g., a clock driver) CLK driver 424.

[0057] like Figure 4 As shown, the charge pump 402 in the circuit 400 includes a plurality of charge pumps connected in series, such as CP1 404, CP2 406, and CPN 408. Examples of charge pumps connected in series are also shown in FIG. Figure 5B In some embodiments, the charge pump 402 may include multiple charge pumps connected in parallel, such as Figure 5A The voltage output of circuit 400 is equal to the voltage output V of the last charge pump CPN 408 in the series-connected charge pump group 402. out The pump output is 410.

[0058] In some embodiments, the feedback voltage v fb 416 is the output from the charge pump output feedback circuit and is linearly proportional to the pump output 410, and v fb The ratio of 416 to the pump output 410 is controlled by two resistors Ra 412 and Rb 414 as shown in Equation 1.

[0059]

[0060] In some embodiments, the feedback voltage v fb 416 and reference voltage v ref 418 to control the operating mode (eg, the second operating mode) of the charge pump 402 as to whether to prevent the increase of the pump output 410. Figure 4 The comparator 422 in performs the comparison. When v ref 418 is greater than v fb 416, the output of the comparator 422 is 1, and the charge pump clock control circuit CLK driver 424 is enabled to output the clock signal pmpclk 426 at a certain frequency, so that the charge pump 402 can continue to increase the pump output 410, and thus increase v fb 416. When v ref 418 is equal to v fb 416, the output of comparator 422 is 0 and prevents the switching of clock signal pmpclk 426, and thus prevents charge pump 402 from changing pump output 410, and thus prevents changing v fb416. The charge pump operation period may include when v ref 418 is greater than v fb 416 hours one or more time periods and when v ref 418 is equal to v fb During the charge pump operation period, according to equation 1, v fb The ratio of 416 to the pump output 410 is controlled by two resistors Ra 412 and Rb 414. In some embodiments, when v ref 418 is greater than v fb 416, the output of the comparator 422 is 0 and the charge pump clock control circuit CLK driver 424 is enabled to output the clock signal pmpclk 426 at a certain frequency, so that the charge pump 402 can continue to increase the pump output 410, and thus increase v fb 416. When v ref 418 is equal to v fb 416, the output of comparator 422 is 1 and blocks the switching of clock signal pmpclk 426, and thus blocks charge pump 402 from changing pump output 410, and thus blocks changing v fb 416.

[0061] In some embodiments, the reference voltage v ref 418 is output from a reference voltage generating circuit (e.g., a digital to analog converter (DAC) 420). An example of DAC 420 is shown in FIG. Figure 6 and described later. ref 418 is equal to v fb 416, the pump output is 410 and v ref 418 is linearly proportional, as shown in Equation 2. Therefore, v can be adjusted by the reference voltage generating circuit DAC 420 ref 418 to control the pump output 410. For example, the reference voltage generation circuit DAC 420 can be used to set v ref 418 to control the rate of increase of the pump output 410, such as Figure 6 shown and described later.

[0062]

[0063] Figure 5A An example of charge pumps connected in parallel is shown. Figure 5BAn example of a charge pump connected in series is shown. In some embodiments, when the charge pump group provides a voltage to support operations in a 3D NAND flash memory, for example, when the charge pump group provides a bias voltage to an unselected word line in a 3D NAND flash memory during a read operation of a memory cell of the 3D NAND flash memory, the main load of the charge pump group comes from a capacitor associated with the unselected word line gate, where the capacitance can be several nF. When the output voltage of the charge pump group increases, the output current of the charge pump group can charge the capacitor and increase the voltage of the unselected word line gate. Equation 3 shows that the output voltage V of the charge pump group is proportional to the output current I and the time T. Q is the charge in the capacitor due to the charging operation of the charge pump group. C is the capacitance of the capacitor associated with the unselected word line gate.

[0064] Q=CV=IT (3)

[0065] In some embodiments, when the output voltage of the charge pump group is relatively low, Figure 5A The parallel connection of the charge pump groups in the embodiment can generate a relatively high output current from the charge pump groups. As the output voltage of the charge pump groups continues to increase, Figure 5B The series connection of the charge pump groups in the embodiment can generate a relatively high output voltage from the charge pump groups, and when the output voltage of the charge pump groups exceeds a threshold value (e.g., a switching threshold), the charge pump groups can switch from the parallel connection to the series connection. In some embodiments, when the feedback voltage v fb When 416 exceeds the threshold, the charge pump group can switch from parallel connection to series connection.

[0066] In some embodiments, when the charge pump group switches from a parallel connection to a series connection, the output current and efficiency of the charge pump group can change. out When the output current of the charge pump group increases, out The output current i of the charge pump group is reduced, and the efficiency of the charge pump group increases before it is reduced, and the efficiency of the charge pump group can be increased before it is reduced. Equations 4 and 5 respectively show the output current i of the charge pump group out and efficiency η.

[0067]

[0068]

[0069] Figure 6 An example of a reference voltage generating circuit 600 is shown. In some implementations, the reference voltage generating circuit 600 may be an example of a DAC 420. Figure 6As shown, the reference voltage generating circuit 600 may include an adder 606, a comparator 618 (eg, a first comparator), a decoder 610, and a digital-to-analog converter 612. The output of the reference voltage generating circuit 600 is a reference voltage v ref 614 , which can be used to control the rate of increase of the pump output 410 through the circuit 400 .

[0070] In some embodiments, the input of adder 606 may include step size ΔDAC 602 and step frequency CK 604, and the output of adder 606 is a digital signal DAC 608. CK 604 may control the sampling period of adder 606. By changing ΔDAC 602 and / or CK 604, DAC 608 may be controlled. For example, DAC 608 may increase by ΔDAC 602 in each sampling period equal to the inverse of step frequency CK 604. DAC 608 then passes through decoder 610, so that DAC 608 is decoded by decoder 610. The output of decoder 610 then passes through digital-to-analog converter 612, so that the output of decoder 610, which is a digital signal, is converted into an analog signal, i.e., reference voltage v ref 614.

[0071] In some implementations, the DAC 608 is compared to the target DAC 616 in the comparator 618 to control the operation mode (e.g., the first operation mode) of the adder 606 as to whether to prevent the increase of the DAC 608. For example, when the DAC 608 is less than the target DAC 616, the comparator 618 outputs the signal En 620 to continue the operation of the adder 606, thereby increasing the DAC 608 based on the ΔDAC 602 and the CK 604. When the DAC 608 is equal to the target DAC 616, the comparator 618 outputs the signal En 620 to prevent the adder 606 from continuing to increase the DAC 608. Using the circuit 400 and Equation 2, v ref 614 can be used to control the pump output 410, such as Figure 7 As shown in and described below.

[0072] Figure 7 An example of a pump output 410 is shown. The rate of increase of the pump output 410 can be adjusted using ΔV and Δt. ΔV can be controlled by a ΔDAC using Equation 2, and Δt can be controlled as the inverse of the step frequency CK 604. Figure 7 Five reference voltage switching points V0 , V1 , V2 , V3 , and V4 are shown in , where at each of the five switching points, the rate of increase of the pump output 410 changes due to a change in the ΔDAC 602 and / or a change in the CK 604 . Figure 6 The target DAC 616 can be used to control Figure 7The level of the pump output 410 at the end of the slope4 segment, which is the final value of the pump output 410. Figure 7 The pump output 410 in includes three segments. The first segment is before the switching point V0 and has a constant voltage Vdd. The second segment is between the switching point V0 and the switching point V4, and includes four sub-segments with corresponding increase rates of the pump output 410, namely, slope1, slope2, slope3, and slope4. The third segment is after the switching point V4 and has a constant voltage greater than Vdd. In some embodiments, at the switching point V1, the increase rate of the pump output 410 can be reduced from slope1 to slope2 by reducing ΔDAC 602 and thereby reducing ΔV, or by reducing CK 604 and thereby increasing Δt. In some embodiments, the charge pump group that outputs the pump output 410 can be used before the switching point V2 at a rate such as Figure 5A Because the pump output 410 continues to increase after the switching point V2, the charge pump group can be switched from the parallel connection to the series connection after the switching point V2, such as Figure 5B In some embodiments, at switching point V3, the rate of increase of pump output 410 can be increased from slope3 to slope4 by increasing ΔDAC 602 and thereby increasing ΔV, or by increasing CK 604 and thereby decreasing Δt.

[0073] Figure 8 An example of simulation results of charge pump output voltage and corresponding peak input current is shown. Curves 1 and 2 show the pump output voltage. Curves 3 and 4 show the corresponding peak input current. Curves 1 and 3 are generated based on a reference voltage with a constant rate of change. Curves 2 and 4 are generated based on Figure 6 The reference voltage generating circuit shown is generated. Curve 2 shows that its pump output voltage is lower than the pump output voltage of curve 1 most of the time. Curve 4 shows that its peak input current is lower than the peak input current of curve 3. Therefore, Figure 6 The reference voltage generating circuit shown can reduce the peak input current to the charge pump by adjusting the increasing rate of the reference voltage.

[0074] Fig. 9 An example of a flow chart of a method for controlling a charge pump voltage in a memory device according to some aspects of the present disclosure is shown. At 902, a peripheral circuit of the memory device adjusts a rate of change of a reference voltage based on a step voltage and a step time duration, wherein adjusting the rate of change of the reference voltage includes changing the reference voltage within a time period equal to the step time duration, and the amount of change of the reference voltage is the step voltage.

[0075] At 904 , the peripheral circuit generates an output voltage from one or more charge pumps using a reference voltage, wherein a ratio between the output voltage and the reference voltage is locked.

[0076] Fig.10 1 is a block diagram of an example system 1000 having a storage device according to some aspects of the present disclosure. The system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. Fig.10 As shown, system 1000 may include a host 1008 and a storage system 1002 having one or more storage devices 1004 and a memory controller 1006. Host 1008 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host 1008 may be configured to send data to storage device 1004 or receive data from storage device 1004.

[0077] The memory device 1004 may be any memory device disclosed in the present disclosure. According to some embodiments, the memory controller 1006 is coupled to the memory device 1004 and the host 1008 and is configured to control the memory device 1004. The memory controller 1006 may manage data stored in the memory device 1004 and communicate with the host 1008. In some embodiments, the memory controller 1006 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1006 is designed to operate in a high duty cycle environment SSD or an embedded multi-media card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 1006 may be configured to control the operation of the memory device 1004, such as read, erase, and program operations. The memory controller 1006 may also be configured to manage various functions regarding data stored or to be stored in the memory device 1004, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 1006 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 1004. The memory controller 1006 may also perform any other suitable functions, such as formatting the memory device 1004.

[0078] The memory controller 1006 may communicate with an external device (e.g., the host 1008) according to a specific communication protocol. For example, the memory controller 1006 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, and the like.

[0079] The memory controller 1006 and the one or more memory devices 1004 may be integrated into various types of storage devices, for example, included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, the storage system 1002 may be implemented and packaged into different types of terminal electronic products. Fig.11A In one example shown, the memory controller 1006 and the single memory device 1004 may be integrated into a memory card 1102. The memory card 1102 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1102 may also include a processor that connects the memory card 1102 to a host (e.g., Fig.10 The host 1008 in the memory card connector 1104 is coupled. Fig. 11B In another example shown, the memory controller 1006 and the plurality of memory devices 1004 may be integrated into an SSD 1106. The SSD 1106 may also include a processor that connects the SSD 1106 to a host (eg, Fig.10 In some embodiments, the storage capacity and / or operating speed of the SSD 1106 is greater than the storage capacity and / or operating speed of the memory card 1102.

[0080] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope that may be claimed, but rather as descriptions of features that may be specific to a particular embodiment. Certain features described in this specification in the context of different embodiments may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments, individually or in any sub-combination. In addition, although the previously described features may be described as working in certain combinations, and even initially claimed to be protected as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may point to a variant of a sub-combination or a sub-combination.

[0081] As used in this disclosure, the terms "a", "an", or "the" are intended to include one or more, unless the context clearly dictates otherwise. Unless otherwise specified, the term "or" refers to a non-exclusive "or". The statement "at least one of A and B" has the same meaning as "A, B, or A and B". In addition, the expressions or terms used in this disclosure (not otherwise defined) are intended to be descriptive only and not limiting. The use of any section headings is intended to aid in reading the document and is not to be construed as limiting; information related to the section heading may appear within or outside that particular section.

[0082] As used in this disclosure, the terms "about" or "approximately" may allow for a certain degree of variability in a value or range, for example, within 10%, within 5%, or within 1% of the stated limit of the stated value or range.

[0083] As used in this disclosure, the term "substantially" means predominantly, or mostly, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0084] Values ​​expressed in range format should be interpreted in a flexible manner to include not only the values ​​explicitly listed as the limits of the range, but also all individual values ​​or sub-ranges contained within the range, as if each value and sub-range were explicitly stated. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3% and 4%) and sub-ranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise specified, the statement "X to Y" has the same meaning as "about X to about Y". Similarly, unless otherwise specified, the statement "X, Y or Z" has the same meaning as "about X, about Y or about Z".

[0085] Specific embodiments of the subject matter have been described. Other embodiments, modifications, and permutations of the described embodiments are within the scope of the following claims and will be apparent to those skilled in the art. Although operations are described in a particular order in the drawings or claims, it is not required that the operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed (some operations may be considered optional), to achieve the desired results. In certain circumstances, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and is performed where deemed appropriate.

[0086] Furthermore, the various system modules and components in the previously described embodiments may not need to be separated or integrated in all embodiments, and the described components and systems may generally be integrated together or packaged into multiple products.

[0087] Therefore, the example embodiments described above do not define or constrain the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

Claims

1. A circuit comprising: one or more charge pumps; as well as A reference voltage generating circuit, wherein the reference voltage generating circuit comprises an adder, the adder being configured to adjust the rate of change of the output voltage of the one or more charge pumps, wherein the input of the adder comprises a step size and a step frequency, and wherein the output of the adder changes within a time period equal to the inverse of the step frequency and the amount of change is the step size to adjust the rate of change of the output voltage.

2. The circuit according to claim 1, wherein The reference voltage generating circuit also includes a first comparator coupled to the adder, the input of the first comparator including a threshold and the output of the adder, and the output of the first comparator controls a first operating mode of the adder based on a comparison between the threshold and the output of the adder.

3. The circuit according to claim 1 or 2, wherein: The reference voltage generation circuit further includes a decoder configured to generate an output for decoding the output of the adder.

4. The circuit according to claim 3, wherein: The reference voltage generation circuit further includes a digital-to-analog converter coupled to the output of the decoder, wherein the digital-to-analog converter is configured to convert the decoded output of the adder into a reference voltage as an output of the reference voltage generation circuit.

5. The circuit according to any one of claims 1 to 4, wherein: The reference voltage generating circuit is configured to output a reference voltage based on the output of the adder during a charge pump operation period, and the charge pump operation period includes one or more time periods, during which the ratio between the output voltage of the one or more charge pumps and the reference voltage is locked.

6. The circuit according to claim 5, wherein: The reference voltage in the charge pump operation period includes three consecutive segments, including a first segment, a second segment and a third segment, the reference voltage in the first segment is a first constant, and the reference voltage in the third segment is a second constant greater than the first constant.

7. The circuit according to claim 6, wherein: The second segment includes two or more consecutive subsegments corresponding to two or more rates of change of the reference voltage.

8. A circuit according to any one of claims 5 to 7, wherein: The circuit also includes a charge pump output feedback circuit, which is configured to output a feedback voltage during the charge pump operation period, and during the charge pump operation period, a ratio of the feedback voltage to the output voltage of the one or more charge pumps is predetermined.

9. The circuit according to claim 8, wherein The charge pump output feedback circuit includes a plurality of resistors.

10. The circuit according to claim 8 or 9, wherein: The circuit also includes a second comparator whose input includes the feedback voltage and the reference voltage, and whose output controls a second operating mode of the one or more charge pumps based on a comparison between the feedback voltage and the reference voltage.

11. The circuit according to claim 10, wherein: The circuit also includes one or more clock drivers, the input of which is the output of the second comparator, and the one or more clock drivers are configured to provide one or more clock signals to the one or more charge pumps based on the output of the second comparator.

12. The circuit according to any one of claims 1 to 11, wherein: The configuration of the one or more charge pumps includes a series connection of the one or more charge pumps or a parallel connection of the one or more charge pumps.

13. The circuit of claim 12, wherein: The configuration of the one or more charge pumps is switched from the parallel connection to the series connection when the output voltage of the one or more charge pumps is greater than a switching threshold.

14. A method comprising: adjusting a rate of change of a reference voltage based on a step voltage and a step time duration, wherein adjusting the rate of change of the reference voltage comprises changing the reference voltage by the step voltage over a period of time equal to the step time duration; and An output voltage is generated from one or more charge pumps using the reference voltage, wherein a ratio between the output voltage and the reference voltage is locked.

15. The method according to claim 14, wherein: The configuration of the one or more charge pumps includes a series connection of the one or more charge pumps or a parallel connection of the one or more charge pumps, and the method further includes: determining that an output voltage of the one or more charge pumps is greater than a switching threshold; and In response to determining that the output voltage of the one or more charge pumps is greater than the switching threshold, the configuration of the one or more charge pumps is switched from the parallel connection to the series connection.

16. The method according to claim 14 or 15, wherein: Adjusting the rate of change of the reference voltage further includes: determining that the reference voltage is greater than or equal to a voltage threshold; and In response to determining that the reference voltage is greater than or equal to the voltage threshold, the rate of change of the reference voltage is set to zero.

17. The method according to any one of claims 14 to 16, wherein: Adjusting the rate of change of the reference voltage also includes changing the step voltage or changing the step time duration.

18. The method according to any one of claims 14 to 17, wherein: The length of the step time duration is the inverse of a step frequency, and adjusting the rate of change of the reference voltage based on the step voltage and the step time duration includes adjusting the rate of change of the reference voltage based on the step voltage and the step frequency.

19. The method according to any one of claims 14 to 18, wherein: Generating the output voltage from the one or more charge pumps based on the reference voltage includes comparing the reference voltage to a feedback voltage to determine an operating mode of the one or more charge pumps, and a ratio of the feedback voltage to the output voltage of the one or more charge pumps is predetermined.

20. A storage device comprising: A memory cell array, comprising a memory cell; as well as Circuit, including: one or more charge pumps operable to provide an output voltage to a word line coupled to one of the memory cells of the memory cell array; and A reference voltage generating circuit, wherein the reference voltage generating circuit comprises an adder, the adder being configured to adjust the rate of change of the output voltage of the one or more charge pumps, wherein the input of the adder comprises a step size and a step frequency, and wherein the output of the adder changes within a time period equal to the inverse of the step frequency and the amount of change is the step size to adjust the rate of change of the output voltage.

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