Voltage control in memory devices

Abstract

Example memory devices, circuits, and methods for voltage control in a memory device are disclosed. One example method includes adjusting a rate of change of a reference voltage based on a step voltage and a step time duration, where adjusting the rate of change of the reference voltage includes changing the reference voltage over a time period equal to the step time duration and by an amount equal to the step voltage. An output voltage from one or more charge pumps is generated using the reference voltage, where a ratio between the output voltage and the reference voltage is locked.

Description

Technical Field

[0001] This disclosure relates to storage devices, circuits, and methods for voltage control in storage devices. Background Technology

[0002] Voltage generators, such as charge pumps, can provide voltage to support operations in storage devices. An example of a storage device is flash memory. Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as read, program (write), and erase operations. Summary of the Invention

[0003] This disclosure relates to storage devices, circuits, and methods for voltage control in storage devices.

[0004] Certain aspects of the subject matter described herein can be implemented as a circuit. This circuit includes: one or more charge pumps; and a reference voltage generation circuit. The reference voltage generation circuit includes an adder configured to adjust the rate of change of the output voltage of the one or more charge pumps, wherein the inputs of the adder include a step size and a step frequency, and the output of the adder changes over a time period equal to the reciprocal of the step frequency, the amount of change being the step size, to adjust the rate of change of the output voltage.

[0005] The circuit may include one or more of the following features.

[0006] In some embodiments, the reference voltage generation circuit further includes a first comparator coupled to the adder, the input of the first comparator including a threshold and the output of the adder, and the output of the first comparator controlling a first operating mode of the adder based on a comparison between the threshold and the output of the adder.

[0007] In some embodiments, the reference voltage generation circuit further includes a decoder configured to generate an output for decoding the output of the adder.

[0008] In some embodiments, the reference voltage generation circuit further includes a digital-to-analog converter coupled to the output of the decoder, wherein the digital-to-analog converter is configured to convert the decoded output of the adder into a reference voltage as the output of the reference voltage generation circuit.

[0009] In some embodiments, the reference voltage generation circuit is configured to output a reference voltage based on the output of the adder during a charge pump operation period, and the charge pump operation period includes one or more time periods during which the ratio between the output voltage of the one or more charge pumps and the reference voltage is locked.

[0010] In some embodiments, the reference voltage during the charge pump operation period comprises three consecutive segments, the three consecutive segments being a first segment, a second segment, and a third segment, wherein the reference voltage in the first segment is a first constant, and the reference voltage in the third segment is a second constant greater than the first constant.

[0011] In some embodiments, the second segment includes two or more consecutive sub-segments corresponding to two or more rates of change of the reference voltage.

[0012] In some embodiments, the circuit further includes a charge pump output feedback circuit configured to output a feedback voltage during the charge pump operation period, wherein the ratio of the feedback voltage to the output voltage of the one or more charge pumps is predetermined during the charge pump operation period.

[0013] In some implementations, the charge pump output feedback circuit includes multiple resistors.

[0014] In some embodiments, the circuit further includes a second comparator, the input of which includes the feedback voltage and the reference voltage, and the output of the second comparator controls a second operating mode of the one or more charge pumps based on a comparison between the feedback voltage and the reference voltage.

[0015] In some embodiments, the circuit further includes one or more clock drivers, the input of which is the output of the second comparator, and the one or more clock drivers are configured to provide one or more clock signals to the one or more charge pumps based on the output of the second comparator.

[0016] In some implementations, the configuration of the one or more charge pumps includes a series connection of the one or more charge pumps or a parallel connection of the one or more charge pumps.

[0017] In some implementations, when the output voltage of the one or more charge pumps is greater than a switching threshold, the configuration of the one or more charge pumps is switched from the parallel connection to the series connection.

[0018] Certain aspects of the subject matter described herein can be implemented as a method. This method includes: adjusting the rate of change of a reference voltage based on a step voltage and a step time duration, wherein adjusting the rate of change of the reference voltage includes changing the reference voltage over a time period equal to the step time duration, and the amount of change being the step voltage. An output voltage is generated from one or more charge pumps using the reference voltage, wherein the ratio between the output voltage and the reference voltage is locked.

[0019] The method may include one or more of the following features.

[0020] In some embodiments, the configuration of the one or more charge pumps includes a series connection of the one or more charge pumps or a parallel connection of the one or more charge pumps. The method further includes: determining that the output voltage of the one or more charge pumps is greater than a switching threshold; and, in response to determining that the output voltage of the one or more charge pumps is greater than the switching threshold, switching the configuration of the one or more charge pumps from the parallel connection to the series connection.

[0021] In some embodiments, adjusting the rate of change of the reference voltage further includes: determining that the reference voltage is greater than or equal to a voltage threshold; and, in response to determining that the reference voltage is greater than or equal to the voltage threshold, setting the rate of change of the reference voltage to zero.

[0022] In some implementations, adjusting the rate of change of the reference voltage further includes changing the step voltage or changing the duration of the step time.

[0023] In some implementations, the length of the step time duration is the reciprocal of the step frequency, and adjusting the rate of change of the reference voltage based on the step voltage and the step time duration includes adjusting the rate of change of the reference voltage based on the step voltage and the step frequency.

[0024] In some implementations, generating the output voltage from the one or more charge pumps based on the reference voltage includes comparing the reference voltage with a feedback voltage to determine the operating mode of the one or more charge pumps, and the ratio of the feedback voltage to the output voltage of the one or more charge pumps is predetermined.

[0025] Certain aspects of the subject matter described herein can be implemented as a storage device. The storage device includes: a memory cell array and circuitry. The memory cell array includes memory cells. The circuitry includes: one or more charge pumps operable to provide an output voltage to a word line coupled to one of the memory cells of the memory cell array; and a reference voltage generation circuit, wherein the reference voltage generation circuit includes an adder configured to adjust the rate of change of the output voltage of the one or more charge pumps, wherein the inputs of the adder include a step size and a step frequency, and wherein the output of the adder changes over a time period equal to the reciprocal of the step frequency, and the amount of change is the step size, to adjust the rate of change of the output voltage.

[0026] These and other aspects of this disclosure, as well as details of the embodiments, are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will be apparent from the specification, drawings, and claims. Attached Figure Description

[0027] Figure 1 Examples of schematic circuit diagrams of storage devices including peripheral circuitry according to some aspects of this disclosure are shown.

[0028] Figure 2 An example of a side view of a cross-section of a memory cell array including NAND memory strings is shown, according to some aspects of this disclosure.

[0029] Figure 3 An example of a transaction between a host and a device is shown in accordance with some aspects of this disclosure.

[0030] Figure 4 An example circuit for charge pump voltage control is shown according to some aspects of this disclosure.

[0031] Figure 5A An example of a charge pump connected in parallel according to some aspects of this disclosure is shown.

[0032] Figure 5B An example of a charge pump connected in series according to some aspects of this disclosure is shown.

[0033] Figure 6 An example of a reference voltage generation circuit according to some aspects of this disclosure is shown.

[0034] Figure 7 An example of pump output 410 according to some aspects of this disclosure is shown.

[0035] Figure 8 Examples of simulation results for the charge pump output voltage and corresponding peak input current according to some aspects of this disclosure are shown.

[0036] Figure 9 An example flowchart of a method for controlling the charge pump voltage in a storage device according to some aspects of this disclosure is shown.

[0037] Figure 10 A block diagram of an example system having a storage device according to some aspects of this disclosure is shown.

[0038] Figure 11A A diagram of a memory card having a storage device according to some aspects of this disclosure is shown.

[0039] Figure 11B A diagram of a solid-state drive (SSD) having a storage device is shown according to some aspects of this disclosure.

[0040] Similar reference numerals and labels in different figures indicate similar elements. Detailed Implementation

[0041] This specification relates to memory devices, circuits, and methods for voltage control in memory devices. In some cases, charge pumps can provide different voltages to support operation in three-dimensional (3D) NAND flash memory. For example, a charge pump group in a 3D NAND flash memory can provide a bias voltage to an unselected word line during programming operations of a memory cell in the 3D NAND flash memory. During programming operations of a memory cell in the 3D NAND flash memory, the bias voltage provided by the charge pump group to the unselected word line can increase from a relatively low value (e.g., 1.8V) to a relatively high value (e.g., 10V). This increase in the bias voltage to the unselected word line can result in a large peak input current to the charge pump group. To reduce the peak input current without significantly reducing the rate of increase of the bias voltage during programming operations of the 3D NAND flash memory, a reference voltage generation circuit can be used. The reference voltage generation circuit can control the rate of increase of the reference voltage, which in turn controls the rate of increase of the bias voltage from the charge pump group. Thus, when the peak input current is relatively high, the reference voltage generation circuit can increase the bias voltage at a slower rate. When the peak input current is relatively low, the reference voltage generation circuit can increase the bias voltage at a higher rate.

[0042] The embodiments of this disclosure can provide one or more of the following technical advantages. For example, the reference voltage generation circuit can use a reference voltage to adjust the rate of change of the bias voltage from the charge pump. This allows the peak input current of the charge pump to be reduced without significantly decreasing the rate of increase of the bias voltage during programming operations of the 3D NAND flash memory. Furthermore, different rates of change of the voltage from the charge pump can be preset for different operations of the NAND flash memory, enabling the charge pump to more effectively support different operations in the NAND flash memory.

[0043] Figure 1 An example of a schematic circuit diagram of a memory device 100 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, wherein memory cells 106 are provided in the form of an array of NAND memory strings 108, each NAND memory string 108 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as voltage or charge depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0044] In some implementations, each memory cell 106 is a single-level cell (SLC) with two possible storage states and thus can store one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each memory cell 106 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also called a triple-level cell (TLC)), or four bits per cell (also called a quad-level cell (QLC)). Each MLC can be programmed to use a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to use one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0045] like Figure 1 As shown, each NAND flash memory string 108 may include a source select gate (SSG) 110 at its source end and a drain select gate (DSG) 112 at its drain end. SSG 110 and DSG 112 can be configured to activate a selected NAND flash memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND flash memory strings 108 in the same block 104 are coupled via a common source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND flash memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the DSG 112 of each NAND flash memory string 108 is coupled to a corresponding bit line 116 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a selection or deselection voltage (e.g., 0V) to the corresponding DSG 112 via one or more DSG lines 113, and / or by applying a selection or deselection voltage (e.g., 0V) to the corresponding SSG 110 via one or more SSG lines 115.

[0046] like Figure 1 As shown, NAND memory strings 108 can be organized into multiple blocks 104, each block 104 may have a common source line 114, for example, the common source line 114 coupled to the ACS. In some implementations, each block 104 is the basic data unit for an erase operation, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and unselected blocks 104 in the same plane as the selected block 104 can be biased with an erase voltage (Vers), which is a high positive voltage (e.g., 20V or higher). In some examples, the erase operation can be performed at the half-block level, quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 106 of adjacent NAND memory strings can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations. Each word line 118 may include multiple control gates (gate electrodes) and gate lines coupled to the control gates at each memory cell 106. Figure 1The example word lines (WL) shown include dummy WL, WL1, WL2, WL3, WL4 and WL5 located between one or more DSG lines 113 and one or more SSG lines 115.

[0047] Figure 2 An example of a side view of a cross-section of a memory cell array 101 including NAND memory strings 108 is shown, according to some aspects of this disclosure. Figure 2 As shown, the NAND memory string 108 can extend vertically through the memory stack 204 above the substrate 202. The substrate 202 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0048] The memory stack 204 may include staggered gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 determines the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 106, DSG 112, or SSG 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between DSG line 113 and SSG line 115.

[0049] Peripheral circuitry 102 can be coupled to memory cell array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 101 by applying voltage and / or current signals to and from each target memory cell in memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some example peripheral circuitry according to certain aspects of this disclosure is shown. The example peripheral circuitry includes a page buffer / sensing amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface 316, and a data bus. In some examples, it may also include... Figure 3 Additional peripheral circuitry not shown.

[0050] Page buffer / sensor amplifier 304 can be configured to read data from and program (write) data to memory cell array 101 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store a page of programming data (write data) to be programmed into a page of memory cell array 101. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been properly programmed into memory cell 106 coupled to selected word line 118. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal from bit line 116 representing data bits stored in memory cell 106 and amplify small voltage swings to a recognizable logic level during read operations. Column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated from voltage generator 310.

[0051] The row decoder / word line driver 308 can be configured, controlled by control logic 312, to select / deselect block 104 of memory cell array 101 and to select / deselect word line 118 of block 104. The row decoder / word line driver 308 can also be configured to drive word line 118 using word line voltage generated from voltage generator 310. In some embodiments, the row decoder / word line driver 308 can also select / deselect and drive SSG line 115 and DSG line 113. The row decoder / word line driver 308 can be configured to apply a read voltage to the selected word line 118 during a read operation on memory cell 106 coupled to the selected word line 118.

[0052] Voltage generator 310 can be configured to be controlled by control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 101.

[0053] Control logic 312 can be coupled to each of the aforementioned peripheral circuits and is configured to control the operation of each peripheral circuit. Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The status register of register 314 may include one or more registers configured to store open block information indicating open blocks (single or multiple) in all blocks 104 of the memory cell array 101, such as a list with an auto dynamic start voltage (ADSV). In some embodiments, the open block information also indicates the last programmed page of each open block.

[0054] Interface 316 can be coupled to control logic 312 and act as a control buffer to buffer and relay control commands received from the host (not shown) to control logic 312 and status information received from control logic 312 to the host. Interface 316 can also be coupled to column decoder / bit line driver 306 via a data bus and serve as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory cell array 101.

[0055] Figure 4 An example circuit 400 for charge pump voltage control is shown. In some embodiments, circuit 400 may be an example of voltage generator 310 in peripheral circuitry 102. Circuit 400 may generate voltages for memory cell array 101, such as word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.).

[0056] In some implementations, circuit 400 includes a charge pump 402, a charge pump output feedback circuit including multiple resistors (e.g., resistors Ra412 and Rb414), a reference voltage generation circuit DAC 420, a comparator 422 (e.g., a second comparator), and a charge pump clock control circuit (e.g., a clock driver) CLK driver 424.

[0057] like Figure 4 As shown, the charge pump 402 in circuit 400 includes multiple charge pumps connected in series, such as CP1 404, CP2 406, and CPN 408. Examples of charge pumps connected in series are also shown in... Figure 5B As shown in the diagram and described later. In some embodiments, charge pump 402 may include multiple charge pumps connected in parallel, such as... Figure 5A As shown and described later, the voltage output of circuit 400 is equal to the voltage output V of the last charge pump CPN 408 in the series-connected charge pump group 402. out The pump output is 410.

[0058] In some implementations, the feedback voltage v fb 416 is the output from the charge pump output feedback circuit and is linearly proportional to the pump output 410, and v fb The ratio of 416 to pump output 410 is controlled by two resistors Ra 412 and Rb 414, as shown in Equation 1.

[0059]

[0060] In some implementations, feedback voltage v can be used. fb 416 and reference voltage v ref The comparison between 418 controls the operating mode of charge pump 402 regarding whether to prevent an increase in pump output 410 (e.g., a second operating mode). Figure 4 Comparator 422 in the code performs the comparison. When v ref 418 is greater than v fb At time 416, the output of comparator 422 is 1, enabling the charge pump clock control circuit CLK driver 424 to output a clock signal pmpclk 426 at a certain frequency, allowing the charge pump 402 to continue increasing the pump output 410, and thus increasing v. fb 416. When v ref 418 equals v fb At time 416, the output of comparator 422 is 0, preventing the switching of clock signal pmpclk 426, and thus preventing charge pump 402 from changing pump output 410, and thus preventing the change of v. fb416. The charge pump operation period may include when v ref 418 is greater than v fb One or more time periods at 416 and when v ref 418 equals v fb One or more time periods at 416. During the charge pump operation period, according to Equation 1, v fb The ratio of 416 to pump output 410 is controlled by two resistors, Ra 412 and Rb 414. In some implementations, when v ref 418 is greater than v fb At time 416, the output of comparator 422 is 0, enabling the charge pump clock control circuit CLK driver 424 to output a clock signal pmpclk 426 at a certain frequency, allowing the charge pump 402 to continue increasing the pump output 410, and thus increasing v. fb 416. When v ref 418 equals v fb At time 416, the output of comparator 422 is 1 and prevents the switching of clock signal pmpclk 426, thus preventing charge pump 402 from changing pump output 410, and thus preventing the change of v. fb 416.

[0061] In some implementations, the reference voltage v ref 418 is output from a reference voltage generation circuit (e.g., a digital-to-analog converter (DAC) 420). An example of a DAC 420 is shown in... Figure 6 As shown and described later. When v ref 418 equals v fb At 416, the pump output is 410 and v ref 418 is linearly proportional, as shown in Equation 2. Therefore, v can be adjusted via the reference voltage generation circuit DAC 420. ref 418 controls the pump output 410. For example, v can be set via the reference voltage generation circuit DAC 420. ref The different increase rates of 418 are used to control the increase rate of pump output 410, such as... Figure 6 As shown and described later.

[0062]

[0063] Figure 5A An example of a charge pump connected in parallel is shown. Figure 5BAn example of a charge pump connected in series is shown. In some implementations, when the charge pump bank provides voltage to support operation in a 3D NAND flash memory, for example, when the charge pump bank provides a bias voltage to an unselected word line in the 3D NAND flash memory during a read operation of a memory cell, the primary load of the charge pump bank comes from a capacitor associated with the gate of the unselected word line, where the capacitance can be several nF. As the output voltage of the charge pump bank increases, the output current of the charge pump bank can charge the capacitor and increase the voltage of the unselected word line gate. Equation 3 shows that the output voltage V of the charge pump bank is proportional to the output current I and time T. Q is the charge in the capacitor due to the charging operation of the charge pump bank. C is the capacitance of the capacitor associated with the gate of the unselected word line.

[0064] Q = CV = IT (3)

[0065] In some implementations, when the output voltage of the charge pump assembly is relatively low, Figure 5A Parallel connection of charge pump assemblies can generate relatively high output current. As the output voltage of the charge pump assemblies continues to increase... Figure 5B The series connection of charge pump groups in the circuit can generate a relatively high output voltage, and the charge pump groups can switch from a parallel connection to a series connection when the output voltage exceeds a threshold (e.g., a switching threshold). In some implementations, when the feedback voltage v fb When 416 exceeds the threshold, the charge pump group can switch from parallel connection to series connection.

[0066] In some implementations, the output current and efficiency of the charge pump group can be changed when the charge pump group is switched from a parallel connection to a series connection. This change occurs when the output voltage V of the charge pump group... out When the current increases, the output current I of the charge pump group out The efficiency of the charge pump group decreases before the decrease, and the efficiency of the charge pump group can be increased before the decrease. Equations 4 and 5 show the output current i of the charge pump group, respectively. out And efficiency η.

[0067]

[0068]

[0069] Figure 6 Example 600 of a reference voltage generation circuit is shown. In some embodiments, the reference voltage generation circuit 600 may be an example of a DAC 420. Figure 6As shown, the reference voltage generation circuit 600 may include an adder 606, a comparator 618 (e.g., a first comparator), a decoder 610, and a digital-to-analog converter 612. The output of the reference voltage generation circuit 600 is a reference voltage v. ref 614, which can be used to control the rate of increase of pump output 410 through circuit 400.

[0070] In some implementations, the inputs to adder 606 may include a step size ΔDAC 602 and a step frequency CK 604, and the output of adder 606 is a digital signal DAC 608. CK 604 can control the sampling time period of adder 606. DAC 608 can be controlled by changing ΔDAC 602 and / or CK 604. For example, DAC 608 can increase by an amount equal to the reciprocal of the step frequency CK 604 in each sampling time period, by an amount equal to ΔDAC 602. DAC 608 then passes through decoder 610, whereby DAC 608 is decoded by decoder 610. The output of decoder 610 then passes through digital-to-analog converter 612, whereby the digital signal output of decoder 610 is converted into an analog signal, i.e., a reference voltage v. ref 614.

[0071] In some implementations, DAC 608 is compared with a target DAC 616 in comparator 618 to control the operating mode (e.g., a first operating mode) of adder 606 regarding whether to prevent increasing DAC 608. For example, when DAC 608 is less than the target DAC 616, comparator 618 outputs signal En 620 to continue the operation of adder 606, thereby increasing DAC 608 based on ΔDAC 602 and CK 604. When DAC 608 is equal to the target DAC 616, comparator 618 outputs signal En 620 to prevent adder 606 from continuing to increase DAC 608. Using circuit 400 and equation 2, v ref 614 can be used to control pump output 410, such as Figure 7 As shown in the diagram and described below.

[0072] Figure 7 An example of pump output 410 is shown. The rate of increase of pump output 410 can be adjusted using ΔV and Δt. ΔV can be controlled by ΔDAC using Equation 2, and Δt can be controlled as the reciprocal of the step frequency CK 604. Figure 7 The diagram shows five reference voltage switching points V0, V1, V2, V3 and V4, where at each of the five switching points, the rate of increase of the pump output 410 changes due to the change of ΔDAC 602 and / or CK 604. Figure 6 The target DAC 616 in the text can be used for control. Figure 7The pump output 410 level at the end of the middle slope 4 segment is the final value of pump output 410. Figure 7 The pump output 410 comprises three segments. The first segment is before the switching point V0 and has a constant voltage Vdd. The second segment is between the switching point V0 and the switching point V4 and includes four sub-segments with corresponding increase rates of the pump output 410, namely, slope1, slope2, slope3, and slope4. The third segment is after the switching point V4 and has a constant voltage greater than Vdd. In some embodiments, at the switching point V1, the increase rate of the pump output 410 can be reduced from slope1 to slope2 by decreasing ΔDAC 602 and thus decreasing ΔV, or by decreasing CK 604 and thus increasing Δt. In some embodiments, the charge pump assembly of the output pump 410 can be positioned before the switching point V2 at a rate such as... Figure 5A The parallel connection shown is used. Because the pump output 410 continues to increase after the switching point V2, the charge pump assembly can switch from a parallel connection to a series connection after the switching point V2, such as... Figure 5B The series connection is shown. In some embodiments, at switching point V3, the rate of increase of pump output 410 can be increased from slope3 to slope4 by increasing ΔDAC 602 and thus increasing ΔV, or by increasing CK 604 and thus decreasing Δt.

[0073] Figure 8 Examples of simulation results for the charge pump output voltage and corresponding peak input current are shown. Curves 1 and 2 show the pump output voltage. Curves 3 and 4 show the corresponding peak input current. Curves 1 and 3 are generated based on a reference voltage with a constant rate of change. Curves 2 and 4 are based on... Figure 6 The reference voltage generated by the circuit is shown. Curve 2 shows that its pump output voltage is lower than that of curve 1 most of the time. Curve 4 shows that its peak input current is lower than that of curve 3. Therefore, Figure 6 The reference voltage generation circuit shown can reduce the peak input current of the charge pump by adjusting the rate of increase of the reference voltage.

[0074] Figure 9 An example flowchart of a method for controlling a charge pump voltage in a storage device according to some aspects of this disclosure is shown. At 902, the peripheral circuitry of the storage device adjusts the rate of change of a reference voltage based on a step voltage and a step time duration, wherein adjusting the rate of change of the reference voltage includes changing the reference voltage over a time period equal to the step time duration, the amount of change being the step voltage.

[0075] In the 904, the peripheral circuitry uses a reference voltage to generate the output voltage from one or more charge pumps, where the ratio between the output voltage and the reference voltage is locked.

[0076] Figure 10 A block diagram of an example system 1000 having a storage device according to some aspects of this disclosure is shown. System 1000 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 10 As shown, system 1000 may include a host 1008 and a storage system 1002 having one or more storage devices 1004 and a memory controller 1006. The host 1008 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 1008 may be configured to send data to or receive data from the storage device 1004.

[0077] Storage device 1004 can be any storage device disclosed herein. According to some embodiments, memory controller 1006 is coupled to storage device 1004 and host 1008 and is configured to control storage device 1004. Memory controller 1006 can manage data stored in storage device 1004 and communicate with host 1008. In some embodiments, memory controller 1006 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 1006 is designed to operate in high duty cycle environments, such as SSDs or embedded multi-media cards (eMMCs), serving as data storage in mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. The memory controller 1006 can be configured to control the operation of the storage device 1004, such as read, erase, and program operations. The memory controller 1006 can also be configured to manage various functions relating to data stored or to be stored in the storage device 1004, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1006 is also configured to process error correction codes (ECCs) relating to data read from or written to the storage device 1004. The memory controller 1006 can also perform any other suitable function, such as formatting the storage device 1004.

[0078] The memory controller 1006 can communicate with external devices (such as the host 1008) according to a specific communication protocol. For example, the memory controller 1006 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.

[0079] The memory controller 1006 and one or more memory devices 1004 can be integrated into various types of storage devices, such as being included in the same package, like a universal flash storage (UFS) package or an eMMC package. That is, the storage system 1002 can be implemented and packaged into different types of end electronic products. Figure 11A In one example shown, the memory controller 1006 and a single storage device 1004 can be integrated into a memory card 1102. The memory card 1102 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a Memory Stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1102 may also include a connection between the memory card 1102 and a host computer (e.g., Figure 10 The memory card connector 1104 is coupled to the host 1008. Figure 11B In another example shown, the memory controller 1006 and multiple storage devices 1004 can be integrated into the SSD 1106. The SSD 1106 may also include a connection between the SSD 1106 and a host (e.g., Figure 10 The SSD connector 1108 is coupled to the host 1008. In some embodiments, the storage capacity and / or operating speed of the SSD 1106 is greater than the storage capacity and / or operating speed of the memory card 1102.

[0080] While this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of possible claims, but rather as descriptions of features that may be specific to particular embodiments. Certain features described in the context of different embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments, individually or in any sub-combination. Furthermore, although previously described features may be described as functioning in certain combinations, and even initially claimed in this way, in some cases, one or more features from the claimed combination may be removed from that combination, and the claimed combination may refer to a sub-combination or a variation of a sub-combination.

[0081] As used in this disclosure, the terms “a,” “an,” or “the” are used to include one or more unless the context clearly specifies otherwise. Unless otherwise stated, the term “or” means a non-exclusive “or.” The statement “at least one of A and B” has the same meaning as “A, B, or A and B.” Furthermore, the wording or terms used in this disclosure (unless otherwise defined) are for descriptive purposes only and not for limitation. The use of any section headings is to aid reading the document and is not to be construed as limiting; information relating to a section heading may appear within or outside that particular section.

[0082] As used in this disclosure, the terms “approximately” or “about” may allow for a degree of variability in the value or range, for example, within 10%, 5%, or 1% of the limits of the value or range.

[0083] As used in this disclosure, the term “substantial” means principally or substantially, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0084] Values ​​expressed in range format should be interpreted flexibly to include not only the values ​​explicitly listed as the limits of the range, but also all individual values ​​or subranges contained within that range, as if each value and subrange were explicitly stated. For example, a range of “0.1% to about 5%” or “0.1% to 5%” should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the range. Unless otherwise stated, the statement “X to Y” has the same meaning as “about X to about Y”. Similarly, unless otherwise stated, the statement “X, Y, or Z” has the same meaning as “about X, about Y, or about Z”.

[0085] Specific embodiments of the subject matter have been described. Other embodiments, modifications, and substitutions of the described embodiments are within the scope of the following claims and will be apparent to those skilled in the art. Although operations are described in a specific order in the drawings or claims, it is not required that these operations be performed in the specific order shown or in a sequential order, or that all illustrated operations be performed (some operations may be considered optional), in order to achieve the desired results. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and performed where deemed appropriate.

[0086] Furthermore, it is not necessary to separate or integrate the various system modules and components described in the previously described embodiments in all implementations, and the described components and systems can often be integrated together or packaged into multiple products.

[0087] Therefore, the exemplary embodiments described above do not limit or restrict this disclosure. Other changes, substitutions, and modifications are possible without departing from the spirit and scope of this disclosure.

Claims

1. A circuit comprising: One or more charge pumps; as well as A reference voltage generation circuit, wherein the reference voltage generation circuit includes an adder configured to adjust the rate of change of the output voltage of one or more charge pumps, wherein the input of the adder includes a step size and a step frequency, and wherein the output of the adder changes over a time period equal to the reciprocal of the step frequency and the amount of change is the step size, to adjust the rate of change of the output voltage.

2. The circuit according to claim 1, wherein, The reference voltage generation circuit further includes a first comparator coupled to the adder, the input of the first comparator including a threshold and the output of the adder, and the output of the first comparator controlling a first operating mode of the adder based on a comparison between the threshold and the output of the adder.

3. The circuit according to claim 1 or 2, wherein, The reference voltage generation circuit also includes a decoder configured to generate an output for decoding the output of the adder.

4. The circuit according to claim 3, wherein, The reference voltage generation circuit further includes a digital-to-analog converter coupled to the output of the decoder, wherein the digital-to-analog converter is configured to convert the decoded output of the adder into a reference voltage as the output of the reference voltage generation circuit.

5. The circuit according to any one of claims 1 to 4, wherein, The reference voltage generation circuit is configured to output a reference voltage based on the output of the adder during a charge pump operation period, and the charge pump operation period includes one or more time periods during which the ratio between the output voltage of the one or more charge pumps and the reference voltage is locked.

6. The circuit according to claim 5, wherein, The reference voltage during the charge pump operation period comprises three consecutive segments, namely a first segment, a second segment, and a third segment. The reference voltage in the first segment is a first constant, and the reference voltage in the third segment is a second constant greater than the first constant.

7. The circuit according to claim 6, wherein, The second segment comprises two or more consecutive sub-segments corresponding to two or more rates of change of the reference voltage.

8. The circuit according to any one of claims 5 to 7, wherein, The circuit also includes a charge pump output feedback circuit configured to output a feedback voltage during the charge pump operation period, wherein the ratio of the feedback voltage to the output voltage of the one or more charge pumps is predetermined during the charge pump operation period.

9. The circuit according to claim 8, wherein, The charge pump output feedback circuit includes multiple resistors.

10. The circuit according to claim 8 or 9, wherein, The circuit further includes a second comparator, the input of which includes the feedback voltage and the reference voltage, and the output of the second comparator controls a second operating mode of the one or more charge pumps based on a comparison between the feedback voltage and the reference voltage.

11. The circuit according to claim 10, wherein, The circuit further includes one or more clock drivers, the input of which is the output of the second comparator, and the one or more clock drivers are configured to provide one or more clock signals to the one or more charge pumps based on the output of the second comparator.

12. The circuit according to any one of claims 1 to 11, wherein, The configuration of the one or more charge pumps includes either a series connection of the one or more charge pumps or a parallel connection of the one or more charge pumps.

13. The circuit according to claim 12, wherein, When the output voltage of the one or more charge pumps is greater than the switching threshold, the configuration of the one or more charge pumps is switched from the parallel connection to the series connection.

14. A method comprising: The rate of change of the reference voltage is adjusted based on the step voltage and the duration of the step time, wherein adjusting the rate of change of the reference voltage includes changing the reference voltage within a time period equal to the duration of the step time, and the amount of change is the step voltage; and An output voltage is generated from one or more charge pumps using the reference voltage, wherein the ratio between the output voltage and the reference voltage is locked.

15. The method according to claim 14, wherein, The configuration of the one or more charge pumps includes a series connection of the one or more charge pumps or a parallel connection of the one or more charge pumps, and the method further includes: Determine that the output voltage of the one or more charge pumps is greater than a switching threshold; and In response to determining that the output voltage of the one or more charge pumps is greater than the switching threshold, the configuration of the one or more charge pumps is switched from the parallel connection to the series connection.

16. The method according to claim 14 or 15, wherein, Adjusting the rate of change of the reference voltage further includes: Determine that the reference voltage is greater than or equal to the voltage threshold; and In response to determining that the reference voltage is greater than or equal to the voltage threshold, the rate of change of the reference voltage is set to zero.

17. The method according to any one of claims 14 to 16, wherein, Adjusting the rate of change of the reference voltage also includes changing the step voltage or changing the duration of the step time.

18. The method according to any one of claims 14 to 17, wherein, The length of the step time duration is the reciprocal of the step frequency, and the rate of change of the reference voltage based on the step voltage and the step time duration includes the rate of change of the reference voltage based on the step voltage and the step frequency.

19. The method according to any one of claims 14 to 18, wherein, Generating the output voltage from the one or more charge pumps based on the reference voltage includes comparing the reference voltage with a feedback voltage to determine the operating mode of the one or more charge pumps, and the ratio of the feedback voltage to the output voltage of the one or more charge pumps is predetermined.

20. A storage device comprising: A storage cell array, comprising storage cells; as well as The circuit includes: One or more charge pumps, operable to provide an output voltage to a word line coupled to one of the memory cells of the memory cell array; and A reference voltage generation circuit, wherein the reference voltage generation circuit includes an adder configured to adjust the rate of change of the output voltage of one or more charge pumps, wherein the input of the adder includes a step size and a step frequency, and wherein the output of the adder changes over a time period equal to the reciprocal of the step frequency and the amount of change is the step size, to adjust the rate of change of the output voltage.

Images