Semiconductor device, operating method thereof, and memory system

Abstract

The invention provides a semiconductor device, an operation method thereof and a storage system. The semiconductor device comprises a mode detection circuit and a charge pump. The mode detection circuit provides a first mode enable signal and a second mode enable signal respectively corresponding to a first state mode and a second state mode of the semiconductor device. The charge pump is respectively in a first action mode for generating a first output current and a second action mode for generating a second output current according to the first mode enable signal and the second mode enable signal; the first state mode includes a same word line access state of memory cells continuously accessed on a same word line. By means of the semiconductor device, the charge pump can be adjusted to be in the standby first action mode, the charge pump can be adjusted to be in the working second action mode only when the word line is switched, high voltage needed by the word line can be maintained, meanwhile, the working current and the refresh frequency of the charge pump can be greatly reduced, and therefore reading power consumption can be greatly reduced.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device, an operating method thereof, and a storage system. Background Art

[0002] Flash memory has the function of data storage, and includes NAND flash memory and NOR flash memory. However, both NAND flash memory and NOR flash memory face the problem of power consumption, which has always been an important indicator of flash memory, especially for mobile devices powered by batteries. In addition, read operation is the most common operation performed by flash memory, so how to reduce read power consumption is an urgent problem to be solved. Summary of the invention

[0003] In view of this, the present application provides a semiconductor device and an operating method thereof, as well as a storage system that can reduce the read power consumption of the semiconductor device and can greatly reduce the refresh frequency.

[0004] In order to solve the above problems, the present application provides a semiconductor device, which includes:

[0005] A mode detection circuit for providing a first mode enable signal and a second mode enable signal respectively corresponding to a first state mode and a second state mode of the semiconductor device; and

[0006] a charge pump, configured to be in a first operation mode for generating a first output current and a second operation mode for generating a second output current respectively according to the first mode enable signal and the second mode enable signal;

[0007] The first state mode includes a same word line access state in which memory cells on the same word line are accessed successively.

[0008] In some embodiments, the second state mode includes an X-word line access state for sequentially accessing memory cells on different word lines.

[0009] In some embodiments, the first state mode also includes a standby state, and the first action mode includes a standby mode.

[0010] In some embodiments, the second state mode includes a working state in which a read instruction is received, and the subsequent access is a subsequent read operation, and the second action mode includes a working mode.

[0011] In some embodiments, the first output current is less than the second output current.

[0012] In some embodiments, the first operation mode generates a first output voltage, the second operation mode generates a second output voltage, and the first output voltage is equal to the second output voltage.

[0013] In some embodiments, the mode detection circuit includes a first mode charge pump detection circuit and a second mode charge pump detection circuit, and a switching selection circuit, wherein the first mode charge pump detection circuit is used to output the first mode enable signal; the second mode charge pump detection circuit is used to output the second mode enable signal; and the switching selection circuit is used to select one of the first mode enable signal and the second mode enable signal to be output to the charge pump according to the first state mode and the second state mode, respectively.

[0014] In some embodiments, the charge pump includes a first sub-charge pump and a second sub-charge pump, the first sub-charge pump is in the first operation mode according to the first mode enable signal; the second sub-charge pump is in the second operation mode according to the second mode enable signal.

[0015] In some embodiments, the charge pump operates at a first refresh frequency and a second refresh frequency in the first operation mode and the second operation mode, respectively, and the first refresh frequency is lower than the second refresh frequency.

[0016] The present application also provides an operating method for a semiconductor device, the operating method comprising:

[0017] providing a first mode enable signal and a second mode enable signal corresponding to a first state mode and a second state mode of the semiconductor device, respectively;

[0018] Setting the same word line access state of a memory cell on the same word line that is accessed successively to the first state mode; and

[0019] According to the first mode enable signal and the second mode enable signal, the charge pump is respectively placed in a first operation mode for generating a first output current and a second operation mode for generating a second output current.

[0020] In some embodiments, the operating method further includes setting an alien word line access state of a memory cell on a different word line that is subsequently accessed to the second state mode.

[0021] In some embodiments, the operating method further includes setting the standby state of the semiconductor device to the first state mode, and setting the charge pump to the first action mode.

[0022] In some embodiments, the operating method further includes setting the working state of receiving the read instruction to the second state mode, and the continuous access is a continuous read operation.

[0023] In some embodiments, the operation method further includes enabling the first operation mode to generate a first output voltage, and enabling the second operation mode to generate a second output voltage, and the first output voltage is equal to the second output voltage.

[0024] In some embodiments, the step of providing a first mode enable signal and a second mode enable signal includes outputting the first mode enable signal and the second mode enable signal to the charge pump through a first mode charge pump detection circuit and a second mode charge pump detection circuit respectively according to the first state mode and the second state mode.

[0025] In some embodiments, the steps of placing the charge pump in a first action mode for generating a first output current and a second action mode for generating a second output current, respectively, include generating the first output current by receiving the first mode enable signal through a first sub-charge pump; and generating the second output current by receiving the second mode enable signal through a second sub-charge pump.

[0026] The present application also provides a memory system, characterized in that it includes: the semiconductor device mentioned above; and a controller configured to control the semiconductor device.

[0027] The semiconductor device and its operation method and storage system provided by the present application are configured to include: a mode detection circuit and a charge pump, wherein the mode detection circuit is used to provide a first mode enable signal and a second mode enable signal respectively corresponding to the first state mode and the second state mode of the semiconductor device; the charge pump is used to be in a first action mode for generating a first output current and a second action mode for generating a second output current respectively according to the first mode enable signal and the second mode enable signal; and the first state mode includes a same word line access state of the storage unit continuously accessed on the same word line. When the area accessed by the internal operation does not need to switch the word line, the charge pump can be adjusted to the first standby action mode, and only adjusted to the second working mode when the word line needs to be switched, so as to maintain the high voltage required by the word line, and at the same time, the working current and refresh frequency of the charge pump can be greatly reduced, thereby greatly reducing the reading power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A schematic block diagram of an exemplary memory disclosed in an embodiment of the present application.

[0030] Figure 2A for Figure 1 A circuit diagram of a storage array in the memory shown.

[0031] Figure 2B for Figure 1 A circuit diagram of another storage array in the memory shown.

[0032] Figure 3 for Figure 1 Schematic block diagram of a voltage generator in the memory shown.

[0033] Figure 4A for Figure 1 Another schematic block diagram of a voltage generator in the memory shown.

[0034] Figure 4B for Figure 1 Yet another schematic block diagram of a voltage generator in the memory is shown.

[0035] Figure 5 The following is an exemplary step diagram of the operating method of the semiconductor device shown in the embodiment of the present application.

[0036] Figure 6 It is a schematic system block diagram of a memory system provided by the present application. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0038] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0039] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0040] First, see Figure 1 , Figure 1 4 shows a schematic block diagram of a semiconductor device using a memory 400 as an exemplary semiconductor device provided by some embodiments of the present application. The memory 400 includes a memory array 420 and other peripheral circuits (not numbered). Figure 1 As shown, the peripheral circuit may include at least other components other than the memory array 420, such as a page buffer / sense amplifier 411, a column decoder / bit line driver 412, a row decoder / word line driver 413, a voltage generator 414, a control logic unit 415, a register 416, an interface 417, and a data bus 418. It should be understood that in some examples, the peripheral circuit may also include components not shown in FIG. Figure 1 Other circuits shown in FIG.

[0041] Figure 1 The block diagram shown can be applied to, for example, a two-dimensional or three-dimensional flash memory type (NAND / NOR flash) or a memory type (DRAM) memory, and the difference lies in the difference in the memory array 420. Therefore, the memory array 420 can be, for example, a memory array of a two-dimensional or three-dimensional flash memory type (NAND / NOR flash) or a memory type (DRAM) memory, and the memory can include DRAM, PCRAM, FeRAM, MRAM, etc. The memory array 420 has at least one large-size block-shaped storage platform (Giant Block, GB), and the storage platform at least includes a plurality of array-arranged storage cells (refer to Figure 2A and Figure 2B The plurality of storage units may be appropriately arranged in accordance with a two-dimensional or three-dimensional structure, or may be appropriately arranged in accordance with a NAND, NOR, or DRAM architecture.

[0042] The page buffer / sense amplifier 411 may be configured to read data from the memory array 420 and program (also referred to as "write") data to the memory array 420 according to a control signal from the control logic unit 415. Specifically, in one example, the page buffer / sense amplifier 411 may store data to be programmed into a memory page of the memory array 420. In another example, the page buffer / sense amplifier 411 may also perform an operation of sensing a low-power signal from the bit line BL representing data stored in a memory cell, and amplify a small voltage swing of the low-power signal to a recognizable logic level in a read operation. The page buffer / sense amplifier 411 may have different arrangements and combinations depending on the type of the memory array 420 and the design of the bit line BL, for example, there may be multiple page buffer / sense amplifiers 411 coordinated with multiple groups of bit line groups.

[0043] The column decoder / bit line driver 412 may be configured to be controlled by the control logic unit 415 and select one or more columns of memory cells by applying the bit line voltage generated by the voltage generator 414. The column decoder / bit line driver 412 may also have different arrangements and combinations in response to different types and designs of the memory array 420, for example, there may be multiple groups of column decoders / bit line drivers 412.

[0044] The row decoder / word line driver 413 may be configured to be controlled by the control logic unit 415 to select different memory cells in the memory array 420. The row decoder / word line driver 413 may also be configured to drive the word line WL using the word line voltage generated by the voltage generator 414. The row decoder / word line driver 413 may also have different arrangements and combinations in response to different types and designs of the memory array 420, for example, there may be multiple groups of row decoders / word line drivers 413.

[0045] Therefore, the voltage generator 414 includes a charge pump, which can be configured to be controlled by the control logic unit 415 and generate the word line voltage and the bit line voltage and the required current to be supplied to the storage array 420. However, it can be understood that the charge pump can be set anywhere in the semiconductor device. Therefore, the so-called voltage generator here broadly includes the charge pump and its related circuits at any location.

[0046] The control logic unit 415 can be coupled to each circuit in the peripheral circuit 410 as described above (e.g., the page buffer / sense amplifier 411, the column decoder / bit line driver 412, the row decoder / word line driver 413, and the voltage generator 414) and control the operation of each circuit.

[0047] The register 416 may be coupled to the control logic unit 415 and may include at least a status register, a command register, and an address register to store status information, a command operation code (OP code), and an address for controlling the operation of each of the above circuits.

[0048] Interface 417 may be coupled to control logic unit 415 and act as a control buffer to perform buffering from Figure 1 The interface 417 is configured to receive a control command received from a controller of the memory array 420 and relay the command to the control logic unit 415, and to perform an operation of buffering status information received from the control logic unit 415 and relaying the command to an external controller (not shown). Furthermore, the interface 417 may also be coupled to the column decoder / bit line driver 412 via a data bus 418, and act as a data I / O (Input / Output) interface and a data buffer to perform an operation of buffering data and relaying the data to the memory array 420, and to perform an operation of relaying or buffering data from the memory array 420.

[0049] In some embodiments, the storage array 420 may be a NOR or NAND flash memory architecture, or a 1T1C or 1TXC memory architecture (T represents transistor, C represents capacitor storage unit, and X represents quantity). In addition, the storage array may be a 2D architecture or a 3D architecture, so the embodiments of the present application are only examples.

[0050] Figure 2A A circuit diagram of a NOR type memory array is shown. The figure only illustrates a memory array composed of three rows of word lines and eight columns of bit lines, that is, the word lines include word lines Word1 / Word2 / Word3, and the bit lines include bit lines Bit0 / Bit1 / Bit2 / Bit3 / Bit4 / Bit5 / Bit6 / Bit7. However, it can be understood that the number of word lines and bit lines can be determined according to the storage capacity of the memory. One bit line represents one bit. Bit0 to Bit7 in the figure have a total of 8 bits, representing one byte. One word line represents one storage page. If a storage page has a capacity of 1KB, it must have 1024 bytes, that is, 1024x8 bit lines. If you want a capacity of 1MB, you can, for example, configure 1024 word lines to form 1024 storage pages, that is, 1024 KB. Therefore, Figure 2A The storage unit configuration is only an exemplary description.

[0051] During the read operation, after the data enters through the interface 417, the command information and address information will be sent to the control logic unit 415, and the control logic unit 415 will decode the address information through the row decoder 413 and the column decoder 412 to obtain the word line and bit line corresponding to the address, and locate the position of the storage cell 42a to be read, such as the word line Word1, and the bit lines Bit0 to Bit7 to be read in sequence, and then the sense amplifier 411 will read out the data of this byte in sequence. It can be understood that different read addresses may appear on the same word line, but on the bit lines of different bytes.

[0052] Figure 2B A circuit diagram of a NAND type memory array is shown. The figure only illustrates a memory array composed of 8 rows of word lines and 8 columns of bit lines, that is, the word lines include word lines Word1 to Word8, and the bit lines include bit lines Bit1 to Bit8. However, it can be understood that the number of word lines and bit lines, like NOR flash memory, can be determined according to the storage capacity of the memory. One bit line represents one bit. Bit1 to Bit8 in the figure have a total of 8 bits, representing one byte. One word line represents one storage page. If a storage page has a capacity of 1KB, it must have 1024 bytes, that is, 1024x8 bit lines. If you want a capacity of 1MB, you can, for example, configure 1024 word lines to form 1024 storage pages, that is, 1024 KB. Therefore, Figure 2B The storage unit configuration is only an exemplary description.

[0053] The architecture of other storage arrays may also be a 2D or 3D memory architecture, which is known to those skilled in the art and will not be described in detail herein, nor is it intended to limit the scope of application of the present application. As long as the technical concept of the present application can be applied, it is within the scope of the present application. Therefore, in the following embodiments, only a 2D NOR flash memory architecture is used as an example, but this does not mean that the present application is limited to a 2D NOR flash memory architecture.

[0054] Power consumption is an important indicator for various memories, especially for Nor flash, and even more so for battery-powered mobile devices. Read operations are the most common operations performed by Nor flash, so how to reduce read power consumption is an urgent problem to be solved.

[0055] When the Nor flash is in standby mode, the control logic unit 415 generates a voltage higher than the power supply through the charge pump in the voltage generator 414 in the standby mode, and periodically refreshes the charge pump that outputs the working voltage through a clock signal with a specific frequency, switches and capacitors. When the user inputs a read command, the charge pump in the standby mode is turned off, and the charge pump in the working mode starts working, and generates and maintains the same voltage as in the standby mode. The working current of the charge pump in the working mode is much larger than that of the charge pump in the standby mode, and the refresh frequency of the charge pump in the working mode is also much faster than that of the charge pump in the standby mode, which greatly increases the power consumption of the circuit. The working mode here can be understood to represent when a specific operation is performed, such as reading or programming, and the working current represents the output current under a specific operation, especially the maximum output current.

[0056] In order to solve the problem of power consumption, Figure 3 A schematic block diagram of a semiconductor device according to an embodiment of the present application is disclosed, and the aforementioned voltage generator 414 is taken as an example of the semiconductor device.

[0057] like Figure 3 As shown, the semiconductor device formed according to the embodiment of the present application includes: a mode detection circuit 10 and a charge pump 20; wherein the mode detection circuit 10 is used to provide a first mode enable signal E1 and a second mode enable signal E2 respectively corresponding to the first state mode M1 and the second state mode M2 ​​of the semiconductor device; and the charge pump 20 is used to be in a first action mode for generating a first output current I1 and a second action mode for generating a second output current I2 respectively according to the first mode enable signal E1 and the second mode enable signal E2; and wherein the first state mode M1 includes a same-word line access state of continuously accessing a storage unit 42a on the same word line.

[0058] In some embodiments, the second state mode M2 ​​includes an X-word line access state in which memory cells 42 a on different word lines are accessed successively.

[0059] In some embodiments, the first state mode M1 also includes a standby state, and the first action mode includes a standby mode.

[0060] In some embodiments, the second state mode M2 ​​includes a working state in which a read instruction is received, and the subsequent access is a subsequent read operation, and the second action mode includes a working mode.

[0061] In some embodiments, the first output current I1 is less than the second output current I2. Here, the first output current refers to the maximum current output value in the first operation mode, and does not represent a constant current value. Those skilled in the art can understand that this is mainly to express that in the first operation mode, the charge pump has a smaller maximum output current and power consumption than in the second operation mode.

[0062] In some embodiments, the charge pump 20 operates at a first refresh frequency and a second refresh frequency according to the first mode enable signal E1 and the second mode enable signal E2 , respectively, and the first refresh frequency is lower than the second refresh frequency.

[0063] Specifically, the mode detection circuit 10 can receive the state of the memory 400 provided by the state logic (not shown) in the control logic unit 415 or the register 416, and detect what state the memory 400 is in. For example, if it is in the standby state waiting to receive a command, the mode detection circuit 10 sets it to the first state mode M1 and outputs the first mode enable signal E1. It can be understood that in some embodiments, the mode detection circuit 10 can receive the first state mode signal M1 without detecting it to know which state mode it is.

[0064] If the control logic unit 415 receives a read command, the state of the memory 400 provided by the state logic (not shown) in the control logic unit 415 or the register 416 will be a read state, and a voltage setting instruction will be sent to the voltage generator 414, and the address information will be sent to the row decoder 413 and the column decoder 412. At this time, after the mode detection circuit 10 receives the voltage setting instruction or the read state provided by the state logic, it can set the state mode of the memory / semiconductor device to the second state mode M2 ​​and output the second mode enable signal E2. It can also be understood that in some embodiments, the mode detection circuit 10 can receive the second state mode signal M2 without having to detect it before knowing which state mode it is.

[0065] Furthermore, if the control logic unit 415 can further determine the word line position of the address after receiving the first address information of the read command, and when receiving the next address information, determine whether the word line position of the next address information has changed, if not, a first mark information is given, and the mode detection circuit 10 receives the first mark information and outputs the first mode enable signal E1. If the word line has changed, a second mark information is given, and the mode detection circuit 10 receives and detects the second mark information and outputs the second mode enable signal E2.

[0066] The above embodiment is an exemplary example of the control logic unit 415 detecting whether the word line has changed, but this detection can also be set to be performed in the mode detection circuit 10, which is not limited here. Therefore, in some embodiments, the mode detection circuit 10 can receive the first or second state mode signal M1 / M2 and be in the first mode detection circuit or the second mode detection circuit. In some embodiments, the mode detection circuit 10 can detect the first or second state mode signal M1 / M2 and be in the first mode detection circuit or the second mode detection circuit.

[0067] Furthermore, in some embodiments, the mode detection circuit 10 is further used to detect the output voltage and output current of the charge pump 20 to determine whether the output of the charge pump 20 meets the requirements. For example, the mode detection circuit 10 may include an output voltage feedback circuit and a comparator (not shown) to detect whether the output of the charge pump 20 meets the requirements and further send an enable signal.

[0068] Then, after receiving the first mode enable signal E1 or the second mode enable signal E2 from the mode detection circuit 10, the charge pump 20 is in a first operation mode for generating a first output current I1 and a second operation mode for generating a second output current I2 according to the first mode enable signal E1 and the second mode enable signal E2. It can be understood that the voltage generator 414 sends the output to the word line decoded by the row decoder 413 through the charge pump 20, so that the row decoder 413 can output the required output voltage and current from the selected word line.

[0069] Specifically, when the word line is changed, that is, the access of the different word line belongs to the second state mode M2 ​​of the general operation, the charge pump 20 will receive the second mode enable signal E2 and operate in the second action mode, and provide a larger current to charge the new word line. If the word line is not changed, that is, the access of the same word line is set to special operation and is set to the first state mode M1, the charge pump 20 will receive the first mode enable signal E1 and operate in the first action mode, providing a smaller output current to reduce power consumption. At this time, since the same word line has been powered, providing a relatively small current can meet the needs.

[0070] In some embodiments, the charge pump 20 may also be in a first operation mode for generating a first output voltage V1 and a second operation mode for generating a second output voltage V2 according to the first mode enable signal E1 and the second mode enable signal E2, and the first output voltage V1 is equal to the second output voltage V2. It can be understood that the charge pump 20 is controlled by the mode detection circuit 10, and the actual voltage waveform provided is a sawtooth shape, and the equal voltage value here refers to the equal voltage target value.

[0071] Furthermore, it is understandable that the charge pump 20 generates the first action mode and the second action mode of different currents according to the first mode enable signal E1 and the second mode enable signal E2, respectively. In some embodiments, the charge pump 20 can operate at the first refresh frequency F1 and the second refresh frequency F2 corresponding to the first action mode and the second action mode, respectively, and the first refresh frequency F1 is lower than the second refresh frequency F2. It is understandable that the load supplied by the charge pump 20, such as a storage array, may have leakage. Therefore, after a period of time, in order to maintain the required output voltage and output current, the output voltage of the charge pump must be increased to meet the required output current. The refresh frequency is the frequency of periodically increasing the output voltage of the charge pump through a clock signal with a specific frequency, and switching switches and capacitors to make the output voltage reach the target value.

[0072] Through the semiconductor device shown in the embodiment of the present application, since the Nor flash reads the data in the storage array sequentially, when the area accessed by the internal read operation does not need to switch the word line, the charge pump can be adjusted to the first action mode to supply the demand with a lower current. It is only adjusted to the working mode when the word line needs to be switched to maintain the high voltage required by the word line. At the same time, the working current of the charge pump (that is, the output current sent to the word line during specific operations such as reading or standby) and the refresh frequency can also be greatly reduced, thereby greatly reducing the read power consumption.

[0073] Furthermore, although the above description uses the read operation as an example, it is understandable that the operation described in the present application may be other operations other than the read operation, such as a programming operation, etc., as long as it involves bias switching of different word lines.

[0074] The structure of the semiconductor device according to the embodiment of the present application is further described below. Figure 4A As shown, Figure 4A for Figure 3 Another schematic block diagram of a voltage generator in the memory shown. Figure 4A The semiconductor device 400 or voltage generator 414 a shown includes a mode detection circuit 10 a and a charge pump 20 . The mode detection circuit 10 a further includes a first mode charge pump detection circuit 11 , a second mode charge pump detection circuit 12 , and a switch selection circuit 13 .

[0075] Specifically, in some embodiments, the first mode charge pump detection circuit 11 can be as follows: Figure 4A As shown in FIG. 1 , the charge pump detection circuit 12 starts to work by receiving the standby state provided by the state logic (not shown) in the control logic unit 415 or the register 416, or the first flag information, and using these signals as the first state mode signal M1. Figure 4AThe device receives the read status provided by the status logic (not shown) in the control logic unit 415 or the register 416, or the second flag information, and uses these signals as the second status mode M2 ​​to start working.

[0076] In some embodiments, the first mode charge pump detection circuit 11 and the second mode charge pump detection circuit 12 respectively send out the first mode enable signal E1 and the second mode enable signal E2; and can send out a control signal (not shown) to the switch selection circuit 13 to control the closing and conducting or opening and disconnection of the switch S1 and the switch S2. In other embodiments, the switch selection circuit 13 can accept the control from the control logic unit 415 to respectively conduct or close the selection switch S1 or S2.

[0077] In the standby mode as the first state mode M1, the switch S1 is closed, the switch S2 is open, the first mode charge pump detection circuit 11 works normally, and the second mode charge pump detection circuit 12 is turned off. The first mode charge pump detection circuit 11 controls the charge pump through the first enable signal E1, so that the charge pump 20 generates and maintains a voltage higher than the power supply voltage, such as V1, and generates the first current I1.

[0078] When a read instruction is input, the second state mode M2 ​​is entered, the switch S2 is closed, the switch S1 is opened, the second mode charge pump detection circuit works normally, and the first mode charge pump detection circuit 11 is turned off. The second mode charge pump detection circuit 12 controls the charge pump 20 through the second enable signal E2, so that the charge pump 20 generates and maintains a voltage V2 higher than the power supply voltage, and generates the second current I2 for driving the word line corresponding to the input read instruction address.

[0079] When each read operation is completed, it is determined whether the next read address needs to switch the word line. If the word line needs to be switched, the second mark signal is generated, the second state mode M2 ​​is entered, the switch S2 is closed, the switch S1 is disconnected, the second mode charge pump detection circuit 12 works normally, and the second enable signal E2 controls the charge pump so that the charge pump 20 can quickly respond to the output voltage of the charge pump 20 to meet the requirements of the next read data for establishing the word line voltage; if the word line does not need to be switched, the first mark signal is generated, the first state mode M1 is entered, the switch S1 is closed, the switch S2 is disconnected, the first mode charge pump detection circuit 11 works normally, and the first enable signal E1 is sent to control the charge pump so that the charge pump 20 provides sufficient driving force to the same word line corresponding to the input read instruction address. With such a setting, since the first mode charge pump detection circuit 11 can operate at a lower response speed than the second mode charge pump detection circuit 12, the charge pump 20 will be started less frequently, thereby reducing the operating current of the entire detection circuit. At the same time, the refresh frequency of the charge pump can be greatly reduced because it can operate in the first action mode at an appropriate time, thereby greatly reducing the reading power consumption.

[0080] In some embodiments, the first output voltage V1 is equal to the second output voltage V2. It is understood that the charge pump 20 is controlled by the first or second mode charge pump detection circuit 11 / 12, and the actual voltage waveform provided is sawtooth shaped, and the equal voltage value here refers to the equal voltage target value.

[0081] Figure 4B Another semiconductor device according to an embodiment of the present application is further shown. Figure 4B As shown, Figure 4B for Figure 3 Another schematic block diagram of a voltage generator in the memory shown. Figure 4B The semiconductor device or voltage generator 414 b shown includes a mode detection circuit 10 and a charge pump 20 b ; wherein the charge pump 20 b further includes a first sub-charge pump 21 and a second sub-charge pump 22 .

[0082] Compare Figure 3 and 4B , understandable, Figure 4B The mode detection circuit 10 and Figure 3 It is the same as the mode detection circuit 10 of FIG. 1 , and will not be described again. It can be understood that the mode detection circuit 10 generates the first mode enable signal E1 and the second mode enable signal E2 in response to the various different states described above.

[0083] It is understood that in some embodiments, Figure 4B The mode detection circuit 10 can also be used with Figure 4AIn this configuration, the first mode detection circuit 11 is connected to the first sub-charge pump 21 through the switch S1; the second mode detection circuit 12 is connected to the second sub-charge pump 22 through the switch S2.

[0084] exist Figure 4B In the embodiment, the charge pump 20b includes a first sub-charge pump 21 and a second sub-charge pump 22. The first sub-charge pump 21 and the second sub-charge pump 22 are in a first operation mode for generating a first output voltage V1 and a first output current I1, and a second operation mode for generating a second output voltage V2 and a second output current I2, respectively, according to the first mode enable signal E1 and the second mode enable signal E2. The first sub-charge pump 21 can be regarded as a charge pump in a standby mode, and the second sub-charge pump 22 can be regarded as a charge pump in a normal working mode. In this way, in the standby mode or in a special reading working mode where the word line does not change, the first sub-charge pump 21 in the standby mode can be used to provide bias voltage and current to the word line; and in the normal reading mode or when the word line changes, the second sub-charge pump 22 in the working mode can be used to provide bias voltage and current to the word line.

[0085] Since Nor flash reads data in the storage array sequentially, when the area accessed by the internal read operation does not need to switch the word line, the second sub-charge pump 22 in the working mode can be turned off and the first sub-charge pump 21 in the standby mode can be turned on to maintain the high voltage required by the word line, thereby greatly reducing the reading power consumption.

[0086] Compared with the semiconductor device exemplified by the memory above, the embodiment of the present application further provides an operating method of the semiconductor device, such as Figure 5 As shown, Figure 5 An exemplary step diagram of a method for operating a semiconductor device according to an embodiment of the present application is shown.

[0087] The operating method of the semiconductor device formed according to the embodiment of the present application includes: providing a first mode enable signal E1 and a second mode enable signal E2 (S11) corresponding to the first state mode M1 and the second state mode M2 ​​of the semiconductor device 400 respectively; setting the same word line access state of a storage unit 42a on the same word line that is subsequently accessed to the first state mode M1 (S12); and, according to the first mode enable signal E1 and the second mode enable signal E2, respectively placing the charge pump 20 in a first action mode for generating a first output current I1 and a second action mode for generating a second output current I2 (S13).

[0088] In some embodiments, the operation method further includes: setting the different word line access state of a memory cell 42a that subsequently accesses a different word line to the second state mode M2.

[0089] In some embodiments, the operating method further includes: setting the standby state of the semiconductor device to the first state mode M1, and setting the charge pump to the first action mode.

[0090] In some embodiments, the operation method further includes: setting the working state of receiving the read instruction to the second state mode M2, and the continuous access is a continuous read operation.

[0091] In some embodiments, the first output current I1 is less than the second output current I2.

[0092] In some embodiments, the operation method further includes enabling the first operation mode to generate a first output voltage V1 , enabling the second operation mode to generate a second output voltage V2 , and the first output voltage V1 is equal to the second output voltage V2 .

[0093] In some embodiments, the step of providing a first mode enable signal E1 and a second mode enable signal E2 includes: outputting the first mode enable signal E1 and the second mode enable signal E2 through a first mode charge pump detection circuit 11 and a second mode charge pump detection circuit 12 respectively according to the first state mode M1 and the second state mode M2; and then selecting one of the first mode enable signal E1 and the second mode enable signal E2 through a switching selection circuit 13 to output to the charge pump 20.

[0094] In some embodiments, the steps of respectively placing the charge pump in a first action mode for generating a first output current and a second action mode for generating a second output current include: generating the first output current I1 by receiving the first mode enable signal E1 through the first sub-charge pump 21; and generating the second output current I2 by receiving the second mode enable signal E2 through the second sub-charge pump 22.

[0095] Through the operation method of the semiconductor device shown in the embodiment of the present application, since the Nor flash reads the data in the storage array sequentially, when the area accessed by the internal read operation does not need to switch the word line, the charge pump can be adjusted to the standby mode, and only adjusted to the general working mode when the word line needs to be switched to maintain the high voltage and current required by the word line. Through such a setting, the refresh frequency of the charge pump can also be greatly reduced, thereby greatly reducing the read power consumption.

[0096] Finally, see Figure 6 , Figure 6 A schematic block diagram of an exemplary electronic system 100 having a memory system 110 according to some embodiments of the present application is shown. The electronic system 100 may be, for example, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0097] like Figure 6 As shown, the electronic system 100 may include at least a storage system 110 and a host 120, wherein the storage system 110 has a controller 111 and one or more memories 112. The memory 112 may be the semiconductor device 400 as described above, and the host 120 may be a processor (e.g., a central processing unit, CPU) or a system on a chip (SoC) (e.g., an application processor, AP) of an electronic device. Specifically, the host 120 may be configured to send data to the memory 112, or to receive data from the memory 112.

[0098] According to some embodiments, the controller 111 is coupled to the memory 112 and the host 120 and is configured to control the memory 112. Further, the controller 111 can manage the data stored in the memory 112 and communicate with the host 120. In some embodiments, the controller 111 is designed to operate in a low duty cycle environment, which can be a Universal Serial Bus (USB) flash drive or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0099] The controller 111 may communicate with an external device (e.g., the host 120) according to a specific communication protocol. For example, the controller 111 may communicate with an external device through at least one of various interface protocols, and the interface protocol may be, for example, a universal serial bus (USB) protocol, a multimedia (Multi Media Card, MMC) protocol, a peripheral component interconnect (Peripheral Component Interconnect, PCI) protocol, a high-speed PCI (Peripheral Component Interconnect Express, PCI-E) protocol, an advanced technology attachment (Advanced Technology Attachment, ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (Small Computer System Interface, SCSI) protocol, an enhanced small disk interface (Enhanced Small Device Interface, ESDI) protocol, an integrated drive electronics (Integrated Drive Electronics, IDE) protocol, and a FireWire protocol.

[0100] Some embodiments of the present application provide a storage system having the same beneficial effects as the above-mentioned memory 112 or semiconductor device 400. .

[0101] The semiconductor device and its operation method and memory system provided by the present application are configured to include: a mode detection circuit and a charge pump, wherein the mode detection circuit is used to provide a first mode enable signal and a second mode enable signal respectively corresponding to the first state mode and the second state mode of the semiconductor device; the charge pump is used to be in a first action mode for generating a first output current and a second action mode for generating a second output current respectively according to the first mode enable signal and the second mode enable signal; and the first state mode includes a same word line access state of the storage unit continuously accessed on the same word line. When the area accessed by the internal operation does not need to switch the word line, the charge pump can be adjusted to the standby mode, and only adjusted to the working mode when the word line needs to be switched, so as to maintain the high voltage required by the word line, and at the same time, the working current and refresh frequency of the charge pump can be greatly reduced, thereby greatly reducing the reading power consumption.

[0102] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A mode detection circuit for providing a first mode enable signal and a second mode enable signal respectively corresponding to a first state mode and a second state mode of the semiconductor device; and a charge pump, configured to be in a first operation mode for generating a first output current and a second operation mode for generating a second output current respectively according to the first mode enable signal and the second mode enable signal; The first state mode includes a same word line access state in which memory cells on the same word line are accessed successively.

2. The semiconductor device according to claim 1, wherein The second state mode includes an X-word line access state for sequentially accessing memory cells on different word lines.

3. The semiconductor device according to claim 1, wherein The first state mode also includes a standby state, and the first operation mode includes a standby mode.

4. The semiconductor device according to claim 1, wherein The second state mode includes a working state in which a read instruction is received, the continuous access is a continuous read operation, and the second action mode includes a working mode.

5. The semiconductor device according to claim 1, wherein: The first output current is smaller than the second output current.

6. The semiconductor device according to claim 1, wherein: The first action mode generates a first output voltage, the second action mode generates a second output voltage, and the first output voltage is equal to the second output voltage.

7. The semiconductor device according to claim 1, wherein: The charge pump operates at a first refresh frequency and a second refresh frequency in the first operation mode and the second operation mode, respectively, and the first refresh frequency is lower than the second refresh frequency.

8. The semiconductor device according to claim 1, wherein The mode detection circuit includes a first mode charge pump detection circuit and a second mode charge pump detection circuit, and a switching selection circuit; the first mode charge pump detection circuit is used to output the first mode enable signal; the second mode charge pump detection circuit is used to output the second mode enable signal; the switching selection circuit selects one of the first mode enable signal and the second mode enable signal to be output to the charge pump according to the first state mode and the second state mode respectively.

9. The semiconductor device according to claim 1, wherein: The charge pump includes a first sub-charge pump and a second sub-charge pump. The first sub-charge pump is in the first operation mode according to the first mode enable signal. The second sub-charge pump is in the second operation mode according to the second mode enable signal.

10. A method for operating a semiconductor device, characterized in that: The operation method comprises: providing a first mode enable signal and a second mode enable signal corresponding to a first state mode and a second state mode of the semiconductor device, respectively; Setting the same word line access state of a memory cell on the same word line that is accessed successively to the first state mode; and According to the first mode enable signal and the second mode enable signal, the charge pump is respectively placed in a first operation mode for generating a first output current and a second operation mode for generating a second output current.

11. The method for operating a semiconductor device according to claim 10, wherein: The operation method further includes: setting an access state of a different word line of a memory cell that is subsequently accessed on a different word line to the second state mode.

12. The method for operating a semiconductor device according to claim 10, wherein: The operating method further includes setting the standby state of the semiconductor device to the first state mode, and setting the charge pump to the first operation mode.

13. The method for operating a semiconductor device according to claim 10, wherein: The operation method further includes: setting the working state of receiving the read instruction to the second state mode, and the continuous access is a continuous read operation.

14. The method for operating a semiconductor device according to claim 10, wherein: The first output current is smaller than the second output current.

15. The method for operating a semiconductor device according to claim 10, wherein: The operation method further includes enabling the first action mode to generate a first output voltage, and enabling the second action mode to generate a second output voltage, wherein the first output voltage is equal to the second output voltage.

16. The method for operating a semiconductor device according to claim 10, wherein: The step of providing a first mode enable signal and a second mode enable signal includes outputting the first mode enable signal and the second mode enable signal to the charge pump through a first mode charge pump detection circuit and a second mode charge pump detection circuit respectively according to the first state mode and the second state mode.

17. The semiconductor device according to claim 10, wherein: The steps of respectively placing the charge pump in a first action mode for generating a first output current and a second action mode for generating a second output current include: generating the first output current by receiving the first mode enable signal through the first sub-charge pump; and generating the second output current by receiving the second mode enable signal through the second sub-charge pump.

18. A memory system, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 9; as well as A controller is configured to control the semiconductor device.

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