Flash memory type storage and calculation integrated circuit, error elimination method for flash memory type storage and calculation integrated circuit, and medium

Abstract

The invention provides a flash memory type storage and calculation integrated circuit, an error elimination method of the flash memory type storage and calculation integrated circuit and a medium, the flash memory type storage and calculation integrated circuit comprises a plurality of flash memory transistors, and the flash memory transistors have a short channel effect, so that the current of the flash memory transistors in a saturation region is not in a saturation state any more; the non-linear error of the flash memory type storage and calculation integrated circuit can be reduced by directly utilizing the short channel effect of the plurality of flash memory transistors, so that the calculation precision of the flash memory type storage and calculation integrated circuit is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a flash memory type storage-computing integrated circuit, an error elimination method for the flash memory type storage-computing integrated circuit, and a medium. Background Art

[0002] The flash memory type storage and computing integrated circuit includes multiple flash memory transistors, which are connected by input wires and output wires. A voltage can be input from the input wires to turn on the flash memory transistors, and then a voltage or current can be output from the output wires.

[0003] There is a multiplication relationship between the voltage or current output by the output wire and the voltage input by the input wire. However, since the current-voltage relationship of the flash memory transistor does not follow the linear relationship of the standard resistor, but has a nonlinear relationship, the above multiplication relationship has a nonlinear error, that is, the flash memory type storage and computing integrated circuit has a nonlinear error.

[0004] Since the flash memory type storage and computing integrated circuit has nonlinear errors, the calculation accuracy of the flash memory type storage and computing integrated circuit is reduced. Therefore, there is currently a demand to reduce the nonlinear errors of the flash memory type storage and computing integrated circuit and improve the calculation accuracy. Summary of the invention

[0005] In view of this, the purpose of the present application is to provide a flash memory type storage and computing integrated circuit, an error elimination method and a medium for the flash memory type storage and computing integrated circuit, which can reduce the nonlinear error of the flash memory type storage and computing integrated circuit and improve the calculation accuracy.

[0006] The present application provides a flash memory type storage and computing integrated circuit, the flash memory type storage and computing integrated circuit comprising a plurality of flash memory transistors;

[0007] The flash memory transistor has a short channel effect, and the short channel effect of multiple flash memory transistors is used to reduce the nonlinear error of the flash memory type storage and computing integrated circuit.

[0008] Optionally, the flash memory transistor comprises a channel;

[0009] The channel length of the flash memory transistor is less than a length threshold.

[0010] Optionally, the flash memory transistor comprises a channel, an insulating layer and a gate, and the insulating layer is arranged between the channel and the gate;

[0011] The thickness of the insulating layer is greater than a thickness threshold.

[0012] Optionally, the flash memory transistor comprises a channel, an insulating layer and a gate, and the insulating layer is arranged between the channel and the gate;

[0013] The dielectric constant of the material of the insulating layer is less than a dielectric constant threshold.

[0014] Optionally, the flash memory transistor comprises a channel, a source and a drain, and the channel is located between the source and the drain;

[0015] The source electrode and the drain electrode partially overlap the channel, respectively.

[0016] Optionally, an overlapping area where the source and the drain overlap the channel portion respectively is greater than an overlapping area threshold.

[0017] Optionally, the overlapping areas of the source and the drain respectively overlapping with the channel portion are controlled by controlling the ion implantation intensity, ion implantation composition, ion diffusion temperature or ion diffusion time when forming the source or the drain.

[0018] Optionally, the area of ​​the flash memory type storage and computing integrated circuit is smaller than a circuit area threshold.

[0019] The present application provides a method for eliminating errors in a flash memory type storage and computing integrated circuit, characterized in that the method is applied to any one of the flash memory type storage and computing integrated circuits described above, and comprises:

[0020] Inputting a set of input vectors into the flash memory type storage and computing integrated circuit, wherein the input vectors include a plurality of voltage values;

[0021] A set of actual output vectors output by the flash memory type integrated storage and computing circuit is obtained, wherein the actual output vectors are calculated using a storage weight matrix and the input vectors, the storage weight matrix is ​​related to the short channel effect of the flash memory transistor, and the nonlinear error between the actual output vector and the ideal output vector is less than an error threshold.

[0022] The present application provides a computer-readable medium, characterized in that it includes instructions, which, when executed on a computer, enable the computer to execute the method described above.

[0023] The present application provides a flash memory type storage and computing integrated circuit, which includes multiple flash memory transistors. The flash memory transistors have a short channel effect, so that the current of the flash memory transistor in the saturation region is no longer in a saturated state, but continues to increase with the increase of the input voltage to reduce the nonlinear error. The short channel effect of the multiple flash memory transistors can be directly used to reduce the nonlinear error of the flash memory type storage and computing integrated circuit, thereby improving the calculation accuracy of the flash memory type storage and computing integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of an ideal current-voltage relationship provided in an embodiment of the present application is shown;

[0026] Figure 2 A schematic diagram of an actual current-voltage relationship provided in an embodiment of the present application is shown;

[0027] Figure 3 A schematic diagram of the structure of a flash memory storage and computing integrated circuit provided in an embodiment of the present application is shown;

[0028] Figure 4 A schematic diagram showing the current-voltage relationship of a flash memory transistor with a short channel effect provided in an embodiment of the present application is shown;

[0029] Figure 5 A schematic cross-sectional structure diagram of a flash memory transistor provided in an embodiment of the present application is shown;

[0030] Figure 6 A schematic cross-sectional structure diagram of another flash memory transistor provided in an embodiment of the present application is shown;

[0031] Figure 7 A schematic cross-sectional structure diagram of another flash memory transistor provided in an embodiment of the present application is shown;

[0032] Figure 8 A flow chart of an error elimination method for a flash memory type integrated storage and computing circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0035] The flash memory type storage and computing integrated circuit includes multiple flash memory transistors, which are connected by input wires and output wires. A voltage can be input from the input wires to turn on the flash memory transistors, and then a voltage or current can be output from the output wires.

[0036] There is a multiplication relationship between the voltage or current output by the output wire and the voltage input by the input wire, and the multiplication relationship includes storing the weight matrix W ij , i and j are the dimensions of the weight matrix. The input voltage is calculated using X i Indicates that i is the number of input voltage values, and the output voltage or current is calculated using Y j Indicates that j is the number of output voltage or current values, then the multiplication relationship can be expressed as Y ij =∑ i X i W ij .

[0037] refer to Figure 1 As shown, it is a schematic diagram of an ideal current-voltage relationship. In an ideal case, the storage weight matrix W ij is the reciprocal of resistance 1 / R and is the slope of the current-voltage curve. Figure 1 It can be seen that the current-voltage relationship of different storage weights is different.

[0038] However, since the current-voltage relationship of the flash memory transistor does not follow the linear relationship of the standard resistor, but has a nonlinear relationship, the above multiplication relationship has a nonlinear error, that is, the flash memory storage and computing integrated circuit has a nonlinear error.

[0039] refer to Figure 2 As shown, this is a schematic diagram of an actual current-voltage relationship. Figure 2 The dashed line in the middle is the linear relationship between current and voltage of the standard resistor. Figure 2 The solid line in the middle is the nonlinear relationship between current and voltage. Figure 2 It can be seen that the storage weights with larger values ​​are less affected by the nonlinear error, while the storage weights with smaller values ​​are more affected by the nonlinear error.

[0040] Since the flash memory type storage and computing integrated circuit has nonlinear errors, the calculation accuracy of the flash memory type storage and computing integrated circuit is reduced. Therefore, there is currently a demand to reduce the nonlinear errors of the flash memory type storage and computing integrated circuit and improve the calculation accuracy.

[0041] Based on this, an embodiment of the present application provides a flash memory type storage and computing integrated circuit, which includes multiple flash memory transistors. The flash memory transistors have a short channel effect, so that the current of the flash memory transistor in the saturation region is no longer in a saturated state, but continues to increase with the increase of the input voltage to reduce the nonlinear error. The short channel effect of multiple flash memory transistors can be directly used to reduce the nonlinear error of the flash memory type storage and computing integrated circuit, thereby improving the calculation accuracy of the flash memory type storage and computing integrated circuit.

[0042] In order to better understand the technical solution and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0043] See also Figure 3 , which is a structural schematic diagram of a flash memory type storage and computing integrated circuit provided in an embodiment of the present application.

[0044] The flash memory type storage and computing integrated circuit provided in this embodiment includes a plurality of flash memory transistors. The flash memory transistor is connected with an input wire (AL) and an output wire (BL), wherein the input wire is connected to one of the source or drain of the flash memory transistor, and the output wire is connected to the other of the source or drain of the flash memory transistor. A voltage can be input to the flash memory transistor through the input wire, and a current or voltage of the flash memory transistor can be output through the output wire.

[0045] As an example, the flash memory transistors may be arranged in an array, with multiple input wires and multiple output wires, and the input wires and the output wires are perpendicular to each other. Figure 3 shown.

[0046] As a possible implementation, the flash memory transistor further includes a control gate, a gate selection or an erase gate, and different wires can be used to connect the control gate, the gate selection or the erase gate, respectively. Figure 3 As shown, a control gate conductor (CL) is used to connect the control gate to achieve switching control of the flash memory transistor.

[0047] The nonlinear region of the flash memory transistor mainly comes from the saturation region of the flash memory transistor, where the input voltage is relatively large. In the saturation region, even if the input voltage is increased, the output current no longer increases significantly with the voltage, and enters a current saturation state. In other words, the saturation region of the flash memory transistor is the main influencing factor of the nonlinear error.

[0048] In practical applications, as the size of flash memory transistors decreases, flash memory transistors have a short channel effect. The manifestation of the short channel effect in the saturation region is that the current in the saturation region is no longer in an obvious saturation state, but will increase as the input voltage continues to increase. The short channel effect is also called the drain induce barrier lowering (DIBL) effect.

[0049] In traditional chip circuits, the short channel effect of flash memory transistors is avoided as much as possible, because the short channel effect will cause leakage of flash memory transistors, affecting the operation of flash memory transistors negatively. However, in the present application, since the output current of the flash memory transistor with short channel effect in the saturation region also increases with the increase of input voltage, the current-voltage relationship of the flash memory transistor with short channel effect can be close to a linear relationship, thereby reducing the nonlinear error of the flash memory transistor, and then using the short channel effect of multiple flash memory transistors to reduce the nonlinear error of the flash memory storage and computing integrated circuit.

[0050] refer to Figure 4 As shown, Figure 4 A schematic diagram of the current-voltage relationship of a flash memory transistor with a short channel effect provided in an embodiment of the present application. Figure 4 It can be seen that no matter how large or small the storage weight is, when the flash memory transistor has a short channel effect, the nonlinear error can be reduced.

[0051] It can be seen that the flash memory type storage and computing integrated circuit provided in the embodiment of the present application includes multiple flash memory transistors with short channel effect, so that the current of the flash memory transistor in the saturation region is no longer in a saturated state, but continues to increase with the increase of the input voltage to reduce the nonlinear error. The short channel effect of multiple flash memory transistors can be directly used to reduce the nonlinear error of the flash memory type storage and computing integrated circuit, thereby improving the calculation accuracy of the flash memory type storage and computing integrated circuit.

[0052] In the embodiments of the present application, based on the fact that the short channel effect of the flash memory transistor can reduce the nonlinear error, a flash memory transistor with the short channel effect can be manufactured and applied to the flash memory type storage and computing integrated circuit to reduce the nonlinear error.

[0053] There are many possible ways to manufacture a flash memory transistor with a short channel effect, such as changing the size of the flash memory transistor, changing the material of the insulating layer included in the flash memory transistor, or increasing the area range of the source or drain included in the flash memory transistor, which are described in detail below.

[0054] The first possible implementation method is to change the size of the flash memory transistor. Since the flash memory transistor includes a source, a drain, a gate, an insulating layer and a channel, changing the size of the flash memory transistor to achieve a short channel effect of the flash memory transistor can be to shorten the channel length or increase the thickness of the insulating layer.

[0055] refer to Figure 5 As shown, Figure 5 The cross-sectional structure diagram of a flash memory transistor provided in an embodiment of the present application is shown in FIG.

[0056] The substrate 110 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a SiGe substrate, a silicon on insulator (SOI) or a germanium on insulator (GOI). In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide (GaAs), indium phosphide (InP) or silicon carbide (SiC), or a stacked structure, such as Si / SiGe, or other epitaxial structures, such as silicon and Germanium on insulator (SGOI). In this embodiment, the substrate 110 is a silicon substrate.

[0057] The channel 120 is disposed in the substrate 110 . The material of the channel 120 may be the same as that of the substrate 110 , or the channel 120 may be obtained by doping the substrate 110 .

[0058] The source 130 and the drain 140 are located at two sides of the channel 120 . The source 130 or the drain 140 may be obtained by doping the substrate 110 .

[0059] An insulating layer 160 is disposed on the channel 120, and a gate 150 is disposed on the insulating layer 160, that is, the insulating layer 160 is disposed between the channel 120 and the gate 150. A floating gate or a charge trapping layer (not shown) is also disposed in the insulating layer 160, and the insulating layer 160 surrounds the floating gate or the charge trapping layer.

[0060] As a possible implementation method, the channel length of the flash memory transistor is less than the length threshold so that the flash memory transistor can have a short channel effect, that is, reducing the channel length of the flash memory transistor can achieve the short channel effect of the flash memory transistor. The channel length refers to the length of the channel along the connection direction of the source and the drain, and the length threshold is the channel length when the short channel effect occurs in the flash memory transistor.

[0061] As an example, refer to Figure 5 As shown, the length of the channel 120 may be smaller than the length of the gate 150 .

[0062] In practical applications, when only the channel length is shortened without taking measures to offset the short channel effect, such as not reducing the thickness of the insulating layer, not modifying the fin field effect transistor structure (FinFET), and not using high-dielectric constant (High-k) insulating layer materials, flash memory transistors with short channel effect can be manufactured more quickly.

[0063] When the short channel effect of the flash memory transistor is achieved by shortening the channel length, the size of the flash memory transistor is also reduced accordingly, which can reduce the area of ​​the flash memory type storage and computing integrated circuit and reduce the manufacturing cost of the flash memory type storage and computing integrated circuit.

[0064] As another possible implementation method, the thickness of the insulating layer is greater than the thickness threshold so that the flash memory transistor can have a short channel effect, that is, increasing the thickness of the insulating layer can achieve the short channel effect of the flash memory transistor, and the thickness threshold is the thickness of the insulating layer when the short channel effect occurs in the flash memory transistor.

[0065] As an example, refer to Figure 6 As shown, the thickness of the insulating layer 160 can be relatively thick.

[0066] In practical applications, when the thickness of the insulating layer is increased, the thickness of the floating gate or charge trapping layer surrounded by the insulating layer may not be changed, and only the thickness of the insulating layer above and below the floating gate or charge trapping layer is increased. By increasing the thickness of the insulating layer above and below the floating gate or charge trapping layer, the coupling capacitance from the gate to the channel can be reduced, the control of the gate over the channel can be weakened, and the short channel effect can also be achieved.

[0067] From the above description, it can be seen that shortening the channel length or increasing the thickness of the insulating layer can realize the short channel effect of the flash memory transistor. It is also possible to simultaneously control the flash memory transistor to shorten the channel length and increase the thickness of the insulating layer to realize the short channel effect of the flash memory transistor.

[0068] The second possible implementation method is to not change the size of the flash memory transistor. Changing the material of the insulating layer included in the flash memory transistor can also achieve the short channel effect of the flash memory transistor. Changing the material of the insulating layer included in the flash memory transistor can be to select an insulating layer material with a lower dielectric constant.

[0069] As a possible implementation method, the dielectric constant of the insulating layer material is less than the dielectric constant threshold value so that the flash memory transistor can have a short channel effect, that is, lowering the dielectric constant of the insulating layer material can achieve the short channel effect of the flash memory transistor, and the dielectric constant threshold value is the dielectric constant when the flash memory transistor exhibits a short channel effect.

[0070] In other words, the short channel effect of the flash memory transistor can be achieved without changing the size of the flash memory transistor, and the manufacturing process of the flash memory transistor is slightly changed.

[0071] A third possible implementation method is to not change the size of the flash memory transistor. Changing the area range of the source or drain included in the flash memory transistor can also realize the short channel effect of the flash memory transistor. Changing the area range of the source or drain included in the flash memory transistor can be to increase the area range of the source or drain included in the flash memory transistor.

[0072] As a possible implementation method, the source and the drain overlap partially with the channel respectively, so that the flash memory transistor can have a short channel effect, that is, the source and the channel overlap partially in parallel to the plane where the substrate is located, and the drain and the channel overlap partially in parallel to the plane where the substrate is located, thereby increasing the area range of the source or drain to realize the short channel effect of the flash memory transistor.

[0073] As an example, refer to Figure 7 As shown, the source 130 and the drain 140 partially overlap the channel 120 , respectively.

[0074] Specifically, the overlapping areas of the source and the drain respectively overlapping with the channel portion are greater than the overlapping area threshold, and the overlapping area threshold is the overlapping areas of the source and the drain respectively overlapping with the channel portion when the short channel effect occurs in the flash memory transistor.

[0075] The overlapping area of ​​the source and drain with the channel portion can be controlled by controlling the ion implantation intensity, ion implantation composition, ion diffusion temperature or ion diffusion time when forming the source or drain, so as to control the region range of the source or drain.

[0076] As an example, the region range of the source or drain can be increased by increasing the ion diffusion temperature or the ion diffusion time, thereby increasing the overlapping areas where the source and drain overlap with the channel portion.

[0077] In an embodiment of the present application, the area of ​​the flash memory type storage and computing integrated circuit is less than the circuit area threshold. The circuit area threshold is the average circuit area of ​​the current flash memory type storage and computing integrated circuit. When the area of ​​the flash memory type storage and computing integrated circuit is less than the circuit area threshold, it means that the area of ​​the flash memory type storage and computing integrated circuit is small.

[0078] Since flash memory transistors are more susceptible to short channel effects than logic transistors, the current production process of embedded flash memory chips stops reducing their size around 40nm-28nm. However, since the flash memory transistors in the flash memory storage and computing integrated circuit in this application have a short channel effect that can reduce nonlinear errors, even if the size of the flash memory transistor is reduced to bring about a short channel effect, it will not affect the performance of the flash memory storage and computing integrated circuit. On the contrary, the short channel effect will be used to improve the calculation accuracy, so that the chip composed of the flash memory storage and computing integrated circuit is expected to be used at a process node below 40nm-28nm, for example, at a process node of 22nm-14nm. In other words, the current flash memory storage and computing integrated circuit can have both a small area and high calculation accuracy.

[0079] Based on a flash memory type storage and computing integrated circuit provided in the above embodiment, an embodiment of the present application further provides an error elimination method for a flash memory type storage and computing integrated circuit, which is described in detail below in conjunction with the accompanying drawings.

[0080] See also Figure 8 , which is a flow chart of an error elimination method for a flash memory type storage and computing integrated circuit provided in an embodiment of the present application. The error elimination method for a flash memory type storage and computing integrated circuit provided in an embodiment of the present application is applied to the flash memory type storage and computing integrated circuit provided in the above embodiment.

[0081] The error elimination method of the flash memory type storage and computing integrated circuit provided in this embodiment includes the following steps:

[0082] S101, input a set of input vectors into the flash memory type integrated storage and computing circuit, where the input vectors include multiple voltage values.

[0083] In an embodiment of the present application, since the flash memory type storage and computing integrated circuit includes a plurality of flash memory transistors, a set of input vectors including a plurality of voltage values ​​corresponding to the number of flash memory transistors can be input.

[0084] S102, obtaining a set of actual output vectors output by the flash memory type storage and computing integrated circuit, where the actual output vectors are calculated using a storage weight matrix and an input vector, the storage weight matrix is ​​related to the short channel effect of the flash memory transistor, and the nonlinear error between the actual output vector and the ideal output vector is less than an error threshold.

[0085] In an embodiment of the present application, after multiple voltage values ​​are input into the flash memory type storage and computing circuit, a set of actual output vectors output by the flash memory type storage and computing circuit is obtained, and the actual output vectors are calculated using the storage weight matrix and the input vector.

[0086] Since the short channel effect of the flash memory transistor will affect the current-voltage relationship in the saturation region, the storage weight matrix is ​​related to the short channel effect of the flash memory transistor. The storage weight matrix is ​​optimized, and the nonlinear error between the actual output vector and the ideal output vector is less than the error threshold, that is, the nonlinear error of the flash memory storage and computing integrated circuit is reduced.

[0087] The embodiment of the present application also provides a computer-readable medium for storing program code, where the program code is used to execute any one of the methods of the aforementioned embodiments.

[0088] It should be noted that the computer-readable medium mentioned above in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0089] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0090] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A flash memory type storage and computing integrated circuit, characterized in that: The flash memory type storage and computing integrated circuit includes a plurality of flash memory transistors; The flash memory transistor has a short channel effect, and the short channel effect of multiple flash memory transistors is used to reduce the nonlinear error of the flash memory type storage and computing integrated circuit.

2. The flash memory type storage and computing integrated circuit according to claim 1, characterized in that: The flash memory transistor includes a channel; The channel length of the flash memory transistor is less than a length threshold.

3. The flash memory type storage and computing integrated circuit according to claim 1, characterized in that: The flash memory transistor comprises a channel, an insulating layer and a gate, wherein the insulating layer is arranged between the channel and the gate; The thickness of the insulating layer is greater than a thickness threshold.

4. The flash memory type storage and computing integrated circuit according to claim 1, characterized in that: The flash memory transistor comprises a channel, an insulating layer and a gate, wherein the insulating layer is arranged between the channel and the gate; The dielectric constant of the material of the insulating layer is less than a dielectric constant threshold.

5. The flash memory type storage and computing integrated circuit according to claim 1, characterized in that: The flash memory transistor comprises a channel, a source and a drain, wherein the channel is located between the source and the drain; The source electrode and the drain electrode partially overlap the channel, respectively.

6. The flash memory type storage and computing integrated circuit according to claim 5, characterized in that: An overlapping area where the source and the drain overlap the channel portion is greater than an overlapping area threshold.

7. The flash memory type storage and computing integrated circuit according to claim 5, characterized in that: The overlapping areas of the source electrode and the drain electrode respectively overlapping with the channel portion are controlled by controlling the ion implantation intensity, ion implantation composition, ion diffusion temperature or ion diffusion time when forming the source electrode or the drain electrode.

8. The flash memory type storage and computing integrated circuit according to any one of claims 1 to 6, characterized in that: The area of ​​the flash memory type storage and computing integrated circuit is smaller than the circuit area threshold.

9. A method for eliminating errors in a flash memory type storage and computing integrated circuit, characterized in that: The method applied to the flash memory storage-computing integrated circuit according to any one of claims 1 to 8 comprises: Inputting a set of input vectors into the flash memory type storage and computing integrated circuit, wherein the input vectors include a plurality of voltage values; A set of actual output vectors output by the flash memory type integrated storage and computing circuit is obtained, wherein the actual output vectors are calculated using a storage weight matrix and the input vectors, the storage weight matrix is ​​related to the short channel effect of the flash memory transistor, and the nonlinear error between the actual output vector and the ideal output vector is less than an error threshold.

10. A computer-readable medium, characterized in that The method comprises instructions which, when executed on a computer, cause the computer to perform the method as claimed in claim 9.

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