Method for cleaning etched through hole and method for forming metal interconnection structure
By depositing a silicon nitride layer on the through hole surface and performing multiple cleaning treatments, the problem of interlayer dielectric loss during the through hole cleaning process is solved, and higher device electrical performance and a more uniform through hole surface are achieved.
Patent Information
- Application Number
- CN202510066677.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2025-05-13
AI Technical Summary
In the existing semiconductor manufacturing processes, interlayer medium (SiO2) is easily lost during the through-hole cleaning, resulting in the impact of the electrical performance of the device.
The silicon nitride layer was pre-deposited on the surface of the through-hole and the first cleaning was performed using a phosphoric acid solution to generate a silicide that inhibits the etching of silica. Subsequently, a second cleaning was performed using a mixed solution of DHF, sulfuric acid and phosphoric acid to remove silicon nitride and metal residues, and by controlling the solution concentration and volume ratio, the loss of the interlayer dielectric is reduced.
It effectively reduces the loss of interlayer dielectric during through hole cleaning, improves the electrical performance of the device, and improves the uniformity of the through hole surface.
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Figure CN119993823A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for cleaning through-holes after etching and a method for forming a metal interconnection structure. Background Art
[0002] In the existing semiconductor integrated circuit manufacturing process, after the device layer is prepared on the wafer, a metal interconnect layer needs to be made on the device layer as a signal transmission channel between devices (such as transistors). The production of the metal interconnect layer is carried out through the back end of line (BEOL) process.
[0003] In the existing metal interconnection process, the interlayer dielectric material between the transistor and the first layer of metal is usually SiO2, and the contact holes on the interlayer dielectric are filled with metal tungsten. In order to facilitate the subsequent copper plating process, UDHF is usually used to clean the through holes, which will inevitably cause loss of the interlayer dielectric (ILD Loss). Excessive loss will affect the electrical performance of the device.
[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0005] The object of the present invention is to provide a method for cleaning through-holes after etching and a method for forming a metal interconnect structure, so as to reduce the loss of interlayer dielectrics during cleaning and improve the electrical performance of devices.
[0006] In order to solve the above problems, the present invention provides a method for cleaning a through hole after etching and a method for forming a metal interconnect structure. In a first aspect, a method for cleaning a through hole after etching is provided, comprising the following steps:
[0007] S1. Providing a substrate, on which a through hole for connecting a first metal interconnection layer and metal tungsten is formed, wherein the metal tungsten is a tungsten contact or a tungsten plug in a first dielectric layer, and the first dielectric layer is silicon dioxide;
[0008] S2, forming a silicon nitride layer on the surface of the through hole;
[0009] S3, performing a first cleaning process using a phosphoric acid solution to remove the silicon nitride layer and generate a silicide that inhibits etching of silicon dioxide;
[0010] S4. Perform a second cleaning process using a mixed solution of DHF, sulfuric acid and phosphoric acid.
[0011] In order to minimize the loss of the interlayer dielectric (SiO2) at the bottom of the through hole when cleaning the through hole, the present invention pre-deposits a layer of silicon nitride on the surface of the through hole after the through hole is completed, and then pre-treats the silicon nitride layer with a phosphoric acid solution. While removing the silicon nitride, a product that inhibits the etching of silicon dioxide is generated, thereby ensuring that the loss of the interlayer dielectric is reduced or even completely avoided in the subsequent cleaning process.
[0012] In the first cleaning process, the concentration of the phosphoric acid solution is 80-88 wt % and the temperature is 120-160° C. Under these process parameters, a high etching selectivity ratio between silicon nitride and silicon dioxide can be achieved, and silicon nitride can be quickly removed without etching silicon dioxide.
[0013] In the second cleaning process, the volume ratio of DHF, sulfuric acid and phosphoric acid solution in the mixed solution is 0.01: (0.2-1): (0.5-1); the concentration range of the DHF solution is 20-30ppm, the concentration range of the sulfuric acid solution is 5-8wt%, and the concentration range of the phosphoric acid solution is 80-88wt%. A certain amount of phosphoric acid solution is added to the UDHF solution, and the etching byproducts, metal residues, etc. in the through hole can be removed by DHF and sulfuric acid, and the added phosphoric acid will also react with the residual silicon nitride to continue to generate products that inhibit the etching of silicon dioxide, further protecting the interlayer dielectric from being lost.
[0014] After step S4, the process further includes rinsing with deionized water for 10-20 minutes. Timely rinsing with deionized water can reduce the residence time of the chemical reagent on the through-hole surface and improve the uniformity of the through-hole surface.
[0015] In a second aspect, the present invention further provides a method for forming a metal interconnect structure, comprising the following steps:
[0016] S1. Provide a substrate, on which a device layer is formed, wherein the device layer includes a first dielectric layer, wherein metal tungsten for contact is formed in the first dielectric layer, wherein the metal tungsten is a tungsten contact or a tungsten plug, and the first dielectric layer is silicon dioxide;
[0017] S2, forming a barrier layer, a second dielectric layer, an anti-reflection layer and a metal hard mask layer in sequence on the surface of the substrate;
[0018] S3, using photolithography and etching processes to form interconnection grooves and through holes up to the surface of the metal tungsten;
[0019] S4, forming a silicon nitride layer on the surface of the substrate;
[0020] S5, performing a first cleaning process using a phosphoric acid solution to remove the silicon nitride layer and generate a silicide that inhibits etching of silicon dioxide;
[0021] S6, using a mixed solution of DHF, sulfuric acid and phosphoric acid for a second cleaning process;
[0022] S7, rinse with deionized water;
[0023] S8. Filling metal material in the interconnection trenches and through holes to form a first metal interconnection layer.
[0024] The method for forming a metal interconnect structure of the present invention adopts the cleaning method described in the first aspect, which can reduce the loss of the interlayer dielectric as much as possible while satisfying the through-hole cleaning effect, thereby forming a high-performance metal interconnect structure.
[0025] In the first cleaning process, the concentration of the phosphoric acid solution is 80-88 wt % and the temperature is 120-160° C.
[0026] The volume ratio of DHF, sulfuric acid and phosphoric acid solution in the mixed solution is 0.01:(0.2-1):(0.5-1); the concentration range of the DHF solution is 20-30 ppm, the concentration range of the sulfuric acid solution is 5-8 wt%, and the concentration range of the phosphoric acid solution is 80-88 wt%.
[0027] In step S3, the process of forming the through hole includes: forming a patterned photoresist layer on the surface of the metal hard mask layer; using the patterned photoresist layer as an etching mask, and adopting a dry etching process to sequentially etch the metal hard mask layer, the anti-reflective layer, the second dielectric layer and the barrier layer to form a through hole reaching the surface of the metal tungsten; and removing the residual photoresist.
[0028] The dry etching process is plasma etching, and the etching gas is chlorine.
[0029] The remaining photoresist is removed by an ashing process, followed by a deionized water cleaning process.
[0030] Compared with the prior art, the beneficial effects of the present invention mainly include the following: in order to minimize the loss of the interlayer dielectric (SiO2) at the bottom of the through hole when cleaning the through hole, the present invention pre-deposits a layer of silicon nitride on the surface of the through hole after the through hole is completed, and then pre-treats the silicon nitride layer with a phosphoric acid solution, thereby removing the silicon nitride and generating a product that inhibits the etching of silicon dioxide, thereby ensuring that the loss of the interlayer dielectric is reduced or even completely avoided in the subsequent cleaning process. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0032] Figure 1 The figure is a flow chart of the preparation of the first metal interconnection layer in the prior art.
[0033] Figure 2 This is a flow chart of the cleaning method after through hole etching provided by the present invention.
[0034] Figure 3 A flow chart for preparing a metal interconnect structure provided by the present invention. DETAILED DESCRIPTION
[0035] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.
[0036] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.
[0037] The steps in the following embodiments do not correspond one to one with the summary of the invention.
[0038] As described in the background technology, in order to realize the interconnection of transistors in the device layer, a metal interconnection structure is used in the prior art. Usually, after the main structure of the device layer is prepared, a tungsten contact (CT) and a tungsten plug are made in the device layer, and then a metal interconnection layer is made on the device layer to provide physical guarantee for signal transmission between devices. The preparation of the metal interconnection layer usually includes etching interconnection grooves and vias in the intermetallic dielectric (IMD) and depositing metal to form metal wiring.
[0039] In the prior art, the metal interconnection layer located above the tungsten contact and the tungsten plug and directly forming an electrical connection with the metal tungsten is called the first metal interconnection layer. Figure 1 The figure shows a flow chart of preparing the first metal interconnection layer in the prior art.
[0040] Step 1: providing a substrate, on which a first metal interconnection layer is to be processed.
[0041] Specifically, refer to Figure 1 A, firstly, a substrate 1 is provided, on which a device layer (not shown) has been formed, and a metal tungsten 3 for contact has been formed in the device layer; it can be understood that the metal tungsten 3 can be a tungsten contact (CT) and a tungsten plug, which is obtained by forming a contact hole in the first dielectric layer 2 and then filling it with tungsten. It can be understood that the first dielectric layer 2 is an inter-layer dielectric (ILD), and usually, the material of the inter-layer dielectric is silicon dioxide. The substrate is subsequently processed with a metal interconnect structure to achieve the connection of different devices.
[0042] Step 2: Perform through-hole etching of the first metal interconnection layer.
[0043] Specifically, refer to Figure 1 b and c, a barrier layer 4, a second dielectric layer 5, an anti-reflection layer 6 (DARC) and a metal hard mask layer 7 are sequentially deposited on the surface of the substrate 1 (i.e., the first dielectric layer 2 and the metal tungsten 3), and a through hole 8 is formed up to the surface of the metal tungsten 3 by photolithography and etching processes. The formation process of the through hole is a prior art, and will not be described in detail here. It can be understood that before etching the through hole, an interconnection trench structure has generally been formed by etching, which is not the focus of this application, and its formation process can refer to the prior art, and will not be described in detail here.
[0044] Step 3: Perform through-hole cleaning and metal filling.
[0045] In the prior art, the first metal layer is usually copper metal, which is generally formed by a copper plating process. Since some etching byproducts and residues are often produced in the previous through-hole etching process, in order to facilitate the subsequent copper plating to form the first metal layer, the through-hole 8 needs to be cleaned and then filled with metal to form the first metal interconnection layer.
[0046] Reference Figure 1 After forming the through hole 8, UDHF cleaning is usually used to remove the byproducts and residues generated during the etching process. Figure 1 As shown in FIG. d, the UDHF solution (a mixed solution of hydrofluoric acid and sulfuric acid) can also easily corrode the interlayer dielectric SiO2 during the cleaning process, causing the loss of the first dielectric layer 2, thereby affecting the electrical performance of the device.
[0047] In order to solve this problem, we provide a method for cleaning through-holes after etching and a method for forming a metal interconnection structure.
[0048] Embodiment 1:
[0049] refer to Figure 2 The present invention provides a method for cleaning through-holes after etching, and the method comprises the following steps.
[0050] Step 1: Provide a substrate on which through-hole etching for connecting the first metal layer and the metal tungsten 3 has been performed, and a through-hole 8 is formed on the surface of the metal tungsten 3 .
[0051] The substrate 1 provided is as Figure 2 As shown in a in the figure, a through-hole structure for connecting the first metal layer and the metal tungsten 3 has been formed thereon. It can be understood that the substrate provided in this step is the structure obtained after step 2 in the above-mentioned prior art. In fact, the present application does not limit the process of obtaining the structure (that is, it is not necessarily consistent with step 2 in the above-mentioned prior art), but for ease of understanding, a formation method in the prior art is provided as an example below. The processing process of the structure obtained after the above-mentioned step 2 generally includes: providing a substrate 1, on which the device layer has been prepared, the device layer includes a first dielectric layer 2, and a metal tungsten 3 for contact has been formed in the first dielectric layer 2; depositing a barrier layer 4, a second dielectric layer 5, an anti-reflection layer 6 and a metal hard mask layer 7 on the surface of the substrate in sequence, and forming a through hole 8 to the surface of the metal tungsten 3 by photolithography and etching processes. It can be understood that before etching the through hole, an interconnection groove structure has generally been formed by etching, which is not the focus of the present application. Its formation process can refer to the prior art and will not be described in detail here.
[0052] In the present embodiment, the substrate 1 is a silicon substrate. In other embodiments, a germanium substrate or a SOI (silicon on insulator) or a substrate of other semiconductor materials may also be used. In the present application, the first dielectric layer 2 is an interlayer dielectric (ILD), which is made of silicon dioxide. The barrier layer 4 may be silicon carbide (SiC) or nitrogen-doped silicon carbide (SiCN). In the present embodiment, the barrier layer 4 is nitrogen-doped silicon carbide. The second dielectric layer 5 is an intermetallic dielectric (IMD). In the present embodiment, the second dielectric layer 5 is a low dielectric constant (Low-K) dielectric, such as carbon-containing silicon dioxide or black diamond. In the present embodiment, the metal hard mask layer 7 is a titanium nitride (TiN) layer.
[0053] Step 2: depositing a silicon nitride (SiN) layer 10 on the surface of the through hole 8 .
[0054] refer to Figure 2 As shown in b, in order to reduce or avoid the interlayer dielectric loss (ILDloss) phenomenon caused by subsequent UDHF cleaning, the present application creatively proposes to deposit a silicon nitride layer 10 before cleaning. In the present application, the formation process of the layer is not limited.
[0055] Step 3: Perform the first cleaning process.
[0056] refer to Figure 2 In c, a phosphoric acid solution is first used for the first cleaning treatment to clean the silicon nitride layer 10 in the through hole 8. Specifically, in the present embodiment, a phosphoric acid solution is sprayed onto the surface of the substrate 1 for cleaning. During the process, the phosphoric acid solution reacts with the silicon nitride to generate silicide that inhibits the corrosion of SiO2, while protecting the side walls from being corroded by phosphoric acid. In the present embodiment, the concentration of the phosphoric acid solution used for phosphoric acid cleaning is 88wt% (wt% i.e. mass percentage), the temperature of the phosphoric acid solution is 120°C, and the cleaning time is determined according to actual conditions, generally 10-30 minutes. In other embodiments, the concentration range of the phosphoric acid solution is 80-88wt%, and the temperature range is 120-160°C. Figure 2 As shown in c in FIG. 1 , after the cleaning process in this step, the silicon nitride layer 10 formed in step 2 has been substantially removed.
[0057] Step 4: Perform a second cleaning process.
[0058] After the first cleaning is completed, a mixed solution of DHF, sulfuric acid and phosphoric acid is used to perform a second cleaning process on the through hole 8 to remove silicon nitride and other metal residues, etc. Specifically, in this embodiment, a mixed solution of DHF, sulfuric acid and phosphoric acid is sprayed on the surface of the substrate 1 for cleaning. During this process, due to the presence of the silicide formed in step 3, it can be ensured that the interlayer dielectric (i.e., the first dielectric layer 2) is not lost.
[0059] In this embodiment, the volume ratio of DHF, sulfuric acid and phosphoric acid solution in the mixed solution is 0.01:(0.2-1):(0.5-1); wherein, the concentration range of DHF solution is 20-30ppm (ppm is a unit used to express the concentration of solute mass in parts per million of the total solution mass, i.e. 1ppm is equal to one millionth), the concentration range of sulfuric acid solution is 5-8wt%, and the concentration range of phosphoric acid solution is 80-88wt%; the cleaning time is determined according to actual conditions, generally 4-6 minutes.
[0060] Step 5: Rinse with deionized water.
[0061] After the above cleaning with the chemical solution, the surface of the through hole 8 is rinsed with deionized water. In this embodiment, the deionized water rinse time is 10-20 minutes to reduce the residence time of the chemical reagent on the surface of the through hole 8 and improve the uniformity of the surface of the through hole 8.
[0062] The above is a cleaning method after through-hole etching provided in this embodiment. The main purpose of the cleaning method provided in this application is to reduce the loss of interlayer dielectric (ILD). The main reason for the loss of interlayer dielectric (SiO2) is that the hydrofluoric acid in the solution when cleaning the through-hole will corrode SiO2. In order to solve this problem, we adopt the method of depositing silicon nitride in the through-hole and cleaning it twice. First, phosphoric acid solution is used for pretreatment. Phosphoric acid has a high etching selectivity for SiN and SiO2 (that is, it etches SiN faster and etches SiO2 less), and it will react with SiN to generate SiO2 during the etching process of SiN, further inhibiting the etching of SiO2. Therefore, this step will only remove SiN without etching the interlayer dielectric. Of course, the etching in the wet cleaning process is isotropic, so it can also inhibit the phosphoric acid solution from eating the side walls of the through-hole during the etching process. After that, a mixed solution of phosphoric acid, DHF, and sulfuric acid is used to clean the through-hole to remove residues. Since the reaction product of sulfuric acid and SiN (i.e., SiO2) will remain in the through-hole during the pretreatment process, it can inhibit the etching of the interlayer dielectric (i.e., SiO2), thereby reducing or even avoiding the loss of the interlayer dielectric while achieving the desired cleaning effect.
[0063] Embodiment 2:
[0064] Figure 3 A flow chart of the preparation of a metal interconnect structure provided by the present invention. Figure 3 The present invention provides a method for forming a metal interconnection structure, comprising the following steps.
[0065] Step 1: Provide a substrate to be processed with a first metal interconnection layer.
[0066] Specifically, refer to Figure 3 A, firstly, a substrate 1 is provided, on which a device layer has been formed, the device layer includes a first dielectric layer 2, and a metal tungsten 3 for contact has been formed in the first dielectric layer 2. It can be understood that the metal tungsten 3 is obtained by forming a contact hole in the first dielectric layer 2 and then filling it with tungsten. It can be understood that the metal tungsten is a tungsten contact or a tungsten plug, and the first dielectric layer 2 is an inter-layer dielectric (ILD). In this embodiment, the material of the inter-layer dielectric is silicon dioxide.
[0067] Step 2: forming a barrier layer 4, a second dielectric layer 5, an anti-reflection layer 6 (DARC) and a metal hard mask layer 7 in sequence on the surface of the substrate.
[0068] Specifically, refer to Figure 3b, a barrier layer 4, a second dielectric layer 5, an anti-reflective layer 6 (DARC) and a metal hard mask layer 7 are sequentially formed on the surface of the substrate 1 (i.e., the first dielectric layer 2 and the metal tungsten 3), and the formation process includes but is not limited to chemical vapor deposition, plasma enhanced chemical vapor deposition or atomic layer deposition process.
[0069] In this embodiment, the substrate 1 is a silicon substrate. In other embodiments, a germanium substrate or SOI (silicon on insulator) or a substrate of other semiconductor materials may also be used. In the present application, the first dielectric layer 2 is made of silicon dioxide. The barrier layer 4 may be silicon carbide (SiC) or nitrogen-doped silicon carbide (SiCN). In the present embodiment, it is nitrogen-doped silicon carbide. The second dielectric layer 5 is an intermetallic dielectric (IMD). In the present embodiment, the second dielectric layer 5 is a low dielectric constant (Low-K) dielectric, such as carbon-containing silicon dioxide or black diamond. In the present embodiment, the metal hard mask layer 7 is a titanium nitride (TiN) layer.
[0070] Step 3: Perform interconnect trench and via etching process on the first metal layer.
[0071] It can be understood that the etching of the interconnection groove (not shown in the figure) and the through hole is a prior art, that is, the required interconnection groove and the through hole 8 up to the surface of the metal tungsten 3 are formed by photolithography and etching processes, generally the interconnection groove is first etched, and then the through hole is etched. The formation of the interconnection groove can refer to the existing process, and will not be described in detail here.
[0072] In this embodiment, the through hole 8 is formed by etching once. Specifically, first, a photoresist is spin-coated on the surface of the metal hard mask layer 7 to form a photoresist layer (not shown in the figure), and then the photoresist layer is patterned (including exposure, development and other processes) to obtain a patterned photoresist layer; then, the patterned photoresist layer is used as an etching mask, and the metal hard mask layer 7, the anti-reflection layer 6, the second dielectric layer 5 and the barrier layer 4 are etched in sequence by a dry etching process until the surface of the metal tungsten 3 is stopped, and the through hole 8 is obtained. The structure obtained by etching is referred to as Figure 3 As shown in c.
[0073] In this embodiment, dry etching uses plasma etching, and the etching gas is chlorine, that is, the plasma generated by chlorine is used for etching. In this embodiment, a through hole 8 is formed by one etching, and in other embodiments, a two-time etching process can also be used. The two-time etching includes: forming a patterned photoresist layer, performing the first etching with the photoresist layer as an etching mask, and etching the metal hard mask layer 7, the anti-reflection layer 6 and the second dielectric layer 5 in sequence until the surface of the barrier layer 4 stops; performing the second etching after cleaning, and forming a through hole 8 up to the surface of the metal tungsten 3 after removing the barrier layer 4.
[0074] Step 4: Remove the remaining photoresist.
[0075] The residual photoresist is removed by an ashing process. Specifically, oxygen is used to perform dry etching to remove the photoresist. This step is a prior art and will not be described in detail here.
[0076] Step 5: Use DIW cleaning to remove particulate matter.
[0077] In this embodiment, DIW (deionized water) is used for cleaning to remove the particles after etching. This process generally includes cleaning with deionized water and then purging and drying with nitrogen, which can effectively remove the particles.
[0078] Step 6: Deposit a silicon nitride (SiN) layer 10 on the surface of the substrate.
[0079] refer to Figure 3 As shown in d, in order to reduce or avoid the interlayer dielectric loss (ILDloss) phenomenon caused by subsequent UDHF cleaning, a silicon nitride layer 10 is deposited before cleaning, and the silicon nitride layer 10 covers the surface of the interconnection grooves and the through holes 8. In the present application, the formation process of this layer is not limited.
[0080] Step 7: Perform the first cleaning process.
[0081] refer to Figure 3 In e, a phosphoric acid solution is first used for the first cleaning treatment to clean the silicon nitride layer 10 in the interconnection grooves and through-holes 8. Specifically, in the present embodiment, the cleaning treatment is performed by spraying a phosphoric acid solution onto the surface of the substrate 1. During the process, the phosphoric acid solution reacts with the silicon nitride to generate a silicide that inhibits the corrosion of SiO2, while protecting the side walls from being corroded by phosphoric acid. In the present embodiment, the concentration of the phosphoric acid solution used for phosphoric acid cleaning is 88wt%, the temperature of the phosphoric acid solution is 120°C, and the cleaning time is determined according to actual conditions, generally 10-30 minutes. In other embodiments, the concentration range of the phosphoric acid solution is 80-88wt%, and the temperature range is 120-160°C. Figure 3 As shown in FIG. 5 e, after the cleaning process in this step, the silicon nitride layer 10 formed in step 5 has been substantially removed.
[0082] Step 8: Perform a second cleaning process.
[0083] After the first cleaning is completed, a mixed solution of DHF, sulfuric acid and phosphoric acid is used to perform a second cleaning process on the interconnection grooves and through holes 8 to remove silicon nitride and other metal residues, etc. Specifically, in this embodiment, a mixed solution of DHF, sulfuric acid and phosphoric acid is sprayed on the surface of the substrate 1 for cleaning. During this process, due to the presence of the silicide formed in step 7, it can be ensured that the interlayer dielectric (i.e., the first dielectric layer 2) is not lost.
[0084] In this embodiment, the volume ratio of DHF, sulfuric acid and phosphoric acid solution in the mixed solution is 0.01:(0.2-1):(0.5-1); wherein the concentration range of DHF solution is 20-30 ppm, the concentration range of sulfuric acid solution is 5-8 wt %, and the concentration range of phosphoric acid solution is 80-88 wt %; the cleaning time is determined according to the actual situation, generally 4-6 minutes.
[0085] Step 8: Rinse with deionized water.
[0086] After the above cleaning with the chemical solution, the surface is rinsed with deionized water. In this embodiment, the deionized water rinse time is 10-20 minutes to reduce the residence time of the chemical reagent on the surface of the interconnection groove and the through hole 8 and improve the uniformity of the surface of the interconnection groove and the through hole 8.
[0087] Step 9: Filling metal material to form a metal layer 11 to obtain a first metal interconnection layer.
[0088] After the interconnection grooves and through-holes 8 are cleaned, the process of forming the first metal layer can be carried out using existing technology. It generally includes: depositing metal on the surface of the metal hard mask layer 7, and the metal fills the interconnection grooves and through-holes 8, and then removing the excess deposited metal and the metal hard mask layer 7 and the anti-reflection layer 6 through a CMP process to form the first metal interconnection layer.
[0089] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.
[0090] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
Claims
1. A method for cleaning through-holes after etching, characterized in that: The steps include: S1. Providing a substrate, on which a through hole for connecting a first metal interconnection layer and metal tungsten is formed, wherein the metal tungsten is a tungsten contact or a tungsten plug in a first dielectric layer, and the first dielectric layer is silicon dioxide; S2, forming a silicon nitride layer on the surface of the through hole; S3, performing a first cleaning process using a phosphoric acid solution to remove the silicon nitride layer and generate a silicide that inhibits etching of silicon dioxide; S4. Perform a second cleaning process using a mixed solution of DHF, sulfuric acid and phosphoric acid.
2. A method for cleaning a through hole after etching according to claim 1, characterized in that: In the first cleaning process, the concentration of the phosphoric acid solution is 80-88 wt % and the temperature is 120-160° C.
3. The method for cleaning a through hole after etching according to claim 1, characterized in that: In the second cleaning process, the volume ratio of DHF, sulfuric acid and phosphoric acid solution in the mixed solution is 0.01:(0.2-1):(0.5-1); the concentration range of the DHF solution is 20-30 ppm, the concentration range of the sulfuric acid solution is 5-8wt%, and the concentration range of the phosphoric acid solution is 80-88wt%.
4. The method for cleaning a through hole after etching according to claim 1, characterized in that: After step S4, the method further includes rinsing with deionized water, wherein the rinsing time of the deionized water is 10-20 minutes.
5. A method for forming a metal interconnect structure, characterized in that: The steps include: S1. Provide a substrate, on which a device layer is formed, wherein the device layer includes a first dielectric layer, wherein metal tungsten for contact is formed in the first dielectric layer, wherein the metal tungsten is a tungsten contact or a tungsten plug, and the first dielectric layer is silicon dioxide; S2, forming a barrier layer, a second dielectric layer, an anti-reflection layer and a metal hard mask layer in sequence on the surface of the substrate; S3, using photolithography and etching processes to form interconnection grooves and through holes up to the surface of the metal tungsten; S4, forming a silicon nitride layer on the surface of the substrate; S5, performing a first cleaning process using a phosphoric acid solution to remove the silicon nitride layer and generate a silicide that inhibits etching of silicon dioxide; S6, using a mixed solution of DHF, sulfuric acid and phosphoric acid for a second cleaning process; S7, rinse with deionized water; S8. Filling metal material in the interconnection trenches and through holes to form a first metal interconnection layer.
6. The method for forming a metal interconnection structure according to claim 5, characterized in that: In the first cleaning process, the concentration of the phosphoric acid solution is 80-88 wt % and the temperature is 120-160° C.
7. The method for forming a metal interconnection structure according to claim 5, characterized in that: The volume ratio of DHF, sulfuric acid and phosphoric acid solution in the mixed solution is 0.01:(0.2-1):(0.5-1); the concentration range of the DHF solution is 20-30 ppm, the concentration range of the sulfuric acid solution is 5-8 wt%, and the concentration range of the phosphoric acid solution is 80-88 wt%.
8. The method for forming a metal interconnection structure according to claim 5, characterized in that: In step S3, the process of forming the through hole includes: forming a patterned photoresist layer on the surface of the metal hard mask layer; Using the patterned photoresist layer as an etching mask, a dry etching process is used to sequentially etch the metal hard mask layer, the anti-reflection layer, the second dielectric layer and the barrier layer to form a through hole extending to the surface of the metal tungsten; Remove the remaining photoresist.
9. The method for forming a metal interconnection structure according to claim 8, characterized in that: The dry etching process is plasma etching, and the etching gas is chlorine.
10. The method for forming a metal interconnection structure according to claim 8, characterized in that: The remaining photoresist is removed by an ashing process, followed by a deionized water cleaning process.