A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The present invention relates to a method for manufacturing a semiconductor structure and a semiconductor structure, belonging to the field of semiconductor technology. In the method for manufacturing the semiconductor structure, when chemical mechanical polishing is performed on the gate material layer, a first loading effect is formed. Subsequently, a preset dry etching is performed on the first gate intermediate layer to form a gate, and this preset dry etching will generate a second loading effect. Since the first loading effect is an effect where the polishing rate is faster when the etching pattern density is larger, while the second loading effect is an effect where the polishing rate is slower when the etching pattern density is larger, that is, the second loading effect and the first loading effect are inverse loading effects. In other words, the second loading effect has a reverse control effect on the first loading effect generated by chemical mechanical polishing, improving the first loading effect generated by chemical mechanical polishing. In addition, when atomic layer etching is performed on the first dielectric material layer, since atomic layer etching is a self-limiting chemical reaction, the etching is more precise and the generation of defects is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the 28nm advanced process node, the gate last process is one of the mainstream methods for forming high-k metal gates, among which chemical mechanical polishing (CMP) plays an important role in the gate last process.

[0003] However, in the process of forming the gate, chemical mechanical polishing will have many problems. First, chemical mechanical polishing will produce a loading effect, resulting in an uneven surface of the formed gate. Second, when using chemical mechanical polishing to form the gate, excessive polishing will cause the gate height to be too low, and too little polishing will cause metal residue and lead to a short circuit. Third, because the gate is soft and active, it is easy to produce defects such as particle residue, scratches, and corrosion during polishing. Therefore, it is very important to improve the loading effect and polishing defects of the gate.

[0004] Based on this, how to improve the gate load effect and grinding defects has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] Based on this, it is necessary to provide a method for preparing a semiconductor structure and a semiconductor structure in order to improve the loading effect and grinding defects of the gate.

[0006] In order to achieve the above object, on the one hand, the present invention provides a method for preparing a semiconductor structure, comprising:

[0007] providing a substrate having a plurality of grooves;

[0008] forming a first dielectric material layer on the upper surface of the substrate and the inner wall of the groove;

[0009] forming a gate material layer on a side of the first dielectric material layer away from the substrate, wherein the gate material layer fills the groove;

[0010] Using the first dielectric material layer as a stop layer, chemical mechanical polishing is performed on the gate material layer to form a first gate intermediate layer, wherein the chemical mechanical polishing has a first loading effect;

[0011] Performing atomic layer etching on the first dielectric material layer to form a first dielectric layer;

[0012] Perform a preset dry etching on the first gate intermediate layer to form a gate. The preset dry etching has a second loading effect, and the second loading effect and the first loading effect are reverse loading effects to each other.

[0013] In one embodiment, the step of performing atomic layer etching on the first gate intermediate layer and the first dielectric material layer to form a first dielectric layer and a gate includes:

[0014] Perform a first atomic layer etching on the first dielectric material layer to form the first dielectric layer.

[0015] In one embodiment, the first dielectric material layer includes at least two sub-dielectric material layers, and the first dielectric layer includes at least two sub-dielectric layers;

[0016] When performing the first atomic layer etching on the first dielectric material layer, different etching gases are used to etch each of the sub-dielectric material layers respectively, and the remaining portions of the sub-dielectric material layers after etching form the corresponding sub-dielectric layers.

[0017] In one embodiment, when etching each of the sub-dielectric material layers respectively, it all includes:

[0018] Introduce a first reaction gas to perform reaction modification on the sub-dielectric material layer;

[0019] Introduce a second reaction gas to react with the modified sub-dielectric material layer to generate a volatile gas.

[0020] In one embodiment, the step of performing a preset dry etching on the first gate intermediate layer to form a gate includes:

[0021] Perform a preset dry etching on the first gate intermediate layer to form a second gate intermediate layer;

[0022] Perform a second atomic layer etching on the second gate intermediate layer to form the gate;

[0023] The step of performing a second atomic layer etching on the second gate intermediate layer to form the gate includes:

[0024] Introduce a third reaction gas to perform reaction modification on the second gate intermediate layer;

[0025] Introduce a fourth reaction gas to react with the modified second gate intermediate layer to generate a volatile gas.

[0026] In one embodiment, the first dielectric material layer includes a first sub-dielectric material layer and a second sub-dielectric material layer sequentially disposed on one side of the substrate. The first sub-dielectric material layer is used to adjust the work function of the semiconductor structure, and the second sub-dielectric material layer is located on the side close to the gate.

[0027] In one embodiment, the step of performing chemical mechanical polishing on the gate material layer with the first dielectric material layer as the stop layer to form the first gate intermediate layer includes:

[0028] Performing chemical mechanical polishing on the gate material layer with the second sub-dielectric material layer as the stop layer to form the first gate intermediate layer.

[0029] In one embodiment, before the step of forming the first dielectric material layer on the upper surface of the substrate and the inner wall of the groove, it further includes:

[0030] Forming a second dielectric layer at the bottom of the groove.

[0031] In one embodiment, the material of the gate material layer is an aluminum metal material.

[0032] On the other hand, the present invention also provides a semiconductor structure, which is prepared according to the preparation method of any one of the above semiconductor structures.

[0033] Compared with the prior art, the above technical solution has the following unexpected technical effects:

[0034] In the preparation method of this semiconductor structure, a first dielectric material layer and a gate material layer are first formed on the substrate. Then, with the first dielectric material layer as the stop layer, chemical mechanical polishing is first performed on the gate material layer to form the first gate intermediate layer. At this time, a first loading effect will be formed. Then, atomic layer etching is performed on the first dielectric material layer to form the first dielectric layer. Since atomic layer etching is a self-limiting chemical reaction and the etching is more precise, the etching position can be well controlled during etching. After that, a preset dry etching is performed on the first gate intermediate layer to form the gate. This preset dry etching will generate a second loading effect. Since the second loading effect and the first loading effect are reverse loading effects to each other, that is to say, the second loading effect has a reverse control effect on the first loading effect generated by chemical mechanical polishing, improving the first loading effect generated by chemical mechanical polishing. Description of the Drawings

[0035] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 This is a schematic diagram of the preparation process of a semiconductor structure provided by an embodiment of the present application;

[0037] Figure 2 This is a schematic diagram of the structure of the substrate of a semiconductor structure provided by an embodiment of the present application;

[0038] Figure 3 This is a schematic diagram of the structure after forming the first dielectric material layer in the preparation process of a semiconductor structure provided by an embodiment of the present application;

[0039] Figure 4 This is a schematic diagram of the structure after forming the gate material layer in the preparation process of a semiconductor structure provided by an embodiment of the present application;

[0040] Figure 5 For Figure 4 the enlarged structure schematic diagram in the dashed box of;

[0041] Figure 6 This is a schematic diagram of the structure after generating the first load effect in the preparation process of a semiconductor structure provided by an embodiment of the present application;

[0042] Figure 7 This is a schematic diagram of the structure after forming the first gate intermediate layer in the preparation process of a semiconductor structure provided by an embodiment of the present application;

[0043] Figure 8 This is a schematic diagram of the structure after forming the second gate intermediate layer in the preparation process of a semiconductor structure provided by an embodiment of the present application;

[0044] Figure 9 For Figure 8 the enlarged structure schematic diagram in the dashed box of;

[0045] Figure 10 This is a schematic diagram of the structure after forming the gate in the preparation process of a semiconductor structure provided by an embodiment of the present application;

[0046] Figure 11 For Figure 10 the enlarged structure schematic diagram in the dashed box of.

[0047] Explanation of the reference numerals: 01-substrate, 02-first dielectric material layer; 03-gate material layer; 04-first gate intermediate layer; 05-first dielectric layer; 06-gate; 07-second dielectric layer; 011-silicon substrate; 012-trench isolation structure; 013-gate oxide layer; 014-dielectric layer; 021-first sub-dielectric material layer; 022-second sub-dielectric material layer; 023-third sub-dielectric material layer; 051-first sub-dielectric layer; 052-second sub-dielectric layer; 053-third sub-dielectric layer; 041-second gate intermediate layer. DETAILED DESCRIPTION

[0048] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0050] It should be understood that when a layer is referred to as being "on," "adjacent to," or "connected to" another layer, it can be directly on, adjacent to, or connected to the other layer, or intervening layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another layer, there are no intervening layers.

[0051] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0052] Based on the content in the background technology, in the existing method of preparing semiconductor structures, when preparing the gate, the gate material is usually polished by chemical mechanical polishing to form the gate, but this chemical mechanical polishing method is very easy to cause a loading effect caused by chemical mechanical polishing, and there will also be defects such as uneven gate height and structural residue. Therefore, in order to solve the CMP loading effect caused by chemical mechanical polishing, a method for preparing a semiconductor structure and a semiconductor structure are proposed.

[0053] The manufacturing method of the semiconductor structure first forms a first dielectric material layer and a gate material layer on a substrate, then uses the first dielectric material layer as a stop layer, and first performs chemical mechanical polishing on the gate material layer to form a first gate intermediate layer. At this time, a first loading effect will be formed. Then, atomic layer etching is performed on the first dielectric material layer to form a first dielectric layer. Since atomic layer etching is a self-limiting chemical reaction and the etching is more precise, the etching position can be well controlled during etching. After that, a preset dry etching is performed on the first gate intermediate layer to form a gate, and this preset dry etching will generate a second loading effect. Since the first loading effect is an effect where the polishing rate is faster when the etching pattern density is larger, and the second loading effect is an effect where the polishing rate is slower when the etching pattern density is larger, that is, the second loading effect and the first loading effect are reverse loading effects. That is to say, the second loading effect has a reverse control effect on the first loading effect generated by chemical mechanical polishing, improving the first loading effect generated by chemical mechanical polishing.

[0054] In order to make the above objects, features, and advantages of the present application more obvious and understandable, the following further detailed description of the present application will be given in conjunction with the accompanying drawings and specific embodiments.

[0055] Refer to Figure 1 , Figure 1 FIG.

[0056] S101: Provide a substrate 01, and the substrate 01 has a plurality of grooves 015 (as Figure 2 shown).

[0057] S102: Form a first dielectric material layer 02 on the upper surface of the substrate 01 and the inner walls of the grooves 015 (as Figure 3 shown).

[0058] S103: Form a gate material layer 03 on the side of the first dielectric material layer 02 facing away from the substrate 01, and the gate material layer 03 fills the grooves 015 (as Figure 4 , Figure 5 shown).

[0059] S104: Use the first dielectric material layer 02 as a stop layer, and perform chemical mechanical polishing on the gate material layer 03 to form a first gate intermediate layer 04, and the chemical mechanical polishing has a first loading effect.

[0060] S105: Perform atomic layer etching on the first dielectric material layer 02 to form a first dielectric layer 05 (as Figure 7 shown).

[0061] S106: performing a preset dry etching on the first gate intermediate layer 04 to form a gate 06, wherein the preset dry etching has a second load effect, and the second load effect is an inverse load effect to the first load effect (such as Figure 10 as shown).

[0062] In the above-mentioned preparation method, a first dielectric material layer 02 and a gate material layer 03 are first formed on the substrate 01, and then the first dielectric material layer 02 is used as a stop layer, and the gate material layer 03 is first subjected to chemical mechanical polishing to form a first gate intermediate layer 04, at which a first load effect is formed, and then the first dielectric material layer 02 is subjected to atomic layer etching to form a first dielectric layer 05. Since atomic layer etching is a self-limiting chemical reaction, etching is more precise, so the etching position can be well controlled during etching. After that, the first gate intermediate layer 04 is subjected to a preset dry etching to form a gate 06, and the preset dry etching will produce a second load effect. Since the first load effect is the effect that the grinding rate is faster when the etching pattern density is greater, and the second load effect is the effect that the grinding rate is slower when the etching pattern density is greater, that is, the second load effect and the first load effect are mutually reverse load effects, that is, the second load effect has a reverse control effect on the first load effect generated by chemical mechanical polishing, thereby improving the first load effect generated by chemical mechanical polishing.

[0063] Specifically, in step S101, before preparing the semiconductor structure, a substrate 01 is first provided, and the substrate 01 has a plurality of grooves 015. The substrate 01 described herein is as follows: Figure 2 As shown, it includes a silicon substrate 011, a shallow trench isolation structure 012, a gate oxide layer 013 and a dielectric layer 014. Among them, the shallow trench isolation structure 012 is located in the silicon substrate 011, and is used to isolate the interference between different structures. The gate oxide layer 013 covers the silicon substrate 011 and the shallow trench isolation structure 012, and is used to lay the foundation for the subsequent structure preparation. The dielectric layer 014 is located on the side of the gate oxide layer 013 away from the silicon substrate 011, and serves as a zero-layer dielectric layer for isolating different components. The dielectric layer 014 is a graphic structure, that is, the dielectric layer 014 has a plurality of grooves, which are grooves 015 of the substrate 01. It should be noted that the substrate 01 provided above is only for illustration, and in actual application, it can be the substrate 01 specifically required by the semiconductor structure, and is not specifically limited here.

[0064] In step S102, Figure 3 As shown, a first dielectric material layer 02 is formed on one side of the substrate 01 , and the first dielectric material layer 02 covers the upper surface of the substrate 01 and the inner wall of the groove 015 . The first dielectric material layer 02 helps to improve the performance of the semiconductor structure.

[0065] In step S103, Figure 4As shown, on the side of the first dielectric material layer 02 facing away from the substrate 01, a gate material layer 03 is formed. The gate material layer 03 fills the groove 015. The gate material layer 03 is formed by deposition. Due to the presence of the groove, there is a height difference on the upper surface of the first dielectric material layer 02, which causes depressions and unevenness on the surface of the gate material layer 03 when depositing the gate material layer 03.

[0066] In step S104, as Figure 6 shown, in order to improve the preparation speed, using the first dielectric material layer 02 as the stop layer, chemical mechanical polishing is performed on the gate material layer 03. At this time, chemical mechanical polishing can be performed on the gate material layer 03 twice. For example, the gate material layer 03 is thinned in the first polishing, and then fine polishing is continued to form the first gate intermediate layer 04. However, when performing chemical mechanical polishing, for the gate material layer 03, the greater the gate pattern density, the faster the polishing rate, so a first loading effect will be generated, and this first loading effect will affect the performance of the semiconductor structure.

[0067] In step S105, atomic layer etching is performed on the first dielectric material layer 02 to form the first dielectric layer 05. Compared with the existing CMP polishing, since atomic layer etching is performed through a self-limiting chemical reaction etching, the etching position can be well controlled.

[0068] In step S106, as Figure 10 shown, a preset dry etching is performed on the first gate intermediate layer 04. In the place where the gate pattern density is large during this preset dry etching, due to the rapid consumption of reactive ions, the etching rate decreases instead, thus generating a second loading effect. This second loading effect and the first loading effect are reverse loading effects to each other, and instead remove the first loading effect generated by chemical mechanical polishing. Therefore, using dry etching is beneficial to reversely control the first loading effect generated by chemical mechanical polishing, that is, reducing the first loading effect.

[0069] It should be noted that when using the preset dry etching, the substrate 01 can be used as the stop layer, and the gate 06 is formed by this dry etching. The main purpose of using the preset dry etching is that the unevenness on the surface of the gate material layer 03 can be reversely controlled by adjusting parameters such as the etching gas, flow rate, and time. The surface conversion gas and flow rate parameters in different regions are adjusted to adjust the etching speed, that is, the flatness of the structure surface is further optimized through dry etching.

[0070] Optionally, referring to Figure 8 , in another embodiment of the present application, before the step of forming the first dielectric material layer 02 on the upper surface of the substrate 01 and the inner wall of the groove 015, it further includes:

[0071] A second dielectric layer 07 is formed at the bottom of the groove 015.

[0072] Specifically, the dielectric layer 014 has a groove 015 that exposes the gate oxide layer 013. On the upper surface of the gate oxide layer 013 exposed by the dielectric layer 014, that is, at the bottom of the groove 015, a second dielectric layer 07 is formed, as Figure 9 shown. The second dielectric layer 07 includes a high-K layer 071 and a TiN layer 072 arranged in sequence. The material of the high-K layer 071 is a dielectric material with a high dielectric constant. The high-K layer 071 is mainly used to increase the capacitance value of the transistor and reduce power consumption, while the TiN layer 072 is used to adjust the threshold voltage and improve the electrical characteristics of the device.

[0073] Optionally, in another embodiment of the present application, the material of the gate material layer 03 is an aluminum metal material.

[0074] Specifically, the present application focuses on improving the load effect of the gate 06 using an aluminum metal material. It should be noted that the selection of the gate material layer 03 is only for illustrative purposes.

[0075] Optionally, in another embodiment of the present application, the step of performing atomic layer etching on the first dielectric material layer 02 to form the first dielectric layer 05 includes:

[0076] Performing a first atomic layer etching on the first dielectric material layer 02 to form the first dielectric layer 05.

[0077] Specifically, when performing atomic layer etching on the first dielectric material layer 02, compared with the existing CMP polishing, since atomic layer etching is performed through a self-limiting chemical reaction, the etching position can be well controlled, so that more precise etching can be achieved, thereby avoiding the generation of load effects.

[0078] Optionally, in another embodiment of the present application, the first dielectric material layer 02 includes at least two sub-dielectric material layers (as Figure 5 shown), and the first dielectric layer 05 includes at least two sub-dielectric layers (as Figure 9 shown).

[0079] When performing the first atomic layer etching on the first dielectric material layer 02, different etching gases are used to etch each sub-dielectric material layer separately, and the remaining parts of each sub-dielectric material layer after etching form the corresponding sub-dielectric layers.

[0080] Specifically, the first dielectric layer 05 is formed by performing the first atomic layer etching on the first dielectric material layer 02, so the first dielectric layer 05 has the same layer structure as the first dielectric material layer 02. It should be noted that the materials of different sub-dielectric material layers are different, so different etching gases are used. The remaining parts after etching are the sub-dielectric layers. Different sub-dielectric layers together improve the overall performance of the semiconductor structure.

[0081] Optionally, in another embodiment of the present application, as Figure 5 shown, the first dielectric material layer 02 includes a first sub-dielectric material layer 021 and a second sub-dielectric material layer 022 sequentially arranged on one side of the substrate 01. The first sub-dielectric material layer 021 is used to adjust the work function of the semiconductor structure, and the second sub-dielectric material layer 022 is located on the side close to the gate.

[0082] Specifically, as Figure 5 shown, a third sub-dielectric material layer 023 is further included between the first sub-dielectric material layer 021 and the substrate 01. The third sub-dielectric material layer 023 can be a TaN layer, and the TaN layer can adjust the effective work function and improve the performance of the transistor. The first sub-dielectric material layer 021 can be a TiAl layer, and the TiAl layer is used to finely control the work function of the gate to optimize the threshold voltage of the transistor. The second sub-dielectric material layer 022 can be a TTN layer, and the TTN layer is mainly used to increase the capacitance value of the transistor, thereby enhancing its ability to drive current.

[0083] Optionally, in another embodiment of the present application, taking the first dielectric material layer 02 as a stop layer, the step of chemically mechanical polishing the gate material layer 03 to form the first gate intermediate layer 04 includes:

[0084] Taking the second sub-dielectric material layer 022 as a stop layer, chemically mechanical polishing the gate material layer 03 to form the first gate intermediate layer 04 (as Figure 7 shown).

[0085] Specifically, the second sub-dielectric material layer 022 can be a TTN layer, and the TTN layer can be used as a stop layer. The TTN layer includes Ti material and TiN material, and the polishing is immediately stopped when the Ti signal is detected. Thus, the gate material layer 03 is chemically mechanically polished to form the first gate intermediate layer 04.

[0086] Optionally, in another embodiment of the present application, when etching each sub-dielectric material layer, it all includes:

[0087] S201: Introduce a first reaction gas to reactively modify the sub-dielectric material layer.

[0088] S202: Introduce a second reaction gas to react with the modified sub-dielectric material layer to generate a volatile gas.

[0089] Specifically, taking the etching of three sub-dielectric material layers to form three sub-dielectric layers as an example for illustration.

[0090] When etching the second sub-dielectric material layer 022, first perform step S01: introduce O3 or H2O2 to oxidize Ti and TiN to TiO2, and then perform step S02: introduce HF to react with TiO2 to generate volatile TiF4. Repeat steps S01 and S02 multiple times until the TTN material is completely removed.

[0091] When etching the first sub-dielectric material layer 021, first perform step S11: oxidize the first sub-dielectric material layer 021, and finally generate TiO2 and Al2O3 after the oxidation treatment; then perform step S12: introduce HF to react to generate volatile TiF4, and then perform step S13: trimethylaluminum (TMA) reacts with AlF3 to generate volatile AlF(CH3)2; repeat steps S11, S12, and S13 multiple times until the TiAl material is completely removed.

[0092] When etching the third sub-dielectric material layer 023, first perform step S21: introduce C4F8, CO gas to react with TaN to generate TaF5 and fluorocarbon polymer; then perform step S22: introduce O2 to react with TaF5 / fluorocarbon polymer and use the O2 gas flow to remove the product; repeat steps S21 and S22 multiple times until the TaN material is completely removed.

[0093] It should be noted that the second sub-dielectric material layer 022, the first sub-dielectric material layer 021, and the third sub-dielectric material layer 023 are subjected to reaction modification, and then the modified sub-dielectric material layers are reacted to generate volatile gases to form the second sub-dielectric layer 052, the first sub-dielectric layer 051, and the third sub-dielectric layer 053. By using the atomic layer etching method, the CMP loading effect is avoided, and over-etching and under-etching are avoided due to more precise etching, reducing the formation of defects.

[0094] Optionally, in another embodiment of the present application, the steps of performing a preset dry etching on the first gate intermediate layer 04 to form the gate 06 include:

[0095] Perform a preset dry etching on the first gate intermediate layer 04 to form a second gate intermediate layer 041 (as Figure 8 shown);

[0096] Perform a second atomic layer etching on the second gate intermediate layer 041 to form the gate 06;

[0097] The steps of performing a second atomic layer etching on the second gate intermediate layer 041 to form the gate 06 include:

[0098] S301: Introduce a third reaction gas to perform reaction modification on the second gate intermediate layer 041.

[0099] S302: Introduce the fourth reaction gas to react with the modified second gate intermediate layer 041 to generate volatile gases.

[0100] Specifically, refer to Figure 7 , perform a preset dry etching on the first gate intermediate layer 04 to form the second gate intermediate layer 041. Refer to Figure 8 , Figure 9 , Figure 10 and Figure 11 , after performing the preset dry etching on the first gate intermediate layer 04, the first loading effect is offset by the second loading effect generated by the dry etching, forming a flat second gate intermediate layer 041. At this time, part of the second gate intermediate layer 041 may be higher than the heights of the second sub-dielectric layer 052, the first sub-dielectric layer 051, and the third sub-dielectric layer 053 (as shown in Figure 8 , Figure 9 ). In order to reduce the influence of the loading effect on the formed gate 06, atomic layer etching can be performed on the second gate intermediate layer 041 again. When etching the second gate intermediate layer 041, first perform step S31: oxidize the second gate intermediate layer 041, oxidize the metal Al to Al2O3 with O2; then perform step S32: introduce HF to react with A l2 O3 to generate AlF3, and then perform step S33: trimethylaluminum (TMA) reacts with AlF3 to generate volatile AlF(CH3)2; repeatedly cycle step S31, step S32, and step S33 until the surface of the gate 06 is flush with the first dielectric layer 05 (as shown in Figure 10 ).

[0101] The above process of the atomic layer etching method uses self-limiting chemical reactions, and each etching cycle only removes one layer of atoms, avoiding over-etching and under-etching. Therefore, a uniform and flat gate 06 can be obtained.

[0102] It should be noted that in some embodiments, the first loading effect may cause the height of the first gate intermediate layer 04 to be lower than the height of the dielectric layer 014. At this time, it is also possible to etch the dielectric layer 014 while etching the second gate intermediate layer 041, without specific limitation.

[0103] Based on the above method for preparing a semiconductor structure, refer to Figure 10 , the present application also provides a semiconductor structure prepared by the above method for preparing a semiconductor structure.

[0104] It should be noted that since the semiconductor structure is obtained by the above preparation method, it has all the above characteristics. The semiconductor structure adopts the second loading effect to offset the first loading effect generated by chemical mechanical polishing, making the loading effect smaller. And because atomic layer etching is a self-limiting chemical reaction and the etching is more precise, over-etching and under-etching can be well avoided during etching, further reducing the polishing defects while improving the loading effect.

[0105] In the description of this specification, the description with reference to terms such as "another embodiment" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0106] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0107] The above-described embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate having a plurality of grooves; forming a first dielectric material layer on the upper surface of the substrate and the inner wall of the groove; forming a gate material layer on a side of the first dielectric material layer away from the substrate, wherein the gate material layer fills the groove; Using the first dielectric material layer as a stop layer, chemical mechanical polishing is performed on the gate material layer to form a first gate intermediate layer, wherein the chemical mechanical polishing has a first loading effect; Performing atomic layer etching on the first dielectric material layer to form a first dielectric layer; The first gate intermediate layer is subjected to a preset dry etching to form a gate, wherein the preset dry etching has a second load effect, and the second load effect and the first load effect are reverse load effects to each other.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of performing atomic layer etching on the first dielectric material layer to form a first dielectric layer includes: Performing a first atomic layer etching on the first dielectric material layer to form the first dielectric layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The first dielectric material layer includes at least two sub-dielectric material layers, and the first dielectric layer includes at least two sub-dielectric layers; When performing the first atomic layer etching on the first dielectric material layer, different etching gases are used to etch each of the sub-dielectric material layers respectively, and the remaining part of each of the sub-dielectric material layers after etching forms the corresponding sub-dielectric layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: When each of the sub-medium material layers is respectively etched, the steps include: Passing a first reaction gas to react and modify the sub-medium material layer; A second reaction gas is introduced to react with the modified sub-dielectric material layer to generate a volatile gas.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of performing a preset dry etching on the first gate intermediate layer to form a gate comprises: Performing a preset dry etching on the first gate intermediate layer to form a second gate intermediate layer; Performing a second atomic layer etching on the second gate intermediate layer to form the gate; The step of performing a second atomic layer etching on the second gate intermediate layer to form the gate includes: Passing a third reaction gas to react and modify the second gate intermediate layer; A fourth reaction gas is introduced to react with the modified second grid intermediate layer to generate a volatile gas.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first dielectric material layer includes a first sub-dielectric material layer and a second sub-dielectric material layer sequentially arranged on one side of the substrate, the first sub-dielectric material layer is used to adjust the work function of the semiconductor structure, and the second sub-dielectric material layer is located on a side close to the gate.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The step of using the first dielectric material layer as a stop layer and performing chemical mechanical polishing on the gate material layer to form a first gate intermediate layer comprises: The second sub-dielectric material layer is used as a stop layer, and the gate material layer is subjected to chemical mechanical polishing to form the first gate intermediate layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before the step of forming a first dielectric material layer on the upper surface of the substrate and the inner wall of the groove, the method further includes: A second dielectric layer is formed at the bottom of the groove.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The gate material layer is made of aluminum metal.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared according to the method for preparing a semiconductor structure according to any one of claims 1 to 9.

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