Method, device and medium for determining effectiveness of interconnection line

Abstract

The embodiment of the invention relates to a method and equipment for determining the effectiveness of an interconnection line and a medium. The method provided by the invention comprises the following steps: for a given line segment in a target interconnection line network, determining a conductivity change on the given line segment after the given line segment has a given structure change, the given structure change of the given line segment being determined based on a simulation morphology of the given line segment after a target process; based on the conductance change of the given line segment, determining the electrical attribute change of a given node in the target interconnection network along with the conductance change; and determining an evaluation result about the effectiveness of the target interconnection network after the target process at least based on whether the electrical attribute change of the given node meets a predetermined electrical attribute requirement or not.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to the field of semiconductor technology, and more particularly, to a method, apparatus, and medium for determining the effectiveness of an interconnect line. Background Art

[0002] Interconnects, as an indispensable component of chips, are responsible for providing the necessary energy support and transmitting signals for core components such as logic circuits on the chip. Interconnects play a vital role in ensuring the overall performance and stable operation of the chip. Once an interconnect fails or fails, the chip may not work properly or even be completely paralyzed. Summary of the invention

[0003] In a first aspect of the present disclosure, a method for determining the effectiveness of an interconnect is provided. The method comprises: for a given line segment in a target interconnect network, determining a change in the conductance of the given line segment after a given structural change occurs, wherein the given structural change of the given line segment is determined based on a simulated morphology of the given line segment after undergoing a target process; based on the change in the conductance of the given line segment, determining a change in the electrical properties of a given node in the target interconnect network with the change in conductance; and determining an evaluation result on the effectiveness of the target interconnect network after undergoing the target process based at least on whether the change in the electrical properties of the given node meets a predetermined electrical property requirement.

[0004] In a second aspect of the present disclosure, an electronic device is provided. The device includes at least one processing unit; and at least one memory, the at least one memory is coupled to the at least one processing unit and stores instructions for execution by the at least one processing unit. When the instructions are executed by the at least one processing unit, the device executes the method of the first aspect.

[0005] In a third aspect of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and the computer program can be executed by a processor to implement the method of the first aspect.

[0006] In a fourth aspect of the present disclosure, a computer program product is provided, which includes computer executable instructions, which, when executed by a processor, implement the method according to the first aspect of the present disclosure.

[0007] It should be understood that the contents described in this content section are not intended to limit the key features or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0009] Figure 1 A schematic diagram showing an example environment in which various embodiments of the present disclosure can be implemented;

[0010] Figure 2 A flowchart showing an example process of a method for determining the validity of an interconnect according to some embodiments of the present disclosure;

[0011] Figure 3 A schematic diagram showing an example process of determining a change in conductance according to some embodiments of the present disclosure;

[0012] Figure 4 A schematic diagram illustrating an example process of determining a change in an electrical property according to some embodiments of the present disclosure;

[0013] Figure 5 A schematic diagram illustrating an example process of determining an adjusted structure according to some embodiments of the present disclosure; and

[0014] Figure 6 A block diagram of an electronic device is shown in which one or more embodiments of the present disclosure may be implemented. DETAILED DESCRIPTION

[0015] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0016] It should be noted that the titles of any sections / subsections provided herein are not restrictive. Various embodiments are described throughout this article, and any type of embodiment may be included under any section / subsection. In addition, the embodiments described in any section / subsection may be combined in any manner with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0017] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may be included below. The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may be included below.

[0018] The embodiments of the present disclosure may involve user data, data acquisition and / or use, etc. These aspects are subject to the corresponding laws, regulations and relevant provisions. In the embodiments of the present disclosure, all data collection, acquisition, processing, processing, forwarding, use, etc. are carried out on the premise that the user knows and confirms. Accordingly, when implementing each embodiment of the present disclosure, the type, scope of use, usage scenario, etc. of the data or information that may be involved should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with the relevant laws and regulations. The specific notification and / or authorization method can vary according to the actual situation and application scenario, and the scope of the present disclosure is not limited in this respect.

[0019] In this specification and the embodiments, if personal information processing is involved, it will be processed on the premise of having a legal basis (such as obtaining the consent of the subject of personal information, or it is necessary to perform a contract, etc.), and will only be processed within the scope of regulations or agreements. If a user refuses to process personal information other than the necessary information for basic functions, it will not affect the user's use of basic functions.

[0020] As briefly described above, interconnects are crucial to the effective operation of chips. During the chip manufacturing process, certain process steps may have adverse effects on the morphology of interconnects, which may lead to abnormal chip operation.

[0021] The following description is based on Chemical Mechanical Polishing (CMP) as an example. CMP flattens the metal layer of the interconnect obtained by processes such as the dual Damascus process by combining mechanical grinding and chemical etching, thereby constructing a multi-layer interconnect network. However, during the implementation of the CMP process, the morphology of the interconnect network may be damaged to a certain extent, causing it to deviate from the original design morphology. This morphological deviation may further cause electrical properties such as resistance in the interconnect network to deviate from the design requirements, thereby affecting the voltage drop of each node in the interconnect network, and ultimately causing some components on the chip to fail to work properly (for example, the voltage of some components exceeds the predetermined voltage range, etc.).

[0022] In view of this, an embodiment of the present disclosure provides a scheme for determining the effectiveness of interconnects. According to the scheme, for a given line segment in a target interconnect network, the conductivity change on the given line segment after a given structural change occurs is determined, wherein the given structural change of the given line segment is determined based on the simulated morphological change of the given line segment after the target process. Next, based on the conductivity change of the given line segment, the electrical property change of a given node in the target interconnect network with the conductivity change is determined. Then, based at least on whether the electrical property change of the given node meets the predetermined electrical property requirements, an evaluation result on the effectiveness of the target interconnect network after the target process is determined.

[0023] It will be more clearly understood through the following description that the scheme of the present disclosure determines the change in conductivity of a given line segment after the target process (such as CMP) by simulating the morphological change of the interconnection network (such as the target interconnection network). This simulation is based on the actual process parameters and the physical properties of the interconnection line, and can accurately reflect the direct impact of the target process on the conductivity of the given line segment. The scheme of the present disclosure also further determines the change in the electrical properties of a given node in the target interconnection network based on the change in the conductivity of the given line segment. The electrical properties include but are not limited to voltage and / or current. The electrical properties of a given node are directly related to the working performance of the components electrically connected to the given node on the chip. By determining whether the change in the electrical properties of a given node meets the predetermined electrical property requirements, the scheme of the present disclosure can accurately determine whether the interconnection network can make the corresponding components work effectively after the target process. If the evaluation result indicates that the interconnection network is an invalid interconnection network, it means that the interconnection network cannot make the corresponding components work effectively after the target process. In this case, the staff or the system can adjust the process parameters or take remedial measures in time to avoid problems in the subsequent processing or use of the chip. This can not only improve the chip yield, but also reduce production costs.

[0024] Various example implementations of the solution will be described in detail below in conjunction with the accompanying drawings.

[0025] Figure 1 A schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented is shown. The example environment 100 may generally include an electronic device 110.

[0026] Reference Figure 1, the electronic device 110 obtains the interconnection network file 130 of the target chip 120. In an embodiment of the present disclosure, the interconnection network file 130 may include one or more information related to the interconnections in the target chip 120. For example, the interconnection network file 130 may include information related to the connection relationship, physical properties, and electrical properties of the interconnections. The interconnection network file 130 may take a variety of forms. For example, the interconnection network file 130 may be a netlist file (netlist), which can list the connection relationship of all components or lines in the interconnections in text form. For another example, the interconnection network file 130 may be a layout file, such as a Graphic Data System (GDS) file. The layout file may include layout information of the interconnections, and the layout information includes but is not limited to the position and shape of the interconnections.

[0027] In an embodiment of the present disclosure, the electronic device 110 may interact with a client (not shown in the figure). The client may be a computer, a server, or any other appropriate device. The electronic device 110 may receive an input message from the client and output a feedback message to the client. In an embodiment of the present disclosure, the input message from the client may include an evaluation request for the interconnect network in the target chip 120. The evaluation request indicates the target process, a given node that needs to be paid attention to in the interconnect network, and a given line segment, etc. After receiving the evaluation request, the electronic device 110 will analyze the electrical properties of the given node and the given line segment in the interconnect network, and then output the evaluation result 140 of the target interconnect network to the client as a feedback message for the evaluation request.

[0028] In the example environment 100 , the electronic device 110 may be any type of device with computing capabilities, such as a terminal device or a server device.

[0029] In some embodiments, the terminal device can be any type of mobile terminal, fixed terminal or portable terminal, including a mobile phone, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a media computer, a multimedia tablet, a personal communication system (PCS) device, a personal navigation device, a personal digital assistant (PDA), an audio / video player, a digital camera / camcorder, a positioning device, a television receiver, a radio broadcast receiver, an e-book device, a gaming device or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof.

[0030] In some embodiments, the server device may be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content distribution networks, and big data and artificial intelligence platforms. The server device may include, for example, a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and the like.

[0031] It should be understood that the structure and function of the various elements in the environment 100 are described for exemplary purposes only and do not imply any limitation on the scope of the present disclosure.

[0032] Figure 2 A flowchart of an example process 200 of a method for determining interconnect validity according to some embodiments of the present disclosure is shown. The process 200 may be implemented at the electronic device 110.

[0033] Reference Figure 2 At block 210, for a given line segment in the target interconnect network, the electronic device 110 determines a change in conductance on the given line segment after a given structural change occurs in the given line segment. The given structural change of the given line segment is determined based on a simulated morphology of the given line segment after the target process.

[0034] In some embodiments, in response to receiving an evaluation request for the validity of a target interconnect network, the electronic device 110 executes block 210. As an example, the evaluation request may indicate a target process, and a given node and a given line segment in the target interconnect network. The given node is electrically connected to the given line segment. As an example, the target interconnect network may refer to an interconnect network that currently needs to be evaluated in the target chip 120. The evaluation here may be to evaluate whether the target interconnect network is a valid interconnect network after the target process. As an example, the electrical connection of a given node in the target interconnect network to a given line segment may refer to the ability to transmit electrical signals between the given node and the given line segment. The electrical signal here includes, but is not limited to, a current or voltage signal.

[0035] The target interconnect network can be composed of multiple nodes and multiple line segments connected between these nodes. As an example, the nodes of the target interconnect network can correspond to the contact points of each component on the target chip 120. As an example, such contact points include but are not limited to the upper and lower ends of the through hole for electrical connection on the target chip 120, the contact points for connecting the external power supply, and the contact points for connecting the target chip 120 logic circuit, etc. As an example, the multiple line segments in the target interconnect network include any wire with conductive properties. Such wires include but are not limited to copper wires, aluminum wires, or wires of other materials, etc.

[0036] As an example, a given node in the target interconnect network may refer to one or more nodes in the target interconnect network that need to be concerned. These nodes may be signal input points, signal output points, or intermediate connection points in the target interconnect network. As an example, a given line segment in the target interconnect network may refer to one or more line segments in the target interconnect network that need to be concerned. These line segments connect different nodes in the target interconnect network and are used to provide energy to these nodes or transmit electrical signals.

[0037] In some embodiments, the given structural change of the given line segment at least indicates a change in cross-sectional area of ​​the given line segment after the target process. The electronic device 110 determines the conductivity change of the given line segment based at least on the change in cross-sectional area of ​​the given line segment after the target process and the conductivity of the given line segment.

[0038] The cross-sectional area of ​​a given line segment may refer to the projected area of ​​the given line segment on a plane perpendicular to its length direction. The cross-sectional area of ​​a given line segment directly affects the conductivity characteristics of the given line segment. As an example, the electronic device 110 may determine the simulated morphology of the given line segment after the target process through any appropriate CMP simulator, and then determine the change in the cross-sectional area of ​​the given line segment. As an example, such CMP simulators include but are not limited to the Calibre CMP Analyzer tool and / or the CMP Predictor tool, etc.

[0039] The conductivity of a given line segment is an inherent property of the material used for the given line segment. The conductivity of a given line segment represents the current passing capacity of a given line segment per unit cross-sectional area and unit length under unit voltage. Therefore, when the cross-sectional area of ​​a given line segment changes, even if the conductivity remains unchanged, the conductivity (i.e., the ability of current to pass) of the given line segment will also change. For example, if the cross-sectional area of ​​a given line segment increases, the conductivity of the given line segment will increase. Conversely, if the cross-sectional area of ​​a given line segment decreases, the conductivity of the given line segment will decrease. The electronic device 110 can calculate the specific change in conductivity by simulating or actually measuring the change in cross-sectional area and combining it with the known conductivity. As an example, the electronic device 110 can calculate the change in conductivity of a given line segment based on any appropriate algorithm or model.

[0040] Figure 3 A schematic diagram of an example process 300 for determining a change in conductance according to some embodiments of the present disclosure is shown. Figure 3 And equation (1) and equation (2) describe more details of block 210.

[0041] At block 310 , the electronic device 110 simulates a change in cross-sectional area of ​​a given line segment in a target interconnect network after a CMP process.

[0042] As an example, the change in cross-sectional area of ​​a given line segment after the CMP process, ΔS, can be calculated using formula (1):

[0043]

[0044] where w j is the width of a given line segment j, T d For metal disc data, T e This is the dielectric oxide layer corrosion data.

[0045] At block 320 , the electronic device 110 determines a change in conductance of the given line segment after the CMP process based on the change in cross-sectional area ΔS of the given line segment, the conductivity of the given line segment, and the length of the given line segment.

[0046] As an example, the conductance change Δg of a given line segment j after the CMP process is j It can be expressed by formula (2):

[0047]

[0048] Among them l j is the length of a given line segment j, and σ is the conductivity of a given line segment j. In this way, the conductivity change of a given line segment after a target process can be quickly and accurately determined.

[0049] It should be noted that, in addition to the change in cross-sectional area, the given structural change of a given line segment may also indicate other structural changes. For example, according to actual needs, the given structural change may also indicate changes in length, width, material and / or connection mode of the given line segment.

[0050] In some embodiments, the target interconnect network is determined in the following manner: the electronic device 110 removes line segments whose resistance is greater than a first resistance threshold in the initial interconnect network to obtain the target interconnect network. Alternatively or additionally, the electronic device 110 merges the endpoints of line segments whose resistance is less than a second resistance threshold in the initial interconnect network to obtain the target interconnect network.

[0051] As an example, the initial interconnect network may refer to part or all of the interconnect networks in the target chip 120. The first resistance threshold may be a pre-set larger resistance value (compared to the second resistance threshold). The first resistance threshold is used to determine which segments in the initial interconnect network have too large resistance, and the excessive resistance indicates that these segments can be equivalent to open circuits. The electronic device 110 can remove these segments, so that the parts of the interconnects that have less electrical influence on each other can be separated. The second resistance threshold may be a pre-set smaller resistance value (compared to the first resistance threshold). The second resistance threshold is used to determine which segments in the initial interconnect network have too small resistance, and the too small resistance indicates that these segments can be equivalent to short circuits. The electronic device 110 can merge the two endpoints of these segments into one endpoint, thereby reducing the number of segments and / or nodes in the interconnect network to reduce the subsequent amount of calculation.

[0052] In some embodiments, the electronic device 110 determines a plurality of interconnect subnetworks in the initial interconnect network. The plurality of interconnect subnetworks are insulated from each other. Then, the electronic device 110 determines a first interconnect subnetwork set including a given node and a second interconnect subnetwork set including a given line segment from the plurality of interconnect subnetworks. Then, the electronic device 110 determines a target interconnect network by merging the first interconnect subnetwork set with the second interconnect subnetwork set.

[0053] As an example, multiple interconnection sub-networks being insulated from each other may mean that different interconnection sub-networks are electrically isolated from each other. Such isolation can prevent electrical signals from being transmitted between different interconnection sub-networks, thereby avoiding problems such as short circuits, interference or signal leakage.

[0054] As an example, the first interconnect subnetwork set may refer to an interconnect subnetwork including multiple nodes (i.e., given nodes) determined by the electronic device 110 from multiple interconnect subnetworks. The second interconnect subnetwork set may refer to an interconnect subnetwork including multiple segments (i.e., given segments) determined by the electronic device 110 from multiple interconnect subnetworks.

[0055] As an example, assume that the given nodes are multiple nodes in the target interconnection network, and the given line segments are multiple line segments in the target interconnection network. The node labels of the multiple nodes are i 0 ,i 1 ,…,i m ,i 0 ,i 1 ,…,i m Interconnect Sub-Network The line segment labels of multiple line segments are j 0 ,j 1 ,…,j n , j0 ,j 1 ,…,j n Interconnect Sub-Network Then the target interconnection subnetwork R can be expressed by formula (3):

[0056]

[0057] Wherein m and n are both positive integers.

[0058] In this way, the electronic device 110 can remove the parts of the initial interconnection line network that are not related to the given node and the given line segment, thereby reducing the complexity and redundancy of the target interconnection line sub-network R.

[0059] In some embodiments, the electronic device 110 determines a graph structure corresponding to the initial interconnect network. The nodes in the graph structure correspond to the nodes in the initial interconnect network, and the edges in the graph structure correspond to the line segments in the initial interconnect network. Then, the electronic device 110 determines the connectivity between the nodes in the graph structure based on the nodes in the graph structure and the edges connected between the nodes. Then, the electronic device 110 divides the graph structure into a plurality of connected graphs based on the determined connectivity. Next, the electronic device 110 determines a plurality of interconnect sub-networks based on the nodes and line segments in the initial interconnect network corresponding to the divided plurality of connected graphs.

[0060] As an example, a graph structure may refer to a data structure composed of nodes (or also referred to as vertices) and edges (or also referred to as lines). A graph structure is used to represent the relationship between entities. In a graph structure, nodes represent entities, and edges represent the relationship between entities. In an embodiment of the present disclosure, the nodes in the graph structure correspond one-to-one to the nodes in the initial interconnection network, and the edges in the graph structure correspond one-to-one to the line segments in the initial interconnection network. This correspondence ensures that the graph structure can accurately reflect the connection relationship of the initial interconnection network.

[0061] As an example, in a graph structure, if there is a path (e.g., a series of continuous edges) between two nodes, the two nodes can be considered to be connected. The electronic device 110 can determine the connectivity between the nodes in the graph structure by any appropriate algorithm. As an example, the algorithm here can include but is not limited to a depth-first search algorithm and / or a breadth-first search algorithm. Such an algorithm can traverse all nodes and edges in the graph structure to find all connected node pairs.

[0062] As an example, in a graph structure, a connected graph may refer to a graph in which any two nodes are connected nodes. As an example, the electronic device 110 may find the nodes and line segments corresponding to each connected graph in the initial interconnection network according to the divided multiple connected graphs. Then, for the nodes and line segments corresponding to each connected graph, the electronic device 110 may divide these nodes and line segments into the same interconnection sub-network, thereby obtaining the nodes and line segments corresponding to the connected graphs. Figure 1 A corresponding interconnection line sub-network.

[0063] In this way, the electronic device 110 can convert the initial interconnection network into a graph structure, and then determine the interconnection sub-network from the initial interconnection network based on the connectivity of the graph structure. This process helps the electronic device 110 better understand the connection relationship between each node and / or line segment in the interconnection network, and provides an effective basis for subsequent interconnection analysis.

[0064] Once the conductance change of the given line segment is determined, at block 220 , the electronic device 110 determines the change of the electrical property of a given node in the target interconnect network as the conductance change occurs based on the conductance change of the given line segment.

[0065] Electrical properties may be properties used to describe the electrical state of a node. For example, electrical properties may include, but are not limited to, voltage, current, resistance, and electromigration, etc. As an example, the structure of a line segment may include, but are not limited to, the length, width, material, and connection method of the line segment. Structural changes in a line segment may directly affect the electrical properties of the line segment (such as conductivity, resistance, capacitance, inductance, etc.), and thus affect the electrical properties of the node electrically connected to the line segment. This relationship can be described by the change in electrical properties corresponding to each node. As an example, electrical property changes may refer to any features that can reflect changes in electrical properties with changes in line segment conductivity, and the representation of these features may be determined based on any appropriate method (such as a historical change relationship).

[0066] In some embodiments, the electronic device 110 determines a target vector for an electrical property. The elements in the target vector correspond to nodes in the target interconnect network, and the value of each element in the target vector is the current value of the electrical property of each node determined based on the conductivity matrix of the target interconnect network. Then, the electronic device 110 updates the value of each element in the target vector based on at least the conductivity change and the conductivity matrix. Subsequently, the electronic device 110 determines the change in the electrical property of a given node with the change in conductivity based on the change in the value of each element in the target vector caused by the update.

[0067] As an example, the elements in the target vector correspond to the nodes in the target interconnect network one by one. The electronic device 110 can specifically quantify the degree of influence of the conductivity change on the electrical properties of each node (especially a given node) in the target interconnect network based on the target vector. As an example, if the electrical property includes voltage, the value of each element in the target vector can be the initial voltage value of the corresponding node before the conductivity change. If the electrical property includes current, the value of each element in the target vector can be the initial current value of the corresponding node before the conductivity change, and so on.

[0068] In an interconnect network, the change in the conductivity of a given line segment will not only affect its own electrical properties, but also the electrical properties of the nodes electrically connected to the given line segment. The electrical properties of a given node are affected differently by the change in the conductivity of a given line segment, depending on the location of the given node in the target interconnect network or the elements connected to it. For example, for a node directly connected to a given line segment, the change in conductivity may have a greater impact; while for an indirectly connected node, the impact may be smaller. The electronic device 110 can take into account the difference in such impact through the conductivity matrix of the target interconnect network, thereby accurately evaluating the actual impact of the conductivity change on a given node.

[0069] After determining the conductance change and the conductance matrix, the electronic device 110 updates the value of each element in the target vector based on the conductance change and the conductance matrix. As an example, the target value of each element in the target vector can be determined by any appropriate algorithm. For example, assuming that each element in the target vector indicates the voltage of the corresponding node, the electronic device 110 can solve the voltage of each node based on a nodal analysis method or a modified nodal analysis method.

[0070] After the target vector is updated, the change in the value of each element reflects the degree of influence of the conductivity change on the electrical properties of the corresponding node. As an example, if the electrical property includes voltage, the updated value of each element in the target vector may be the voltage value of the corresponding node after the conductivity change. If the electrical property includes current, the updated value of each element in the target vector may be the current value of the corresponding node after the conductivity change, and so on.

[0071] In some embodiments, the electronic device 110 determines a reference vector. The elements in the reference vector correspond to nodes in the target interconnect network, and in the reference vector, the elements corresponding to the reference nodes connected to at least one end of a given line segment have valid values, and the elements corresponding to other nodes other than the reference nodes have invalid values. The valid values ​​are determined based on the conductance change. Then, the electronic device 110 updates the value of each element in the target vector based at least on the product of the reference vector and the conductance matrix.

[0072] As an example, the reference node can be a node connected to either end of a given line segment, or two nodes connected to opposite ends of a given line segment. When the conductivity of a given line segment changes, the nodes connected to either end of the given line segment are most affected, so in the reference vector, the element corresponding to the reference node is set to a valid value, and this valid value is determined based on the conductivity change. In addition to the reference node, the elements corresponding to other nodes in the reference vector have invalid values. In this way, the electronic device 110 can focus on the nodes most affected by the conductivity change during the calculation process, thereby improving the accuracy and efficiency of the analysis.

[0073] As an example, in the reference vector, the initial value of the element corresponding to the reference node can be set to "1", and the final value of the element can be determined by performing any appropriate mathematical operation on the initial value and the conductivity change. In addition, in the reference vector, the initial value of the element corresponding to other nodes can be set to "0". It should be noted that the above is only an exemplary description. According to actual needs, the valid values ​​and invalid values ​​in the reference vector can also be represented by other methods, and the embodiments of the present disclosure are not limited thereto.

[0074] The electronic device 110 updates the value of each element in the target vector based at least on the product of the reference vector and the conductivity matrix. The electronic device 110 can obtain a result vector reflecting the current flow and mutual influence between nodes after the conductivity change occurs in the given line segment by calculating at least the product of the reference vector and the conductivity matrix. Each element in the result vector represents the possible change amount of the corresponding element in the target vector.

[0075] As an example, the electronic device 110 may update the target vector by adding the target vector to the result vector. In addition, the operation here may also include a multiplication operation or a more complex function operation, etc., which is not limited by the embodiments of the present disclosure. The new target vector can reflect the new value of the electrical property of a given node after a given change occurs in the structure of a given line segment.

[0076] In some embodiments, the conductance matrix is ​​a conductance matrix obtained by performing matrix decomposition on an original conductance matrix of the target interconnect network.

[0077] As an example, matrix decomposition can refer to decomposing a conductivity matrix into the product of two or more matrices. This decomposition not only helps to simplify the complex conductivity matrix, but also reveals the inherent structure and properties of the conductivity matrix. As an example, the predetermined matrix decomposition strategy can include any appropriate decomposition strategy. For example, the predetermined matrix decomposition strategy includes but is not limited to singular value decomposition (SVD), QR decomposition, LU decomposition, etc.

[0078] Through the matrix decomposition strategy, the electronic device 110 can more deeply understand the intrinsic structure and properties of the conductivity matrix, extract useful information, and simplify complex calculation processes.

[0079] After the target vector is updated, the electronic device 110 may determine the change in the electrical property of the given node as the conductance changes based on the change in the value of each element in the target vector caused by the update.

[0080] In some embodiments, the change in electrical properties can be represented by a mathematical expression or a functional relationship, so as to facilitate the electronic device 110 to understand and predict the impact of the change in the conductivity of the line segment on the electrical properties of the node. For example, the change in electrical properties can be represented by a voltage gradient that changes with the conductivity of a given line segment. For another example, the change in electrical properties can also be represented by a current density gradient or an electric field strength gradient that changes with the conductivity of a given line segment.

[0081] Figure 4 A schematic diagram of an example process 400 for determining a change in an electrical property according to some embodiments of the present disclosure is shown. In the following, the electrical property includes voltage, and the change in the electrical property is represented by a voltage gradient that varies with the conductance of a given line segment. Figure 4 And equations (4) to (13) describe more details of block 220.

[0082] In block 410, the electronic device 110 obtains a voltage column vector and a conductance matrix of a target interconnect network. As an example, the voltage column vector and the conductance matrix can be expressed by formula (4):

[0083] G 0 v 0 =I 0 ; (4)

[0084] Among them G 0 is the conductivity matrix, I 0 is the current column vector, v 0 is the voltage column vector. The voltage column vector v 0 This is the initial target vector.

[0085] In block 420, the electronic device 110 decomposes the conductance matrix G by using a matrix decomposition strategy. 0 As an example, the matrix decomposition strategy may include LU decomposition, and such a decomposition process may be expressed by formula (5):

[0086] G 0 =LU; (5)

[0087] Where L is a lower triangular matrix and U is an upper triangular matrix.

[0088] In block 430, the electronic device 110 generates a signal based on the reference vector and the decomposed conductivity matrix G. 0 , determine the updated voltage column vector (That is, the updated target vector). As an example, this process can be determined by formula (6) and formula (7):

[0089]

[0090] where ε j represents the conductivity g of a given line segment j j The change in e p For only the p position is 1 and the other positions are 0, it has the same Column vectors of the same dimension, e q For only the q position is 1 and the other positions are 0, it has the same Column vectors of the same dimension, p and q are the node labels of the two reference nodes connected to a given line segment j, u j is the reference vector (only the q and p positions are valid values, and the rest are invalid values), represents the reference vector u j The transpose of Denotes the conductivity matrix G 0 The inverse matrix of .

[0091] As an example, formula (6) can be further simplified to obtain formula (8) to formula (10):

[0092]

[0093] where x p is the reference node p with respect to the conductivity matrix G 0 The column vector, x q For the reference node q, the conductivity matrix G 0 , is the column vector x p The value of the element corresponding to the reference node p in , is the column vector x q The value of the element corresponding to the reference node q in is the column vector x p The value of the element corresponding to the reference node q in is the column vector x q The value of the element corresponding to the reference node p in is the voltage column vector v 0 The value of the element corresponding to the reference node q in is the voltage column vector v 0 The value of the element in corresponding to the reference node p. is the change in each element in the target vector (such as the result vector described above), which reflects the impact of the conductivity change on each node in the given node.

[0094] As an example, the column vector x p and the column vector x q It can be determined based on the lower triangular matrix L and the upper triangular matrix U by forward and / or backward substitution.

[0095] In block 440 , the electronic device 110 determines the effect of the conductance change on the electrical property changes of nodes in the target interconnect network R based on the change in the value of each element in the voltage column vector caused by the update, and then determines the electrical property changes of a given node with the conductance change.

[0096] As an example, the change in electrical properties can be represented by a voltage gradient, which can be expressed by calculating the voltage v i Conductivity g j The derivative of To determine, where the voltage v i Represents the updated voltage column vector The voltage indicated by the element corresponding to a given node i in . As an example, the voltage v can be determined by approximating the differential using the difference. i The conductivity g of a given line segment j j The derivative of Such a derivative The column vector x p and the column vector x q As an example, the derivative It can be expressed by formula (11):

[0097]

[0098] in is the voltage column vector v 0 The value of the element corresponding to a given node i in is the voltage column vector The value of the element corresponding to a given node i in is the column vector x p The value of the element corresponding to a given node i in is the column vector x q The value of the element in corresponding to a given node i.

[0099] As an example, when a given node i is a plurality of nodes in the target interconnect network R, the change of the electrical properties of each node can be represented by a Jacobian matrix, which can be shown as formula (12):

[0100]

[0101] in Represents node i 0 For line segment j 0 The electrical properties of Represents node i 0 For line segment j 1 The electrical properties of Represents node i m For line segment j n The electrical properties of the device change, and so on.

[0102] Once the electrical property variation of the given node is determined, at block 230 , the electronic device 110 determines an evaluation result regarding the effectiveness of the target interconnect network after undergoing the target process based at least on whether the electrical property variation of the given node meets a predetermined electrical property requirement.

[0103] As an example, the predetermined electrical property requirement may be set according to factors such as the design specification, performance target, and operating conditions of the target chip 120. The predetermined electrical property requirement may indicate the electrical performance that the target interconnect network needs to meet when the target chip 120 is operating normally, such as keeping a given node in the target interconnect network within a predetermined voltage range.

[0104] As an example, the electronic device 110 may compare the electrical property change of a given node with the predetermined electrical property requirement. If the electrical property change of a given node is within the range limited by the predetermined electrical property requirement, the electronic device 110 may consider that the electrical property change of the given node meets the predetermined electrical property requirement. In this case, the electronic device 110 may further determine that the target interconnect network is a valid interconnect network after the target process. The valid interconnect network indicates that the target interconnect network can still maintain the required electrical performance after the target process. If the electrical property change of a given node is outside the range limited by the predetermined electrical property requirement, the electronic device 110 may consider that the electrical property change of the given node does not meet the predetermined electrical property requirement. In this case, the electronic device 110 may further determine that the target interconnect network is an invalid interconnect network after the target process. The invalid interconnect network indicates that the target interconnect network cannot maintain the required electrical performance after the target process.

[0105] In some embodiments, the electronic device 110 determines the attribute value of the electrical attribute of the given node after the conductance change occurs in the given line segment based on the electrical attribute change and the conductance change. Next, the electronic device determines that the electrical attribute change of the given node meets the predetermined electrical attribute requirement in response to the attribute value of the given node being within a predetermined range. Alternatively or additionally, the electronic device determines that the electrical attribute change of the given node does not meet the predetermined electrical attribute requirement in response to the attribute value of the given node being outside the predetermined range.

[0106] In some embodiments, the electronic device 110 may use the change in the electrical property of a given node and the change in the conductivity of a given line segment as inputs, and calculate the change in the property value of the electrical property of the given node after the conductivity change by establishing an electrical model or using a simulation tool. Then, the electronic device 110 may determine the final property value of the electrical property of the given node after the conductivity change by superimposing the current property value of the electrical property of the given node with the change in the property value.

[0107] As an example, following the formula (12) above, the change Δv of the electrical property value of a given node after the conductance changes can be expressed by formula (13):

[0108]

[0109] in is line segment j 0 The change in conductivity, is line segment j 1 The conductivity change of is line segment j n The conductivity changes, and so on.

[0110] Next, the electronic device 110 can compare the attribute value of the electrical property of the given node with the predetermined range. If the attribute value of the electrical property of the given node is within the predetermined range, the electronic device 110 can determine that the change in the electrical property of the given node meets the predetermined electrical property requirements. This means that the interconnect network can still maintain the electrical performance required for the given node after undergoing the target process, and will not adversely affect the operation of the target chip 120. On the contrary, if the attribute value of the electrical property of the given node is outside the predetermined range, the electronic device 110 can determine that the change in the electrical property of the given node does not meet the predetermined electrical property requirements. This means that after the target process, the electrical performance of the given node of the interconnect network has deviated from the design requirements, which may cause the target chip 120 to work abnormally or degrade in performance.

[0111] In some embodiments, the electronic device determines that the target interconnect network is a valid interconnect network after the target process in response to the electrical property change of the given node meeting the predetermined electrical property requirement. Also, the electronic device determines that the target interconnect network is an invalid interconnect network after the target process in response to the electrical property change of the given node not meeting the predetermined electrical property requirement.

[0112] In some embodiments, the electrical property change includes a voltage change, and the predetermined electrical property requirement indicates that the voltage drop on a given node is less than a predetermined voltage drop. As an example, the predetermined voltage drop can be represented by a voltage drop threshold value, which is used to measure the degree of voltage drop on a given node. The predetermined voltage drop indicates that the voltage drop amount of a given node must be less than the predetermined voltage drop during the operation of the target interconnect line, thereby ensuring that each component on the target interconnect line can be effectively operated.

[0113] In some embodiments, in the target interconnect network, the predetermined voltage drop of nodes at different positions can be determined according to the expected voltage of the node. As an example, for the node connected to the positive pole of the external power supply in the target interconnect network, the expected voltage should be greater than or equal to 90% to 95% of the power supply voltage. For the node connected to the negative pole of the external power supply in the target interconnect network, the expected voltage should be less than or equal to 5% to 10% of the power supply voltage. In addition, the expected voltages of these nodes can also be set to other values, which can be determined according to actual needs, and the embodiments of the present disclosure are not limited to this.

[0114] As an example, it is assumed that the predetermined electrical property requirement indicates that the voltage drop of a given node does not exceed 5%. If the electronic device 110 determines that the actual voltage drop of a given node after the target process is 4%. Then, the electronic device 110 can determine that the actual voltage drop of the given node meets the requirement after comparing the actual voltage drop of the given node with the predetermined electrical property requirement. Then, the electronic device 110 can further determine that the target interconnection network is a valid interconnection network after the target process, and the valid interconnection network means that the given node still meets the requirements in terms of voltage drop performance after the interconnection network passes through the target process. If the electronic device 110 determines that the actual voltage drop of a given node after the target process is 6%. Then, the electronic device 110 can determine that the actual voltage drop of a given node does not meet the requirements after comparing the actual voltage drop of a given node with the predetermined electrical property requirement. Then, the electronic device 110 can further determine that the target interconnection network is an invalid interconnection network after the target process, and the invalid interconnection network means that the given node does not meet the requirements in terms of voltage drop performance after the interconnection network passes through the target process.

[0115] Based on the evaluation result, the electronic device 110 may take further measures, such as adjusting process parameters, optimizing interconnection line design, or performing other necessary repair work to ensure that the target interconnection line network can meet the predetermined electrical property requirements, so as to ensure that the target chip 120 can work normally.

[0116] In some embodiments, in response to determining that the target interconnect network is an invalid interconnect network after the target process, the electronic device 110 adjusts the structure of the given line segment at least once until the target interconnect network is a valid interconnect network after the target process.

[0117] In some embodiments, at least one adjustment to the structure of a given line segment may be determined by performing at least one iteration.

[0118] As an example, in a first iteration, the electronic device 110 changes the current structure of a given line segment based on the reference structural change. Then, the electronic device 110 determines the attribute value of the electrical attribute of the given node when the given line segment adopts the reference structural change based on the electrical attribute change of the given node. Then, in response to determining that the attribute value of the electrical attribute of the given node meets the predetermined electrical attribute requirement, the electronic device 110 determines the reference structural change as a candidate structural change.

[0119] In some embodiments, in response to the electrical property change of a given node not satisfying a predetermined electrical property requirement, the electronic device 110 may update the reference structure change to perform a second iteration subsequent to the first iteration.

[0120] As an example, the first iteration may be any iteration in at least one iteration. In the first iteration, the electronic device 110 first determines the reference structure change of the given line segment. Such a reference structure change may be selected from the existing reference structure changes, or may be generated in real time according to the actual situation, and the embodiments of the present disclosure do not limit this. Then, based on the electrical property change of the given node (such as the change of voltage and / or current, etc.), the electronic device 110 simulates the attribute value of the electrical property of the given node under the reference structure change. Next, the electronic device 110 compares the attribute value of the simulated electrical property with the predetermined electrical property requirement. If the attribute value of the electrical property meets the predetermined electrical property requirement, the electronic device 110 determines the current reference structure change as a candidate structure change. If the attribute value of the electrical property does not meet the predetermined electrical property requirement, or the result of the current iteration has not yet reached the predetermined convergence condition, the electronic device 110 will update the reference structure change. The update may involve adjusting the length, width, material or layout of the given line segment, etc. This update is intended to improve the electrical property of the given node so that the electrical property of the given node can meet the predetermined electrical property requirement.

[0121] As an example, in each iteration described above, for the reference structural change used in the iteration, the electronic device 110 can simulate the voltage drop on a given node. Then, the electronic device 110 identifies the given structural change with a voltage drop lower than the predetermined voltage drop as a candidate structural change.

[0122] Based on the updated reference structure change, the electronic device 110 will perform a second iteration to repeat the candidate structure change determination process described above. The iteration process will continue until the iteration result satisfies a predetermined convergence condition. As an example, the predetermined convergence condition may include, but is not limited to, stability of the property value of the electrical property, reaching a predetermined optimization target, or reaching a predetermined number of iterations.

[0123] In response to satisfying a predetermined convergence condition, the electronic device 110 selects a candidate structural change that satisfies a predetermined change amplitude requirement from the candidate structural changes determined through multiple iterations.

[0124] As an example, the electronic device 110 may select one from all determined candidate structural changes to determine a final adjusted structure based on any appropriate screening strategy. Such an adjusted structure may be understood as an optimal line segment structure that enables a given node to meet predetermined electrical property requirements.

[0125] Through the above iterative process, the adjusted structure finally determined can provide stable and reliable circuit performance while enabling a given node to meet predetermined electrical property requirements.

[0126] In some embodiments, the candidate structural changes include a size change of a given line segment in a predetermined direction. The electronic device 110 determines the size change of the given line segment after each candidate structural change is adopted. Then, the electronic device 110 determines the candidate structural change that minimizes the size change of the given line segment as the candidate structural change that meets the predetermined change amplitude requirement.

[0127] As an example, for each candidate structural change, the electronic device 110 may evaluate the size change of a given line segment after adopting the candidate structural change from the original size. The size change here may include but is not limited to the length change, width change, position shift, etc. of the line segment.

[0128] When selecting from the candidate structural changes, the electronic device 110 can compare the size changes of the given line segment under different candidate structural changes, that is, the size change amplitude between the given line segment and the original size after adopting different candidate structural changes. Then, the electronic device 110 confirms the candidate structural change with the smallest size change amplitude as the final required structural change. Next, the adjusted structure can be determined by superimposing the structural change with the current structure of the given line segment (or any other appropriate method).

[0129] The adjusted structure determined in this way can ensure that a given node meets predetermined electrical property requirements while minimizing the adjustment amplitude of a given line segment, thereby facilitating the stability of the given line segment structure.

[0130] Figure 5 FIG. 5 is a schematic diagram of an example process 500 for determining an adjusted structure according to some embodiments of the present disclosure. Figure 5 And formula (14) to formula (19) describe more details of process 200.

[0131] In block 510, the electronic device 110 constructs an optimization target and a constraint condition. The optimization target at least includes the predetermined variation requirement described above, and the constraint condition at least includes the predetermined electrical property requirement described above.

[0132] As an example, the optimization objective can be expressed by formula (14):

[0133] min∑ j l j Δw j ; (14)

[0134] Among them l j and w j are the length and width of a given line segment j, Δw j is the change in the width of a given line segment j, min∑ j l j Δw j It means that when only the width of a given line segment j is changed to optimize the voltage drop, the total amount of width modification of a given line segment j is required to be minimal.

[0135] As an example, the constraint condition can be expressed by formula (15):

[0136]

[0137] where v i is the voltage at a given node i, and are the maximum and minimum values ​​of the expected voltage at a given node i, respectively.

[0138] As an example, based on formula (14) and formula (15), formula (16) to formula (18) can be obtained through linearization processing:

[0139]

[0140] Where Δg jis the conductivity change of a given line segment j, σ is the conductivity of the target interconnect network, and h j is the thickness of the given line segment j, and formula (18) is the constraint condition after linearization.

[0141] At block 520 , an adjusted structure is determined by solving the optimal structure for a given line segment j using a linear programming optimizer based on the optimization objective and constraints.

[0142] As an example, the linear programming optimizer includes but is not limited to any appropriate optimizer. Such optimizers include, for example, but are not limited to, LINDO (LINear Interactive and Diserete Optimizer) optimizer, Gurobi (Gurobi Optimizer) optimizer, PuLP (Python Linear Programming) optimizer, and GLPK (GNULinear Programming Kit) optimizer. As an example, using the linear programming optimizer, the electronic device 110 can obtain the target width modification Δw (e.g., reference structure changes) for a given line segment j. The target width modification Δw enables a given node i to meet a predetermined voltage drop requirement, and the width modification of a given line segment j is minimized. For a given line segment j, the final width of the line segment is (i.e., the adjusted structure of a given line segment j) can be expressed by formula (19):

[0143]

[0144] where w j is the original width of the given line segment j before adjustment.

[0145] It should be noted that in the above examples, the adjusted structure of a given line segment j is used as the width of the given line segment j for exemplary description, but this does not constitute a limitation on the embodiments of the present disclosure. According to actual needs, the adjusted structure can also be the length and / or thickness of the given line segment j, etc., and the embodiments of the present disclosure are not listed one by one here.

[0146] Once the adjusted structure of the given line segment is determined, the electronic device 110 can perform blocks 210 to 230 again to re-determine the evaluation result regarding the effectiveness of the target interconnect network after the target process. As an example, the electronic device 110 can repeatedly perform the above process until the evaluation result of the target interconnect network indicates that the target interconnect network is a valid interconnect network.

[0147] It can be clearly understood from the various embodiments described above that the embodiments of the present disclosure can be used to study the impact of processes such as CMP on voltage drop, thereby helping to improve chip reliability, while also helping to determine the process window and achieve design-technology co-optimization.

[0148] In addition, the embodiments of the present disclosure also convert the adjustment of the interconnection line structure into an optimization problem based on the change of electrical properties, and then use the linear optimizer to quickly obtain the interconnection line network structure that meets the predetermined voltage drop requirements based on the optimization target and constraint conditions. Compared with the traditional trial and error method that relies on experience, the embodiments of the present disclosure have higher accuracy and are suitable for the interconnection line network design of large-scale integrated circuit chips.

[0149] Figure 6 1 is a block diagram of an electronic device 600 in which one or more embodiments of the present disclosure may be implemented. The electronic device 600 may be used to implement, for example, Figure 1 The electronic device 110 shown. It should be understood that Figure 6 The electronic device 600 shown is merely exemplary and should not constitute any limitation on the functionality and scope of the embodiments described herein.

[0150] Reference Figure 6 , the electronic device 600 is in the form of a general electronic device. The components of the electronic device 600 may include, but are not limited to, one or more processors or processing units 610, a memory 620, a storage device 630, one or more communication units 640, one or more input devices 650, and one or more output devices 660. The processing unit 610 may be an actual or virtual processor and is capable of performing various processes according to a program stored in the memory 620. In a multi-processor system, multiple processing units execute computer executable instructions in parallel to improve the parallel processing capability of the electronic device 600.

[0151] The electronic device 600 typically includes a plurality of computer storage media. Such media can be any available media accessible to the electronic device 600, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 620 can be a volatile memory (e.g., registers, caches, random access memory (RAM)), a non-volatile memory (e.g., a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), flash memory) or some combination thereof. The storage device 630 can be a removable or non-removable medium, and can include a machine-readable medium, such as a flash drive, a disk, or any other medium, which can be used to store information and / or data and can be accessed within the electronic device 600.

[0152] The electronic device 600 may further include additional removable / non-removable, volatile / non-volatile storage media. Figure 6 As shown in , a disk drive for reading or writing from a removable, non-volatile disk (e.g., a "floppy disk") and an optical drive for reading or writing from a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to the bus (not shown) by one or more data media interfaces. The memory 620 may include a computer program product 625 having one or more program modules that are configured to perform various methods or actions of various embodiments of the present disclosure.

[0153] The communication unit 640 implements communication with other electronic devices through a communication medium. Additionally, the functions of the components of the electronic device 600 can be implemented with a single computing cluster or multiple computing machines that can communicate through a communication connection. Therefore, the electronic device 600 can operate in a networked environment using a logical connection with one or more other servers, a network personal computer (PC), or another network node.

[0154] The input device 650 may be one or more input devices, such as a mouse, a keyboard, a tracking ball, etc. The output device 660 may be one or more output devices, such as a display, a speaker, a printer, etc. The electronic device 600 may also communicate with one or more external devices (not shown) through the communication unit 640 as needed, such as a storage device, a display device, etc., communicate with one or more devices that allow a user to interact with the electronic device 600, or communicate with any device that allows the electronic device 600 to communicate with one or more other electronic devices (e.g., a network card, a modem, etc.). Such communication may be performed via an input / output (I / O) interface (not shown).

[0155] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored, wherein the computer-executable instructions are executed by a processor to implement the method described above. According to an exemplary implementation of the present disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, and the computer-executable instructions are executed by a processor to implement the method described above.

[0156] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices, equipment, and computer program products implemented according to the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0157] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0158] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0159] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple implementations of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some implementations as replacements, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0160] The above descriptions of various implementations of the present disclosure are exemplary, non-exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The determination of the terms used herein is intended to best explain the principles of the implementations, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the various implementations disclosed herein.

Claims

1. A method for determining the effectiveness of an interconnection line, comprising: For a given line segment in a target interconnect network, determining a change in conductance of the given line segment after a given structural change occurs to the given line segment, wherein the given structural change of the given line segment is determined based on a simulated morphology of the given line segment after undergoing a target process; Based on the conductance change of the given line segment, determining a change in an electrical property of a given node in the target interconnect network as a result of the conductance change; as well as An evaluation result on the effectiveness of the target interconnect network after undergoing the target process is determined based at least on whether the electrical property change of the given node meets a predetermined electrical property requirement.

2. The method according to claim 1, wherein the given structural change at least indicates a change in the cross-sectional area of ​​the given line segment after the target process, and Wherein determining the change in conductance on the given line segment after a given structural change occurs on the given line segment comprises: The change in conductivity of the given line segment is determined based at least on a change in cross-sectional area of ​​the given line segment after the given line segment has passed through the target process and the conductivity of the given line segment.

3. The method of claim 1 , wherein determining whether the electrical property change of the given node satisfies a predetermined electrical property requirement comprises: Based on the electrical property change and the conductance change, determining a property value of the electrical property of the given node after the conductance change occurs in the given line segment; In response to the property value of the given node being within a predetermined range, determining that the change in the electrical property of the given node satisfies the predetermined electrical property requirement; as well as In response to the property value of the given node being outside the predetermined range, it is determined that the electrical property change of the given node does not satisfy the predetermined electrical property requirement.

4. The method according to claim 1, wherein determining an evaluation result regarding the effectiveness of the target interconnect network after being subjected to a target process comprises: In response to the electrical property change of the given node satisfying the predetermined electrical property requirement, determining that the target interconnect network is a valid interconnect network after undergoing the target process; as well as In response to the electrical property change of the given node not satisfying the predetermined electrical property requirement, it is determined that the target interconnection line network is an invalid interconnection line network after undergoing the target process.

5. The method according to claim 1, further comprising: In response to determining that the target interconnect network is an invalid interconnect network after the target process, the structure of the given line segment is adjusted at least once until the target interconnect network is a valid interconnect network after the target process. The method according to claim 1 , wherein the target process comprises at least a chemical mechanical polishing process.

7. The method according to claim 1, wherein the target interconnect network is determined by: determining a plurality of interconnect sub-networks in the initial interconnect network, wherein the plurality of interconnect sub-networks are insulated and spaced apart from each other; Determining, from the plurality of interconnection line sub-networks, a first interconnection line sub-network set including the given node and a second interconnection line sub-network set including the given line segment; and The target interconnect network is determined by merging the first interconnect sub-network set and the second interconnect sub-network set.

8. The method of claim 7, wherein determining a plurality of interconnect subnetworks in the initial interconnect network comprises: Determining a graph structure corresponding to the initial interconnect network, wherein nodes in the graph structure correspond to nodes in the initial interconnect network, and edges in the graph structure correspond to line segments in the initial interconnect network; Determining connectivity between nodes in the graph structure based on the nodes in the graph structure and the edges connecting the nodes; Based on the determined connectivity, dividing the graph structure into a plurality of connected graphs; as well as The plurality of interconnection line sub-networks are determined based on the nodes and line segments in the initial interconnection line network corresponding to the divided plurality of connectivity graphs.

9. The method according to claim 1, wherein based on the conductance change, determining a change in an electrical property of a given node in the target interconnect network as the conductance changes comprises: Determine a target vector for an electrical property, wherein elements in the target vector correspond to nodes in the target interconnect network, and a value of each element in the target vector is a current value of the electrical property of each node determined based on a conductance matrix of the target interconnect network; updating a value of each element in the target vector based at least on the conductance change and the conductance matrix; as well as A change in an electrical property of the given node as a function of the conductance change is determined based on the change in value of each element in the target vector caused by the update.

10. The method of claim 9, wherein updating the value of each element in the target vector based at least on the conductance change and the conductance matrix comprises: determining a reference vector, wherein elements in the reference vector correspond to nodes in the target interconnection line network, and in the reference vector, elements corresponding to reference nodes connected to at least one end of the given line segment have valid values, and elements corresponding to other nodes except the reference nodes have invalid values, wherein the valid values ​​are determined based on the conductance change; as well as The value of each element in the target vector is updated based on at least the product of the reference vector and the conductance matrix. 11 . The method according to claim 9 , wherein the conductance matrix is ​​a conductance matrix obtained by performing matrix decomposition on an original conductance matrix of the target interconnect network.

12. The method of claim 1, wherein the electrical property change comprises a voltage change, the predetermined electrical property requirement indicating that a voltage drop at the given node is less than a predetermined voltage drop.

13. The method according to claim 1, wherein the target interconnect network is determined by performing at least one of the following on the initial interconnect network: removing line segments in the initial interconnect network whose resistance is greater than a first resistance threshold, or The endpoints of the line segments in the initial interconnection line network whose resistance is less than a second resistance threshold are merged.

14. An electronic device comprising: at least one processing unit; as well as At least one memory, the at least one memory being coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions causing the electronic device to perform the method according to any one of claims 1 to 13 when executed by the at least one processing unit.

15. A computer-readable storage medium having a computer program stored thereon, wherein the computer program can be executed by a processor to implement the method according to any one of claims 1 to 13.

16. A computer program product comprising computer executable instructions, wherein the computer executable instructions, when executed by a processor, implement the method according to any one of claims 1 to 13.

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