Semiconductor structure, preparation method and electronic equipment
By patterning and etching the dielectric layer on the substrate of the semiconductor high-voltage device, the problem of uneven thickness of the gate oxide layer is solved, and the electrical performance and reliability of the device are improved.
Patent Information
- Application Number
- CN202510191801.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-20
- Publication Date
- 2025-05-13
AI Technical Summary
During the preparation process of semiconductor high-voltage devices, the thickness of the gate oxide layer is uneven, which affects the electrical performance and reliability of the device.
By providing a substrate, the second dielectric layer covering the trench and the active region, the second dielectric layer is patterned to expose a portion of the top surface of the first dielectric layer, and the first dielectric layer is etched based on the patterned second dielectric layer to expose the target top surface of the active region.
This method simplifies the etching process of the gate dielectric layer, avoids damage and uneven thickness problems of the first dielectric layer during the etching process, and thus improves the electricality and reliability of the semiconductor device.
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Figure CN119993902A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a preparation method and an electronic device. Background Art
[0002] Semiconductor high-voltage devices have the advantages of low on-resistance, fast switching speed, and high thermal conductivity. They can operate in high voltage environments and are widely used in power electronics, new energy vehicles, photovoltaic energy storage, data centers and other fields.
[0003] However, during the preparation process of semiconductor high-voltage devices, the thickness of the gate oxide layer between the source and drain regions of the high-voltage devices becomes uneven, which in turn affects the electrical properties of the high-voltage asymmetric devices, such as the threshold voltage and breakdown voltage, and reduces the reliability of the semiconductor devices. Summary of the invention
[0004] The purpose of this application is to provide a semiconductor structure, a preparation method and an electronic device, which solves the problem that the thickness of the gate oxide layer in the semiconductor structure is uneven, thereby affecting the electrical performance of the semiconductor device, and improves the reliability and electrical properties of the semiconductor structure. To achieve the purpose of this application, this application provides the following technical solutions:
[0005] In a first aspect, the present application provides a method for preparing a semiconductor structure, comprising:
[0006] Providing a substrate, wherein the substrate includes grooves arranged at intervals along a first direction parallel to a top surface of the substrate, active areas defined by adjacent grooves, and a dielectric layer covering the grooves and the top surfaces of the active areas, wherein the dielectric layer includes a first dielectric layer and a second dielectric layer covered by the first dielectric layer;
[0007] patterning the second dielectric layer to expose a portion of a top surface of the first dielectric layer;
[0008] Based on the patterned second dielectric layer, the first dielectric layer is etched to expose a target top surface of the active region.
[0009] The preparation method of the semiconductor structure of the present application first provides a substrate, wherein the substrate includes grooves arranged at intervals along a first direction parallel to the top surface of the substrate, active areas defined by adjacent grooves, and a dielectric layer covering the top surfaces of the grooves and the active areas, wherein the dielectric layer includes a first dielectric layer and a second dielectric layer covered by the first dielectric layer, and the second dielectric layer is further patterned to expose a portion of the top surface of the first dielectric layer. Finally, based on the patterned second dielectric layer, the first dielectric layer is etched to expose the target top surface of the active area. The second dielectric layer covers the top surface of the first dielectric layer, and the process of removing the second dielectric layer can be eliminated while the target area of the active area is defined by the second dielectric layer. The second dielectric layer is patterned so that the patterned second dielectric layer serves as a mask layer of the first dielectric layer, and the first dielectric layer is further etched based on the patterned second dielectric layer. There is no need to add an additional mask layer on the top surface of the first dielectric layer, which simplifies the step of etching the first dielectric layer. The second dielectric layer can protect the top surface of the first dielectric layer, avoid etching damage to the first dielectric layer during the etching process, and protect the top surface morphology of the first dielectric layer, thereby avoiding the problem of uneven thickness of the first dielectric layer caused by etching, and improving the electrical properties and reliability of the semiconductor device.
[0010] In some embodiments, after providing the substrate and before patterning the second dielectric layer, the method further includes:
[0011] Grinding the top surface of the first dielectric layer to make the top surface of the first dielectric layer flush with the top surface of the second dielectric layer;
[0012] An isolation layer is formed on the top surface of the second dielectric layer and the top surface of the first dielectric layer.
[0013] In some embodiments, patterning the second dielectric layer includes:
[0014] The second dielectric layer and the isolation layer are etched based on the mask layer to expose a portion of the top surface of the first dielectric layer.
[0015] In some embodiments, after etching the first dielectric layer based on the patterned second dielectric layer to expose the target top surface of the active region, the method further includes:
[0016] The second dielectric layer and the isolation layer are removed to form a gate dielectric layer including a first through hole and a second through hole.
[0017] In some embodiments, the first through hole exposes the source region of the active region, and the second through hole exposes the drain region of the active region; or, the first through hole exposes the drain region of the active region, and the second through hole exposes the source region of the active region.
[0018] In some embodiments, the second dielectric layer is disposed corresponding to the active region, and an orthographic projection of the active region on its longitudinal section coincides with a projection edge of an orthographic projection of the second dielectric layer on the longitudinal section of the active region.
[0019] In some embodiments, the first dielectric layer comprises silicon oxide; and / or
[0020] The second dielectric layer includes silicon nitride.
[0021] In a second aspect, the present application further provides a semiconductor structure, which is prepared by the method for preparing a semiconductor structure described in any one of the above embodiments;
[0022] The semiconductor structure comprises:
[0023] A substrate, comprising grooves arranged at intervals along a first direction parallel to a top surface of the substrate, and active areas defined by adjacent grooves;
[0024] The top surface of the active region includes a gate dielectric layer, and the gate dielectric layer includes an opening, and the opening exposes a target top surface of the active region.
[0025] The semiconductor structure of the present application includes a substrate, a groove, an active area, and a gate dielectric layer. By covering the top surface of the first dielectric layer with a second dielectric layer, the process of removing the second dielectric layer can be eliminated while defining the target area of the active area in the second dielectric layer. By patterning the second dielectric layer so that the patterned second dielectric layer serves as a mask layer of the first dielectric layer, the first dielectric layer is further etched based on the patterned second dielectric layer, and there is no need to add an additional mask layer on the top surface of the first dielectric layer, thereby simplifying the step of etching the first dielectric layer. In addition, the second dielectric layer can protect the top surface of the first dielectric layer, avoid etching damage to the first dielectric layer during the etching process, and protect the top surface morphology of the first dielectric layer, thereby avoiding the problem of uneven thickness of the first dielectric layer caused by etching, and improving the electrical properties and reliability of the semiconductor device.
[0026] In some embodiments, an orthographic projection of the active region on its longitudinal section coincides with a projection edge of an orthographic projection of the gate dielectric layer on the longitudinal section of the active region.
[0027] In a third aspect, the present application further provides an electronic device, including:
[0028] Prepared by the method for preparing a semiconductor structure according to any one of the first aspects; or
[0029] The semiconductor structure described in the second aspect.
[0030] The electronic device of the present application first provides a substrate, wherein the substrate includes grooves arranged at intervals along a first direction parallel to the top surface of the substrate, active areas defined by adjacent grooves, and a dielectric layer covering the top surfaces of the grooves and the active areas, wherein the dielectric layer includes a first dielectric layer and a second dielectric layer covered by the first dielectric layer, and the second dielectric layer is further patterned to expose a portion of the top surface of the first dielectric layer. Finally, based on the patterned second dielectric layer, the first dielectric layer is etched to expose the target top surface of the active area. The second dielectric layer covers the top surface of the first dielectric layer, and the process of removing the second dielectric layer can be eliminated while the target area of the active area is defined by the second dielectric layer. The second dielectric layer is patterned so that the patterned second dielectric layer serves as a mask layer of the first dielectric layer, and the first dielectric layer is further etched based on the patterned second dielectric layer. There is no need to add an additional mask layer on the top surface of the first dielectric layer, which simplifies the step of etching the first dielectric layer. The second dielectric layer can protect the top surface of the first dielectric layer, avoid etching damage to the first dielectric layer during the etching process, and protect the top surface morphology of the first dielectric layer, thereby avoiding the problem of uneven thickness of the first dielectric layer caused by etching, and improving the electrical properties and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0032] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;
[0033] Figure 2 is a schematic cross-sectional view of a structure obtained in step S11 of a method for preparing a semiconductor structure provided in an embodiment;
[0034] Figure 3 is a schematic cross-sectional view of a structure obtained in step S14 of a method for preparing a semiconductor structure provided in an embodiment;
[0035] Figure 4 is a schematic diagram of a cross-sectional structure of a structure obtained in step S15 in a method for preparing a semiconductor structure provided in an embodiment;
[0036] Figure 5 is a flow chart of a method for preparing a semiconductor structure provided in another embodiment;
[0037] Figure 6is a schematic cross-sectional view of a structure obtained in step S12 of a method for preparing a semiconductor structure provided in an embodiment;
[0038] Figure 7 is a schematic cross-sectional view of a structure obtained in step S13 of a method for preparing a semiconductor structure provided in an embodiment;
[0039] Figure 8 is a schematic cross-sectional structural diagram of a structure obtained in a method for preparing a semiconductor structure provided in another embodiment;
[0040] Fig. 9 It is a schematic diagram of the cross-sectional structure of a structure obtained in a method for preparing a semiconductor structure provided in another embodiment.
[0041] Description of Reference Numerals
[0042] 10. substrate; 20. trench; 30. active area; 40. dielectric layer; 401. first dielectric layer; 402. second dielectric layer; 50. isolation layer; 60. mask layer; 70. gate dielectric layer; 80. trench oxide layer. DETAILED DESCRIPTION
[0043] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0045] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0046] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0047] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0048] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.
[0049] Semiconductor high-voltage devices have the advantages of low on-resistance, fast switching speed, and high thermal conductivity. They can operate in high voltage environments and are widely used in power electronics, new energy vehicles, photovoltaic energy storage, data centers and other fields.
[0050] In the traditional technology, in the process of forming a gate oxide layer of a semiconductor high-voltage device, it is necessary to first remove the silicon nitride film layer, block the high-voltage device by photoresist coating, and use dry etching and wet etching processes to remove the oxide layer of the low and medium voltage devices, and open the source and drain of the high-voltage device. However, during the wet etching process, the oxide layer on both sides of the source and drain of the high-voltage device will be damaged, making the gate oxide thickness of the high-voltage asymmetric device uneven, thereby affecting the electrical properties of the high-voltage asymmetric device such as the threshold voltage and breakdown voltage, and reducing the reliability of the semiconductor device.
[0051] The present invention provides a method for preparing a semiconductor structure. Figure 1 , the preparation method of the semiconductor structure comprises:
[0052] S11: Provide a substrate, the substrate comprising grooves spaced apart along a first direction parallel to a top surface of the substrate, active areas defined by adjacent grooves, and a dielectric layer covering the grooves and the top surface of the active area, wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer covered by the first dielectric layer.
[0053] For example, see Figure 2 The substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium silicon wafer. In this embodiment, the substrate 10 is a silicon substrate.
[0054] Exemplarily, the first direction is as follows Figure 2 OX direction shown in .
[0055] For example, please refer to Figure 2 The first dielectric layer 401 may be formed by, but is not limited to, a thermal oxidation process.
[0056] For example, please refer to Figure 2 The second dielectric layer 402 may be formed by, but is not limited to, a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma chemical vapor deposition process (HDP-CVD), or a high aspect ratio process (HARP).
[0057] Please refer to Figure 2 The second dielectric layer 402 covers the first dielectric layer 401 on the top surface of the substrate 10 , and can define a target area of the active area 30 to provide an implantation area for forming the active area 30 .
[0058] For example, please refer to Figure 2 The substrate 10 may be etched by, but not limited to, a wet etching or dry etching process to form the trench 20 . The longitudinal cross-section of the trench 20 may include, but not limited to, an inverted trapezoid.
[0059] For example, please refer to Figure 2 The active region 30 may be formed by, but is not limited to, an ion implantation process.
[0060] S14: patterning the second dielectric layer to expose a portion of the top surface of the first dielectric layer.
[0061] For example, see Figure 3 The second dielectric layer 402 may be patterned using, but not limited to, a photolithography process to expose a portion of the top surface of the first dielectric layer 401 .
[0062] S15: etching the first dielectric layer based on the patterned second dielectric layer to expose a target top surface of the active region.
[0063] For example, see Figure 4 The first dielectric layer 401 may be etched based on the patterned second dielectric layer 402 using, but not limited to, a photolithography process to expose the target top surface of the active region 30 so as to subsequently guide the active region 30 out from the target top surface of the active region 30 .
[0064] The preparation method of the semiconductor structure of the present application first provides a substrate, wherein the substrate includes grooves arranged at intervals along a first direction parallel to the top surface of the substrate, active areas defined by adjacent grooves, and a dielectric layer covering the top surfaces of the grooves and the active areas, wherein the dielectric layer includes a first dielectric layer and a second dielectric layer covered by the first dielectric layer, and the second dielectric layer is further patterned to expose a portion of the top surface of the first dielectric layer. Finally, based on the patterned second dielectric layer, the first dielectric layer is etched to expose the target top surface of the active area. The second dielectric layer covers the top surface of the first dielectric layer, and the process of removing the second dielectric layer can be eliminated while the target area of the active area is defined by the second dielectric layer. The second dielectric layer is patterned so that the patterned second dielectric layer serves as a mask layer of the first dielectric layer, and the first dielectric layer is further etched based on the patterned second dielectric layer. There is no need to add an additional mask layer on the top surface of the first dielectric layer, which simplifies the step of etching the first dielectric layer. The second dielectric layer can protect the top surface of the first dielectric layer, avoid etching damage to the first dielectric layer during the etching process, and protect the top surface morphology of the first dielectric layer, thereby avoiding the problem of uneven thickness of the first dielectric layer caused by etching, and improving the electrical properties and reliability of the semiconductor device.
[0065] In some embodiments, see Figure 5 , after providing the substrate 10 and before patterning the second dielectric layer 402, further comprising:
[0066] S12: grinding the top surface of the first dielectric layer to make the top surface of the first dielectric layer flush with the top surface of the second dielectric layer.
[0067] For example, see Figure 6 The top surface of the first dielectric layer 401 may be polished by, but not limited to, a chemical mechanical polishing process, so that the top surface of the first dielectric layer 401 is flush with the top surface of the second dielectric layer 402 .
[0068] S13: forming an isolation layer on the top surface of the second dielectric layer and the top surface of the first dielectric layer.
[0069] For example, see Figure 7 The isolation layer 50 may be formed on the top surface of the second dielectric layer 402 and the top surface of the first dielectric layer 401 by a thermal oxidation process but not limited thereto. The isolation layer 50 may include but not limited to an oxide layer.
[0070] The method for preparing the semiconductor structure provided in the embodiment of the present application can grind the top surface of the first dielectric layer 401 to make the top surface of the first dielectric layer 401 flush with the top surface of the second dielectric layer 402, and can further form an isolation layer 50 on the top surface of the second dielectric layer 402 and the top surface of the first dielectric layer 401. The isolation layer 50 can protect the first dielectric layer 401 to prevent the top surface of the first dielectric layer 401 from being damaged when the patterned mask layer 60 is subsequently removed. In addition, the top surface morphology of the first dielectric layer 401 can be protected, the electrical isolation performance of the first dielectric layer 401 can be improved, and the electrical performance of the semiconductor structure can be improved.
[0071] In some embodiments, please refer to Figure 8 , patterning the second dielectric layer 402 , including: etching the second dielectric layer 402 and the isolation layer 50 based on the mask layer to expose a portion of the top surface of the first dielectric layer 401 .
[0072] Illustratively, the mask layer 60 includes an opening, and the opening defines a portion of a top surface of the first dielectric layer 401 .
[0073] The method for preparing a semiconductor structure provided in an embodiment of the present application can form a second dielectric layer 402 having a target pattern by etching the second dielectric layer 402 and the isolation layer 50 based on the mask layer 60, and then etching the first dielectric layer 401 based on the patterned second dielectric layer 402. There is no need to form an additional mask layer 60 on the top surface of the first dielectric layer 401, thereby avoiding etching damage to the first dielectric layer 401 during the etching process, protecting the top surface morphology of the first dielectric layer 401, and avoiding the problem of uneven thickness of the first dielectric layer 401 due to etching, thereby improving the electrical properties and reliability of the semiconductor device.
[0074] In some embodiments, see Fig. 9 After etching the first dielectric layer 401 based on the patterned second dielectric layer 402 to expose the target top surface of the active area 30, the method further includes: removing the second dielectric layer 402 and the isolation layer 50 to form a gate dielectric layer 70 including a first through hole and a second through hole.
[0075] For example, the second dielectric layer 402 and the isolation layer 50 may be removed by, but not limited to, an etching process to form a gate dielectric layer 70 including a first through hole and a second through hole.
[0076] It should be noted that the first through hole and the second through hole of the gate dielectric layer 70 can expose the target top surface of the active region 30 , and can electrically conduct the active region 30 .
[0077] It should be noted that after etching the first dielectric layer 401 , the first dielectric layer 401 covering the top surface of the substrate 10 forms a gate dielectric layer 70 , and the first dielectric layer 401 filling the trench 20 forms a trench oxide layer 80 .
[0078] The method for preparing a semiconductor structure provided in an embodiment of the present application forms a gate dielectric layer 70 including a first through hole and a second through hole by removing the second dielectric layer 402 and the isolation layer 50. The first through hole and the second through hole of the gate dielectric layer 70 can expose the target top surface of the active area 30, and can electrically guide the active area 30. The gate dielectric layer 70 can prevent current leakage between the gate and the channel, and can regulate the carrier concentration in the channel by the gate voltage, thereby controlling the device to be turned on and off, so that the semiconductor device can work normally.
[0079] In some embodiments, please refer to Fig. 9 The first through hole exposes the source region of the active region 30 , and the second through hole exposes the drain region of the active region 30 .
[0080] Exemplarily, the first through hole exposes the source region of the active region 30, and the second through hole exposes the drain region of the active region 30. The first through hole can serve as an electrical lead-out channel for the source region, and the second through hole can serve as an electrical lead-out channel for the drain region.
[0081] In the method for preparing the semiconductor structure provided in the embodiment of the present application, the source region of the active region 30 is exposed through the first through hole, and the drain region of the active region 30 is exposed through the second through hole. The first through hole can be used as an electrical lead-out channel for the source region, and the second through hole can be used as an electrical lead-out channel for the drain region, so as to form a current conduction channel between the source region and the drain region, thereby ensuring the normal operation of the semiconductor device.
[0082] In some embodiments, please refer to Fig. 9 The first through hole exposes the drain region of the active region 30 , and the second through hole exposes the source region of the active region 30 .
[0083] Exemplarily, the first through hole exposes the drain region of the active region 30, and the second through hole exposes the source region of the active region 30. The first through hole can serve as an electrical lead-out channel for the drain region, and the second through hole can serve as an electrical lead-out channel for the source region.
[0084] In the method for preparing the semiconductor structure provided in the embodiment of the present application, the first through hole exposes the drain region of the active region 30, and the second through hole exposes the source region of the active region 30. The first through hole can be used as an electrical lead-out channel for the drain region, and the second through hole can be used as an electrical lead-out channel for the source region, so as to form a current conduction channel between the source region and the drain region, thereby ensuring the normal operation of the semiconductor device.
[0085] In some embodiments, see Figure 2The second dielectric layer 402 is arranged corresponding to the active area 30 , and the projection edge of the orthographic projection of the active area 30 on its longitudinal section coincides with the projection edge of the orthographic projection of the second dielectric layer 402 on the longitudinal section of the active area 30 .
[0086] Exemplarily, the second dielectric layer 402 is disposed corresponding to the active region 30, and the orthographic projection of the active region 30 on its longitudinal section coincides with the projection edge of the orthographic projection of the second dielectric layer 402 on the longitudinal section of the active region 30, that is, Figure 2 The second dielectric layer 402 shown in FIG. 4 completely covers the top surface of the active region 30 .
[0087] In the method for preparing a semiconductor structure provided in an embodiment of the present application, the second dielectric layer 402 is arranged corresponding to the active area 30, and the projection edge of the orthographic projection of the active area 30 on its longitudinal section coincides with the projection edge of the orthographic projection of the second dielectric layer 402 on the longitudinal section of the active area 30, thereby ensuring that the second dielectric layer 402 completely covers the top surface of the active area 30, and further allowing the second dielectric layer 402 to accurately define the target area of the active area 30, so as to provide an accurate injection position for the subsequent formation of the active area 30, thereby improving the accuracy of the semiconductor structure preparation process.
[0088] In some embodiments, please refer to Figure 2 , the first dielectric layer 401 includes silicon oxide.
[0089] By way of example, the first dielectric layer 401 may include silicon oxide, such as silicon dioxide.
[0090] The method for preparing the semiconductor structure provided in the embodiment of the present application, by setting the first dielectric layer 401 to silicon oxide, can utilize the insulating properties of silicon oxide to effectively prevent the flow of electrons between the gate and the substrate 10, thereby ensuring that the semiconductor device can work normally.
[0091] In some embodiments, please refer to Figure 2 , the second dielectric layer 402 includes silicon nitride.
[0092] By way of example, the second dielectric layer 402 may include silicon nitride, such as silicon nitride.
[0093] The method for preparing the semiconductor structure provided in the embodiment of the present application can utilize silicon nitride as an insulating layer for defining the active area 30 by setting the second dielectric layer 402 to silicon nitride, thereby avoiding the problem of the active area 30 being etched during the process of etching the groove 20 .
[0094] The present application embodiment provides a semiconductor structure. Fig. 9, prepared by the preparation method of the semiconductor structure of any one of the above embodiments; the semiconductor structure includes: a substrate 10, which includes grooves 20 arranged at intervals along a first direction parallel to the top surface of the substrate 10, and an active area 30 defined by adjacent grooves 20; the top surface of the active area 30 includes a gate dielectric layer 70, and the gate dielectric layer 70 includes an opening, and the opening exposes the target top surface of the active area 30.
[0095] Exemplarily, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium silicon wafer. In this embodiment, the substrate 10 is a silicon substrate.
[0096] Exemplarily, the first direction is as follows Figure 2 The ox direction shown in .
[0097] For example, the first dielectric layer 401 may include but is not limited to an oxide layer. The second dielectric layer 402 may include but is not limited to a silicon nitride layer.
[0098] It should be noted that the second dielectric layer 402 covers the oxide layer on the top surface of the substrate 10 , and can define a target area of the active area 30 to provide an implantation area for forming the active area 30 .
[0099] For example, the longitudinal cross-section of the groove 20 may include, but is not limited to, an inverted trapezoid.
[0100] For example, the gate dielectric layer 70 may include, but is not limited to, an oxide layer. The opening of the gate dielectric layer 70 may expose the target top surface of the active region 30 to electrically conduct the active region 30 .
[0101] The semiconductor structure of the present application includes a substrate 10 , a trench 20 , an active region 30 , and a gate dielectric layer 70 . By covering the top surface of the first dielectric layer 401 with the second dielectric layer 402, the target area of the active area 30 can be defined in the second dielectric layer 402, while the process of removing the second dielectric layer 402 can be avoided. By patterning the second dielectric layer 402 so that the patterned second dielectric layer 402 serves as the mask layer 60 of the first dielectric layer 401, the first dielectric layer 401 is further etched based on the patterned second dielectric layer 402, without the need to additionally add the mask layer 60 on the top surface of the first dielectric layer 401, thereby simplifying the step of etching the first dielectric layer 401, and the second dielectric layer 402 can protect the top surface of the first dielectric layer 401, avoid the first dielectric layer 401 from being etched during the etching process, protect the top surface morphology of the first dielectric layer 401, and thus avoid the problem of uneven thickness of the first dielectric layer 401 caused by etching, thereby improving the electrical properties and reliability of the semiconductor device.
[0102] An embodiment of the present application provides an electronic device, which is manufactured by the method for manufacturing a semiconductor structure in any of the above embodiments.
[0103] The electronic device of the present application first provides a substrate, wherein the substrate includes grooves arranged at intervals along a first direction parallel to the top surface of the substrate, active areas defined by adjacent grooves, and a dielectric layer covering the top surfaces of the grooves and the active areas, wherein the dielectric layer includes a first dielectric layer and a second dielectric layer covered by the first dielectric layer, and the second dielectric layer is further patterned to expose a portion of the top surface of the first dielectric layer. Finally, based on the patterned second dielectric layer, the first dielectric layer is etched to expose the target top surface of the active area. The second dielectric layer covers the top surface of the first dielectric layer, and the process of removing the second dielectric layer can be eliminated while the target area of the active area is defined by the second dielectric layer. The second dielectric layer is patterned so that the patterned second dielectric layer serves as a mask layer of the first dielectric layer, and the first dielectric layer is further etched based on the patterned second dielectric layer. There is no need to add an additional mask layer on the top surface of the first dielectric layer, which simplifies the step of etching the first dielectric layer. The second dielectric layer can protect the top surface of the first dielectric layer, avoid etching damage to the first dielectric layer during the etching process, and protect the top surface morphology of the first dielectric layer, thereby avoiding the problem of uneven thickness of the first dielectric layer caused by etching, and improving the electrical properties and reliability of the semiconductor device.
[0104] An embodiment of the present application provides an electronic device, comprising the semiconductor structure in the above embodiment.
[0105] The electronic device of the present application includes a substrate 10 , a trench 20 , an active region 30 , and a gate dielectric layer 70 . By covering the top surface of the first dielectric layer 401 with the second dielectric layer 402, the target area of the active area 30 can be defined in the second dielectric layer 402, while the process of removing the second dielectric layer 402 can be avoided. By patterning the second dielectric layer 402 so that the patterned second dielectric layer 402 serves as the mask layer 60 of the first dielectric layer 401, the first dielectric layer 401 is further etched based on the patterned second dielectric layer 402, without the need to additionally add the mask layer 60 on the top surface of the first dielectric layer 401, thereby simplifying the step of etching the first dielectric layer 401, and the second dielectric layer 402 can protect the top surface of the first dielectric layer 401, avoid the first dielectric layer 401 from being etched during the etching process, protect the top surface morphology of the first dielectric layer 401, and thus avoid the problem of uneven thickness of the first dielectric layer 401 caused by etching, thereby improving the electrical properties and reliability of the semiconductor device.
[0106] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0107] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate includes grooves arranged at intervals along a first direction parallel to a top surface of the substrate, active areas defined by adjacent grooves, and a dielectric layer covering the grooves and the top surfaces of the active areas, wherein the dielectric layer includes a first dielectric layer and a second dielectric layer covered by the first dielectric layer; patterning the second dielectric layer to expose a portion of a top surface of the first dielectric layer; Based on the patterned second dielectric layer, the first dielectric layer is etched to expose a target top surface of the active region.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: After providing the substrate and before patterning the second dielectric layer, the method further includes: Grinding the top surface of the first dielectric layer to make the top surface of the first dielectric layer flush with the top surface of the second dielectric layer; An isolation layer is formed on the top surface of the second dielectric layer and the top surface of the first dielectric layer.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The patterning of the second dielectric layer comprises: The second dielectric layer and the isolation layer are etched based on the mask layer to expose a portion of the top surface of the first dielectric layer.
4. The method for preparing a semiconductor structure according to claim 2, characterized in that: After etching the first dielectric layer based on the patterned second dielectric layer to expose the target top surface of the active area, the method further includes: The second dielectric layer and the isolation layer are removed to form a gate dielectric layer including a first through hole and a second through hole.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The first through hole exposes the source region of the active region, and the second through hole exposes the drain region of the active region; or the first through hole exposes the drain region of the active region, and the second through hole exposes the source region of the active region.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The second dielectric layer is arranged corresponding to the active area, and the projection edge of the orthographic projection of the active area on the longitudinal section thereof coincides with the projection edge of the orthographic projection of the second dielectric layer on the longitudinal section of the active area.
7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first dielectric layer comprises silicon oxide; and / or The second dielectric layer includes silicon nitride.
8. A semiconductor structure, characterized in that: include: Prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 7; The semiconductor structure comprises: A substrate, comprising grooves arranged at intervals along a first direction parallel to a top surface of the substrate, and active areas defined by adjacent grooves; The top surface of the active region includes a gate dielectric layer, and the gate dielectric layer includes an opening, and the opening exposes a target top surface of the active region.
9. The semiconductor structure according to claim 8, characterized in that: The orthographic projection of the active region on its longitudinal section coincides with a projection edge of the orthographic projection of the gate dielectric layer on the longitudinal section of the active region.
10. An electronic device, characterized in that: include: Prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 7; or The semiconductor structure of claim 8.