Preparation method of chip packaging structure and chip packaging structure
By making and bonding the circuit layers on the first glass core substrate and the second glass core substrate respectively, the problem of warping of the packaging structure is solved and the product yield is improved.
Patent Information
- Application Number
- CN202510152085.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-12
- Publication Date
- 2025-05-13
AI Technical Summary
In the existing semiconductor packaging technology, the chip packaging structure is prone to warping, affecting product yield.
After the first and second wiring layers are made on the first glass core substrate and the second glass core substrate, the two are bonded together to reduce the warping phenomenon caused by mismatch in material CTE.
It effectively reduces the warpage of the chip packaging structure and improves product yield.
Smart Images
Figure CN119993909A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a method for preparing a chip packaging structure and a chip packaging structure. Background Art
[0002] In the field of semiconductor packaging, copper pillars are usually made on one side of a glass core substrate, and then a redistribution layer (RDL) or an accumulation wiring film (ABF) is constructed on the copper pillars after plastic encapsulation and grinding. Then, RDL or ABF is also made on the other side of the glass core substrate, and finally, the chip and conductive balls are arranged to form a chip packaging structure. However, this packaging method easily causes the chip packaging structure to warp, thereby affecting the product yield of the chip packaging structure. Summary of the invention
[0003] In order to overcome the technical problems mentioned in the above background technology, an embodiment of the present application provides a method for preparing a chip packaging structure, the method comprising:
[0004] Providing a first glass core substrate and a second glass core substrate, wherein the glass core substrate is provided with a conductive trace penetrating the glass core substrate;
[0005] A first circuit layer and a second circuit layer are respectively manufactured on one side of the first glass core substrate and the second glass core substrate, wherein the conductive traces in the first glass core substrate are connected to the traces in the first circuit layer, and the conductive traces in the second glass core substrate are connected to the traces in the second circuit layer;
[0006] Bonding a side of the first glass core substrate away from the first circuit layer and a side of the second glass core substrate away from the second circuit layer, wherein the conductive traces in the first glass core substrate and the conductive traces in the second glass core substrate are connected;
[0007] Arrange at least one chip connected to the wiring in the first circuit layer on the first circuit layer, and make a plastic packaging layer that at least encapsulates the chip;
[0008] A plurality of conductive balls connected to the wiring in the second circuit layer are arranged on the second circuit layer to obtain a chip packaging structure.
[0009] In a possible implementation, in the step of providing a first glass core substrate and a second glass core substrate, the method includes:
[0010] Providing a first carrier board and a second carrier board;
[0011] Coating a first removable adhesive layer and a second removable adhesive layer on one side of the first carrier plate and the second carrier plate respectively;
[0012] A first glass core substrate is disposed on the first separable adhesive layer, and a second glass core substrate is disposed on the second separable adhesive layer.
[0013] In a possible implementation, after the step of respectively manufacturing the first circuit layer and the second circuit layer on one side of the first glass core substrate and the second glass core substrate, the method includes:
[0014] The first separable adhesive layer is removed to separate the first carrier plate from the first glass core substrate, and the second separable adhesive layer is removed to separate the second carrier plate from the second glass core substrate.
[0015] In a possible implementation, in the step of respectively manufacturing the first circuit layer and the second circuit layer on one side of the first glass core substrate and the second glass core substrate, the method includes:
[0016] A plurality of first wiring layers are sequentially manufactured on one side of the first glass core substrate, and an insulating layer is manufactured between adjacent first wiring layers, so as to obtain a first circuit layer on one side of the first glass core substrate;
[0017] Multiple layers of second wiring layers are sequentially manufactured on one side of the second glass core substrate, and insulating layers are manufactured between adjacent second wiring layers, so that a second circuit layer is manufactured on one side of the second glass core substrate.
[0018] Another object of the present application is to provide a method for preparing a chip packaging structure, the method comprising:
[0019] Providing a third glass core substrate and a fourth glass core substrate, wherein the third glass core substrate comprises two third sub-glass core substrates stacked and connected to each other, and the fourth glass core substrate comprises two fourth sub-glass core substrates stacked and connected to each other, wherein the glass core substrate is provided with a conductive trace penetrating the glass core substrate;
[0020] A first circuit layer is fabricated on two opposite sides of the third glass core substrate, and a second circuit layer is fabricated on two opposite sides of the third glass core substrate, wherein the conductive traces in the third glass core substrate are connected to the traces in the first circuit layer, and the conductive traces in the fourth glass core substrate are connected to the traces in the second circuit layer;
[0021] Bonding a side of any one of the third sub-glass core substrates away from the first circuit layer and a side of any one of the fourth sub-glass core substrates away from the second circuit layer, wherein the conductive traces in the third sub-glass core substrate and the conductive traces in the fourth sub-glass core substrate are connected;
[0022] Arrange at least one chip connected to the wiring in the first circuit layer on the first circuit layer, and make a plastic packaging layer that at least encapsulates the chip;
[0023] A plurality of conductive balls connected to the wiring in the second circuit layer are arranged on the second circuit layer to obtain a chip packaging structure.
[0024] In a possible implementation, in the step of providing a third glass core substrate and a fourth glass core substrate, the method includes:
[0025] The two third sub-glass core substrates are bonded together through a first bonding layer to obtain a third glass core substrate, and the two fourth sub-glass core substrates are bonded together through a second bonding layer to obtain a fourth glass core substrate.
[0026] In a possible implementation manner, it is characterized in that the first circuit layer and the second circuit layer have the same type of circuit layer structure, or the first circuit layer and the second circuit layer have different types of circuit layer structures;
[0027] Among them, the types of circuit layer structures include redistribution layer structure and ABF circuit layer structure.
[0028] Another object of the present application is to provide a chip packaging structure, the chip packaging structure comprising:
[0029] a first glass core substrate;
[0030] A second glass core substrate is disposed on one side of the first glass core substrate, wherein the glass core substrate is provided with a conductive trace penetrating the glass core substrate, and the conductive trace in the first glass core substrate is connected to the conductive trace in the second glass core substrate;
[0031] A first circuit layer is arranged on a side of the first glass core substrate away from the second glass core substrate, and the wiring in the first circuit layer is connected to the conductive wiring in the first glass core substrate;
[0032] A second circuit layer is arranged on a side of the second glass core substrate away from the first glass core substrate, and the wiring in the second circuit layer is connected to the conductive wiring in the second glass core substrate;
[0033] A chip is arranged on a side of the first circuit layer away from the first glass core substrate, and the chip is connected to the wiring in the first circuit layer;
[0034] A plastic packaging layer, at least arranged around the chip;
[0035] The conductive balls are arranged on a side of the second circuit layer away from the second glass core substrate, and the conductive balls are connected to the wiring in the second circuit layer.
[0036] In a possible implementation manner, the conductive traces of the second glass core substrate are arranged corresponding to the conductive traces of the second glass core substrate and are connected to each other.
[0037] In a possible implementation, the first circuit layer includes a plurality of stacked first routing layers and an insulating layer between adjacent first routing layers, and adjacent first routing layers are connected via insulating layer through holes;
[0038] The second circuit layer includes a plurality of stacked second wiring layers and an insulating layer between adjacent second wiring layers, and adjacent second wiring layers are connected via insulating layer through holes.
[0039] Based on any of the above aspects, the embodiments of the present application provide a method for preparing a chip packaging structure and a chip packaging structure. In this way, the above scheme reduces the warping phenomenon of the chip packaging structure caused by CTE mismatch between materials when manufacturing on the same glass core substrate by manufacturing the first circuit layer and the second circuit layer on the first glass core substrate and bonding them together, thereby improving the product yield of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0041] Figure 1 This is a step diagram of a method for preparing a chip packaging structure provided in this embodiment;
[0042] Figure 2a-2c for Figure 1 The corresponding process diagram;
[0043] Figure 3 A second step diagram of a method for preparing a chip packaging structure provided in this embodiment;
[0044] Figure 4a-4c for Figure 3 The corresponding process diagram;
[0045] Figure 5 A schematic diagram of a chip packaging structure provided in this embodiment.
[0046] Icons: 1-chip packaging structure, 10-first glass core substrate, 20-second glass core substrate, 30-first circuit layer, 301-first routing layer, 40-second circuit layer, 401-second routing layer, 50-chip, 60-plastic sealing layer, 70-conductive ball, 80-third glass core substrate, 801-third sub-glass core substrate, 90-fourth glass core substrate, 901-fourth sub-glass core substrate. DETAILED DESCRIPTION
[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0048] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0049] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0050] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0051] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0052] In order to solve the technical problems mentioned in the background technology, the inventor innovatively designed the following technical solution, and the specific implementation solution of this application will be described in detail with reference to the accompanying drawings.
[0053] See also Figure 1 and Figure 2a-2c , Figure 1A step diagram of a method for preparing a chip packaging structure 1 provided in this embodiment, Figure 2a-2c for Figure 1 The corresponding process flow chart, where: Figure 2a and Figure 2b is a process flow chart corresponding to step S110 and step S120, Figure 2c The process flow chart of step S130, step S140 and step S150 is shown in FIG. 1 . The method for preparing the chip packaging structure 1 includes:
[0054] Step S110 , providing a first glass core substrate 10 and a second glass core substrate 20 , wherein the glass core substrate is provided with a conductive trace penetrating the glass core substrate.
[0055] In this embodiment, the conductive traces are used to achieve electrical connection between different glass core substrates, and the conductive traces are made of a material including metal, such as copper.
[0056] Step S120, respectively making a first circuit layer 30 and a second circuit layer 40 on one side of the first glass core substrate 10 and the second glass core substrate 20, wherein the conductive traces in the first glass core substrate 10 are connected to the traces in the first circuit layer 30, and the conductive traces in the second glass core substrate 20 are connected to the traces in the second circuit layer 40.
[0057] In this embodiment, a first circuit layer 30 and a second circuit layer 40 for realizing electrical connection are respectively manufactured on one side of the first glass core substrate 10 and the second glass core substrate 20 .
[0058] Step S130 , bonding a side of the first glass core substrate 10 away from the first circuit layer 30 and a side of the second glass core substrate 20 away from the second circuit layer 40 , wherein the conductive traces in the first glass core substrate 10 are connected to the conductive traces in the second glass core substrate 20 .
[0059] In this step, chemical mechanical polishing (CMP) is first performed on the side of the first glass core substrate 10 away from the first circuit layer 30 and the side of the second glass core substrate 20 away from the second circuit layer 40, so that the side of the first glass core substrate 10 away from the first circuit layer 30 and the side of the second glass core substrate 20 away from the second circuit layer 40 remain flat. Then the two are hybrid bonded, which is usually performed in a high temperature environment, and finally the electrical connection between the first circuit layer 30, the first glass core substrate 10, the second glass core substrate 20 and the second circuit layer 40 is achieved.
[0060] In the related art, a copper pillar is usually first made on one side of a glass core substrate, and then a redistribution layer (RDL) or an accumulated wiring film layer (ABF) is constructed on the copper pillar after plastic encapsulation and grinding, and then RDL or ABF is also made on the other side of the glass core substrate, and finally the chip and the conductive balls are arranged to form a chip packaging structure 1. However, this packaging method is prone to warping of the chip packaging structure 1 due to the mismatch of the coefficient of thermal expansion (CTE) of the materials between the RDL, ABF and the copper pillars, thereby affecting the product yield of the chip packaging structure 1. In this embodiment, the first circuit layer 30 and the second circuit layer 40 are respectively made on the first glass core substrate 10 and the second glass core substrate 20 and then bonded together, thereby reducing the warping of the chip packaging structure 1 caused by the CTE mismatch between the materials when made on the same glass core substrate, thereby improving the product yield of the chip packaging structure 1.
[0061] Step S140 , disposing at least one chip 50 connected to the wiring in the first circuit layer 30 on the first circuit layer 30 , and manufacturing a plastic packaging layer 60 for packaging at least the chip 50 .
[0062] In this embodiment, the plastic layer 60 is used to protect the chip 50 from the influence of the external environment, such as moisture, dust or mechanical impact.
[0063] Step S150 , disposing a plurality of conductive balls 70 on the second circuit layer 40 and connected to the wiring in the second circuit layer 40 , to obtain a chip packaging structure 1 .
[0064] In this embodiment, the conductive balls 70 are used to realize electrical connection between the chip package structure 1 and other external circuit elements or substrates.
[0065] It is worth noting that the conductive ball 70 can be a solder ball.
[0066] Furthermore, in step S110, the method includes:
[0067] First, a first carrier board and a second carrier board are provided.
[0068] In this embodiment, the first carrier plate and the second carrier plate are used as a temporary supporting structure for fixing and carrying the first glass core substrate 10 and the second glass core substrate 20 .
[0069] It is worth noting that the materials of the first carrier plate and the second carrier plate can be silicon, ceramic or metal, etc. The materials of the first carrier plate and the second carrier plate are not specifically limited here and can be selected according to actual conditions.
[0070] Next, a first removable adhesive layer and a second removable adhesive layer are coated on one side of the first carrier plate and the second carrier plate respectively.
[0071] In this embodiment, the first removable adhesive layer and the second removable adhesive layer generally have good adhesion and controllable separation performance, and can be easily removed after the production of the first circuit layer 30 and the second circuit layer 40 is completed, so as to separate the first carrier board and the first glass core substrate 10, and separate the second carrier board and the second glass core substrate 20.
[0072] Finally, a first glass core substrate 10 is disposed on the first separable adhesive layer, and a second glass core substrate 20 is disposed on the second separable adhesive layer.
[0073] Further, after step S120, the method includes:
[0074] The first removable adhesive layer is removed to separate the first carrier plate and the first glass core substrate 10 , and the second removable adhesive layer is removed to separate the second carrier plate and the second glass core substrate 20 .
[0075] Further, in step S120, the method includes:
[0076] First, multiple layers of first wiring layers 301 are sequentially manufactured on one side of the first glass core substrate 10 , and insulating layers are manufactured between adjacent first wiring layers 301 , so that the first circuit layer 30 is manufactured on one side of the first glass core substrate 10 .
[0077] Next, multiple layers of second wiring layers 401 are sequentially manufactured on one side of the second glass core substrate 20 , and insulating layers are manufactured between adjacent second wiring layers 401 , so that a second circuit layer 40 is manufactured on one side of the second glass core substrate 20 .
[0078] In this embodiment, when a multi-layer circuit structure is required, the first wiring layer 301 and the insulating layer should be repeatedly and alternately manufactured to form the first wiring layer 30, and the second wiring layer 401 and the insulating layer should be repeatedly and alternately manufactured to form the second wiring layer 40. The first wiring layer 301 or the second wiring layer 401 of each layer realizes electrical connection between layers to meet complex circuit requirements.
[0079] Based on the same inventive concept, see Figure 3 and Figure 4a-4c , Figure 3 A step diagram of a method for preparing a chip packaging structure 1 provided in this embodiment, Figure 4a-4c for Figure 3 The corresponding process flow chart, where: Figure 4a and Figure 4b is a process flow chart corresponding to step S210 and step S220, Figure 4c 2 is a process flow chart corresponding to step S230, step S240 and step S250. Another object of the present application is to provide a method for preparing a chip packaging structure 1, the method comprising:
[0080] Step S210, providing a third glass core substrate 80 and a fourth glass core substrate 90, wherein the third glass core substrate 80 includes two third sub-glass core substrates 801 stacked and interconnected, and the fourth glass core substrate 90 includes two fourth sub-glass core substrates 901 stacked and interconnected, wherein the glass core substrate is provided with a conductive trace running through the glass core substrate.
[0081] In this step, one side of two third sub-glass core substrates 801 are connected to each other through a first adhesive layer, and one side of two fourth sub-glass core substrates 901 are connected to each other through a second adhesive layer.
[0082] Step S220, making a first circuit layer 30 on opposite sides of the third glass core substrate 80, and making a second circuit layer 40 on opposite sides of the third glass core substrate 80, wherein the conductive traces in the third glass core substrate 80 are connected to the traces in the first circuit layer 30, and the conductive traces in the fourth glass core substrate 90 are connected to the traces in the second circuit layer 40.
[0083] Step S230 , bonding a side of any third sub-glass core substrate 801 away from the first circuit layer 30 and a side of any fourth sub-glass core substrate 901 away from the second circuit layer 40 , wherein the conductive traces in the third sub-glass core substrate 801 are connected to the conductive traces in the fourth sub-glass core substrate 901 .
[0084] In this step, chemical mechanical polishing (CMP) is first performed on the side of any third sub-glass core substrate 801 away from the first circuit layer 30 and the side of any fourth sub-glass core substrate 901 away from the second circuit layer 40, so that the side of the third glass core substrate 80 away from the first circuit layer 30 and the side of the fourth sub-glass core substrate 901 away from the second circuit layer 40 remain flat. Then the two are hybrid bonded, which is usually performed in a high temperature environment, and finally the electrical connection between the first circuit layer 30, the third sub-glass core substrate 801, the fourth sub-glass core substrate 901 and the second circuit layer 40 is achieved.
[0085] In this embodiment, after the first circuit layer 30 and the second circuit layer 40 are respectively manufactured on the opposite sides of the third glass core substrate 80 and the fourth glass core substrate 90, the first circuit layer 30 of the third glass core substrate 80 and the second circuit layer 40 of the second glass core substrate 20 are bonded together, thereby reducing the warping phenomenon of the chip packaging structure 1 caused by the CTE mismatch between the materials when manufactured on the same glass core substrate, thereby improving the product yield of the chip packaging structure 1. In addition, the circuit layers are simultaneously manufactured on the opposite sides of the third glass core substrate 80 and the fourth glass core substrate 90, thereby improving the production efficiency of the chip packaging structure 1.
[0086] Step S240 , disposing at least one chip 50 connected to the wiring in the first circuit layer 30 on the first circuit layer 30 , and manufacturing a plastic packaging layer 60 for packaging at least the chip 50 .
[0087] Step S250 , disposing a plurality of conductive balls 70 connected to the wirings in the second circuit layer 40 on the second circuit layer 40 , to obtain a chip packaging structure 1 .
[0088] Further, in step S210, the method includes:
[0089] The third glass core substrate 80 is obtained by bonding two third sub-glass core substrates 801 through a first bonding layer, and the fourth glass core substrate 90 is obtained by bonding two fourth sub-glass core substrates 901 through a second bonding layer.
[0090] In this embodiment, the materials of the first adhesive layer and the second adhesive layer may be epoxy resin or other adhesive materials. The materials of the first adhesive layer and the second adhesive layer are not specifically limited here and can be selected according to actual conditions.
[0091] Furthermore, the first circuit layer 30 and the second circuit layer 40 of the present embodiment have the same type of circuit layer structure, wherein the types of circuit layer structures include redistribution layer structure (RDL) and ABF circuit layer structure.
[0092] For example, the first circuit layer 30 and the second circuit layer 40 can be multi-layer RDL or multi-layer ABF. RDL is mainly composed of dielectric materials such as polyimide and copper metal, and ABF is made of a composite material mainly composed of epoxy resin, silicon powder and curing agent.
[0093] Furthermore, the first circuit layer 30 and the second circuit layer 40 of this embodiment have different types of circuit layer structures. For example, the first circuit layer 30 may be a multi-layer RDL, and the second circuit layer 40 may be a multi-layer ABF, or the first circuit layer 30 may be a multi-layer ABF, and the second circuit layer 40 may be a multi-layer RDL.
[0094] Based on the same inventive concept, another object of the present application is to provide a chip packaging structure 1, see Figure 5 , Figure 5 The schematic diagram of a chip packaging structure 1 provided in this embodiment includes a first glass core substrate 10 , a second glass core substrate 20 , a first circuit layer 30 , a second circuit layer 40 , a chip 50 , a plastic packaging layer 60 and a conductive ball 70 .
[0095] The second glass core substrate 20 is disposed on one side of the first glass core substrate 10 , wherein the glass core substrate is provided with a conductive trace penetrating the glass core substrate, and the conductive trace in the first glass core substrate 10 is connected to the conductive trace in the second glass core substrate 20 .
[0096] The first circuit layer 30 is arranged on a side of the first glass core substrate 10 away from the second glass core substrate 20, and the routing in the first circuit layer 30 is connected to the conductive routing in the first glass core substrate 10. The second circuit layer 40 is arranged on a side of the second glass core substrate 20 away from the first glass core substrate 10, and the routing in the second circuit layer 40 is connected to the conductive routing in the second glass core substrate 20.
[0097] In this embodiment, the side of the first glass core substrate 10 facing away from the first circuit layer 30 and the side of the first circuit layer 30 of the second glass core substrate 20 are hybrid bonded to achieve electrical connection between the first circuit layer 30, the first glass core substrate 10, the second glass core substrate 20 and the second circuit layer 40.
[0098] The chip 50 is disposed on a side of the first circuit layer 30 away from the first glass core substrate 10 . The chip 50 is connected to the wiring in the first circuit layer 30 . The plastic packaging layer 60 is at least disposed around the chip 50 .
[0099] In this embodiment, the plastic layer 60 is used to protect the chip 50 from the influence of the external environment, such as moisture, dust or mechanical impact.
[0100] The conductive balls 70 are disposed on a side of the second circuit layer 40 away from the second glass core substrate 20 , and the conductive balls 70 are connected to the wiring in the second circuit layer 40 .
[0101] In this embodiment, the conductive balls 70 are used to realize electrical connection between the chip package structure 1 and other external circuit elements or substrates.
[0102] Further, please see again Figure 5 In this embodiment, the conductive traces of the first glass core substrate 10 and the conductive traces of the second glass core substrate 20 are arranged correspondingly and connected to each other. In this way, the electrical connection between the first circuit layer 30, the first glass core substrate 10, the second glass core substrate 20, and the second circuit layer 40 is achieved.
[0103] Further, please see again Figure 5The first circuit layer 30 includes a plurality of stacked first routing layers 301 and an insulating layer (not shown) between adjacent first routing layers 301, and adjacent first routing layers 301 are connected through insulating layer through holes (not shown). The second circuit layer 40 includes a plurality of stacked second routing layers 401 and an insulating layer between adjacent second routing layers 401, and adjacent second routing layers 401 are connected through insulating layer through holes.
[0104] In this embodiment, the types of the first wiring layer 301 and the second wiring layer 401 can be RDL or ABF at the same time, that is, the first wiring layer 30 and the second wiring layer 40 can be multi-layer RDL or multi-layer ABF at the same time.
[0105] In addition, the type of the first wiring layer 301 can be RDL, and the type of the second wiring layer 401 can be ABF, then the first wiring layer 30 is a multi-layer RDL, and the second wiring layer 40 is a multi-layer ABF. Or, the type of the first wiring layer 301 can be ABF, and the type of the second wiring layer 401 can be RDL, then the first wiring layer 30 is a multi-layer ABF, and the second wiring layer 40 is a multi-layer RDL.
[0106] In summary, the present application provides a method for preparing a chip packaging structure and a chip packaging structure. First, a first glass core substrate and a second glass core substrate are provided, wherein the glass core substrate is provided with a conductive trace that runs through the glass core substrate. Then, a first circuit layer and a second circuit layer are respectively made on one side of the first glass core substrate and the second glass core substrate. Then, the side of the first glass core substrate facing away from the first circuit layer and the side of the second glass core substrate facing away from the second circuit layer are bonded. Finally, at least one chip connected to the trace in the first circuit layer is arranged on the first circuit layer, and a plastic sealing layer for encapsulating at least the chip is prepared, and a plurality of conductive balls connected to the trace in the second circuit layer are arranged on the second circuit layer to obtain a chip packaging structure. In this way, the above scheme can reduce the warping phenomenon of the chip packaging structure, thereby improving the product yield of the chip packaging structure.
[0107] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a chip packaging structure, characterized in that: The method comprises: Providing a first glass core substrate and a second glass core substrate, wherein the glass core substrate is provided with a conductive trace penetrating the glass core substrate; A first circuit layer and a second circuit layer are respectively manufactured on one side of the first glass core substrate and the second glass core substrate, wherein the conductive traces in the first glass core substrate are connected to the traces in the first circuit layer, and the conductive traces in the second glass core substrate are connected to the traces in the second circuit layer; Bonding a side of the first glass core substrate away from the first circuit layer and a side of the second glass core substrate away from the second circuit layer, wherein the conductive traces in the first glass core substrate and the conductive traces in the second glass core substrate are connected; Arrange at least one chip connected to the wiring in the first circuit layer on the first circuit layer, and make a plastic packaging layer that at least encapsulates the chip; A plurality of conductive balls connected to the wiring in the second circuit layer are arranged on the second circuit layer to obtain a chip packaging structure.
2. The method for preparing a chip packaging structure according to claim 1, characterized in that: In the step of providing a first glass core substrate and a second glass core substrate, the method includes: Providing a first carrier board and a second carrier board; Coating a first removable adhesive layer and a second removable adhesive layer on one side of the first carrier plate and the second carrier plate respectively; A first glass core substrate is disposed on the first separable adhesive layer, and a second glass core substrate is disposed on the second separable adhesive layer.
3. The method for preparing a chip packaging structure according to claim 2, characterized in that: After the step of respectively manufacturing the first circuit layer and the second circuit layer on one side of the first glass core substrate and the second glass core substrate, the method includes: The first separable adhesive layer is removed to separate the first carrier plate from the first glass core substrate, and the second separable adhesive layer is removed to separate the second carrier plate from the second glass core substrate.
4. The method for preparing a chip packaging structure according to claim 1, characterized in that: In the step of respectively manufacturing the first circuit layer and the second circuit layer on one side of the first glass core substrate and the second glass core substrate, the method includes: A plurality of first wiring layers are sequentially manufactured on one side of the first glass core substrate, and an insulating layer is manufactured between adjacent first wiring layers, so as to obtain a first circuit layer on one side of the first glass core substrate; Multiple layers of second wiring layers are sequentially manufactured on one side of the second glass core substrate, and insulating layers are manufactured between adjacent second wiring layers, so that a second circuit layer is manufactured on one side of the second glass core substrate.
5. A method for preparing a chip packaging structure, characterized in that: The method comprises: Providing a third glass core substrate and a fourth glass core substrate, wherein the third glass core substrate comprises two third sub-glass core substrates stacked and connected to each other, and the fourth glass core substrate comprises two fourth sub-glass core substrates stacked and connected to each other, wherein the glass core substrate is provided with a conductive trace penetrating the glass core substrate; A first circuit layer is fabricated on two opposite sides of the third glass core substrate, and a second circuit layer is fabricated on two opposite sides of the third glass core substrate, wherein the conductive traces in the third glass core substrate are connected to the traces in the first circuit layer, and the conductive traces in the fourth glass core substrate are connected to the traces in the second circuit layer; Bonding a side of any one of the third sub-glass core substrates away from the first circuit layer and a side of any one of the fourth sub-glass core substrates away from the second circuit layer, wherein the conductive traces in the third sub-glass core substrate and the conductive traces in the fourth sub-glass core substrate are connected; Arrange at least one chip connected to the wiring in the first circuit layer on the first circuit layer, and make a plastic packaging layer that at least encapsulates the chip; A plurality of conductive balls connected to the wiring in the second circuit layer are arranged on the second circuit layer to obtain a chip packaging structure.
6. The method for preparing a chip packaging structure according to claim 5, characterized in that: In the step of providing a third glass core substrate and a fourth glass core substrate, the method includes: The two third sub-glass core substrates are bonded together through a first bonding layer to obtain a third glass core substrate, and the two fourth sub-glass core substrates are bonded together through a second bonding layer to obtain a fourth glass core substrate.
7. The method for preparing a chip packaging structure according to any one of claims 1 to 6, characterized in that: The first circuit layer and the second circuit layer have the same type of circuit layer structure, or the first circuit layer and the second circuit layer have different types of circuit layer structures; Among them, the types of circuit layer structures include redistribution layer structure and ABF circuit layer structure.
8. A chip packaging structure, characterized in that: The chip packaging structure comprises: a first glass core substrate; A second glass core substrate is disposed on one side of the first glass core substrate, wherein the glass core substrate is provided with a conductive trace penetrating the glass core substrate, and the conductive trace in the first glass core substrate is connected to the conductive trace in the second glass core substrate; A first circuit layer is arranged on a side of the first glass core substrate away from the second glass core substrate, and the wiring in the first circuit layer is connected to the conductive wiring in the first glass core substrate; A second circuit layer is arranged on a side of the second glass core substrate away from the first glass core substrate, and the wiring in the second circuit layer is connected to the conductive wiring in the second glass core substrate; A chip is arranged on a side of the first circuit layer away from the first glass core substrate, and the chip is connected to the wiring in the first circuit layer; A plastic packaging layer, at least arranged around the chip; The conductive balls are arranged on a side of the second circuit layer away from the second glass core substrate, and the conductive balls are connected to the wiring in the second circuit layer.
9. The chip packaging structure according to claim 8, characterized in that: The conductive traces of the second glass core substrate are arranged corresponding to the conductive traces of the second glass core substrate and are connected to each other.
10. The chip packaging structure according to claim 8, characterized in that: The first circuit layer includes a plurality of stacked first wiring layers and an insulating layer between adjacent first wiring layers, and adjacent first wiring layers are connected via insulating layer through holes; The second circuit layer includes a plurality of stacked second wiring layers and an insulating layer between adjacent second wiring layers, and adjacent second wiring layers are connected via insulating layer through holes.