Chip packaging structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a chip packaging structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of chip packaging, and aims to solve the problems that when a plurality of bare chips are stacked in the chip packaging structure, the mechanical property of the chip packaging structure is reduced, the overall strength is reduced, and the bending deformation resistance becomes poor. The chip packaging structure comprises a substrate, a bare chip, a spacing layer, a first adhesive film and a second adhesive film. The plurality of bare chips are stacked in a direction perpendicular to the substrate; the spacing layer is arranged on one side, far away from the substrate, of the plurality of bare chips; the first adhesive film is located between the spacing layer and the plurality of bare chips; the second adhesive film is located between the substrate and the plurality of bare chips. Wherein the elastic modulus of the first adhesive film is greater than that of the second adhesive film. The chip packaging structure can be applied to a storage system so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of chip packaging technology, and in particular to a chip packaging structure and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] Some semiconductor chips (e.g., flash memory) have been widely used for data storage. Users of these semiconductor chips expect that data storage capacity will continue to grow, and manufacturers strive to provide larger storage capacity in a low-cost manner while maintaining a standard package size to ensure compatibility with existing electronic devices. Summary of the invention

[0003] Embodiments of the present disclosure provide a chip packaging structure and a method for preparing the same, a storage system, and an electronic device, aiming to improve the overall strength of the chip packaging structure and its ability to resist bending and deformation.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, a chip packaging structure is provided. The chip packaging structure includes a substrate, a plurality of bare chips, a spacer layer, a first adhesive film, and a second adhesive film. The plurality of bare chips are stacked in a direction perpendicular to the substrate; the spacer layer is disposed on a side of the plurality of bare chips away from the substrate; the first adhesive film is located between the spacer layer and the plurality of bare chips; and the second adhesive film is located between the substrate and the plurality of bare chips. The elastic modulus of the first adhesive film is greater than the elastic modulus of the second adhesive film.

[0006] The chip packaging structure provided by the above-mentioned embodiments of the present disclosure can reduce the tensile stress on the chip packaging structure under positive bending by arranging a spacer layer on the side of the multiple bare chips away from the substrate, and arranging a first adhesive film between the spacer layer and the multiple bare chips, and the elastic modulus of the first adhesive film is greater than the elastic modulus of the second adhesive film located between the substrate and the multiple bare chips. This can enable the chip packaging structure to resist greater deformation and improve the ability of the chip packaging structure to resist external loads. That is, such a design improves the mechanical properties of the chip packaging structure, and improves the overall strength of the chip packaging structure and the ability to resist bending deformation.

[0007] In some embodiments, the elastic modulus of the first adhesive film is 1 GPa♂10 GPa. Since the first adhesive film has a high elastic modulus, the tensile stress of the chip packaging structure under positive bending can be reduced, which is beneficial to further improve the overall ability of the chip packaging structure to resist external loads and bending deformation.

[0008] In some embodiments, the thickness of the first adhesive film is less than the thickness of the second adhesive film, that is, the thickness of the second adhesive film is larger, which can protect the bare die closest to the substrate among the multiple bare die, and reduce the probability of warping or even breaking of the bare die closest to the substrate among the multiple bare die during the preparation of the chip packaging structure.

[0009] In some embodiments, the elastic modulus of the spacer layer is 100 GPa to 500 GPa. Since the spacer layer has a higher elastic modulus, it is beneficial to improve the overall ability of the chip packaging structure to resist external loads and bending deformation.

[0010] In some embodiments, the plastic strain of the spacer layer is greater than or equal to 0.5%. Since the spacer layer has a higher plastic strain, it is beneficial to improve the ability of the chip packaging structure to resist fracture in a high stress area.

[0011] In some embodiments, the chip packaging structure further includes a packaging layer, which is located on the substrate and surrounds the spacer layer and the plurality of bare chips. By providing the packaging layer, the strength of the chip packaging structure can be increased, and the bare chips in the chip packaging structure can be protected from the influence of the external environment (water vapor, temperature, pollution, etc.).

[0012] In some embodiments, the bonding strength between the spacer layer and the packaging layer is greater than or equal to the bonding strength between the plurality of bare chips and the packaging layer, which can prevent the bonding interface between the spacer layer and the packaging layer from separating when the chip packaging structure is bent under force.

[0013] In some embodiments, the thermal expansion coefficient of the spacer layer is greater than or equal to the thermal expansion coefficient of the bare chip, and less than or equal to the thermal expansion coefficient of the packaging layer. This can reduce the stress generated during the manufacturing process of the chip packaging structure, thereby reducing the risk of cracking at the connection interface between the packaging layer and the spacer layer, and the connection interface between the spacer layer and the bare chip in the chip packaging structure, which is beneficial to improving the stability of the chip packaging structure.

[0014] In some embodiments, a surface of the spacer layer away from the substrate is at least partially flush with a surface of the packaging layer away from the substrate; or, a surface of the spacer layer away from the substrate is lower than a surface of the packaging layer away from the substrate, and the packaging layer covers the surface of the spacer layer away from the substrate.

[0015] In some embodiments, the spacer layer and the first adhesive film have the same shape and are equal in size, and the orthographic projection of the first adhesive film on the spacer layer overlaps with the spacer layer.

[0016] In some embodiments, the stacking manner between the spacer layer and the die farthest from the substrate among the multiple dies is staggered stacking, which can expose the die bonding points set on the top surface of the die farthest from the substrate among the multiple dies, making it convenient to use the die bonding points for further wire bonding.

[0017] In some embodiments, the stacking manner between two adjacent die in the plurality of die is staggered stacking, which can expose the die bonding pads on the top surfaces of the die, so that the die bonding pads can be used for further wire bonding.

[0018] In some embodiments, the chip packaging structure further includes a third adhesive film, and the third adhesive film is located between two adjacent bare chips among the plurality of bare chips. The elastic modulus of the first adhesive film is greater than the elastic modulus of the third adhesive film. The third adhesive film can be used to connect two adjacent bare chips among the plurality of bare chips, which is beneficial to improving the stability of the chip packaging structure.

[0019] On the other hand, a method for preparing a chip packaging structure is provided, comprising: providing a substrate; stacking a plurality of bare chips in a vertical direction of the substrate, wherein the substrate and the plurality of bare chips are connected by a second adhesive film; stacking a spacer layer on a side of the plurality of bare chips away from the substrate, wherein the spacer layer and the plurality of bare chips are connected by a first adhesive film; and the elastic modulus of the first adhesive film is greater than the elastic modulus of the second adhesive film.

[0020] In some embodiments, two adjacent dies among the plurality of dies are connected via a third adhesive film, and an elastic modulus of the first adhesive film is greater than an elastic modulus of the third adhesive film.

[0021] On the other hand, a storage system is provided, comprising: the chip packaging structure as described above and a controller; the controller is electrically connected to the chip packaging structure.

[0022] On the other hand, an electronic device is provided, comprising: a processor and the storage system as described above, wherein the processor is coupled to the storage system; or comprising: a printed circuit board, and the chip packaging structure as described above, wherein the chip packaging structure is arranged on the printed circuit board and electrically connected to the printed circuit board.

[0023] It can be understood that the beneficial effects that can be achieved by the chip packaging structure preparation method, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the chip packaging structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0025] Figure 1A structural diagram of a chip packaging structure provided in the related art;

[0026] Figure 2 A structural diagram of a chip packaging structure provided according to some embodiments;

[0027] Figure 3 It is a schematic diagram of the three-point bending test;

[0028] Figure 4 A schematic diagram of the force of a chip packaging structure provided according to the relevant technology;

[0029] Figure 5 A schematic diagram of the force of a chip packaging structure provided according to some embodiments;

[0030] Figure 6 A coordinate diagram of displacement and strain of a top die and a packaging layer in a chip packaging structure provided according to some embodiments and related technologies when subjected to force;

[0031] Figure 7 A comparison diagram of strains of the first adhesive film and the packaging layer with different elastic moduli under the same force provided by some embodiments;

[0032] Figure 8 Another structural diagram of a chip packaging structure provided according to some embodiments;

[0033] Fig. 9 is another structural diagram of a chip packaging structure provided according to some embodiments;

[0034] Fig.10 A flowchart of a chip packaging structure preparation method according to some embodiments;

[0035] Fig.11 A structural diagram of a storage system provided according to some embodiments;

[0036] Fig.12 A structural diagram of an electronic device provided according to some embodiments;

[0037] Fig.13 Another structural diagram of an electronic device provided according to some embodiments. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0039] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0040] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0041] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0042] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0043] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0044] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0045] The bare die involved in the embodiments of the present disclosure is a device that has not been packaged after the wafer has been cut and tested. This bare die has a pad for packaging and may not be directly applied to an actual circuit. When the bare die is packaged into a semiconductor chip, it can be applied to an actual circuit.

[0046] The above-mentioned bare chips may include NAND-type flash memory bare chips, DRAM (dynamic random access memory) bare chips, SRAM (static random access memory) bare chips, etc.

[0047] By stacking multiple semiconductor dies (which can be expressed as Die in English) in a single chip package structure, the storage density of a single chip package structure can be increased. Compared with a single die, the increase in the number of dies will correspondingly increase the storage capacity. Figure 1 As shown, a plurality of dies 3 can be stacked on the substrate 2 in a vertical direction. However, when the number of dies 3 in the chip packaging structure 10' is large, the overall strength of the chip packaging structure 10' will be reduced, and the ability to resist bending deformation will be poor.

[0048] Based on this, in order to improve the overall strength of the chip packaging structure and the ability to resist bending deformation, an embodiment of the present disclosure provides a chip packaging structure.

[0049] Figure 2 A structural diagram of a chip packaging structure 10 provided in some embodiments of the present disclosure. The chip packaging structure 10 includes a substrate 2, a plurality of bare chips 3, a spacer layer 5, a first adhesive film 41 and a second adhesive film 42. The plurality of bare chips 3 are stacked in a direction perpendicular to the substrate 2, and the substrate 2 is used to carry the plurality of bare chips 3. It should be noted that, as Figure 2As shown, eight dies 3 are vertically stacked on the substrate 2. However, based on actual needs, the number of dies 3 attached to the substrate 2 may not be limited to eight, and the dies 3 may be vertically stacked on each other and / or spaced apart laterally.

[0050] Please refer again Figure 2 The spacer layer 5 is disposed on the side of the plurality of dies 3 away from the substrate 2, that is, the spacer layer 5 is closer to the die 3 farthest from the substrate 2 among the plurality of dies 3 (hereinafter collectively referred to as the top die 3 for simplicity of description). When the chip package structure 10 is deformed (e.g., bent) by force, the top die 3 is usually the first to break, and the spacer layer 5 can protect the top die 3, and reduce the probability of the top die 3 breaking when the chip package structure 10 is deformed (e.g., bent) by force.

[0051] Please continue to refer to Figure 2 The second adhesive film 42 is located between the substrate 2 and the plurality of bare chips 3, that is, the second adhesive film 42 is located between the substrate 2 and the bare chip 3 closest to the substrate 2 among the plurality of bare chips 3 (hereinafter collectively referred to as the bottom bare chip 3 for simplicity of description), and can be used to connect the substrate 2 and the bottom bare chip 3. The first adhesive film 41 is located between the spacer layer 5 and the plurality of bare chips 3, that is, the first adhesive film 41 is located between the spacer layer 5 and the top bare chip 3, and can be used to connect the spacer layer 5 and the top bare chip 3. The elastic modulus of the first adhesive film 41 is greater than the elastic modulus of the second adhesive film 42.

[0052] It can be understood that the elastic modulus represents the stiffness of the material and is an indicator of the material's ability to resist elastic deformation. The smaller the elastic modulus, the easier it is to deform when subjected to external force.

[0053] By arranging a spacer layer 5 on a side of the plurality of bare chips 3 away from the substrate 2, and arranging a first adhesive film 41 between the spacer layer 5 and the plurality of bare chips 3, and the elastic modulus of the first adhesive film 41 is greater than the elastic modulus of the second adhesive film 42 located between the substrate 2 and the plurality of bare chips 3, the tensile stress on the chip packaging structure 10 under the action of positive bending can be reduced, so that the chip packaging structure 10 can resist greater deformation, and the ability of the chip packaging structure 10 to resist external loads can be improved. That is, such a design improves the mechanical properties of the chip packaging structure 10, and improves the overall strength and the ability of the chip packaging structure 10 to resist bending deformation.

[0054] Figure 4 FIG. 1 is a schematic diagram of the force of a chip packaging structure 10 ′ provided in the related art. Figure 5 FIG. 1 is a schematic diagram of the force acting on a chip package structure 10 provided according to some embodiments. Figure 4 and Figure 5In the figure, the arrows point to the stress positions of the chip package structure 10 or 10' in the three-point bending test, the AA layer represents the neutral layer of the chip package structure 10 when it is bent under stress, and the AA' layer represents the neutral layer of the chip package structure 10' when it is bent under stress.

[0055] It should be noted that the three-point bending test refers to placing the object to be tested on two supporting points at a certain distance, applying an upward load to the object to be tested below the midpoint between the two supporting points, and three-point bending occurs when the three contact points of the object to be tested form two equal moments. The three-point bending test can be used to test the mechanical properties of the object to be tested.

[0056] like Figure 3 As shown, during the bending process of the tested object (chip package structure 10 or 10'), one side of the tested object (chip package structure 10 or 10') is stretched (hereinafter referred to as the tensile surface for simplicity of description), and the other side is squeezed (hereinafter referred to as the compressive surface for simplicity of description). There is a transition layer between the tensile surface and the compressive surface that is neither tensile nor compressive, and the stress is almost zero. The transition layer here is a neutral layer, that is, the aforementioned neutral layer AA or AA'. And the closer the position of the tested object (chip package structure 10 or 10') is to the neutral layer, the smaller the tensile stress or compressive stress it is subjected to.

[0057] like Figure 4 and Figure 5 As shown, in the three-point bending test, the top die 3 is subjected to tensile stress.

[0058] Figure 4 The distance between the neutral layer AA' and the top die 3 of the middle chip package structure 10' is d1. Figure 4 , Figure 5 The neutral layer AA of the middle chip package structure 10 is closer to the top die 3, that is, Figure 5 The distance d2 between the neutral layer AA and the top die 3 is less than Figure 4 The distance between the neutral layer AA' and the top die 3 is d1. Since the closer to the neutral layer AA / AA', that is, the smaller the distance between the neutral layer AA / AA', the smaller the tensile stress or compressive stress it is subjected to, in the three-point bending test, Figure 5 The tensile stress on the top die 3 in the chip package structure 10 is less than Figure 4 The top die 3 in the mid-chip package structure 10'.

[0059] That is, by arranging a spacer layer 5 on the side of the plurality of bare chips 3 away from the substrate 2, and arranging a first adhesive film 41 between the spacer layer 5 and the plurality of bare chips 3, and the elastic modulus of the first adhesive film 41 is greater than the elastic modulus of the second adhesive film 42 located between the substrate 2 and the plurality of bare chips 3, the position of the neutral layer AA in the chip packaging structure 10 can be changed, so that the distance between the neutral layer AA and the top bare chip 3 is reduced. Since the closer the top bare chip 3 is to the neutral layer AA, the smaller the tensile stress it is subjected to, the tensile stress of the top bare chip 3 under the positive bending action decreases, so that the chip packaging structure 10 can resist greater deformation when performing a three-point bending test, and the ability of the chip packaging structure 10 to resist external loads can be improved. It can be understood that the overall strength and the ability to resist bending deformation of the chip packaging structure 10 are improved by adopting such a design.

[0060] Furthermore, Figure 6 The coordinate diagram of the displacement and strain of the packaging layer 1 and the top die 3 in the chip packaging structure 10 provided in some embodiments and the chip packaging structure 10' provided in the related art when subjected to force deformation. The X-axis represents displacement, the Y-axis represents strain, the dotted line B represents the limit strain of the packaging layer 1, and the dotted line C represents the limit strain of the top die 3. The solid line M' represents the corresponding relationship between the displacement and strain of the packaging layer 1 in the chip packaging structure 10' when subjected to force deformation, the solid line N' represents the corresponding relationship between the displacement and strain of the top die 3 in the chip packaging structure 10' when subjected to force deformation, and the solid arrow L1 represents the displacement when the top die 3 in the chip packaging structure 10' is at the limit strain. The dotted line M represents the corresponding relationship between the displacement and strain of the packaging layer 1 in the chip packaging structure 10 when subjected to force deformation, the dotted line N represents the corresponding relationship between the displacement and strain of the top die 3 in the chip packaging structure 10 when subjected to force deformation, and the dotted arrow L2 represents the displacement when the top die 3 in the chip packaging structure 10 is at the limit strain.

[0061] It should be noted that the above displacement refers to the change in the spatial position of the center point inside the packaging layer 1 or the top die 3 after the packaging layer 1 or the top die 3 is deformed by force. The above strain refers to the relative deformation degree of the center point inside the packaging layer 1 or the top die 3 under the action of external forces and other factors. The limit strain refers to the stage of plastic deformation of the packaging layer 1 or the top die 3 after exceeding its elastic limit. When the strain of the packaging layer 1 or the top die 3 reaches the limit strain, the packaging layer 1 or the top die 3 will not be able to restore its original shape and will show obvious plastic deformation.

[0062] like Figure 6As shown, the solid line M' and the dotted line M coincide, that is, the slopes of the solid line M' and the dotted line M are the same. Since the solid line M' represents the corresponding relationship between the displacement and strain of the packaging layer 1 in the chip packaging structure 10' when it is deformed by force, and the dotted line M represents the corresponding relationship between the displacement and strain of the packaging layer 1 in the chip packaging structure 10 when it is deformed by force, the corresponding relationship between the displacement and strain of the packaging layer 1 in the chip packaging structure 10' when it is deformed by force is the same as the corresponding relationship between the displacement and strain of the packaging layer 1 in the chip packaging structure 10 when it is deformed by force.

[0063] The slope of the solid line N' is greater than the slope of the dotted line N. Since the solid line N' represents the corresponding relationship between the displacement and strain of the top die 3 in the chip packaging structure 10' when it is deformed by force, and the dotted line N represents the corresponding relationship between the displacement and strain of the top die 3 in the chip packaging structure 10 when it is deformed by force, when the top die 3 in the chip packaging structure 10' and the top die 3 in the chip packaging structure 10 produce the same displacement, the strain of the top die 3 in the chip packaging structure 10' is greater. Figure 6 As shown, when the strains of the top die 3 in the chip package structure 10' and the top die 3 in the chip package structure 10 are the same and both are limit strains, the displacement L1 corresponding to the top die 3 in the chip package structure 10' is smaller than the displacement L2 corresponding to the top die 3 in the chip package structure 10. That is to say, compared with the top die 3 in the chip package structure 10', the top die 3 in the chip package structure 10 can resist greater bending deformation, further enabling the chip package structure 10 to resist greater deformation, and can improve the ability of the chip package structure 10 to resist external loads.

[0064] In some embodiments, the elastic modulus of the first adhesive film 41 is 1 GPa♂10 GPa.

[0065] Illustratively, the elastic modulus of the first adhesive film 41 may be 1 Gpa, 2 Gpa, 2.5 Gpa, 3 Gpa, 3.5 Gpa, 4 Gpa, 4.5 Gpa, 5 Gpa, 5.5 Gpa, 6 Gpa, 6.5 Gpa, 7 Gpa, 7.5 Gpa, 8 Gpa, 8.5 Gpa, 9 Gpa, 9.5 Gpa and 10 Gpa.

[0066] like Figure 7 As shown, Figure 7 The figure is a comparison diagram of the strain of the first adhesive film 41 and the packaging layer 1 with different elastic moduli when the top die 3 is subjected to the same force according to some embodiments. It should be noted that: Figure 7 FIG. 4 also shows the strain of the packaging layer 1 in the chip packaging structure 10 ′ when the top die 3 is subjected to the same force.

[0067] First, when the top die 3 is subjected to the same force, the strain of the encapsulation layer 1 in the chip encapsulation structure 10 is greater than that of the chip encapsulation structure 10'. That is, in order to make the top die 3 in the chip encapsulation structure 10 and the top die 3 in the chip encapsulation structure 10' subjected to the same force, the strain of the encapsulation layer 1 in the chip encapsulation structure 10 needs to be greater than the strain of the encapsulation layer 1 in the chip encapsulation structure 10'. That is, by arranging a spacer layer 5 on the side of the plurality of die 3 away from the substrate 2, and arranging a first adhesive film 41 between the spacer layer 5 and the plurality of die 3, and the elastic modulus of the first adhesive film 41 is greater than the elastic modulus of the second adhesive film 42, the chip encapsulation structure 10 can resist greater deformation and has a stronger ability to resist strain.

[0068] Secondly, when the top die 3 is subjected to the same force, as the elastic modulus of the first adhesive film 41 increases, the strain of the packaging layer 1 in the chip packaging structure 10 also increases, that is, the deformation degree of the packaging layer 1 increases, and the ability of the chip packaging structure 10 to resist bending deformation is gradually enhanced.

[0069] In some embodiments, Figure 2 As shown, the thickness h1 of the first adhesive film 41 is less than the thickness h2 of the second adhesive film 42. Since the second adhesive film 42 is located between the substrate 2 and the plurality of bare chips 3, and the second adhesive film 42 can be used to connect the substrate 2 and the bottom bare chip 3 among the plurality of bare chips 3, when the thickness h2 of the second adhesive film 42 is large, it can protect the bottom bare chip 3 and reduce the probability of warping or even breaking of the bottom bare chip 3 during the preparation of the chip packaging structure 10.

[0070] In some embodiments, the stacking mode between two adjacent dies 3 among the plurality of dies 3 is staggered stacking. That is, each die 3 is offset in a certain direction by a certain distance in turn, so that the orthographic projections of the plurality of dies 3 on the substrate 2 do not completely overlap, so as to ensure that the die bonding point disposed on the top surface of each die 3 is exposed for further wire bonding.

[0071] In some embodiments, the stacking mode between the spacer layer and the die 3 farthest from the substrate 2 (i.e., the top die 3) among the plurality of die 3 is also staggered stacking. The die bonding pads arranged on the top surface of the top die 3 can be exposed, so that the die bonding pads can be used for further wire bonding.

[0072] In some embodiments, the spacer layer 5 and the first adhesive film 41 have the same shape and are equal in size, and a boundary of the first adhesive film 41 coincides with a boundary of the spacer layer 5 .

[0073] In some embodiments, the elastic modulus of the spacer layer 5 is 100 GPa-500 GPa.

[0074] Exemplarily, the elastic modulus of the spacer layer 5 may be 100 Gpa, 200 Gpa, 250 Gpa, 300 Gpa, 400 Gpa or 500 Gpa.

[0075] In some embodiments, the plastic strain of the spacer layer 5 is greater than or equal to 0.5%. It should be noted that plastic strain refers to the irreversible deformation of an object when an external force is applied to the object and the external force exceeds a certain value.

[0076] Exemplarily, the plastic strain of the spacer layer 5 is 0.5%, 0.6%, 0.8%, 1%, 1.2%, 2%, 3%, 5%, or 6%.

[0077] Since the spacer layer 5 has a relatively high plastic strain and elastic modulus, the chip packaging structure 10 can improve its ability to resist fracture in high stress areas, and further improve the overall strength and the ability to resist bending deformation of the chip packaging structure 10 .

[0078] In some embodiments, the material of the spacer layer 5 includes metal. For example, the metal may be tungsten, stainless steel, titanium alloy, and of course, other suitable metal materials may also be selected, and the present disclosure does not make any specific limitation on this.

[0079] In some embodiments, the chip packaging structure 10 further includes a packaging layer 1. The packaging layer 1 is located on the substrate 2 and surrounds the spacer layer 5 and the plurality of bare chips 3; the packaging layer 1 is disposed outside the bare chips 3 by coating. On the one hand, the packaging layer 1 can increase the strength of the chip packaging structure 10, and on the other hand, the packaging layer 1 can also protect the bare chips 3 in the chip packaging structure 10, so that the bare chips 3 are not affected by the external environment (water vapor, temperature, pollution, etc.).

[0080] Exemplarily, the encapsulation layer 1 may include epoxy resin, expansion monomer and curing agent.

[0081] Exemplarily, the shape of the encapsulation layer 1 can be a cuboid, a cylinder, etc. When the encapsulation layer 1 is in a cuboid or a cylinder, the shape of the substrate 2 also matches the shape of the encapsulation layer 1. Specifically, the substrate 2 and the encapsulation layer 1 can be cut into a cylinder or a cuboid in the cutting process, and the final product shape is formed. The shape of the product after cutting is not specifically limited in this application.

[0082] For example, Figure 2 As shown, the above “encapsulation layer 1 surrounds the spacer layer 5” may be that the side surface of the spacer layer 5 away from the substrate 2 is set lower than the side surface of the encapsulation layer 1 away from the substrate 2, and the encapsulation layer 1 covers the side surface of the spacer layer 5 away from the substrate 2. It can be understood that the spacer layer 5 can be completely set in the encapsulation layer 1.

[0083] Or, if Figure 8 and Fig. 9 As shown, the above “encapsulation layer 1 surrounds the spacer layer 5” may also mean that the side surface of the spacer layer 5 away from the substrate 2 may also be set to be at least partially flush with the side surface of the encapsulation layer 1 away from the substrate 2. In this case, the encapsulation layer 1 does not cover the side surface of the spacer layer 5 away from the substrate 2, but is arranged around the spacer layer 5 and the plurality of bare chips 3.

[0084] For example, Figure 8 As shown, part of the surface of the side of the spacer layer 5 away from the substrate 2 is flush with the surface of the side of the encapsulation layer 1 away from the substrate 2, and part of the surface is lower or higher than the surface of the side of the encapsulation layer 1 away from the substrate 2. It can be understood that the surface of the side of the spacer layer 5 away from the substrate 2 may be undulating or rough, so that the lower position of the surface of the side of the spacer layer 5 away from the substrate 2 may be lower than the surface of the side of the encapsulation layer 1 away from the substrate 2, and the higher position of the surface of the side of the spacer layer 5 away from the substrate 2 may be higher than the surface of the side of the encapsulation layer 1 away from the substrate 2. Of course, there may be some areas on the surface of the side of the spacer layer away from the substrate 2 that are flush with the surface of the side of the encapsulation layer 1 away from the substrate 2.

[0085] For example, Fig. 9 As shown, the surface of the spacer layer 5 away from the substrate 2 is completely flush with the surface of the packaging layer 1 away from the substrate 2 .

[0086] In some embodiments, the bonding strength between the spacer layer 5 and the packaging layer 1 is greater than or equal to the bonding strength between the plurality of bare chips 3 and the packaging layer 1, which can avoid separation of the bonding interface between the spacer layer 5 and the packaging layer 1 when the chip packaging structure 10 is bent under force.

[0087] In some embodiments, the thermal expansion coefficient of the spacer layer 5 is greater than or equal to the thermal expansion coefficient of the die 3, and less than or equal to the thermal expansion coefficient of the encapsulation layer 1. It is understandable that the thermal expansion coefficient of the spacer layer 5 is between the thermal expansion coefficient of the die 3 and the thermal expansion coefficient of the encapsulation layer 1 and includes two end point values. Through the above-mentioned setting, the problem of excessive stress generated by heating and cooling during the manufacturing process of the chip packaging structure 10 can be improved, thereby reducing the risk of cracking of the connection interface between the encapsulation layer 1 and the spacer layer 5, and the connection interface between the spacer layer 5 and the die 3 in the chip packaging structure 10, which is conducive to improving the stability of the chip packaging structure 10.

[0088] In some embodiments, Figure 2 As shown, the chip packaging structure 10 further includes a third adhesive film 43. The third adhesive film 43 is located between two adjacent bare chips 3 among the plurality of bare chips 3, and can be used to connect two adjacent bare chips 3 among the plurality of bare chips 3.

[0089] In some embodiments, the elastic modulus of the first adhesive film 41 is greater than the elastic modulus of the third adhesive film 43. The first adhesive film 41 can have a relatively large elastic modulus, so that the tensile stress of the chip packaging structure 10 under the positive bending action is reduced, so that the chip packaging structure 10 can resist greater deformation, and the ability of the chip packaging structure 10 to resist external loads can be improved.

[0090] Exemplarily, the elastic modulus of the second adhesive film 42 and the third adhesive film 43 may be the same.

[0091] Exemplarily, the first adhesive film 41, the second adhesive film 42 and the third adhesive film 43 may all be DAF (Die Attach Film) adhesive films. It should be noted that, since the elastic modulus of the first adhesive film 41 is greater than the elastic modulus of the second adhesive film 42 and the third adhesive film 43, when the first adhesive film 41, the second adhesive film 42 and the third adhesive film 43 are all DAF (Die Attach Film) adhesive films, the first adhesive film 41 is a DAF (Die Attach Film) adhesive film with a different elastic modulus from the second adhesive film 42 or the third adhesive film 43.

[0092] Some embodiments of the present disclosure also provide a method for preparing a chip packaging structure 10, such as Fig.10 As shown, the preparation method comprises the following steps:

[0093] S1: providing a substrate 2;

[0094] S2: stacking a plurality of bare chips 3 in a vertical direction of the substrate 2, wherein the substrate 2 and the plurality of bare chips 3 are connected via a second adhesive film 42;

[0095] S3: stacking a spacer layer 5 on the side of the plurality of bare chips 3 away from the substrate 2, and connecting the spacer layer 5 and the plurality of bare chips 3 via a first adhesive film 41. The elastic modulus of the first adhesive film 41 is greater than the elastic modulus of the second adhesive film 42.

[0096] It should be noted that the elastic modulus and material of the first adhesive film 41, the elastic modulus, plasticity, and bonding strength, thermal expansion coefficient and material of the spacer layer 5, and the packaging layer 1 in the preparation method of the chip packaging structure 10 are the same as those of the first adhesive film 41 and the spacer layer 5 in the aforementioned chip packaging structure 10, and will not be repeated here.

[0097] Exemplarily, the encapsulation layer 1 may include epoxy resin, expansion monomer, curing agent and the like.

[0098] Exemplarily, the process of forming the encapsulation layer 1 may be one of a compression molding process, a transfer molding process, a liquid sealant curing molding process, a vacuum lamination process, and a spin coating process.

[0099] In some embodiments, two adjacent dies 3 among the plurality of dies 3 are connected via a third adhesive film 43 , wherein the elastic modulus of the third adhesive film 43 is smaller than the elastic modulus of the first adhesive film 41 .

[0100] Some embodiments of the present disclosure also provide a storage system 100. Fig.11 As shown, the storage system 100 includes: a controller 6 and a chip packaging structure 10 provided in any of the above embodiments. The bare die 3 in the chip packaging structure 10 may be a bare die including a storage array. The controller 6 may be electrically connected to the chip packaging structure 10 to control the chip packaging structure 10 to store data.

[0101] Exemplarily, the controller 6 is integrated with the chip packaging structure 10, the controller 6 is attached to the substrate 2, and the packaging layer 1 of the chip packaging structure 10 covers the controller 6. The controller 6 can also be arranged outside the chip packaging structure 10 and electrically connected to the chip packaging structure 10 through leads or a transfer layer.

[0102] The storage system 100 may be integrated into a memory card. The memory card includes, for example, any one of a PC card (Personal Computer Memory Card International Association, PCMCIA), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

[0103] The storage system 100 can also be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is, the storage system 100 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0104] In some embodiments, the controller 6 in the storage system 100 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0105] In other embodiments, the controller 6 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0106] In some embodiments, the controller 6 may be configured to manage data stored in the chip package structure 10 and communicate with an external device (eg, a host).

[0107] In some embodiments, the controller 6 may also be configured to control operations of the chip package structure 10 , such as read, erase, and program operations.

[0108] In some embodiments, the controller 6 may also be configured to manage various functions regarding data stored or to be stored in the chip package structure 10 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0109] In some embodiments, the controller 6 is further configured to process an error correction code on data read from or written to the chip package structure 10 .

[0110] Of course, the controller 6 may also perform any other suitable functions, such as formatting the chip package structure 10; for example, the controller 6 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0111] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0112] like Fig.12 and Fig.13As shown, the embodiment of the present disclosure further provides an electronic device 1000. The electronic device 1000 includes but is not limited to any one of a mobile phone, a tablet computer, a laptop, a television, a personal digital assistant (PDA), an ultra-mobile personal computer (UMPC), a netbook, a wearable device (such as a smart watch, a smart bracelet, smart glasses), etc. The embodiment of the present application does not limit the type of the electronic device.

[0113] In some embodiments, Fig.12 As shown, the electronic device 1000 may include the storage system 100 described above, and may also include a processor 7 , where the processor 7 is coupled to the storage system 100 to interact with the storage system 100 .

[0114] Exemplarily, the processor 7 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0115] In other embodiments, Fig.13 As shown, the electronic device 1000 further includes a printed circuit board 8 and a chip packaging structure 10 described in any of the above embodiments, and the chip packaging structure 10 is disposed on the printed circuit board 8 and electrically connected to the printed circuit board 8. Thus, the chip packaging structure 10 can realize signal transmission with other chips on the printed circuit board 8.

[0116] Exemplarily, one or more chip packaging structures 10 may be provided on the printed circuit board 8. In the case where multiple chip packaging structures 10 are provided on the printed circuit board 8, these chip packaging structures 10 may implement the same or different functions, for example, these chip packaging structures 10 may include a chip packaging structure 10 for logic operations, a chip packaging structure 10 with a storage function, etc.

[0117] Exemplarily, the chip package structure 10 can be electrically connected to the printed circuit board 8 via a ball grid array (BGA). In an optional embodiment, if the size of the chip package structure 10 is relatively large. In order to ensure the reliability of the electrical connection between the chip package structure 10 and the printed circuit board 8, a connection terminal (socket) with a slot-type fixing structure can also be used for connection, and the connection terminal can also be called a connector, a plug-in connector, etc.

[0118] For example, components such as capacitors, resistors, and inductors may also be disposed on the printed circuit board 8. Among them, the resistor can control the magnitude of the current through the resistance value, so that the current is properly adjusted in the circuit; the capacitor can store charge and release it when needed, and has the function of smoothing the power supply voltage, stabilizing the current, and in some cases can complete the filtering function of the electrical signal; the inductor has the characteristics of storing and releasing energy, and can complete the energy conversion and distribution of the circuit.

[0119] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: substrate; a plurality of dies stacked in a direction perpendicular to the substrate; A spacer layer is disposed on a side of the plurality of dies away from the substrate; A first adhesive film is located between the spacer layer and the plurality of bare chips; A second adhesive film is located between the substrate and the plurality of dies; Wherein, the elastic modulus of the first adhesive film is greater than the elastic modulus of the second adhesive film.

2. The chip packaging structure according to claim 1, characterized in that: The elastic modulus of the first adhesive film is 1 GPa to 10 GPa.

3. The chip packaging structure according to claim 1, characterized in that: The thickness of the first adhesive film is smaller than the thickness of the second adhesive film.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The elastic modulus of the spacer layer is 100 Gpa to 500 Gpa.

5. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The plastic strain of the spacer layer is greater than or equal to 0.5%.

6. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure further includes a packaging layer, which is located on the substrate and surrounds the spacer layer and the plurality of bare chips.

7. The chip packaging structure according to claim 6, characterized in that: The bonding strength between the spacer layer and the packaging layer is greater than or equal to the bonding strength between the plurality of dies and the packaging layer.

8. The chip packaging structure according to claim 6, characterized in that: The thermal expansion coefficient of the spacer layer is greater than or equal to the thermal expansion coefficient of the die, and less than or equal to the thermal expansion coefficient of the packaging layer.

9. The chip packaging structure according to claim 6, characterized in that: A surface of the spacer layer on one side away from the substrate is at least partially flush with a surface of the encapsulation layer on one side away from the substrate; or, A surface of the spacer layer on one side away from the substrate is lower than a surface of the packaging layer on one side away from the substrate, and the packaging layer covers a surface of the spacer layer on one side away from the substrate.

10. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The spacer layer and the first adhesive film have the same shape and are equal in size, and the orthographic projection of the first adhesive film on the spacer layer overlaps with the spacer layer.

11. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The stacking manner between the spacer layer and the die farthest from the substrate among the plurality of die is staggered stacking.

12. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The stacking mode between two adjacent bare chips in the plurality of bare chips is staggered stacking.

13. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure further includes a third adhesive film, wherein the third adhesive film is located between two adjacent bare chips among the plurality of bare chips; The elastic modulus of the first adhesive film is greater than the elastic modulus of the third adhesive film.

14. A method for preparing a chip packaging structure, characterized in that: include: providing a substrate; Stacking a plurality of bare chips in a vertical direction of the substrate, wherein the substrate and the plurality of bare chips are connected by a second adhesive film; A spacer layer is stacked on a side of the plurality of bare chips away from the substrate, and the spacer layer and the plurality of bare chips are connected via a first adhesive film; the elastic modulus of the first adhesive film is greater than the elastic modulus of the second adhesive film.

15. The method for preparing a chip packaging structure according to claim 14, characterized in that: Two adjacent bare chips among the plurality of bare chips are connected via a third adhesive film, and an elastic modulus of the first adhesive film is greater than an elastic modulus of the third adhesive film.

16. A method for preparing a chip packaging structure according to claim 14 or 15, characterized in that: The elastic modulus of the first adhesive film is 1 GPa to 10 GPa.

17. A storage system, characterized in that: include: The chip packaging structure according to any one of claims 1 to 13; A controller is electrically connected to the chip packaging structure.

18. An electronic device, characterized in that: include: A processor, and a storage system as claimed in claim 17, wherein the processor is coupled to the storage system; or, The invention comprises: a printed circuit board, and a chip packaging structure as claimed in any one of claims 1 to 13, wherein the chip packaging structure is arranged on the printed circuit board and is electrically connected to the printed circuit board.

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