Three-dimensional integrated circuit including switching cells

Abstract

The three-dimensional integrated circuit may include: a first switching unit on a first substrate within a first die of the plurality of dies, and configured to output a dummy power supply voltage based on a power supply voltage received from the outside; a first interface module on the first substrate and configured to enter an active mode based on a virtual supply voltage; and a second interface module on the second substrate within a second die of the plurality of dies bonded to the first die, and configured to enter an active mode with the first interface module based on a virtual power supply voltage.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0156752 filed in the Korean Intellectual Property Office on November 13, 2023, and Korean Patent Application No. 10-2024-0018836 filed in the Korean Intellectual Property Office on February 7, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a three-dimensional integrated circuit including a switch cell. Background Art

[0003] As electronic devices such as portable electronic devices are miniaturized, semiconductor devices mounted on electronic devices are also becoming increasingly miniaturized and lightweight. As semiconductor devices are miniaturized, in order to integrate more circuits in a limited space, three-dimensional integrated circuits stacking multiple chips are manufactured.

[0004] At the same time, as semiconductor devices become smaller and lighter, the demand for power saving is increasing. As one of these power saving methods, power gating technology is used. Power gating refers to a technology that uses a switch unit to provide a power supply voltage to a logic circuit in an active mode of the logic circuit and blocks the power supply voltage provided to the logic circuit in a sleep mode of the logic circuit, thereby reducing leakage current in the logic circuit. Summary of the invention

[0005] In general, in some embodiments, the present disclosure relates to a three-dimensional integrated circuit including a switch unit capable of effectively utilizing areas of a plurality of integrated circuits, and a three-dimensional integrated circuit including a switch unit capable of reducing power consumption.

[0006] An integrated circuit may include: a first switch unit on a first substrate within a first die among a plurality of stacked dies, the first switch unit being configured to output a virtual power supply voltage based on a power supply voltage received from outside the first die; a first interface circuit on the first substrate being configured to enter an active mode based on the virtual power supply voltage; and a second interface circuit on a second substrate within a second die bonded to the first die among the plurality of dies, the second interface circuit being configured to enter an active mode together with the first interface circuit based on the virtual power supply voltage.

[0007] An integrated circuit may include: a first die among a plurality of dies, the first die including: a first plurality of metal lines extending along a first direction; a plurality of switch units, arranged to overlap with the first plurality of metal lines and configured to provide a virtual power supply voltage to the first plurality of metal lines based on a power supply voltage received from outside the first die; and a first interface circuit, configured to enter an active mode based on the virtual power supply voltage; and a second die among the plurality of dies, the second die including: a second plurality of metal lines extending along the first direction, configured to receive the virtual power supply voltage from the first die; and a second interface circuit, arranged to overlap with the second plurality of metal lines, and enter an active mode together with the first interface circuit based on the virtual power supply voltage received from the second plurality of metal lines.

[0008] A semiconductor device may include: a first die, including: a switch unit, configured to output a first level of virtual power voltage based on a power voltage received from outside the first die; a first interface circuit, configured to output a logic signal based on the first level of virtual power voltage received from the switch unit; a level shifter, configured to output a second level of virtual power voltage different from the first level based on the first level of virtual power voltage received from the switch unit; a first through silicon via, configured to transmit the second level of virtual power voltage to the outside of the first die; and a second through silicon via, configured to transmit the logic signal to the outside of the first die; and a second die, including a second interface circuit, the second interface circuit receiving the logic signal through the second through silicon via based on the second level of virtual power voltage received from the first through silicon via. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a diagram illustrating an example of a three-dimensional integrated circuit with through silicon vias (TSVs) according to some embodiments.

[0011] Figure 2 is a diagram illustrating an example of a switch unit according to some embodiments.

[0012] Figure 3 is a diagram illustrating an example of a method of operating a three-dimensional integrated circuit according to some embodiments.

[0013] Figure 4 is a diagram showing that according to some embodiments Figure 3 A diagram of an example of a layout of a first semiconductor die.

[0014] Figure 5 is a diagram three-dimensionally illustrating an example of a metal line connected to a switching unit according to some embodiments.

[0015] Figure 6 is a schematic diagram showing a method according to some embodiments Figure 3 A diagram of an example of a layout of a second semiconductor die.

[0016] Figure 7 is a diagram three-dimensionally illustrating an example of a connection between a first semiconductor die and a second semiconductor die according to some embodiments.

[0017] Figure 8 is a schematic cross-sectional view of an example of a three-dimensional integrated circuit according to some embodiments.

[0018] Fig. 9 is a schematic cross-sectional view of an example of a three-dimensional integrated circuit according to some embodiments.

[0019] Fig.10 is a schematic cross-sectional view of an example of a three-dimensional integrated circuit according to some embodiments.

[0020] Fig.11 is a schematic cross-sectional view of an example of a three-dimensional integrated circuit according to some embodiments.

[0021] Fig.12 is a diagram for schematically illustrating an example of an operating method of a three-dimensional integrated circuit according to some embodiments.

[0022] Fig.13 is a diagram for schematically illustrating an example of an operating method of a three-dimensional integrated circuit according to some embodiments.

[0023] Fig.14 is a diagram illustrating an example of a three-dimensional integrated circuit according to some embodiments.

[0024] Fig.15 is a diagram illustrating an example of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0026] In the present disclosure, the size of the components is not limited to the disclosed ranges or values, but may vary according to process conditions and / or desired device characteristics. In addition, forming a first structure on or above a second structure may include an embodiment in which the first structure and the second structure are formed by direct contact, and may also include an embodiment in which an additional structure is formed between the first structure and the second structure so that the first structure and the second structure are not in direct contact. For simplicity and clarity, various structures may be arbitrarily drawn in different scales.

[0027] In addition, in order to facilitate the description of the relationship between the elements or structures shown in the figures and other elements or structures, terms with spatial relationships may be used, such as "below", "lower", "beneath", "above" and "top". In this specification, similar reference numerals represent similar elements.

[0028] In addition, unless explicit expressions such as "one" or "single" are used, expressions described in the singular may be interpreted as singular or plural. Terms including ordinal numbers (such as first and second) may be used to describe various components, but the components are not limited by these terms. These terms may be used for the purpose of distinguishing one component from another.

[0029] Figure 1 is a diagram illustrating an example of a three-dimensional integrated circuit with through silicon vias (TSVs) according to some embodiments. Figure 1 In the embodiment, the three-dimensional integrated circuit 10 may include semiconductor dies 11, 13, and 15 and a printed circuit board (PCB) 17. Each of the semiconductor dies 11, 13, and 15 of the three-dimensional integrated circuit 10 may be connected through a through silicon via 12. Each of the semiconductor dies 11, 13, and 15 may transmit and receive a logic signal or a power supply voltage through the through silicon via 12.

[0030] In some embodiments, at least one through silicon via 12 may configure a unit through via structure 19. The unit through via structure 19 may include a plurality of regularly arranged through silicon vias 18. For example, each of the semiconductor dies 11, 13, and 15 may transmit and receive logic signals or power supply voltages through the unit through via structure 19.

[0031] Additionally, in some embodiments, microbumps, solder bumps, hybrid copper bonds (HCBs), etc. may be located between semiconductor dies 11, 13, and 15. Semiconductor dies 11, 13, and 15 may be electrically connected by microbumps, solder bumps, hybrid copper bonds, etc. located between semiconductor dies 11, 13, and 15.

[0032] In some embodiments, at least one of the semiconductor dies 11, 13, and 15 may include a switch unit. The switch unit may receive a power supply voltage RVDD, and may output a virtual power supply voltage VVDD applied to a logic circuit that performs a preset logic operation. In some embodiments, only some (at least one) of the semiconductor dies 11, 13, and 15 may include a switch unit. The switch unit included only in at least one of the semiconductor dies 11, 13, and 15 may output a virtual power supply voltage, and may transmit the virtual power supply voltage to the remaining semiconductor dies through at least one through silicon via 12. The interface module included in each of the semiconductor dies 11, 13, and 15 may send and receive logic signals between the semiconductor dies 11, 13, and 15 based on the virtual power supply voltage.

[0033] Semiconductor dies 11 , 13 , and 15 and printed circuit board 17 may be electrically connected via microbumps, solder bumps, solder balls 14 , or the like.

[0034] Figure 2 is a diagram showing an example of a switch unit according to some embodiments. Figure 2 In the embodiment, the integrated circuit 200 may include a logic circuit 230 and a switch unit 210 configured to provide a power supply voltage to the logic circuit 230. Here, the integrated circuit 200 may refer to Figure 1 The integrated circuit 200 may be a system on chip (SOC), but is not limited thereto.

[0035] In some embodiments, the switch unit 210 may receive a power supply voltage RVDD from the outside. The switch unit 210 may represent an element configured to selectively prevent current from flowing through the switch unit 210 based on the control signal EN. The power supply voltage selectively output by the switch unit 210 may be referred to as a virtual power supply voltage VVDD. Depending on the virtual power supply voltage VVDD selectively output by the switch unit 210, the logic circuit 230 may operate in different modes. For example, in the active mode of the logic circuit 230, the switch unit 210 may provide the virtual power supply voltage VVDD to the logic circuit 230, and in the dormant mode of the logic circuit 230, the switch unit 210 may prevent the virtual power supply voltage VVDD from being provided to the logic circuit 230. Since the switch unit 210 selectively outputs the virtual power supply voltage VVDD according to the operation mode of the logic circuit 230, the leakage current of the logic circuit 230 may be reduced.

[0036] In some embodiments, the logic circuit 230 may receive a virtual power supply voltage VVDD from the switch unit 210, and also receive a ground voltage GND from the outside. The logic circuit 230 may receive or output a logic signal based on the virtual power supply voltage VVDD. The logic circuit 230 may include various units for implementing a logic circuit. For example, the logic circuit 230 may include various logic devices, such as an AND gate, an OR gate, a NOR gate, an XOR gate, an inverter, etc., or various memory elements, such as a latch, a flip-flop, etc., or may be one of them.

[0037] Figure 3 is a diagram illustrating an example of a method of operating a three-dimensional integrated circuit according to some embodiments. Figure 3In the embodiment, the three-dimensional integrated circuit 300 may include a first semiconductor die 310 and a second semiconductor die 320. The first semiconductor die 310 may include a switch unit 311. The switch unit 311 may receive a power supply voltage RVDD from outside the first semiconductor die 310 and may output a virtual power supply voltage VVDD. The second semiconductor die 320 may not include a switch unit.

[0038] In some embodiments, the switch unit 311 may provide a virtual power supply voltage VVDD to the logic circuit 313 and the first interface module (circuit) 315, and may provide a virtual power supply voltage VVDD to the second interface module (circuit) 321 within the second semiconductor die 320. The switch unit 311 may provide the virtual power supply voltage VVDD to the second interface module 321 through a substrate through-hole, a microbump, a solder bump, a hybrid copper bond (HCB), etc. that electrically connects the first semiconductor die 310 and the second semiconductor die 320. The logic circuit 313, the first interface module 315, and the second interface module 321 may operate in an active mode based on the virtual power supply voltage VVDD. The logic circuit 313, the first interface module 315, and the second interface module 321 may operate in an active mode based on the virtual power supply voltage VVDD at the same time. The logic circuit 313, the first interface module 315, and the second interface module 321 may receive or output a logic signal in the active mode.

[0039] In some embodiments, the first interface module 315 and the second interface module 321 included in each of the first semiconductor die 310 and the second semiconductor die 320 may be circuits configured to send and receive logic signals between the first semiconductor die 310 and the second semiconductor die 320. The first interface module 315 and the second interface module 321 may include various logic devices, such as an AND gate, an OR gate, a NOR gate, an XOR gate, an inverter, etc., or various memory elements, such as latches, triggers, etc. The first interface module 315 and the second interface module 321 may receive a virtual power supply voltage VVDD from the switch unit 311 and may enter an active mode. The first interface module 315 and the second interface module 321 may send and receive logic signals in the active mode through a substrate through-via, a microbump, a solder bump, a hybrid copper bond (HCB), etc. that electrically connects the first semiconductor die 310 and the second semiconductor die 320.

[0040] Figure 4 is a schematic diagram showing a method according to some embodiments Figure 3 FIG. 1 is a diagram of an example of a layout of a first semiconductor die. Specifically, the first semiconductor die is a semiconductor die including a switch unit.

[0041] exist Figure 4In the embodiment, the first semiconductor die 400 may include a switch cell SW_CELL. The first semiconductor die 400 may further include a standard cell SC disposed between the switch cells SW_CELL. Here, the standard cell SC may include a logic device, a memory element, a filler cell, and the like.

[0042] In some embodiments, the switch cells SW_CELL adjacent in the row R direction may be arranged in different rows. For example, the row direction may represent the X direction. The interval between the switch cells SW_CELL adjacent in the row direction may be preset. The interval between the switch cells SW_CELL adjacent in the row direction may be preset to stably provide the virtual power supply voltage VVDD to the standard cell SC. The switch cells SW_CELL may be arranged to cross in the column direction. For example, the column direction may represent the Y direction. However, the arrangement of the switch cells SW_CELL is not limited to Figure 4 , and may be arranged in various ways in an appropriate structure to provide a virtual power supply voltage VVDD to the standard cell SC.

[0043] In some embodiments, the first semiconductor die 400 may include a plurality of metal lines ML extending in a row direction (e.g., an X direction). The plurality of metal lines ML may cross each other to provide a virtual power supply voltage VVDD and a ground voltage GND. In some embodiments, the switch unit SW_CELL may be disposed to overlap with the metal line ML. The standard cell SC may also be disposed to overlap with the metal line ML. Here, the switch unit SW_CELL and the standard cell SC are shown to be disposed in each row R, but are not limited thereto, and the switch unit SW_CELL and the standard cell SC may be formed to span across a plurality of rows R. The switch unit SW_CELL may provide the virtual power supply voltage VVDD to the standard cell SC through the metal line ML. This will be referred to later. Figure 5 This is described in detail.

[0044] Figure 5 FIG. 4 is a diagram three-dimensionally illustrating an example of a metal line connected to a switching unit according to some embodiments. Figure 5 In the embodiment, a first via hole V1 and a second via hole V2 may be formed on the switch unit 510. The first via hole V1 may be electrically connected to the first metal line ML1. The second via hole V2 may be electrically connected to the second metal line ML. The directions in which the first metal line ML1 and the second metal line ML extend may be the same as or different from each other. Figure 5 The structure is only for better understanding and convenience of description, and the number, position, extension direction, etc. of metal lines and vias are not limited to Figure 5 The structure shown.

[0045] In some embodiments, the switch unit 510 may receive the power supply voltage RVDD from the outside through the first metal line ML1 and the first via V1. The switch unit 510 may provide the virtual power supply voltage VVDD to the surrounding through the second via V2 and the second metal line ML. Here, the second metal line ML may represent Figure 4 The metal wire ML.

[0046] In some embodiments, the switch unit 510 may provide a virtual power supply voltage VVDD to the standard cell SC through the second metal line ML. The standard cell SC may be disposed to overlap with the second metal line ML, and accordingly, the virtual power supply voltage VVDD from the switch unit 510 may be provided through the second metal line ML. The standard cell SC may enter an active mode based on the virtual power supply voltage VVDD received through the metal line ML. The virtual power supply voltage VVDD may be provided to the standard cell SC through a via connected to the second metal line ML and the standard cell SC, etc.

[0047] Figure 6 is a schematic diagram showing a method according to some embodiments Figure 3 FIG. 1 is a diagram of an example of a layout of a second semiconductor die. Specifically, the second semiconductor die is a semiconductor die that does not include a switch unit.

[0048] exist Figure 6 In, with Figure 4 Similar to the first semiconductor die 400, the second semiconductor die 600 may include a plurality of metal lines ML extending along a row direction (e.g., an X direction). The second semiconductor die 600 may include a plurality of standard cells SC. Here, the standard cells may include logic devices, memory elements, filling cells, etc. In some embodiments, the standard cells SC may be arranged to overlap with the metal lines ML. In addition, the standard cells SC may be formed to span across a plurality of rows R.

[0049] A plurality of metal lines ML may cross each other to provide a virtual power supply voltage VVDD and a ground voltage GND. The standard cell SC may receive the virtual power supply voltage VVDD and the ground voltage GND through the metal line ML. The standard cell SC may enter an active mode based on the virtual power supply voltage VVDD received through the metal line ML. Since the second semiconductor die 600 does not include a switching unit, the metal line ML may receive the virtual power supply voltage VVDD from the outside. The metal line ML of the second semiconductor die 600 may receive the virtual power supply voltage VVDD from the outside through a substrate through-hole, a bump, a mixed copper bond, etc.

[0050] Figure 7is a diagram showing an example of a connection between a first semiconductor die and a second semiconductor die in three dimensions according to some embodiments. Specifically, a virtual power supply voltage is passed from the first semiconductor die to the second semiconductor die. Here, an example of providing a virtual power supply voltage through a substrate through-via will be described. However, in similar structures and methods, the virtual power supply voltage can be provided from the first semiconductor die to the second semiconductor die through a bump, a hybrid copper bond, etc.

[0051] exist Figure 7 In the three-dimensional integrated circuit 700 , the second semiconductor die 730 may receive a virtual power supply voltage (VVDD) from the first semiconductor die 710 . The first semiconductor die 710 may provide the virtual power supply voltage to the second semiconductor die 730 through a through silicon via 721 penetrating a substrate 720 .

[0052] In some embodiments, the first semiconductor die 710 may include a switch unit. The switch unit of the first semiconductor die 710 may be arranged to overlap with the metal line 711 on the first semiconductor die 710. The switch unit of the first semiconductor die 710 may provide a virtual power supply voltage to the standard cell on the first semiconductor die 710 through the metal line 711. The structure in which the switch unit and the standard cell are arranged in the first semiconductor die 710 may be the same as that in the reference Figure 4 and Figure 5 The structures described are the same or similar.

[0053] In some embodiments, the second semiconductor die 730 may include a plurality of standard cells. The first semiconductor die 710 may provide a virtual power supply voltage to the plurality of standard cells on the second semiconductor die 730 through a through silicon via 721. The through silicon via 721 may be electrically connected to a metal line 711 on the first semiconductor die 710 and a metal line 731 on the second semiconductor die 730. The first semiconductor die 710 may provide a virtual power supply voltage to the metal line 731 on the second semiconductor die 730 through the through silicon via 721. The plurality of standard cells on the second semiconductor die 730 may be arranged to overlap with the metal line 731 on the second semiconductor die 730. The virtual power supply voltage may be provided to the plurality of standard cells on the second semiconductor die 730 through vias or metal lines connected to the second semiconductor die 730. The structure of the standard cells arranged in the second semiconductor die 730 may be the same as that of the reference numeral 711. Figure 6 The structures described are the same or similar.

[0054] Meanwhile, the region provided with the virtual power supply voltage from the first semiconductor die 710 may be the entire region of the second semiconductor die 730 or may be a partial region thereof.

[0055] In addition, although the three-dimensional integrated circuit 700 includes two semiconductor dies, it is not limited thereto, and the three-dimensional integrated circuit 700 may further include at least one semiconductor die above and / or below the first semiconductor die 710 and the second semiconductor die 730 .

[0056] The three-dimensional integrated circuit can realize power gating by using the switch unit, thereby reducing power consumption. In addition, since only some (at least one) semiconductor dies among the multiple semiconductor dies of the three-dimensional integrated circuit are designed to include the switch unit, the area of ​​the integrated circuit can be effectively utilized.

[0057] Figure 8 800 is a schematic cross-sectional view of an example of a three-dimensional integrated circuit according to some embodiments. Specifically, the second semiconductor die DIE2 includes a switch unit SW_CELL, and in the three-dimensional integrated circuit 800, the front surface 810f of the first semiconductor die DIE1 and the rear surface 830b of the second semiconductor die DIE2 are arranged to contact each other. The first semiconductor die DIE1 can be a top die, and the second semiconductor die DIE2 can be a bottom die. Here, although only a portion of the three-dimensional integrated circuit 800 is shown, each die can include more configurations. In addition, the three-dimensional integrated circuit 800 may include additional dies above and / or below the first semiconductor die DIE1 and the second semiconductor die DIE2.

[0058] In some embodiments, the first semiconductor die DIE1 may include a first back-end-of-line (BEOL) layer 810a and a first substrate layer 810b. For example, the first substrate layer 810b may be a semiconductor substrate material such as silicon, or may include a semiconductor substrate material. The first semiconductor device 811 may be disposed above the first substrate layer 810b and / or within the first substrate layer 810b. For example, the first semiconductor device 811 may be an active element, such as a metal oxide semiconductor field effect transistor (MOSFET), etc. Hereinafter, the first semiconductor device 811 included in the first substrate layer may be referred to as a first interface module (circuit), which is configured to send and receive logic signals between different dies.

[0059] In some embodiments, the first semiconductor die DIE1 may include a first BEOL layer 810a disposed adjacent to the first substrate layer 810b. The first BEOL layer 810a may include a first plurality of metal layers 813. The first plurality of metal layers may include a plurality of metal lines and a plurality of metal vias connecting the metal lines. In some embodiments, the first plurality of metal layers 813 may include a plurality of metal lines and a plurality of metal vias connecting the metal lines. Figure 6 and Figure 7 The first interface module 811 may receive a power supply voltage through the first plurality of metal layers 813 , or transmit and receive a logic signal.

[0060] In some embodiments, the second semiconductor die DIE2 may include a second BEOL layer 820a and a second substrate layer 820b. For example, the second substrate layer 820b may be a semiconductor substrate material, such as silicon, or may include a semiconductor substrate material. The second semiconductor device 821 and the switch unit 822 may be disposed above the second substrate layer 820b and / or within the second substrate layer 820b. Hereinafter, the second semiconductor device 821 included in the second substrate layer 820b may be referred to as a second interface module (circuit), which is configured to send and receive logic signals between different dies.

[0061] In some embodiments, the second semiconductor die DIE2 may include a second BEOL layer 820a disposed adjacent to the second substrate layer 820b. The second BEOL layer 820a may include a second plurality of metal layers 823. The second plurality of metal layers 823 may include a plurality of metal lines and vias. In some embodiments, the second plurality of metal layers 823 may include a plurality of metal lines and vias. Figure 4 and Figure 5 The switch unit 822 may receive the power supply voltage through the second plurality of metal layers 823 and output the virtual power supply voltage VVDD. The second interface module 821 may receive the virtual power supply voltage VVDD through the second plurality of metal layers 823 and may output or receive a logic signal.

[0062] In some embodiments, the second substrate layer 820b may include through silicon vias 825a and 825b extending through the second substrate layer 820b. The through silicon vias 825a and 825b may extend from a surface of the second substrate layer 820b in contact with the second BEOL layer 820a to an opposite surface (e.g., a rear surface 830b of the second substrate). The through silicon vias 825a and 825b may provide electrical connections between the second plurality of metal layers 823 and redistribution layers (RDLs) 833a and 833b through conductive materials within the through silicon vias 825a and 825b.

[0063] In some embodiments, redistribution layers 833a and 833b for forming electrical connections with adjacent dies may be located on the rear surface 830b of the second substrate layer 820b. The redistribution layers 833a and 833b may include a plurality of metallization patterns between adjacent dies. The redistribution layers 833a and 833b may form electrical connections with the second plurality of metal layers 823 through conductive materials within through silicon vias 825a and 825b.

[0064] In some embodiments, the upper metal lines of the first plurality of metal layers 813 may be connected to interconnect structures 831a and 831b. Here, the interconnect structures 831a and 831b may include bumps (e.g., microbumps or solder bumps), mixed copper bonding, etc. The interconnect structures 831a and 831b may be formed of conductive materials such as copper, aluminum, etc. The first plurality of metal layers 813 may send power supply voltages and logic signals to the outside and receive power supply voltages and logic signals from the outside through the interconnect structures 831a and 831b. The first semiconductor die DIE1 and the second semiconductor die DIE2 may send and receive power supply voltages and logic signals through the interconnect structures 831a and 831b, the redistribution layers 833a and 833b, the through silicon vias 825a and 825b, etc. However, in some embodiments, some of these configurations may be omitted or other necessary configurations may be added as needed.

[0065] In some embodiments, the switch unit 822 may receive a power supply voltage RVDD from the outside through a first path 831. The switch unit 822 may output a virtual power supply voltage VVDD based on a control signal. The switch unit 822 may provide the virtual power supply voltage VVDD to the second interface module 821 through a second path 833, and may provide the virtual power supply voltage VVDD to the first interface module 811 through a third path 835. The switch unit 822 may provide the virtual power supply voltage VVDD to the second interface module 821 through a second plurality of metal layers 823. For example, the switch unit 822 may provide the virtual power supply voltage VVDD to the second interface module 821 through a metal layer in a routing path leading to the second interface module 821 among the second plurality of metal layers 823. The switch unit 822 may provide the virtual power supply voltage VVDD to the first interface module 811 through a through silicon via 825a, a redistribution layer 833a, an interconnect structure 831a, and the like. For example, the switch unit 822 can provide a virtual power supply voltage VVDD to the first interface module 811 through a metal layer in the second plurality of metal layers 823 located in a routing path from the switch unit 822 to the through silicon via 825a, the through silicon via 825a, the redistribution layer 833a, the interconnection structure 831a, and a metal layer in the first plurality of metal layers 813 located in a routing path from the interconnection structure 831a to the first interface module 811.

[0066] In some embodiments, the first interface module 811 and the second interface module 821 may operate in an active mode based on a virtual power supply voltage VVDD. The first interface module 811 and the second interface module 821 may operate together in an active mode based on a virtual power supply voltage VVDD. When the second interface module 821 enters the active mode, the second interface module 821 may receive a first input logic signal from an external or other logic device through a fourth path 841. The second interface module 821 may output a first output logic signal as a response to the first input logic signal. The second interface module 821 may output a first output logic signal through a fifth path 843. For example, the first output logic signal may be provided to the first interface module 811 as a second input logic signal through silicon vias 825b, a redistribution layer 833b, an interconnect structure 831b, etc. The first output logic signal can be provided to the first interface module 811 as a second input logic signal through a metal layer in the second plurality of metal layers 823 located in a routing path from the second interface module 821 to the through silicon via 825b, the through silicon via 825b, the redistribution layer 833b, the interconnection structure 831b, and a metal layer in the first plurality of metal layers 813 located in a routing path from the interconnection structure 831a to the first interface module 811.

[0067] However, although it is described that the first interface module 811 receives the logic signal output by the second interface module 821, the scope of the present disclosure is not limited thereto. For example, the second interface module 821 may receive the logic signal output by the first interface module 811 based on the virtual power supply voltage VVDD. At this time, the path along which the logic signal moves may be similar to the path of the above-mentioned logic signal.

[0068] Fig. 9 is a schematic cross-sectional view of an example of a three-dimensional integrated circuit according to some embodiments. Specifically, the second semiconductor die DIE2 includes a switch unit SW_CELL, and in the three-dimensional integrated circuit 900, the front surface 910f of the first semiconductor die DIE1 and the front surface 930f of the second semiconductor die DIE2 are arranged in contact with each other. The first semiconductor die DIE1 may be a top die, and the second semiconductor die DIE2 may be a bottom die. Here, although only a portion of the three-dimensional integrated circuit 900 is shown, each die may include more configurations. In addition, the three-dimensional integrated circuit 900 may include additional dies located above and / or below the first semiconductor die DIE1 and the second semiconductor die DIE2. In addition, the three-dimensional integrated circuit 900 is not included here. Figure 8 Duplicate description.

[0069] The first plurality of metal layers 913 of the first semiconductor die DIE1 and the second plurality of metal layers 923 of the second semiconductor die DIE2 may be connected to the interconnect structures 931a and 931b. The first semiconductor die DIE1 and the second semiconductor die DIE2 may send and receive power supply voltages and logic signals through the interconnect structures 931a and 931b.

[0070] In some embodiments, the first substrate layer 910 b of the first semiconductor die DIE1 may include a first interface module (circuit) 911 . The second substrate layer 920 b of the second semiconductor die DIE2 may include a switch unit 922 and a second interface module (circuit) 921 .

[0071] In some embodiments, the switch unit 922 may receive the power supply voltage RVDD from the outside through the through silicon via 925. The switch unit 922 may receive the power supply voltage RVDD from the outside through the first path 931.

[0072] In some embodiments, the switch unit 922 may output a virtual power supply voltage VVDD based on a control signal. The switch unit 922 may provide the virtual power supply voltage VVDD to the second interface module 921 through the second path 933, and may provide the virtual power supply voltage VVDD to the first interface module 911 through the third path 935. The switch unit 922 may provide the virtual power supply voltage VVDD to the second interface module 921 through the second plurality of metal layers 923. The switch unit 922 may provide the virtual power supply voltage VVDD to the second interface module 921 through a metal layer in the second plurality of metal layers 923 that is located within a routing path from the switch unit 922 to the second interface module 921. The switch unit 922 may provide the virtual power supply voltage VVDD to the first interface module 911 through the second plurality of metal layers 923, the interconnect structure 931a, the first plurality of metal layers 913, and the like. For example, the switch unit 922 can provide a virtual power supply voltage VVDD to the first interface module 911 through a metal layer in the second plurality of metal layers 923 located in a routing path from the switch unit 922 to the interconnect structure 931a, the interconnect structure 931a, and a metal layer in the first plurality of metal layers 913 located in a routing path from the interconnect structure 931a to the first interface module 911.

[0073] In some embodiments, the first interface module 911 and the second interface module 921 may operate in an active mode based on a virtual power supply voltage VVDD. The first interface module 911 and the second interface module 921 may operate together in an active mode based on a virtual power supply voltage VVDD. When the second interface module 921 enters the active mode, the second interface module 921 may receive a first input logic signal from an external or other logic device, and may output a first output logic signal as a response to the first input logic signal. The second interface module 921 may output a first output logic signal through a fourth path 941. The first output logic signal may be provided to the first interface module 911 as a second input signal through a second plurality of metal layers 923, an interconnection structure 931b, a first plurality of metal layers 913, and the like. For example, the first output logic signal may be provided to the first interface module 911 as a second input logic signal through a metal layer in the second plurality of metal layers 923 located in a routing path from the second interface module 921 to the interconnection structure 931b, the interconnection structure 931b, and a metal layer in the first plurality of metal layers 913 located in a routing path from the interconnection structure 931b to the first interface module 911. The first interface module 911 may receive a second input logic signal through a fourth path 941 in an active mode.

[0074] However, although it is described here that the first interface module 911 receives the logic signal output by the second interface module 921, the scope of the present disclosure is not limited thereto. For example, the second interface module 921 may receive the logic signal output by the first interface module 911 based on the virtual power supply voltage VVDD. At this time, the path along which the logic signal moves may be similar to the path of the above-mentioned logic signal.

[0075] Fig.10 is a schematic cross-sectional view of an example of a three-dimensional integrated circuit according to some embodiments. Specifically, the first semiconductor die DIE1 includes a switch unit SW_CELL, and in the three-dimensional integrated circuit 1000, the front surface 1010f of the first semiconductor die DIE1 and the rear surface 1030b of the second semiconductor die DIE2 are arranged in contact with each other. The first semiconductor die DIE1 may be a top die, and the second semiconductor die DIE2 may be a bottom die. Here, although only a portion of the three-dimensional integrated circuit 1000 is shown, each die may include more configurations. In addition, the three-dimensional integrated circuit 1000 may include additional dies located above and / or below the first semiconductor die DIE1 and the second semiconductor die DIE2. For the sake of brevity, the components related to the three-dimensional integrated circuit 1000 may not be included here. Figure 8 and Fig. 9 Duplicate description.

[0076] The first plurality of metal layers 1013 of the first semiconductor die DIE1 and the second plurality of metal layers 1023 of the second semiconductor die DIE2 may be connected to interconnect structures 1033a, 1033b, and 1033c. The first semiconductor die DIE1 and the second semiconductor die DIE2 may send and receive power supply voltages and logic signals through the interconnect structures 1033a, 1033b, and 1033c, redistribution structures, through silicon vias 1025a, 1025b, and 1025c, and the like.

[0077] In some embodiments, the first substrate layer 1010 b of the first semiconductor die DIE1 may include a switch unit 1012 and a first interface module 1011 . The second substrate layer 1020 b of the second semiconductor die DIE2 may include a second interface module 1021 .

[0078] In some embodiments, the switch unit 1012 may receive the power supply voltage RVDD from the outside of the first semiconductor die DIE1 through the second semiconductor die DIE2. For example, the switch unit 1012 may receive the power supply voltage RVDD from the outside through the second plurality of metal layers 1023, the through silicon via 1025a, the interconnect structure 1033a, the first plurality of metal layers 1013, etc. within the second BEOL layer 1020a. For example, the switch unit 1012 may receive the power supply voltage RVDD from the outside through a metal layer in the second plurality of metal layers 1023 located in a routing path from the outside to the through silicon via 1025a, the through silicon via 1025a, the interconnect structure 1033a, and a metal layer in the first plurality of metal layers 1013 located in a routing path from the interconnect structure 1033a to the switch unit 1012. The switch unit 1012 may receive the power supply voltage RVDD from the outside through the first path 1031.

[0079] In some embodiments, the switch unit 1012 may output a virtual power supply voltage VVDD based on a control signal. The switch unit 1012 may provide the virtual power supply voltage VVDD to the first interface module 1011 through the second path 1033, and may provide the virtual power supply voltage VVDD to the second interface module 1021 through the third path 1035. The switch unit 1012 may provide the virtual power supply voltage VVDD to the first interface module 1011 through the first plurality of metal layers 1013. For example, the switch unit 1012 may provide the virtual power supply voltage VVDD to the first interface module 1011 through a metal layer in the first plurality of metal layers 1013 that is located within a routing path from the switch unit 1012 to the first interface module 1011. The switch unit 1012 may provide the virtual power supply voltage VVDD to the second interface module 1021 through the first plurality of metal layers 1013, the interconnect structure 1033b, the through silicon via 1025b, etc. For example, the switch unit 1012 can provide a virtual power supply voltage VVDD to the second interface module 1021 through a metal layer in the first plurality of metal layers 1013 located in a routing path from the switch unit 1012 to the interconnect structure 1033b, the interconnect structure 1033b, the through silicon via 1025b, and a metal layer in the second plurality of metal layers 1023 located in a routing path from the through silicon via 1025b to the second interface module 1021.

[0080] In some embodiments, the first interface module 1011 and the second interface module 1021 may operate in an active mode based on a virtual power supply voltage VVDD. The first interface module 1011 and the second interface module 1021 may operate together in an active mode based on the virtual power supply voltage VVDD. When the second interface module 1021 enters the active mode, the second interface module 1021 may receive a first input logic signal from an external or other logic device, and may output a first output logic signal as a response to the first input logic signal. The second interface module 1021 may output a first output logic signal through a fourth path 1041. The first output logic signal may be provided to the first interface module 1011 as a second input signal through the second plurality of metal layers 1023, through silicon vias 1025c, interconnect structures 1033c, first plurality of metal layers 1013, etc. For example, the first output logic signal may be provided to the first interface module 1011 as the second input signal through a metal layer in the second plurality of metal layers 1023 located in a routing path from the second interface module 1021 to the through silicon via 1025c, the interconnect structure 1033c, and a metal layer in the first plurality of metal layers 1013 located in a routing path from the interconnect structure 1033c to the first interface module 1011. The first interface module 1011 may receive the second input logic signal through the fourth path 1041 in the active mode.

[0081] However, although it is described here that the first interface module 1011 receives the logic signal output by the second interface module 1021, the scope of the present disclosure is not limited thereto. For example, the second interface module 1021 may receive the logic signal output by the first interface module 1011 based on the virtual power supply voltage VVDD. At this time, the path along which the logic signal moves may be similar to the path of the above-mentioned logic signal.

[0082] Fig.11 is a schematic cross-sectional view of an example of a three-dimensional integrated circuit according to some embodiments. Specifically, the first semiconductor die DIE1 includes a switch unit SW_CELL, and in the three-dimensional integrated circuit 1100, the front surface 1110f of the first semiconductor die DIE1 and the front surface 1130f of the second semiconductor die DIE2 are arranged in contact with each other. The first semiconductor die DIE1 may be a top die, and the second semiconductor die DIE2 may be a bottom die. Here, although only a portion of the three-dimensional integrated circuit 1100 is shown, each die may include more configurations. In addition, the three-dimensional integrated circuit 1100 may include additional dies located above and / or below the first semiconductor die DIE1 and the second semiconductor die DIE2. In addition, the three-dimensional integrated circuit 1100 is not included here. Figures 8 to 10 Duplicate description.

[0083] The first plurality of metal layers 1113 of the first semiconductor die DIE1 and the second plurality of metal layers 1123 of the second semiconductor die DIE2 may be connected to interconnect structures 1133a, 1133b, and 1133c. The first semiconductor die DIE1 and the second semiconductor die DIE2 may transmit and receive power supply voltages and logic signals through the interconnect structures 1133a, 1133b, and 1133c.

[0084] In some embodiments, the first substrate layer 1110b of the first semiconductor die DIE1 may include a switch unit 1112 and a first interface module 1111. The second substrate layer 1120b of the second semiconductor die DIE2 may include a second interface module 1121.

[0085] In some embodiments, the switch unit 1112 may receive the power supply voltage RVDD from the outside of the first semiconductor die DIE1 through the second semiconductor die DIE2. For example, the switch unit 1112 may receive the power supply voltage RVDD from the outside through the second plurality of metal layers 1123 in the second BEOL layer 1120a, the interconnect structure 1133a, the first plurality of metal layers 1113 in the first BEOL layer 1110a, and the like. For example, the switch unit 1112 may receive the power supply voltage RVDD from the outside through the through silicon via 1125a, the metal layers in the second plurality of metal layers 1123 located in the routing path from the through silicon via 1125a to the interconnect structure 1133a, the interconnect structure 1133a, and the metal layers in the first plurality of metal layers 1113 located in the routing path from the interconnect structure 1133a to the switch unit 1112. The switch unit 1112 may receive the power supply voltage RVDD from the outside through the first path 1131.

[0086] In some embodiments, the switch unit 1112 may output a virtual power supply voltage VVDD based on a control signal. The switch unit 1112 may provide the virtual power supply voltage VVDD to the first interface module 1111 through the second path 1133, and may provide the virtual power supply voltage VVDD to the second interface module 1121 through the third path 1135. The switch unit 1112 may provide the virtual power supply voltage VVDD to the first interface module 1111 through the first plurality of metal layers 1113. For example, the switch unit 1112 may provide the virtual power supply voltage VVDD to the first interface module 1111 through a metal layer in the first plurality of metal layers 1113 that is located within a routing path from the switch unit 1112 to the first interface module 1111. The switch unit 1112 may provide the virtual power supply voltage VVDD to the second interface module 1121 through the first plurality of metal layers 1113, the interconnect structure 1133b, the second plurality of metal layers 1123, and the like. For example, the switch unit 1112 can provide a virtual power supply voltage VVDD to the second interface module 1121 through a metal layer in the first plurality of metal layers 1113 located in a routing path from the switch unit 1112 to the interconnect structure 1133b, the interconnect structure 1133b, and a metal layer in the second plurality of metal layers 1123 located in a routing path from the interconnect structure 1133b to the second interface module 1121.

[0087] In some embodiments, the first interface module 1111 and the second interface module 1121 may operate in an active mode based on a virtual power supply voltage VVDD. The first interface module 1111 and the second interface module 1121 may operate together in an active mode based on the virtual power supply voltage VVDD. When the second interface module 1121 enters the active mode, the second interface module 1121 may receive a first input logic signal from an external or other logic device, and may output a first output logic signal as a response to the first input logic signal. The second interface module 1121 may output a first output logic signal through a fourth path 1141. The first output logic signal may be provided to the first interface module 1111 as a second input logic signal through the second plurality of metal layers 1123, the interconnect structure 1133c, the first plurality of metal layers 1113, etc. For example, the first output logic signal may be provided to the first interface module 1111 as a second input logic signal through a metal layer in the second plurality of metal layers 1123 located in a routing path from the second interface module 1121 to the interconnect structure 1133c, the interconnect structure 1133c, and a metal layer in the first plurality of metal layers 1013 located in a routing path from the interconnect structure 1133c to the first interface module 1111. The first interface module 1111 may receive the second input logic signal through the fourth path 1141 in an active mode.

[0088] However, although it is described here that the first interface module 1111 receives the logic signal output by the second interface module 1121, the scope of the present disclosure is not limited thereto. For example, the second interface module 1121 may receive the logic signal output by the first interface module 1111 based on the virtual power supply voltage VVDD. At this time, the path along which the logic signal moves may be similar to the path of the above-mentioned logic signal.

[0089] In some embodiments, it is described that the first semiconductor die DIE1 and the second semiconductor die DIE2 have the same size as an example. However, when the area of ​​the first semiconductor die DIE1 including the switch unit is larger than the area of ​​the second semiconductor die DIE2, the first semiconductor die DIE1 can directly receive the power supply voltage RVDD from the outside without passing through the second semiconductor die DIE2. For example, the first semiconductor die DIE1 can directly receive the power supply voltage RVDD from the outside through a copper post (Cu post) or the like, but is not limited thereto.

[0090] In addition, the three-dimensional integrated circuit may include a plurality of semiconductor dies, wherein the rear surface of the first semiconductor die DIE1 and the rear surface of the second semiconductor die DIE2 are disposed in contact with each other. In some embodiments, at least one of the plurality of semiconductor dies may include a switch unit, and the power supply voltage and logic signal transmission and reception method between the plurality of semiconductor dies may be the same as that of the reference Figures 8 to 11 The methods described are the same or similar.

[0091] exist Figures 8 to 11 In the three-dimensional integrated circuit, the semiconductor dies in the three-dimensional integrated circuit can be arranged in contact with each other in various structures, and the power supply voltage and logic signal can be sent and received through different structures according to the structures arranged in contact with each other. In the three-dimensional integrated circuit, considering the area of ​​the semiconductor die, the number of logic devices in the semiconductor die, wiring, etc., the switch unit is only arranged in some of the multiple semiconductor dies, thereby effectively utilizing the area of ​​the multiple semiconductor dies.

[0092] Fig.12 is a diagram for schematically illustrating an example of an operating method of a three-dimensional integrated circuit according to some embodiments. Specifically, the levels of power supply voltages for operating logic devices within semiconductor dies included in the three-dimensional integrated circuit are different.

[0093] In some embodiments, the three-dimensional integrated circuit 1200 may include a first semiconductor die 1210 and a second semiconductor die 1220. The first semiconductor die 1210 may include a switch unit 1211. The switch unit 1211 may receive a power supply voltage RVDD from outside the first semiconductor die 1210, and may provide a virtual power supply voltage VVDD to the logic circuit 1213 and the first interface module 1215, and may also provide the virtual power supply voltage VVDD to the second interface module 1221 within the second semiconductor die 1220. The logic circuit 1213, the first interface module 1215, and the second interface module 1221 may simultaneously operate in an active mode based on the virtual power supply voltage VVDD. The logic circuit 1213, the first interface module 1215, and the second interface module 1221 may receive or output a logic signal in the active mode.

[0094] In some embodiments, the level of the virtual power supply voltage used by the second interface module 1221 in the active mode may be different from the level of the virtual power supply voltage used by the first interface module 1215 in the active mode. Therefore, the second interface module 1221 needs to be supplied with a virtual power supply voltage of a level different from the level of the virtual power supply voltage VVDD.

[0095] In some embodiments, the first semiconductor die 1210 may include a voltage level shifter 1212. The voltage level shifter 1212 may receive a virtual power supply voltage VVDD and may output a virtual power supply voltage D_VVDD having a converted level. The first semiconductor die 1210 may provide the virtual power supply voltage D_VVDD having a converted level to the second semiconductor die 1220. The first semiconductor die 1210 may provide the virtual power supply voltage D_VVDD having a converted level to the second semiconductor die 1220 through a substrate through-via, a microbump, a solder bump, a hybrid copper bond, etc. The second interface module 1221 may enter an active mode based on the virtual power supply voltage D_VVDD having a converted level and receive a logic signal from the first semiconductor die 1210 in the active mode.

[0096] The structures of the first semiconductor die 1210 and the second semiconductor die 1220 and the method of transmitting and receiving the power supply voltage and the logic signal by the first semiconductor die 1210 and the second semiconductor die 1220 may be the same as those of reference 1. Figures 8 to 11 The structures and methods described are the same or similar.

[0097] Fig.13 1 is a diagram schematically illustrating an example of an operating method of a three-dimensional integrated circuit according to some embodiments. Specifically, the levels of power supply voltages for operating logic devices within semiconductor dies included in the three-dimensional integrated circuit are different, and the three-dimensional integrated circuit includes three or more semiconductor dies.

[0098] In some embodiments, the three-dimensional integrated circuit 1300 may include a first semiconductor die 1310, a second semiconductor die 1320, and a third semiconductor die 1330. The first semiconductor die 1310 may include a switch unit 1311. The switch unit 1311 may receive a power supply voltage RVDD from outside the first semiconductor die 1310, and may provide a virtual power supply voltage VVDD to the logic circuit 1313 and the first interface module (circuit) 1315, and may also provide the virtual power supply voltage VVDD to the second interface module (circuit) 1321 and the third semiconductor die 1330 within the second semiconductor die 1320. The logic circuit 1313, the first interface module 1315, and the second interface module 1321 may operate in an active mode at the same time based on the virtual power supply voltage VVDD. The logic circuit 1313, the first interface module 1315, and the second interface module 1321 may receive or output a logic signal in the active mode.

[0099] In some embodiments, the third semiconductor die 1330 may include a voltage level shifter 1331 and a third interface module (circuit) 1335. The level of the power supply voltage used by the third interface module 1335 in the active mode may be different from the level of the power supply voltage used by the first interface module 1315 and the second interface module 1321 in the active mode. Therefore, the third interface module 1335 needs to be supplied with a virtual power supply voltage of a level different from the level of the virtual power supply voltage VVDD. The third semiconductor die 1330 may include a voltage level shifter 1331 to provide the third interface module 1335 with a virtual power supply voltage D_VVDD having a converted level. The voltage level shifter 1331 may receive the virtual power supply voltage VVDD from the second semiconductor die 1320, and may output the virtual power supply voltage D_VVDD having a converted level. The third interface module 1335 may operate in the active mode simultaneously with the logic circuit 1313, the first interface module 1315, and the second interface module 1321 based on the virtual power supply voltage D_VVDD having a converted level. The third interface module 1335 may enter an active mode based on the virtual power supply voltage D_VVDD having the converted level, and receive a logic signal from the second semiconductor die 1320 in the active mode.

[0100] Fig.14 is a diagram showing an example of a three-dimensional integrated circuit according to some embodiments. Specifically, some semiconductor dies in the three-dimensional integrated circuit include a switching unit, and a structure required to transmit and receive a power supply voltage and a logic signal is modularized.

[0101] In some embodiments, the three-dimensional integrated circuit 1400 may include a first semiconductor die 1410 and a second semiconductor die 1420, and only the first semiconductor die 1410 may include a switch unit 1433. In order to provide a virtual power supply voltage VVDD generated by the switch unit 1433, the virtual power supply voltage VVDD may be provided to a second interface module (circuit) 1421 of the second semiconductor die 1420 through a first through silicon via 1432. When power supply voltage levels for operating a logic device of the first semiconductor die 1410 and a logic device of the second semiconductor die 1420 are different, a voltage level shifter 1431 may be necessary. The first semiconductor die 1410 and the second semiconductor die 1420 may transmit and receive the virtual power supply voltage VVDD through a first interconnect structure 1441a.

[0102] In some embodiments, the first interface module (circuit) 1435 of the first semiconductor die 1410 may output a logic signal based on the virtual power supply voltage VVDD. The logic signal may be provided to the second interface module 1421 through the second through silicon via 1434. The first semiconductor die 1410 and the second semiconductor die 1420 may send and receive logic signals through the second interconnect structure 1441b.

[0103] In some embodiments, the structure required for the first semiconductor die 1410 to transmit the virtual power supply voltage VVDD and the logic signal to the second semiconductor die 1420 can be implemented as one macro circuit 1430. For example, the macro circuit 1430 may include a voltage level shifter 1431, a switch unit 1433, a first interface module 1435, a first through silicon via 1432 for transmitting and receiving the virtual power supply voltage VVDD, and a second through silicon via 1434 for transmitting and receiving the logic signal. The first semiconductor die 1410 may include a plurality of macro circuits 1430, and by arranging the plurality of macro circuits 1430 at appropriate intervals, the virtual power supply voltage VVDD and the logic signal can be effectively transmitted to the second semiconductor die 1420. However, the configuration of the macro circuit 1430 is not limited thereto, and some configurations may be omitted or other configurations may be added.

[0104] Fig.15 is a diagram showing an example of a semiconductor device according to some embodiments. Fig.15 , the semiconductor device 1500 may be a memory module (circuit) including a system on chip (SOC) 1550 and at least one stacked semiconductor chip 1530 mounted on a package substrate 1510 (eg, a printed circuit board).

[0105] In some embodiments, an insertion layer 1520 may be further provided on the package substrate 1510. The stacked semiconductor chip 1530 may be formed as a chip on chip (CoC). The stacked semiconductor chip 1530 may include at least one memory chip 1540 stacked on a buffer chip 1560 (e.g., a logic chip). The buffer chip 1560 and the at least one memory chip 1540 may be interconnected by through silicon vias (TSVs). In some embodiments, the buffer chip 1560 and the at least one memory chip 1540 may include a reference Figures 1 to 14 Therefore, the semiconductor device 1500 may be designed such that at least one memory chip 1540 as part of the stacked semiconductor chip 1530 may include a switch unit, so that the area of ​​the semiconductor device 1500 may be effectively utilized. In some embodiments, the stacked semiconductor chip 1530 may be a high bandwidth memory HBM of, for example, 500 GB / sec to 1 TB / sec or more.

[0106] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of possible protection. In a single embodiment, specific features described in the present disclosure in the context of separate embodiments may also be implemented in combination. Conversely, the individual features described in the context of a single embodiment may also be implemented separately in multiple embodiments, or in appropriate sub-combinations. In addition, although features may be described above as working in a particular combination, one or more features from a combination may be deleted from the combination in some cases, and a combination may be directed to a sub-combination or a variant of a sub-combination.

Claims

1. An integrated circuit, comprising: a first switch unit on a first substrate within a first die among the plurality of dies, the first switch unit being configured to output a virtual power supply voltage based on a power supply voltage received from outside the first die; a first interface circuit on the first substrate, the first interface circuit being configured to enter an active mode based on the virtual power supply voltage; as well as A second interface circuit is on a second substrate within a second die bonded to the first die among the plurality of dies, the second interface circuit being configured to enter the active mode together with the first interface circuit based on the virtual power supply voltage.

2. The integrated circuit according to claim 1, in, The first switch unit is configured to provide the virtual power supply voltage to the first interface circuit through a first path, and The first switch unit is configured to provide the virtual power supply voltage to the second interface circuit through a second path different from the first path.

3. The integrated circuit according to claim 2, wherein: The back surface of the first die is bonded to the front surface of the second die.

4. The integrated circuit according to claim 3, in, In the active mode, the first interface circuit and the second interface circuit are configured to send and receive logic signals through a third path different from the first path and the second path, The first die includes a first through silicon via and a second through silicon via penetrating the first substrate. wherein the second path includes the first through silicon via, and Wherein, the third path includes the second through silicon via.

5. The integrated circuit according to claim 4, in, The first path includes a first metal layer within a routing path from the first switch unit to the first interface circuit, the first metal layer being among a first plurality of metal layers formed on the first substrate, The second path includes: a second metal layer in a routing path from the first switch unit to the first through silicon via, the second metal layer being among the first plurality of metal layers; and a third metal layer in a routing path from the first through silicon via to the second interface circuit, the third metal layer being among the second plurality of metal layers formed on the second substrate, and Wherein, the third path includes: a fourth metal layer within the routing path from the first interface circuit to the second through silicon via, the fourth metal layer being among the first plurality of metal layers; and a fifth metal layer within the routing path from the second through silicon via to the second interface circuit, the fifth metal layer being among the second plurality of metal layers.

6. The integrated circuit according to claim 2, wherein: The front surface of the first die is bonded to the front surface of the second die.

7. The integrated circuit according to claim 6, in, In the active mode, the first interface circuit and the second interface circuit are configured to send and receive logic signals through a third path different from the first path and the second path, wherein the integrated circuit further comprises a first interconnect structure and a second interconnect structure attached between the front surface of the first die and the front surface of the second die, wherein the second path includes the first interconnect structure, and Wherein, the third path includes the second interconnect structure.

8. The integrated circuit according to claim 7, wherein: The first interconnect structure and the second interconnect structure include bump bonding or hybrid copper bonding.

9. The integrated circuit according to claim 7, in, The second substrate includes a first through silicon via, and The first switch unit is configured to receive the power supply voltage through the first through silicon via.

10. The integrated circuit of claim 2, wherein: The front surface of the first die is bonded to the back surface of the second die.

11. The integrated circuit according to claim 10, in, In the active mode, the first interface circuit and the second interface circuit are configured to send and receive logic signals through a third path different from the first path and the second path, wherein the second die includes a first through silicon via, a second through silicon via, and a third through silicon via extending into the second substrate, The first switch unit is configured to receive the power supply voltage through the first through silicon via. wherein the second path includes the second through silicon via, and Wherein, the third path includes the third through silicon via.

12. The integrated circuit of claim 1 , further comprising: A third interface circuit is located on a third substrate within a third die bonded to the second die, and the third interface circuit is configured to enter the active mode together with the first interface circuit and the second interface circuit based on the virtual power supply voltage received from the first switch unit through the second die.

13. An integrated circuit comprising: a first die among the plurality of dies, the first die comprising: a first plurality of metal lines extending in a first direction; a plurality of switch units arranged to overlap the first plurality of metal lines and configured to provide a virtual power supply voltage to the first plurality of metal lines based on a power supply voltage received from outside the first die; and a first interface circuit configured to enter an active mode based on the virtual power supply voltage; and A second die among the plurality of die, the second die comprising: a second plurality of metal lines extending along the first direction and configured to receive the virtual power supply voltage from the first die; and a second interface circuit arranged to overlap with the second plurality of metal lines and enter the active mode together with the first interface circuit based on the virtual power supply voltage received from the second plurality of metal lines.

14. The integrated circuit according to claim 13, in, At least one of the plurality of dies comprises the plurality of switch units, and The second die is excluded from the at least one die.

15. The integrated circuit according to claim 13, in, The first die further includes: a voltage level shifter configured to output a virtual power voltage of a second level different from the first level based on the virtual power voltage of the first level output by the plurality of switch units, and Wherein, the second plurality of metal lines are configured to receive the second level of virtual power voltage from the first die.

16. The integrated circuit of claim 13, further comprising: A first through silicon via is configured to transmit the virtual power supply voltage from the first die to the second die.

17. The integrated circuit according to claim 16, in, The first interface circuit and the second interface circuit are configured to send and receive logic signals in the active mode, and Wherein, the integrated circuit further includes: a second through silicon via configured to transmit the logic signal.

18. The integrated circuit of claim 13, further comprising a third die, the third die comprising: a third plurality of metal lines extending along the first direction and configured to receive the virtual supply voltage from the first die; and a third interface circuit disposed to overlap the third plurality of metal lines and enter the active mode together with the first interface circuit and the second interface circuit based on the virtual power supply voltage received from the third plurality of metal lines.

19. A semiconductor device comprising: A first die, comprising: a switch unit configured to output a first level of virtual power voltage based on a power voltage received from outside the first die; a first interface circuit configured to output a logic signal based on the first level of virtual power voltage received from the switch unit; a level shifter configured to output a second level of virtual power voltage different from the first level based on the first level of virtual power voltage received from the switch unit; a first through silicon via configured to transmit the second level of virtual power voltage to outside the first die; and a second through silicon via configured to transmit the logic signal to outside the first die; and The second die includes a second interface circuit, wherein the second interface circuit receives the logic signal through the second through silicon via based on the second level of virtual power supply voltage received from the first through silicon via.

20. The semiconductor device of claim 19, wherein the second die is bonded to the first die.

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