High-efficiency heat-dissipation high-power radio frequency chip multilayer stacking structure and preparation method thereof

Abstract

The invention discloses an efficient heat dissipation high-power radio frequency chip multilayer stacking structure and a preparation method thereof. The structure sequentially comprises a substrate layer structure, a first active device layer, a first metal interconnection layer, a heat dissipation buffer layer, a second active device layer, a second metal interconnection layer and a top heat dissipation structure from bottom to top, wherein the heat dissipation buffer layer is of a micro-channel structure filled with a phase change material, and active temperature regulation and control are achieved; the top-layer heat dissipation structure adopts a graphene-microneedle array composite design and has a switchable heat dissipation mode; according to the structure, the heat dissipation efficiency of the high-power radio frequency chip is remarkably improved, the reliability of the device is improved, the influence of the heat dissipation structure on the radio frequency performance is reduced, and the structure is suitable for high-frequency high-power application scenes such as 5G communication.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency integrated circuit heat dissipation technology, and in particular to a multi-layer stacking structure of a high-efficiency heat dissipation high-power radio frequency chip and a preparation method thereof. Background Art

[0002] The operating frequency and power density of RF integrated circuits continue to increase, and the problem of chip heating is becoming increasingly prominent; traditional single-layer RF chips have a single heat dissipation channel and large thermal resistance, which makes it difficult to meet the heat dissipation requirements of high-power devices; during the chip stacking process, it is difficult to match the thermal stress between the functional layers, which can easily lead to a decrease in device reliability; the existing heat dissipation structure has a large electromagnetic interference to high-frequency signals, affecting RF performance; there is a lack of an effective temperature control mechanism, and local overheating is prone to occur under high-power working conditions.

[0003] At present, although the industry has proposed a variety of improvement plans, such as using microchannel heat dissipation, phase change material filling and other technologies, these plans often only solve one aspect of the problem and lack a systematic solution.

[0004] Therefore, it is urgent to develop a new type of multi-layer stacking structure that can simultaneously solve multiple key problems such as heat dissipation efficiency, thermal stress matching, and electromagnetic compatibility. Summary of the invention

[0005] The purpose of the present invention is to solve the problems of low heat dissipation efficiency, poor thermal stress matching and large electromagnetic interference in the prior art. Based on the multi-physics field coupling theory, new composite materials and micro-nano structures are used, and a hierarchical heat dissipation strategy is adopted to achieve the purpose of efficient heat dissipation and reliable operation of high-power radio frequency chips.

[0006] In order to achieve the above-mentioned purpose of the present invention, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a multi-layer stacking structure of high-power radio frequency chips with high efficiency in heat dissipation, wherein the stacking structure comprises, from bottom to top, a base layer structure, a first active device layer, a first metal interconnection layer, a heat dissipation buffer layer, a second active device layer, a second metal interconnection layer, and a top heat dissipation structure.

[0008] The base layer structure includes from bottom to top: a metal substrate, an insulating dielectric layer, and a surface micro-groove structure; the metal substrate is made of a metal material with a thermal conductivity of not less than 200 W / (m·K) and a thickness of 0.5-2mm; the insulating dielectric layer is composed of aluminum nitride or aluminum oxide, with a thermal conductivity of not less than 170 W / (m·K) and a thickness of 0.2-0.5mm; the surface micro-groove structure is periodically distributed, with a groove depth of 10-50μm, a period of 50-200μm, and a groove wall inclination of 55°-75°.

[0009] The first active device layer includes: a radio frequency power amplifier chip, a signal processing chip, gold wire bonding interconnections between chips, and a solder layer. The wire diameter of the gold wire bonding interconnections is 18-25 μm, and the arc height is 100-150 μm.

[0010] The first metal interconnection layer is used to connect the first active device layer and the heat dissipation buffer layer, and includes: multi-layer metal wiring with gradient line width, vertical interconnection channel TSV and dielectric layer; the minimum line width of the signal line is 3μm and the maximum line width is 20μm; the vertical interconnection channel TSV adopts a copper filling structure with an aspect ratio of not less than 10:1; the dielectric constant of the dielectric layer is not greater than 3.0, and the loss tangent is not greater than 0.002.

[0011] The heat dissipation buffer layer includes a plurality of microchannel structures, with a channel width of 50-200 μm, a depth of 150-300 μm, and a spacing of 200-400 μm; the microchannel structure is filled with a phase change material, with a phase change temperature range of 60-80°C and a latent heat of not less than 150 J / g; the channel wall coating is a hydrophilic coating with a contact angle of less than 30°.

[0012] The second active device layer includes: a radio frequency transceiver chip and a digital control circuit; the second active device layer is evenly distributed with a flip-chip interconnect structure and a heat dissipation bump array, the solder joint spacing of the flip-chip interconnect structure is not greater than 100 μm; the heat dissipation bump array has a spacing of 200-400 μm and a height of 50-80 μm.

[0013] The second metal interconnection layer is used to connect the second active device layer and the top heat dissipation structure, and the second metal interconnection layer includes: a differential pair wiring structure, a line spacing of not more than 3 times the line width; a power distribution network, a grid structure, a grid size of not more than λ / 20; an electromagnetic shielding wall, a height of not less than 5 times the signal line spacing.

[0014] The top heat dissipation structure is composed of a copper heat diffusion layer, a graphene heat conduction layer, a phase change material layer and a microneedle array from bottom to top; the copper heat diffusion layer has a purity of not less than 99.9% and a thickness of 0.3-0.8 mm; the number of graphene heat conduction layers is 20-50, and the thermal conductivity is not less than 3000 W / (m·K); the thermal conductivity of the phase change material layer is not less than 5 W / (m·K); the needle height of the microneedle array is 0.5-1.5 mm, the needle diameter is 50-100 μm, and the arrangement density is not less than 25 needles / mm 2 .

[0015] Furthermore, the metal substrate is made of a copper-molybdenum-copper composite material or a copper-tungsten-copper composite material, and the thermal expansion coefficient of the composite material matches that of the silicon chip, which is 6-8ppm / K; a grid-like micro-groove structure is provided at the bottom of the metal substrate, with a groove depth of 100-200μm and a groove width of 200-400μm.

[0016] Furthermore, the phase change material in the heat dissipation buffer layer is a paraffin-based carbon nanotube composite material with a carbon nanotube volume fraction of 5-10%; silver particles with a diameter of 1-5 μm are evenly distributed in the phase change material, and the surface of the silver particles is covered with an organic insulating layer with a thickness of 20-50 nm.

[0017] Furthermore, the first metal interconnection layer and the second metal interconnection layer adopt the same multi-layer metal process, including a three-layer metal interconnection structure; the top and bottom metals adopt copper wires with a thickness of 3-5 μm, and the middle metal adopts aluminum wires with a thickness of 1-2 μm; the density of the vertical interconnection channel TSV in the first active device layer area is not less than 100 / mm², and in the heat dissipation buffer layer area is not less than 50 / mm 2 .

[0018] Furthermore, the microneedle array of the top-level heat dissipation structure is made of a copper-based alloy material, and the radius of curvature of the needle tip is less than 10 μm; the surface of the microneedle is plated with a gold layer with a thickness of 0.5-1 μm to prevent oxidation; the microneedle array is used in conjunction with an air-cooled radiator or a liquid-cooled radiator. When the operating temperature exceeds 90°C, the heat dissipation system automatically switches to a forced liquid cooling mode, and the coolant flow rate is not less than 0.5 L / min.

[0019] Furthermore, the optimal thickness of the heat dissipation buffer layer is Determined by a multi-physics field coupling model, the expression of the multi-physics field coupling model is: .

[0020] in, ;

[0021] ;

[0022] ;

[0023] In the formula, is the base thickness of the heat dissipation buffer layer, which is 200 μm. is the effective thermal conductivity of the heat dissipation buffer layer, which varies with the state of the phase change material and ranges from 5 to 20 W / (m·K); is the reference thermal conductivity, which is taken as 1W / (m·K); The temperature gradient of the heat dissipation buffer layer shall not exceed 15K under normal working conditions; is the Rayleigh number of the microchannel in the heat dissipation buffer layer, and its value range is - ; is the reference temperature gradient, which is 1K; is the Prandtl number of the phase change material, ranging from 5 to 15. is the dielectric constant of the heat dissipation buffer layer, ranging from 2.5 to 3.5; is the reference dielectric constant, which is taken as 1.0; is the frequency response coefficient of the heat dissipation buffer layer; is the operating frequency, ranging from 28 to 40 GHz; is the reference frequency, which is 30GHz; is the surface roughness of the heat dissipation buffer layer, ranging from 0.5 to 2 μm; is the elastic modulus of the heat dissipation buffer layer, ranging from 15 to 25 GPa; is the reference elastic modulus, which is 1 GPa; is the yield strength of the heat dissipation buffer layer, ranging from 50-80Mpa; is the reference stress, the value is 1Mpa is the Poisson's ratio of the heat dissipation buffer layer, ranging from 0.28 to 0.32; The working stress of the heat dissipation buffer layer shall not exceed 30Mpa.

[0024] Furthermore, the graphene heat conduction layer thickness of the top heat dissipation structure is Calculated by the formula: ;in, is the number of graphene layers, ranging from 20 to 50 layers; is the thermal expansion coefficient of graphene, which is / K; is the operating temperature, in K, As the reference temperature, take 293K.

[0025] A nano silver paste transition layer with a thickness of 5-10 μm is provided between the graphene heat conduction layer and the phase change material layer. The silver content of the nano silver paste is not less than 85wt%, the sintering temperature is not higher than 250°C, and the thermal conductivity after sintering is not less than 250W / (m·K).

[0026] In a second aspect, the present invention provides a method for preparing a multilayer stack structure of high-power radio frequency chips with high heat dissipation efficiency, which is used to prepare the multilayer stack structure of the first aspect; the preparation method comprises the following steps:

[0027] Step S1, preparing a metal substrate;

[0028] The metal substrate is processed by an electrochemical polishing method, and a grid-like micro-groove structure is formed at the bottom of the metal substrate by a laser etching process; the metal plate is cut into a required size, and the metal plate is made of copper or a composite metal of copper and molybdenum; the surface roughness reaches Ra≤0.2μm by an electrochemical polishing method to form a metal substrate; a grid-like micro-groove structure is formed at the bottom of the metal substrate by a laser etching process; and the surface of the metal substrate is subjected to plasma activation treatment to improve the bonding strength with the insulating medium layer.

[0029] Step S2, preparing an insulating dielectric layer and a micro-groove structure;

[0030] The insulating dielectric layer is deposited on the metal substrate by plasma enhanced chemical vapor deposition, and the surface micro-groove structure is prepared by photolithography.

[0031] Aluminum nitride or aluminum oxide thin film is deposited on the metal substrate by plasma enhanced chemical vapor deposition (PECVD) method; the deposition temperature is controlled at , the deposition rate is After the deposition is completed, Anneal in a nitrogen atmosphere for 4-8 hours to eliminate internal stress.

[0032] The surface of the insulating dielectric layer is coated with photoresist, and the micro-groove pattern is formed by exposure and development; the micro-groove structure is formed by reactive ion etching (RIE) process; after removing the photoresist, atomic layer deposition (ALD) is used to deposit on the inner wall of the groove. of Passivation layer.

[0033] Step S3, preparing a first active device layer;

[0034] Titanium / copper / gold multilayer metal film is deposited on the micro-groove surface by magnetron sputtering as the chip welding layer; solder is applied using precision template screen printing technology with a thickness of 30-50μm; RF power amplifier chips and signal processing chips are placed using a precision placement machine; reflow soldering is performed in a nitrogen atmosphere at 250-280℃; ultrasonic gold wire bonding technology is used to complete chip interconnection, with a wire diameter of 18-25μm and an arc height of 100-150μm.

[0035] Step S4, preparing a first metal interconnection layer;

[0036] Low-temperature PECVD is used to deposit a dielectric layer with a dielectric constant not greater than 3.0; DRIE is used to form a vertical interconnect channel TSV with an aspect ratio of not less than 10:1; ion beam assisted deposition is used to deposit a diffusion barrier layer on the inner wall of the TSV; a pulse electroplating process is used to fill the TSV; a dual inlay process is used to form multi-layer metal wiring with a gradient line width, with a minimum signal line width of 3μm and a maximum line width of 20μm.

[0037] Step S5, preparing a heat dissipation buffer layer;

[0038] A DRIE process is used to form a microchannel structure with a channel width of 50-200μm, a depth of 150-300μm, and a spacing of 200-400μm. A hydrophilic coating is deposited on the inner wall of the microchannel using an electrochemical deposition technique to make a contact angle less than 30°. A phase change material with a phase change temperature range of 60-80°C and a latent heat of not less than 150 J / g is prepared. The microchannel is filled using a vacuum infusion method. Heat treatment is performed at 90-110°C for 1-2 hours.

[0039] Step S6, preparing a second active device layer;

[0040] The RF transceiver chip and digital control circuit are placed using a flip-chip process, with the solder joint spacing no greater than 100 μm; a heat dissipation bump array is prepared with a spacing of 200-400 μm and a height of 50-80 μm.

[0041] Step S7, preparing a second metal interconnection layer;

[0042] A differential pair wiring structure is formed with the line spacing no greater than 3 times the line width; a grid-like power distribution network is made with a grid size no greater than λ / 20, where λ is the free space wavelength corresponding to the operating frequency; and an electromagnetic shielding wall is set with a height no less than 5 times the signal line spacing.

[0043] Step S8, preparing a top heat dissipation structure;

[0044] Deposit a copper heat diffusion layer with a purity of not less than 99.9% and a thickness of 0.3-0.8mm; grow 20-50 layers of graphene heat conduction layer with a thermal conductivity of not less than 3000 W / (m·K); apply a phase change material layer with a thermal conductivity of not less than 5 W / (m·K); make needles with a height of 0.5-1.5mm, a needle diameter of 50-100μm, and an arrangement density of not less than 25 needles / mm 2 of microneedle arrays.

[0045] Furthermore, electrochemical polishing uses a mixed solution of phosphoric acid and sulfuric acid with a volume ratio of 3:1, the temperature is controlled at 40±5°C, and the current density is 20-30mA / cm 2 ; Laser etching uses pulsed laser with a wavelength of 1064nm, a pulse width of 100-200ns, and an energy density of 2-5J / cm 2 ;

[0046] The process gas for PECVD deposition is a mixture of trimethylaluminum and ammonia, with a flow ratio of 1:5, a RF power of 200-300W, and a substrate temperature of 350±20℃; positive photoresist is used for photolithography, and the exposure energy is 100-150mJ / cm 2 .

[0047] Furthermore, the thickness ratio of the multilayer metal film is Ti / Cu / Au=50nm / 2μm / 0.5μm; the welding temperature gradient is controlled within 2°C / s; and the bonding force of the gold wire bonding is 20-30gf.

[0048] The loss tangent of the dielectric layer is no more than 0.002; the thickness of the diffusion barrier layer on the inner wall of the TSV is 50-100nm; the current density of the pulse plating is 2-5mA / cm 2 .

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] The present invention adopts a multi-layer stacking structure and multiple heat dissipation channels, which significantly improves the heat dissipation efficiency; tests show that under the same power density, the thermal resistance of the present invention is reduced by more than 50% compared with the traditional structure; the heat dissipation buffer layer is innovatively introduced, and a microchannel structure filled with phase change material is adopted to achieve active temperature control, which can effectively prevent local overheating; through optimized material design and structural matching, the thermal expansion coefficient matching between the functional layers is achieved, which significantly improves the reliability and service life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a schematic diagram of a multi-layer stacking structure of high-power radio frequency chips with high efficiency heat dissipation according to the present invention. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention is described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] Example 1

[0054] like Figure 1 As shown, the present invention provides a multi-layer stacking structure of high-power RF chips with high efficiency in heat dissipation, and the stacking structure includes, from bottom to top, a base layer structure, a first active device layer, a first metal interconnection layer, a heat dissipation buffer layer, a second active device layer, a second metal interconnection layer and a top heat dissipation structure.

[0055] The base layer structure includes from bottom to top: a metal substrate, an insulating dielectric layer, and a surface micro-groove structure; the metal substrate is made of a metal material with a thermal conductivity of not less than 200 W / (m·K) and a thickness of 0.5-2mm; the insulating dielectric layer is composed of aluminum nitride or aluminum oxide, with a thermal conductivity of not less than 170 W / (m·K) and a thickness of 0.2-0.5mm; the surface micro-groove structure is periodically distributed, with a groove depth of 10-50μm, a period of 50-200μm, and a groove wall inclination of 55°-75°.

[0056] The first active device layer includes: a radio frequency power amplifier chip, a signal processing chip, gold wire bonding interconnections between chips, and a solder layer. The wire diameter of the gold wire bonding interconnections is 18-25 μm, and the arc height is 100-150 μm.

[0057] The first metal interconnection layer is used to connect the first active device layer and the heat dissipation buffer layer, and includes: multi-layer metal wiring with gradient line width, vertical interconnection channel TSV and dielectric layer; the minimum line width of the signal line is 3μm and the maximum line width is 20μm; the vertical interconnection channel TSV adopts a copper filling structure with an aspect ratio of not less than 10:1; the dielectric constant of the dielectric layer is not greater than 3.0, and the loss tangent is not greater than 0.002.

[0058] The heat dissipation buffer layer includes a plurality of microchannel structures, with a channel width of 50-200 μm, a depth of 150-300 μm, and a spacing of 200-400 μm; the microchannel structure is filled with a phase change material, with a phase change temperature range of 60-80°C and a latent heat of not less than 150 J / g; the channel wall coating is a hydrophilic coating with a contact angle of less than 30°.

[0059] The second active device layer includes: a radio frequency transceiver chip and a digital control circuit; the second active device layer is evenly distributed with a flip-chip interconnect structure and a heat dissipation bump array, the solder joint spacing of the flip-chip interconnect structure is not greater than 100 μm; the heat dissipation bump array has a spacing of 200-400 μm and a height of 50-80 μm.

[0060] The second metal interconnection layer is used to connect the second active device layer and the top heat dissipation structure, and the second metal interconnection layer includes: a differential pair wiring structure, a line spacing of not more than 3 times the line width; a power distribution network, a grid structure, a grid size of not more than λ / 20; an electromagnetic shielding wall, a height of not less than 5 times the signal line spacing.

[0061] The top heat dissipation structure is composed of a copper heat diffusion layer, a graphene heat conduction layer, a phase change material layer and a microneedle array from bottom to top; the copper heat diffusion layer has a purity of not less than 99.9% and a thickness of 0.3-0.8 mm; the number of graphene heat conduction layers is 20-50, and the thermal conductivity is not less than 3000 W / (m·K); the thermal conductivity of the phase change material layer is not less than 5 W / (m·K); the needle height of the microneedle array is 0.5-1.5 mm, the needle diameter is 50-100 μm, and the arrangement density is not less than 25 needles / mm 2 .

[0062] The metal substrate is made of a copper-molybdenum-copper composite material or a copper-tungsten-copper composite material. The thermal expansion coefficient of the composite material matches that of the silicon chip, which is 6-8ppm / K. A grid-like micro-groove structure is provided at the bottom of the metal substrate. The groove depth is 100-200μm and the groove width is 200-400μm.

[0063] The phase change material in the heat dissipation buffer layer is a paraffin-based carbon nanotube composite material with a carbon nanotube volume fraction of 5-10%; silver particles with a diameter of 1-5 μm are evenly distributed in the phase change material, and the surface of the silver particles is covered with an organic insulating layer with a thickness of 20-50 nm.

[0064] The first metal interconnection layer and the second metal interconnection layer adopt the same multi-layer metal process, including a three-layer metal interconnection structure; the top and bottom metals adopt copper wires with a thickness of 3-5μm, and the middle metal adopts aluminum wires with a thickness of 1-2μm; the density of the vertical interconnection channel TSV in the first active device layer area is not less than 100 / mm², and in the heat dissipation buffer layer area is not less than 50 / mm 2 .

[0065] The microneedle array of the top-level heat dissipation structure is made of a copper-based alloy material, and the radius of curvature of the needle tip is less than 10 μm; the surface of the microneedle is plated with a gold layer with a thickness of 0.5-1 μm to prevent oxidation; the microneedle array is used in conjunction with an air-cooled radiator or a liquid-cooled radiator. When the operating temperature exceeds 90°C, the heat dissipation system automatically switches to a forced liquid cooling mode, and the coolant flow rate is not less than 0.5 L / min.

[0066] The optimal thickness of the heat dissipation buffer layer Determined by a multi-physics field coupling model, the expression of the multi-physics field coupling model is: .

[0067] in, ;

[0068] ;

[0069] ;

[0070] In the formula, is the base thickness of the heat dissipation buffer layer, which is 200 μm. is the effective thermal conductivity of the heat dissipation buffer layer, which varies with the state of the phase change material and ranges from 5 to 20 W / (m·K); is the reference thermal conductivity, which is taken as 1W / (m·K); The temperature gradient of the heat dissipation buffer layer shall not exceed 15K under normal working conditions; is the Rayleigh number of the microchannel in the heat dissipation buffer layer, and its value range is - ; is the reference temperature gradient, which is 1K; is the Prandtl number of the phase change material, ranging from 5 to 15. is the dielectric constant of the heat dissipation buffer layer, ranging from 2.5 to 3.5; is the reference dielectric constant, which is taken as 1.0; is the frequency response coefficient of the heat dissipation buffer layer; is the operating frequency, ranging from 28 to 40 GHz; is the reference frequency, which is 30GHz; is the surface roughness of the heat dissipation buffer layer, ranging from 0.5 to 2 μm; is the elastic modulus of the heat dissipation buffer layer, ranging from 15 to 25 GPa; is the reference elastic modulus, which is 1 GPa; is the yield strength of the heat dissipation buffer layer, ranging from 50-80Mpa; is the reference stress, the value is 1Mpa is the Poisson's ratio of the heat dissipation buffer layer, ranging from 0.28 to 0.32; The working stress of the heat dissipation buffer layer shall not exceed 30Mpa.

[0071] The thickness of the graphene heat conduction layer of the top heat dissipation structure Calculated by the formula: ;in, is the number of graphene layers, ranging from 20 to 50 layers; is the thermal expansion coefficient of graphene, which is / K; is the operating temperature, in K, As the reference temperature, take 293K.

[0072] A nano silver paste transition layer with a thickness of 5-10 μm is provided between the graphene heat conduction layer and the phase change material layer. The silver content of the nano silver paste is not less than 85wt%, the sintering temperature is not higher than 250°C, and the thermal conductivity after sintering is not less than 250W / (m·K).

[0073] In addition, an electromagnetic compatibility isolation structure is provided between the first active device layer and the second active device layer, and the isolation structure comprises: an electromagnetic shielding layer with a thickness of 10-30 μm, using copper- , the band gap width is 5-15GHz.

[0074] Radiation suppression groove array, the groove depth is , the spacing is ;in is the free space wavelength corresponding to the operating frequency; the total thickness of the electromagnetic compatibility isolation structure Determined by the following relationship:

[0075] Where: is the conductivity of the electromagnetic shielding layer S / m; is the magnetic permeability of the electromagnetic shielding layer H / m; is the operating frequency Hz.

[0076] A grounding ring with a width of not less than 200 μm is provided at the edge region of the electromagnetic compatibility isolation structure, and the grounding ring is connected to the metal substrate via not less than 4 TSVs on each side.

[0077] In order to further improve the heat dissipation efficiency and electromagnetic shielding effect, the following optimization measures can be taken between the layers:

[0078] A heat diffusion layer with a thickness of 30-50 μm is added between the first active device layer and the heat dissipation buffer layer, and a diamond-filled copper-based composite material with high thermal conductivity (>380 W / m·K) is used to effectively alleviate the hot spot effect.

[0079] Ground shielding lines are set on both sides of the differential pair wiring in the second metal interconnection layer, and the line width is 1.5-2 times that of the signal line, reducing crosstalk by more than 30%.

[0080] Plasma treatment is performed on the surface of the microneedle array of the top heat dissipation structure to form a microstructure with a roughness Ra of 0.8-1.2 μm, thereby increasing the contact area with the coolant.

[0081] A periodic microgroove structure is arranged on the inner wall of the microchannel of the heat dissipation buffer layer, with a groove depth of 2-5 μm and a period of 10-20 μm, thereby enhancing the heat transfer coefficient by 15-25%.

[0082] Example 2

[0083] A method for preparing a multi-layer stacking structure of high-power radio frequency chips with high efficiency in heat dissipation is used to prepare the multi-layer stacking structure of Example 1.

[0084] The preparation method comprises the following steps:

[0085] Step S1, preparing a metal substrate;

[0086] The metal substrate is processed by an electrochemical polishing method, and a grid-like micro-groove structure is formed at the bottom of the metal substrate by a laser etching process; the metal plate is cut into a required size, and the metal plate is made of copper or a composite metal of copper and molybdenum; the surface roughness reaches Ra≤0.2μm by an electrochemical polishing method to form a metal substrate; a grid-like micro-groove structure is formed at the bottom of the metal substrate by a laser etching process; and the surface of the metal substrate is subjected to plasma activation treatment to improve the bonding strength with the insulating medium layer.

[0087] Step S2, preparing an insulating dielectric layer and a micro-groove structure;

[0088] The insulating dielectric layer is deposited on the metal substrate by plasma enhanced chemical vapor deposition, and the surface micro-groove structure is prepared by photolithography.

[0089] Aluminum nitride or aluminum oxide thin film is deposited on the metal substrate by plasma enhanced chemical vapor deposition (PECVD) method; the deposition temperature is controlled at , the deposition rate is After the deposition is completed, Anneal in a nitrogen atmosphere for 4-8 hours to eliminate internal stress.

[0090] The surface of the insulating dielectric layer is coated with photoresist, and the micro-groove pattern is formed by exposure and development; the micro-groove structure is formed by reactive ion etching (RIE) process; after removing the photoresist, atomic layer deposition (ALD) is used to deposit on the inner wall of the groove. of Passivation layer.

[0091] Step S3, preparing a first active device layer;

[0092] Titanium / copper / gold multilayer metal film is deposited on the micro-groove surface by magnetron sputtering as the chip welding layer; solder is applied using precision template screen printing technology with a thickness of 30-50μm; RF power amplifier chips and signal processing chips are placed using a precision placement machine; reflow soldering is performed in a nitrogen atmosphere at 250-280℃; ultrasonic gold wire bonding technology is used to complete chip interconnection, with a wire diameter of 18-25μm and an arc height of 100-150μm.

[0093] Step S4, preparing a first metal interconnection layer;

[0094] Low-temperature PECVD is used to deposit a dielectric layer with a dielectric constant not greater than 3.0; DRIE is used to form a vertical interconnect channel TSV with an aspect ratio of not less than 10:1; ion beam assisted deposition is used to deposit a diffusion barrier layer on the inner wall of the TSV; a pulse electroplating process is used to fill the TSV; a dual inlay process is used to form multi-layer metal wiring with a gradient line width, with a minimum signal line width of 3μm and a maximum line width of 20μm.

[0095] Step S5, preparing a heat dissipation buffer layer;

[0096] A DRIE process is used to form a microchannel structure with a channel width of 50-200μm, a depth of 150-300μm, and a spacing of 200-400μm. A hydrophilic coating is deposited on the inner wall of the microchannel using an electrochemical deposition technique to make a contact angle less than 30°. A phase change material with a phase change temperature range of 60-80°C and a latent heat of not less than 150 J / g is prepared. The microchannel is filled using a vacuum infusion method. Heat treatment is performed at 90-110°C for 1-2 hours.

[0097] Step S6, preparing a second active device layer;

[0098] The RF transceiver chip and digital control circuit are placed using a flip-chip process, with the solder joint spacing no greater than 100 μm; a heat dissipation bump array is prepared with a spacing of 200-400 μm and a height of 50-80 μm.

[0099] Step S7, preparing a second metal interconnection layer;

[0100] A differential pair wiring structure is formed with the line spacing no greater than 3 times the line width; a grid-like power distribution network is made with a grid size no greater than λ / 20, where λ is the free space wavelength corresponding to the operating frequency; and an electromagnetic shielding wall is set with a height no less than 5 times the signal line spacing.

[0101] Step S8, preparing a top heat dissipation structure;

[0102] Deposit a copper heat diffusion layer with a purity of not less than 99.9% and a thickness of 0.3-0.8mm; grow 20-50 layers of graphene heat conduction layer with a thermal conductivity of not less than 3000 W / (m·K); apply a phase change material layer with a thermal conductivity of not less than 5 W / (m·K); make needles with a height of 0.5-1.5mm, a needle diameter of 50-100μm, and an arrangement density of not less than 25 needles / mm 2 of microneedle arrays.

[0103] Electrochemical polishing uses a mixed solution of phosphoric acid and sulfuric acid with a volume ratio of 3:1, the temperature is controlled at 40±5℃, and the current density is 20-30mA / cm 2 ; Laser etching uses pulsed laser with a wavelength of 1064nm, a pulse width of 100-200ns, and an energy density of 2-5J / cm 2 ;

[0104] The process gas for PECVD deposition is a mixture of trimethylaluminum and ammonia, with a flow ratio of 1:5, a RF power of 200-300W, and a substrate temperature of 350±20℃; positive photoresist is used for photolithography, and the exposure energy is 100-150mJ / cm 2 .

[0105] The thickness ratio of the multilayer metal film is Ti / Cu / Au=50nm / 2μm / 0.5μm; the welding temperature gradient is controlled within 2℃ / s; and the bonding force of the gold wire bonding is 20-30gf.

[0106] The loss tangent of the dielectric layer is no more than 0.002; the thickness of the diffusion barrier layer on the inner wall of the TSV is 50-100nm; the current density of the pulse plating is 2-5mA / cm 2 .

[0107] The electrochemically deposited hydrophilic coating uses a nickel-phosphorus alloy with a deposition potential of -0.8 to -1.2 V; the phase change material is a paraffin-based carbon nanotube composite material with a carbon nanotube volume fraction of 5-10%;

[0108] In step S6, the flip-chip soldering adopts lead-free solder paste, and the maximum reflow temperature is controlled at 260±5℃; the heat dissipation bump adopts copper pillar electroplating process, and the current density is 10-15mA / cm²; in step S7, the characteristic impedance of the differential pair wiring is controlled at 100±5Ω; the electromagnetic shielding wall adopts copper nickel plating process, and the nickel layer thickness is 0.5-1μm; in step S8, graphene is grown by chemical vapor deposition, and the growth temperature is 1000±50℃; the microneedle array adopts electrochemical corrosion process, and the corrosion liquid is ferric chloride solution.

[0109] The multi-layer stacking structure of the present invention is applied to a 5G millimeter wave base station power amplifier, and the specific parameters are as follows:

[0110] Operating frequency: 39GHz; Output power: >10W; Power density: >5W / mm²; Operating temperature range: -40℃ to +85℃.

[0111] The test results after continuous operation for 8 hours using the stacking structure of the present invention are as follows:

[0112] Junction temperature: maximum temperature 85.6℃, temperature uniformity ±3.2℃; thermal resistance: 0.42℃ / W, 56% lower than the traditional structure; RF performance: small signal gain 24.5dB, output power saturation point 42.5dBm, power added efficiency (PAE) 45%; reliability: no performance degradation after 1000 times of -40℃ / +125℃ temperature cycle.

[0113] Compared with existing technologies, the heat dissipation performance is improved: thermal resistance is reduced by 56%, and temperature uniformity is improved by 40%; RF performance is improved: PAE is increased by 5 percentage points, and output power is increased by 1.2dB; reliability is improved: MTTF (mean time to failure) is increased by 2.5 times.

[0114] The above test results show that the multi-layer stacking structure of the present invention significantly improves the heat dissipation effect and reliability of high-power RF chips while ensuring high-frequency performance, meeting the actual application requirements of 5G millimeter wave base stations.

[0115] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A multi-layer stacking structure of high-power radio frequency chips with high efficiency heat dissipation, characterized in that: The stacked structure includes, from bottom to top, a base layer structure, a first active device layer, a first metal interconnection layer, a heat dissipation buffer layer, a second active device layer, a second metal interconnection layer, and a top heat dissipation structure; The base layer structure includes from bottom to top: a metal substrate, an insulating dielectric layer, and a surface micro-groove structure; the metal substrate is made of a metal material with a thermal conductivity of not less than 200 W / (m·K) and a thickness of 0.5-2mm; the insulating dielectric layer is made of aluminum nitride or aluminum oxide, with a thermal conductivity of not less than 170 W / (m·K) and a thickness of 0.2-0.5mm; the surface micro-groove structure is periodically distributed, with a groove depth of 10-50μm, a period of 50-200μm, and a groove wall inclination of 55°-75°; The first active device layer includes: a radio frequency power amplifier chip, a signal processing chip, gold wire bonding interconnection between chips and a solder layer, wherein the wire diameter of the gold wire bonding interconnection is 18-25 μm and the arc height is 100-150 μm; The first metal interconnection layer is used to connect the first active device layer and the heat dissipation buffer layer, including: multi-layer metal wiring with gradient line width, vertical interconnection channel TSV and dielectric layer; the minimum line width of the signal line is 3μm, and the maximum line width is 20μm; the vertical interconnection channel TSV adopts a copper filling structure with an aspect ratio of not less than 10:1; the dielectric constant of the dielectric layer is not greater than 3.0, and the loss tangent is not greater than 0.002; The heat dissipation buffer layer includes a plurality of microchannel structures, with a channel width of 50-200 μm, a depth of 150-300 μm, and a spacing of 200-400 μm; the microchannel structure is filled with a phase change material, with a phase change temperature range of 60-80°C and a latent heat of not less than 150 J / g; the channel wall coating is a hydrophilic coating with a contact angle of less than 30°; The second active device layer includes: a radio frequency transceiver chip and a digital control circuit; the second active device layer is evenly distributed with a flip-chip interconnect structure and a heat dissipation bump array, the solder joint spacing of the flip-chip interconnect structure is not greater than 100 μm; the heat dissipation bump array has a spacing of 200-400 μm and a height of 50-80 μm; The second metal interconnection layer is used to connect the second active device layer and the top heat dissipation structure, and the second metal interconnection layer includes: a differential pair wiring structure, the line spacing is not greater than 3 times the line width; a power distribution network, using a grid structure, the grid size is not greater than λ / 20; an electromagnetic shielding wall, the height of which is not less than 5 times the signal line spacing; The top heat dissipation structure is composed of a copper heat diffusion layer, a graphene heat conduction layer, a phase change material layer and a microneedle array from bottom to top; the copper heat diffusion layer has a purity of not less than 99.9% and a thickness of 0.3-0.8 mm; the number of graphene heat conduction layers is 20-50, and the thermal conductivity is not less than 3000 W / (m·K); the thermal conductivity of the phase change material layer is not less than 5 W / (m·K); the needle height of the microneedle array is 0.5-1.5 mm, the needle diameter is 50-100 μm, and the arrangement density is not less than 25 needles / mm 2 .

2. The multi-layer stacking structure of high-power radio frequency chips with high heat dissipation efficiency according to claim 1, characterized in that: The metal substrate is made of a copper-molybdenum-copper composite material or a copper-tungsten-copper composite material. The thermal expansion coefficient of the composite material matches that of the silicon chip, which is 6-8ppm / K. A grid-like micro-groove structure is provided at the bottom of the metal substrate. The groove depth is 100-200μm and the groove width is 200-400μm.

3. The multi-layer stacking structure of high-power radio frequency chips with high heat dissipation efficiency according to claim 2 is characterized in that: The phase change material in the heat dissipation buffer layer is a paraffin-based carbon nanotube composite material with a carbon nanotube volume fraction of 5-10%; silver particles with a diameter of 1-5 μm are evenly distributed in the phase change material, and the surface of the silver particles is covered with an organic insulating layer with a thickness of 20-50 nm.

4. The multi-layer stacking structure of high-power radio frequency chips with high heat dissipation efficiency according to claim 3 is characterized in that: The first metal interconnection layer and the second metal interconnection layer adopt the same multi-layer metal process, including a three-layer metal interconnection structure; the top and bottom metals adopt copper wires with a thickness of 3-5μm, and the middle metal adopts aluminum wires with a thickness of 1-2μm; the density of the vertical interconnection channel TSV in the first active device layer area is not less than 100 / mm², and in the heat dissipation buffer layer area is not less than 50 / mm 2 .

5. The multi-layer stacking structure of high-power radio frequency chips with high heat dissipation efficiency according to claim 4, characterized in that: The microneedle array of the top-level heat dissipation structure is made of a copper-based alloy material, and the radius of curvature of the needle tip is less than 10 μm; the surface of the microneedle is plated with a gold layer with a thickness of 0.5-1 μm to prevent oxidation; the microneedle array is used in conjunction with an air-cooled radiator or a liquid-cooled radiator. When the operating temperature exceeds 90°C, the heat dissipation system automatically switches to a forced liquid cooling mode, and the coolant flow rate is not less than 0.5 L / min.

6. The multi-layer stacking structure of high-power radio frequency chips with high heat dissipation efficiency according to any one of claims 1 to 5, characterized in that: The optimal thickness of the heat dissipation buffer layer Determined by a multi-physics field coupling model, the expression of the multi-physics field coupling model is: ; in, ; ； ； In the formula, is the base thickness of the heat dissipation buffer layer, which is 200 μm. is the effective thermal conductivity of the heat dissipation buffer layer, which varies with the state of the phase change material and ranges from 5 to 20 W / (m·K); is the reference thermal conductivity, which is taken as 1W / (m·K); The temperature gradient of the heat dissipation buffer layer shall not exceed 15K under normal working conditions; is the Rayleigh number of the microchannel in the heat dissipation buffer layer, and its value range is - ; is the reference temperature gradient, which is 1K; is the Prandtl number of the phase change material, ranging from 5 to 15. is the dielectric constant of the heat dissipation buffer layer, ranging from 2.5 to 3.5; is the reference dielectric constant, which is taken as 1.0; is the frequency response coefficient of the heat dissipation buffer layer; is the operating frequency, ranging from 28 to 40 GHz; is the reference frequency, which is 30GHz; is the surface roughness of the heat dissipation buffer layer, ranging from 0.5 to 2 μm; is the elastic modulus of the heat dissipation buffer layer, ranging from 15 to 25 GPa; is the reference elastic modulus, which is 1 GPa; is the yield strength of the heat dissipation buffer layer, ranging from 50-80Mpa; is the reference stress, the value is 1Mpa is the Poisson's ratio of the heat dissipation buffer layer, ranging from 0.28 to 0.32; The working stress of the heat dissipation buffer layer shall not exceed 30Mpa.

7. The multi-layer stacking structure of high-power radio frequency chips with high heat dissipation efficiency according to claim 6, characterized in that: The thickness of the graphene heat conduction layer of the top heat dissipation structure Calculated by the formula: ;in, is the number of graphene layers, ranging from 20 to 50 layers; is the thermal expansion coefficient of graphene, which is / K; is the operating temperature, in K, As the reference temperature, 293K is taken; A nano silver paste transition layer with a thickness of 5-10 μm is provided between the graphene heat conduction layer and the phase change material layer. The silver content of the nano silver paste is not less than 85wt%, the sintering temperature is not higher than 250°C, and the thermal conductivity after sintering is not less than 250W / (m·K).

8. A method for preparing a multi-layer stacking structure of high-power radio frequency chips with high efficiency heat dissipation, used for preparing the multi-layer stacking structure according to any one of claims 1 to 7; characterized in that: The preparation method comprises the following steps: Step S1, preparing a metal substrate; The metal substrate is processed by an electrochemical polishing method, and a grid-like micro-groove structure is formed at the bottom of the metal substrate by a laser etching process; the metal plate is cut into a required size, and the metal plate is made of copper or a composite metal of copper and molybdenum; the surface roughness reaches Ra≤0.2μm by an electrochemical polishing method to form a metal substrate; a grid-like micro-groove structure is formed at the bottom of the metal substrate by a laser etching process; the surface of the metal substrate is subjected to plasma activation treatment to improve the bonding strength with the insulating dielectric layer; Step S2, preparing an insulating dielectric layer and a micro-groove structure; The insulating dielectric layer is deposited on the metal substrate by plasma enhanced chemical vapor deposition method, and the surface micro-groove structure is prepared by photolithography process; Aluminum nitride or aluminum oxide thin film is deposited on the metal substrate by plasma enhanced chemical vapor deposition (PECVD) method; the deposition temperature is controlled at , the deposition rate is After the deposition is completed, Anneal in a nitrogen atmosphere for 4-8 hours to eliminate internal stress; The surface of the insulating dielectric layer is coated with photoresist, and the micro-groove pattern is formed by exposure and development; the micro-groove structure is formed by reactive ion etching (RIE) process; after removing the photoresist, atomic layer deposition (ALD) is used to deposit on the inner wall of the groove. of Passivation layer; Step S3, preparing a first active device layer; Titanium / copper / gold multilayer metal films are deposited on the micro-groove surface by magnetron sputtering as chip welding layers; solder is applied using precision template screen printing technology with a thickness of 30-50μm; RF power amplifier chips and signal processing chips are placed using precision placement machines; reflow soldering is performed in a nitrogen atmosphere at 250-280℃; ultrasonic gold wire bonding technology is used to complete chip interconnection, with a wire diameter of 18-25μm and an arc height of 100-150μm; Step S4, preparing a first metal interconnection layer; Low-temperature PECVD is used to deposit a dielectric layer with a dielectric constant of no more than 3.0; DRIE is used to form a vertical interconnect channel TSV with an aspect ratio of no less than 10:1; ion beam assisted deposition is used to deposit a diffusion barrier layer on the inner wall of the TSV; a pulse electroplating process is used to fill the TSV; a dual damascene process is used to form a multi-layer metal wiring with a gradient line width, with a minimum signal line width of 3μm and a maximum line width of 20μm; Step S5, preparing a heat dissipation buffer layer; The microchannel structure is formed by using DRIE process, with a channel width of 50-200 μm, a depth of 150-300 μm, and a spacing of 200-400 μm; a hydrophilic coating is deposited on the inner wall of the microchannel by using electrochemical deposition technology to make the contact angle less than 30°; a phase change material with a phase change temperature range of 60-80°C and a latent heat of not less than 150 J / g is prepared; the microchannel is filled by vacuum infusion method; and heat treatment is performed at 90-110°C for 1-2 hours; Step S6, preparing a second active device layer; The RF transceiver chip and digital control circuit are placed using a flip-chip process, with the solder joint spacing no greater than 100 μm; a heat dissipation bump array is prepared with a spacing of 200-400 μm and a height of 50-80 μm; Step S7, preparing a second metal interconnection layer; Form a differential pair wiring structure with a line spacing no greater than 3 times the line width; make a grid-shaped power distribution network with a grid size no greater than λ / 20, where λ is the free space wavelength corresponding to the operating frequency; set up an electromagnetic shielding wall with a height no less than 5 times the signal line spacing; Step S8, preparing a top heat dissipation structure; Deposit a copper heat diffusion layer with a purity of not less than 99.9% and a thickness of 0.3-0.8mm; grow 20-50 layers of graphene heat conduction layer with a thermal conductivity of not less than 3000 W / (m·K); apply a phase change material layer with a thermal conductivity of not less than 5 W / (m·K); make needles with a height of 0.5-1.5mm, a needle diameter of 50-100μm, and an arrangement density of not less than 25 needles / mm 2 of microneedle arrays.

9. The method for preparing a multi-layer stacked structure of high-power radio frequency chips with high efficiency heat dissipation according to claim 8, characterized in that: Electrochemical polishing uses a mixed solution of phosphoric acid and sulfuric acid with a volume ratio of 3:1, the temperature is controlled at 40±5℃, and the current density is 20-30mA / cm 2 ; Laser etching uses pulsed laser with a wavelength of 1064nm, a pulse width of 100-200ns, and an energy density of 2-5J / cm 2 ; The process gas for PECVD deposition is a mixture of trimethylaluminum and ammonia, with a flow ratio of 1:5, a RF power of 200-300W, and a substrate temperature of 350±20℃; positive photoresist is used for photolithography, and the exposure energy is 100-150mJ / cm 2 .

10. The method for preparing a multi-layer stacked structure of high-power radio frequency chips with high efficiency heat dissipation according to claim 8, characterized in that: The thickness ratio of the multilayer metal film is Ti / Cu / Au=50nm / 2μm / 0.5μm; the welding temperature gradient is controlled within 2℃ / s; the bonding force of the gold wire bonding is 20-30gf; The loss tangent of the dielectric layer is no more than 0.002; the thickness of the diffusion barrier layer on the inner wall of the TSV is 50-100nm; the current density of the pulse plating is 2-5mA / cm 2 .

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