Semiconductor device and electronic system including the same

Abstract

The invention relates to a semiconductor device and an electronic system including the same. The semiconductor device may include a circuit element wiring, a lower wiring connected to the circuit element wiring, a lower interlayer insulating layer on the lower wiring, and a first contact pad penetrating the lower interlayer insulating layer. The first contact pad may include a first portion connected to the lower wiring, a second portion including a void on the first portion, and a third portion on the second portion. The maximum width between the two outer surfaces of the second part in the horizontal direction can be larger than the width of the third part in the horizontal direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] In an electronic system requiring data storage, a semiconductor device capable of storing high-capacity data may be required. Therefore, methods of increasing the data storage capacity of semiconductor devices are being studied. For example, as one of the methods of increasing the data storage capacity of semiconductor devices, a semiconductor device including a three-dimensionally arranged storage cell instead of a two-dimensionally arranged storage cell has been proposed. Summary of the invention

[0003] The present disclosure seeks to provide a semiconductor device capable of improving performance and reliability.

[0004] According to example embodiments, a semiconductor device may include: a circuit element wiring; a lower wiring connected to the circuit element wiring; a lower interlayer insulating layer on the lower wiring; and a first contact pad penetrating the lower interlayer insulating layer. The first contact pad may include a first portion, a second portion on the first portion, and a third portion on the second portion. The first portion of the first contact pad may be connected to the lower wiring. The second portion of the first contact pad may include a gap on the first portion of the first contact pad. The maximum width of the second portion of the first contact pad in the horizontal direction may be greater than the width of the third portion of the first contact pad in the horizontal direction, and the maximum width of the second portion of the first contact pad in the horizontal direction may be a distance from a first outer surface of the second portion of the first contact pad to a second outer surface of the second portion of the first contact pad.

[0005] According to example embodiments, a semiconductor device may include a first contact structure and a second contact structure on the first contact structure. The first contact structure may include a lower interlayer insulating layer, a first bonding insulating layer on the lower interlayer insulating layer, and a first contact pad penetrating the lower interlayer insulating layer and the first bonding insulating layer. The second contact structure may include a second bonding insulating layer on the first contact structure and a second contact pad connected to the first contact pad, the second contact pad penetrating the second bonding insulating layer. The first contact pad may include a first portion extending in one direction, a second portion below the first bonding insulating layer, and a third portion penetrating the first bonding insulating layer. The second portion of the first contact pad may protrude further in a horizontal direction than the first portion of the first contact pad, and the second portion of the first contact pad may include an internal buried void.

[0006] According to example embodiments, a semiconductor device may include a peripheral structure and a unit structure stacked on the peripheral structure. The peripheral structure may include a first substrate, a circuit element on the first substrate, a lower interlayer insulating layer on the first substrate, a first bonding insulating layer on the lower interlayer insulating layer, and a first contact pad penetrating the lower interlayer insulating layer and the first bonding insulating layer. The unit structure may include a second substrate electrically connected to the first substrate, a gate stack structure, a channel structure penetrating the gate stack structure in a cell array region of the second substrate, a second bonding insulating layer between the gate stack structure and the first bonding insulating layer, and a second contact pad connected to the first contact pad and penetrating the second bonding insulating layer. The second substrate may include a cell array region and an extension region. The first surface of the second substrate may face the peripheral structure, and the second surface of the second substrate may be opposite to the first surface. The gate stack structure may include a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked on the first surface of the second substrate. The first contact pad may include a first portion extending in one direction, a second portion between the first portion and the first bonding insulating layer, and a third portion penetrating the first bonding insulating layer. The second portion of the first contact pad may include an internally buried void. The second portion of the first contact pad may protrude further than the third portion of the first contact pad in a horizontal direction.

[0007] According to the semiconductor device according to the embodiment, the second portion of the first contact pad may include a gap, so when the annealing process is performed, the first contact pad may thermally expand into the gap. Therefore, the first contact structure and the second contact structure may be limited and / or prevented from being separated or the first contact pad and the second contact pad may be disconnected. Therefore, the reliability of the semiconductor device may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0009] Figure 2 yes Figure 1 An enlarged cross-sectional view of area A1.

[0010] Figures 3 to 10 is corresponding to Figure 1 A cross-sectional view of a region A1 of a semiconductor device according to some embodiments is shown.

[0011] Figures 11 to 15 is a cross-sectional view showing a semiconductor device according to some embodiments.

[0012] Fig.16 yes Fig.15 An enlarged cross-sectional view of area A2.

[0013] Fig.17 is a cross-sectional view showing a semiconductor device according to some embodiments.

[0014] Figures 18 to 29 is a cross-sectional view showing an intermediate operation of a method for manufacturing a semiconductor device according to an embodiment.

[0015] Figure 30 to Figure 35 are cross-sectional views showing intermediate operations of a method of manufacturing a semiconductor device according to some embodiments.

[0016] Fig.36 is a plan view schematically showing a semiconductor device according to an embodiment.

[0017] Fig.37 is a cross-sectional view schematically showing a semiconductor device according to an embodiment.

[0018] Fig.38 is a cross-sectional view showing a channel structure of a semiconductor device according to an embodiment.

[0019] Fig.39 is a cross-sectional view showing a channel structure of a semiconductor device according to some embodiments.

[0020] Fig.40 is a diagram schematically showing an electronic system including a semiconductor device according to an embodiment.

[0021] Fig.41 is a perspective view schematically showing an electronic system including a semiconductor device according to an embodiment.

[0022] Fig.42 is a cross-sectional view schematically showing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0023] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. As those skilled in the art will appreciate, the described embodiments can be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0024] In order to clearly describe the present disclosure, parts or portions irrelevant to the description are omitted, and the same or similar constituent elements are denoted by the same reference numerals throughout the specification.

[0025] In addition, in the drawings, for ease of description, the size and thickness of each element are arbitrarily shown, and the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, for ease of description, the thickness of layers, films, panels, regions, areas, etc. are exaggerated for clarity.

[0026] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, in the specification, the words "on..." or "over..." mean disposed on or below an object part, and do not necessarily mean disposed on the upper side of the object part based on the direction of gravity.

[0027] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising” or “including,” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0028] Furthermore, throughout the specification, the phrase “in a top view” or “on a plane” means observing a target portion from the top, and the phrase “in a cross-sectional view” or “on a section” means observing a section formed by vertically cutting the target portion from the side.

[0029] In the following, reference will be made to Figure 1 and Figure 2 A semiconductor device according to an embodiment is described.

[0030] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 2 yes Figure 1 An enlarged cross-sectional view of area A1.

[0031] Reference Figure 1 and Figure 2 , a semiconductor device according to an embodiment may include a circuit element wiring PTM, a first contact structure ST1 located on the circuit element wiring PTM, and a second contact structure ST2 located on the first contact structure ST1.

[0032] In an embodiment, the circuit element wiring PTM may be connected to various circuit elements that control the operation of the semiconductor device. That is, the circuit element wiring PTM may represent wiring connected to the circuit elements that control the operation of the semiconductor device. For example, the circuit elements may constitute a peripheral circuit structure such as a decoder circuit ( Fig.40 Reference numeral 1110 in the figure), page buffer ( Fig.40 Reference numeral 1120 in the figure), logic circuit ( Fig.40 1130 in the figure). The circuit element may include, for example, a transistor, but example embodiments are not limited thereto. For example, the circuit element may include not only active elements such as transistors, but also passive elements such as capacitors, resistors, and inductors.

[0033] The circuit element wiring PTM may be located within the inter-wiring insulating layer 250. For example, the circuit element wiring PTM may penetrate the inter-wiring insulating layer 250. The circuit element wiring PTM may be located at the same or substantially the same level as an upper surface of the inter-wiring insulating layer 250.

[0034] The first and second contact structures ST1 and ST2 may be located on the circuit element wiring PTM.

[0035] In an embodiment, the first contact structure ST1 and the second contact structure ST2 may be a bonded semiconductor device of a chip-to-chip (C2C) structure bonded by a wafer bonding method (eg, hybrid bonding). For example, each of the first contact structure ST1 and the second contact structure ST2 may be Fig.37 The peripheral structure of the semiconductor device shown in ( Fig.37 PERI) and unit structure ( Fig.37 Alternatively, as another example, each of the first contact structure ST1 and the second contact structure ST2 may be a portion corresponding to at least a portion of the CELL included in the Fig.40 The first contact structure ST1 and the second contact structure ST2 may be a portion corresponding to at least a portion of the peripheral structure PERI and the cell structure CELL of the semiconductor device 1100 in the electronic system 1000 shown in FIG. As another example, each of the first contact structure ST1 and the second contact structure ST2 may be a portion corresponding to at least a portion of the peripheral structure PERI and the cell structure CELL of the semiconductor device 1100 in the electronic system 1000 shown in FIG. Fig.42 2. However, example embodiments are not limited thereto, and the first contact structure ST1 and the second contact structure ST2 may be applied to all semiconductor devices including a chip-to-chip (C2C) structure bonded by a wafer bonding method (e.g., hybrid bonding).

[0036] In an embodiment, the first contact structure ST1 may include a first surface and a second surface opposite to each other. The first surface of the first contact structure ST1 may be a surface facing the second contact structure ST2, and the second surface of the first contact structure ST1 may be a surface away from the second contact structure ST2. Here, the first surface of the first contact structure ST1 may mean the front side of the first contact structure ST1, and the second surface of the first contact structure ST1 may mean the rear side of the first contact structure ST1. In addition, the second contact structure ST2 may include a first surface and a second surface opposite to each other. The first surface of the second contact structure ST2 may be a surface facing the first contact structure ST1. The second surface of the second contact structure ST2 may be a surface away from the first contact structure ST1.

[0037] In an embodiment, the first surface of the first contact structure ST1 adjacent to the second contact structure ST2 may be a bonding surface relative to the second contact structure ST2. In addition, the first surface of the second contact structure ST2 adjacent to the first contact structure ST1 may be a bonding surface relative to the first contact structure ST1. That is, the first surface of the first contact structure ST1 and the first surface of the second contact structure ST2 may be a bonding surface between the first contact structure ST1 and the second contact structure ST2.

[0038] At this time, the first surface of the first contact structure ST1 and the first surface of the second contact structure ST2 can be joined by hybrid bonding. Specifically, the first contact pad 600 of the first contact structure ST1 and the second contact pad 700 of the second contact structure ST2 can be joined in direct contact to form a metal joint. In addition, the first bonding insulating layer 450 of the first contact structure ST1 and the second bonding insulating layer 350 of the second contact structure ST2 can be joined to form a bonding insulating layer. In this way, the first contact pad 600 of the first contact structure ST1 and the second contact pad 700 of the second contact structure ST2 can be joined, and an electrical connection path can be provided between the first contact structure ST1 and the second contact structure ST2. For example, the element connected to the second contact structure ST2 can be electrically connected to the circuit element connected to the circuit element wiring PTM through the first contact pad 600 and the second contact pad 700.

[0039] In the embodiment, it is shown that the first contact structure ST1 and the second contact structure ST2 are located on the circuit element wiring PTM, but the example embodiment is not limited thereto. For example, the first contact structure ST1 and the second contact structure ST2 may be located on at least one contact structure. As another example, the semiconductor device according to some embodiments may not be provided with the circuit element wiring PTM. In this case, the first contact structure ST1 may be located on the circuit element.

[0040] The first contact structure ST1 of the semiconductor device according to the embodiment may include a first insulating structure 400 on the circuit element wiring PTM, a lower contact via LC1 and a lower wiring LM1 penetrating at least a portion of the first insulating structure 400 , and a first contact pad 600 electrically connected to the lower wiring LM1 .

[0041] The first insulating structure 400 may include a plurality of lower barrier layers LB on the circuit element wirings PTM and the inter-wiring insulating layer 250 , a plurality of lower interlayer insulating layers 410 , 420 , and 430 on each of the plurality of lower barrier layers LB, and a first bonding insulating layer 450 on the third lower interlayer insulating layer 430 .

[0042] The plurality of lower barrier layers LB may include a first lower barrier layer LB1 and a second lower barrier layer LB2.

[0043] The first lower barrier layer LB1 may be located on the circuit element wiring PTM and the inter-wiring insulating layer 250. For example, the first lower barrier layer LB1 may be located on the upper surface of the circuit element wiring PTM. The first lower barrier layer LB1 may cover the circuit element wiring PTM and the inter-wiring insulating layer 250. The bottom surface of the first lower barrier layer LB1 may contact the circuit element wiring PTM and the inter-wiring insulating layer 250. The first lower barrier layer LB1 may be located between the first lower interlayer insulating layer 410 and the inter-wiring insulating layer 250.

[0044] The second lower barrier layer LB2 may be located on the first lower barrier layer LB1. For example, the second lower barrier layer LB2 may be located to be spaced apart from the first lower barrier layer LB1 in a direction away from the circuit element wiring PTM. That is, the second lower barrier layer LB2 may be located to be spaced apart from the first lower barrier layer LB1 in a third direction (Z direction). The second lower barrier layer LB2 may be located between the second lower interlayer insulating layer 420 and the third lower interlayer insulating layer 430. The second lower barrier layer LB2 may be located on the lower wiring LM1.

[0045] In an embodiment, the plurality of lower barrier layers LB1 and LB2 may include silicon nitride. However, example embodiments are not limited thereto, and each of the plurality of lower barrier layers LB1 and LB2 may include at least one of silicon oxynitride and silicon carbon nitride. In a process of manufacturing the lower wiring LM1 and the lower contact path LC1, the plurality of lower barrier layers LB1 and LB2 may be used as a barrier to limit and / or prevent a material forming the lower wiring LM1 and the lower contact path LC1 from diffusing to the surroundings.

[0046] exist Figure 1 and Figure 2 , the number of the plurality of lower barrier layers LB1 and LB2 is shown as 2, but example embodiments are not limited thereto. For example, the first insulating structure 400 may include one lower barrier layer. As another example, the first insulating structure 400 may include three or more lower barrier layers. As yet another example, the first insulating structure 400 may not include the plurality of lower barrier layers LB1 and LB2. This will be referred to later. Fig.14 Detailed description.

[0047] The plurality of lower interlayer insulating layers 410, 420, and 430 of the semiconductor device according to the embodiment may include a first lower interlayer insulating layer 410, a second lower interlayer insulating layer 420, and a third lower interlayer insulating layer 430. In the embodiment, the lower contact path LC1 may be located in the first lower interlayer insulating layer 410, and the lower wiring LM1 may be located in the second lower interlayer insulating layer 420. However, this is only an example, and the example embodiment is not limited thereto. For example, the lower contact path LC1 and the lower wiring LM1 may be located in one of the plurality of lower interlayer insulating layers 410, 420, and 430.

[0048] In more detail, the first lower interlayer insulating layer 410 may be stacked on the first lower barrier layer LB1, and the second lower interlayer insulating layer 420 may be stacked on the first lower interlayer insulating layer 410. In addition, the third lower interlayer insulating layer 430 may be located on the second lower barrier layer LB2. That is, the second lower barrier layer LB2 may be located between the second lower interlayer insulating layer 420 and the third lower interlayer insulating layer 430.

[0049] The lower wiring LM1 may be located within the second lower interlayer insulating layer 420. The upper surface of the lower wiring LM1 may contact the bottom surface of the second lower barrier layer LB2. That is, the upper surface of the lower wiring LM1 may be located at the same or substantially the same level as the upper surface of the second lower interlayer insulating layer 420. The bottom surface and side surfaces of the lower wiring LM1 may be surrounded by the plurality of lower interlayer insulating layers 410, 420, and 430. For example, the side surface of the lower wiring LM1 may be surrounded by the second lower interlayer insulating layer 420. The bottom surface of the lower wiring LM1 may be surrounded by the first lower interlayer insulating layer 410.

[0050] The lower wiring LM1 may be connected to the circuit element wiring PTM through the lower contact path LC1 penetrating the first lower barrier layer LB1. At this time, the lower contact path LC1 may penetrate the first lower interlayer insulating layer 410 and the first lower barrier layer LB1. Therefore, the lower wiring LM1 may be electrically connected to the circuit element through the circuit element wiring PTM. The lower wiring LM1 may be integrally formed with the first lower contact path LC1 without an interface, but example embodiments are not limited thereto.

[0051] In an embodiment, the lower wiring LM1 and the lower contact path LC1 may include a conductive material. For example, the lower wiring LM1 and the lower contact path LC1 may include copper (Cu). However, example embodiments are not limited thereto, and the lower wiring LM1 and the lower contact path LC1 may include a conductive material such as tungsten (W) or aluminum (Al).

[0052] In an embodiment, the plurality of lower interlayer insulating layers 410, 420, and 430 may include an insulating material. The plurality of lower interlayer insulating layers 410, 420, and 430 may include the same material, but example embodiments are not limited thereto. The plurality of lower interlayer insulating layers 410, 420, and 430 may include a material having an etching selectivity relative to the plurality of lower barrier layers LB1 and LB2. In addition, the plurality of lower interlayer insulating layers 410, 420, and 430 may include a material having an etching selectivity relative to the first bonding insulating layer 450 described later. For example, the plurality of lower interlayer insulating layers 410, 420, and 430 may include silicon oxide. However, example embodiments are not limited thereto, and each of the plurality of lower interlayer insulating layers 410, 420, and 430 may include at least one of silicon oxynitride and silicon carbon nitride.

[0053] The first bonding insulating layer 450 may be located on the plurality of lower interlayer insulating layers 410, 420, and 430. Specifically, the first bonding insulating layer 450 may be located on the uppermost third lower interlayer insulating layer 430. In an embodiment, a bottom surface of the first bonding insulating layer 450 may contact the third lower interlayer insulating layer 430, but example embodiments are not limited thereto.

[0054] In an embodiment, the upper surface of the first bonding insulating layer 450 may constitute a bonding surface where the first contact structure ST1 and the second contact structure ST2 are bonded. For example, the first bonding insulating layer 450 may be bonded to the second bonding insulating layer 350 of the second contact structure ST2 to configure a portion of the bonding surface between the first contact structure ST1 and the second contact structure ST2.

[0055] The first bonding insulating layer 450 may include an insulating material. The first bonding insulating layer 450 may include a material having an etching selectivity relative to the plurality of lower interlayer insulating layers 410, 420, and 430. Specifically, the first bonding insulating layer 450 may include a material having an etching selectivity relative to the third lower interlayer insulating layer 430 in contact with the first bonding insulating layer 450. For example, the first bonding insulating layer 450 may include silicon carbon nitride. However, example embodiments are not limited thereto, and the first bonding insulating layer 450 may be changed in various ways within a range of having an etching selectivity relative to the third lower interlayer insulating layer 430.

[0056] exist Figure 1 and Figure 2, two lower interlayer insulating layers are sequentially stacked between the first lower barrier layer LB1 and the second lower barrier layer LB2, but example embodiments are not limited thereto. For example, one lower interlayer insulating layer may be provided between the first lower barrier layer LB1 and the second lower barrier layer LB2. As another example, three or more lower interlayer insulating layers may be sequentially stacked between the first lower barrier layer LB1 and the second lower barrier layer LB2.

[0057] exist Figure 1 and Figure 2 , one lower interlayer insulating layer is shown to be located between the second lower barrier layer LB2 and the first bonding insulating layer 450 , but example embodiments are not limited thereto. For example, two or more lower interlayer insulating layers may be sequentially stacked between the second lower barrier layer LB2 and the first bonding insulating layer 450 .

[0058] In an implementation, the first contact pad 600 may be located within the first insulating structure 400 .

[0059] In more detail, the first contact pad 600 may penetrate at least a portion of the plurality of lower interlayer insulating layers 410, 420, and 430 and at least a portion of the plurality of lower barrier layers LB1 and LB2. For example, the first contact pad 600 may penetrate the third lower interlayer insulating layer 430 and the second lower barrier layer LB2, and be connected to the lower wiring LM1. However, example embodiments are not limited thereto, and the first contact pad 600 may be positioned to penetrate at least one of the lower interlayer insulating layers 410, 420, and 430. Alternatively, the first contact pad 600 may not penetrate the plurality of lower barrier layers LB1 and LB2. Hereinafter, as an example, an embodiment in which the first contact pad 600 penetrates the third lower interlayer insulating layer 430 and the second lower barrier layer LB2 will be described in detail.

[0060] The first contact pad 600 may be located between the lower wiring LM1 and the second contact structure ST2. The first contact pad 600 may be electrically connected to the lower wiring LM1. The first contact pad 600 may be electrically connected to the circuit element wiring PTM through the lower wiring LM1 and the lower contact path LC1. In addition, the first contact pad 600 may be bonded to the second contact pad 700 of the second contact structure ST2 by hybrid bonding. The first contact pad 600 may be bonded to the second contact pad 700 of the second contact structure ST2 in a direct contact state, and a metal bond may be formed.

[0061] Further references Figure 2, the first contact pad 600 may fill at least a portion of the contact recess PRS. The bottom surface of the contact recess PRS may be defined by the second lower interlayer insulating layer 420. The side surface of the contact recess PRS may be defined by the second lower barrier layer LB2, the third lower interlayer insulating layer 430, and the first bonding insulating layer 450. At this time, the first contact pad 600 may be conformally positioned along the inner sidewall of the contact recess PRS. In an embodiment, the first contact pad 600 may fill at least a portion of the space defined by the contact recess PRS. Therefore, the first contact pad 600 may include a void VD defined by the inner surface of the first contact pad 600. That is, the void VD may mean a portion of the first contact pad 600 that is not formed in the space defined by the contact recess PRS. The void VD will be described in detail later.

[0062] In an embodiment, the side surface of the first contact pad 600 may include a rounded shape. Therefore, the first contact pad 600 may include a portion whose width increases and then decreases along the horizontal direction (first direction (X direction) and / or second direction (Y direction)) as the distance from the bottom surface of the first bonding insulating layer 450 increases, but example embodiments are not limited thereto. This will be described in detail later when describing the second portion 620 of the first contact pad 600.

[0063] The first contact pad 600 may include a first conductive layer 600 a , a second conductive layer 600 b , and a third conductive layer 600 c sequentially located on the inner sidewall of the contact recess PRS.

[0064] The first conductive layer 600a may be conformally positioned along the inner sidewall of the contact recess PRS. The first conductive layer 600a may surround the second conductive layer 600b. The first conductive layer 600a may contact the first bonding insulating layer 450, the third lower interlayer insulating layer 430, and the second lower barrier layer LB2. The first conductive layer 600a may be located on the second lower interlayer insulating layer 420.

[0065] The second conductive layer 600b may be located inside the first conductive layer 600a. The second conductive layer 600b may be conformally positioned along the inner surface of the first conductive layer 600a. The second conductive layer 600b may surround the third conductive layer 600c. The second conductive layer 600b may be located between the first conductive layer 600a and the third conductive layer 600c. The second conductive layer 600b may contact the first conductive layer 600a and the third conductive layer 600c. In an embodiment, the second conductive layer 600b may be located on a portion of the first conductive layer 600a located on the second lower interlayer insulating layer 420. That is, the second conductive layer 600b may cover the upper surface of the first conductive layer 600a located on the first portion 610. The second conductive layer 600b may not be located on the bottom surface of the second bonding insulating layer of the second contact structure ST2. This may be due to the process characteristics of sequentially forming the first conductive layer 600a to the third conductive layer 600c in the contact recess PRS. The second conductive layer 600b may include a conductive material. For example, the second conductive layer 600b may include metal oxide, metal nitride, etc. For example, the second conductive layer 600b may include tantalum nitride, but example embodiments are not limited thereto.

[0066] The third conductive layer 600c may be located inside the second conductive layer 600b. The third conductive layer 600c may surround the void VD. The third conductive layer 600c may fill at least a portion of the contact recess PRS. For example, the third conductive layer 600c may fill at least a portion of the contact recess PRS so that the void VD is provided in the interior of the contact recess PRS (for example, at the center portion). The third conductive layer 600c may cover the upper surface of the second conductive layer 600b located on the first portion 610. In addition, the third conductive layer 600c may contact the second contact pad 700 of the second contact structure ST2. The third conductive layer 600c may include a conductive material. For example, the third conductive layer 600c may include copper, but example embodiments are not limited thereto.

[0067] In the embodiment, it is described that the first contact pad 600 includes the first conductive layer 600a to the third conductive layer 600c, but the example embodiment is not limited thereto. For example, the first contact pad 600 may be formed of two or fewer layers. Alternatively, the first contact pad 600 may be formed of four or more layers.

[0068] The first contact pad 600 of the semiconductor device according to the embodiment may include a first portion 610 penetrating the third lower interlayer insulating layer 430 , a second portion 620 including the void VD on the first portion 610 , and a third portion 630 on the second portion 620 .

[0069] The first portion 610 of the first contact pad 600 may be located on the second lower interlayer insulating layer 420. The first portion 610 may extend in the third direction (Z direction) and penetrate the second lower barrier layer LB2, and may pass through at least a portion of the third lower interlayer insulating layer 430. However, this is merely an example embodiment, and the first portion 610 may penetrate at least one layer of the plurality of lower interlayer insulating layers 410, 420, and 430, or may penetrate the plurality of lower barrier layers LB1 and LB2. Alternatively, the first portion 610 may not penetrate the plurality of lower barrier layers LB1, LB2. Alternatively, the first portion 610 may not penetrate the plurality of lower interlayer insulating layers 410, 420, and 430. This will be described later. Fig.10 Detailed description.

[0070] The side surface of the first part 610 may have a shape that is inclined relative to the upper surface of the circuit element wiring PTM, and at this time, the inclined surface may have an inverted cone shape. That is, the first width W1 of the first part 610 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may increase away from the upper surface of the circuit element wiring PTM. In other words, the first width W1 of the first part 610 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may decrease as the distance from the bottom surface of the first bonding insulating layer 450 increases.

[0071] In an embodiment, the first portion 610 may be electrically connected to the lower wiring LM1. For example, the bottom surface of the first conductive layer 600a located in the first portion 610 may contact the lower wiring LM1, and thus, the first portion 610 may be connected to the circuit element wiring PTM through the lower wiring LM1. At this time, the second conductive layer 600b may be positioned on the bottom surface of the third conductive layer 600c located on the first portion 610, and the first conductive layer 600a may be positioned on the bottom surface of the second conductive layer 600b located on the first portion 610. That is, the second conductive layer 600b may cover the bottom surface of the third conductive layer 600c located in the first portion 610, and the first conductive layer 600a may cover the bottom surface of the second conductive layer 600b located in the first portion 610.

[0072] The second portion 620 of the first contact pad 600 may be located on the first portion 610. The second portion 620 may be located within the third lower interlayer insulating layer 430. The second portion 620 may overlap the third lower interlayer insulating layer 430 in a horizontal direction (a first direction (X direction) and / or a second direction (Y direction)).

[0073] In an embodiment, the second portion 620 may be located between the first bonding insulating layer 450 and the second lower barrier layer LB2. That is, the second portion 620 may be located on the bottom surface of the first bonding insulating layer 450. For example, the upper surface 620_U of the second portion 620 may contact the bottom surface of the first bonding insulating layer 450, but example embodiments are not limited thereto. Therefore, the second portion 620 may not overlap the first bonding insulating layer 450 and the second lower barrier layer LB2 in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)).

[0074] In an embodiment, the second portion 620 may protrude in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) more than the first portion 610. For example, the second portion 620 may protrude from the outer surface of the first portion 610 in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). In addition, the second portion 620 may protrude from the outer surface of the third portion 630 in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). Therefore, the second width W2 between the two opposite outer surfaces 620_E of the second portion 620 in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be greater than the first width W1 of the first portion 610 in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). In addition, the second width W2 between the two opposite outer surfaces 620_E of the second part 620 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be greater than the third width W3 of the third part 630 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). Here, the second width W2 between the two opposite outer surfaces 620_E of the second part 620 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may represent the maximum width between the first outer surface 620_E1 and the second outer surface 620_E2 of the second part 620 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)), and the first outer surface 620_E1 and the second outer surface 620_E2 face each other along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)).

[0075] In an embodiment, the outer surface 620_E of the second portion 620 may include a rounded shape. Therefore, the second width W2 between the two opposite outer surfaces 620_E of the second portion 620 in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may increase and then decrease as the distance from the bottom surface of the first bonding insulation layer 450 increases. In addition, the inner surface 620_I of the second portion 620 may include a rounded shape. At this time, the curvature of the outer surface 620_E of the second portion 620 may be smaller than the curvature of the inner surface 620_I of the second portion 620. However, example embodiments are not limited thereto. For example, the outer surface 620_E and / or the inner surface 620_I of the second portion 620 may have a shape inclined relative to the upper surface of the circuit element wiring PTM, and at this time, the inclined surface may have an inverted cone shape. As another example, the outer surface 620_E and / or the inner surface 620_I of the second portion 620 may have a shape perpendicular to the upper surface of the circuit element wiring PTM. This will be referred to later Figure 8 and Fig. 9 Detailed description.

[0076] In an embodiment, the second portion 620 may include a void VD located in the center portion. The void VD may be buried in the interior of the third conductive layer 600c located in the second portion 620. The void VD may be defined by the inner surface 620_I of the second portion 620. That is, the void VD may be located between the first inner surface 620_I1 and the second inner surface 620_I2 of the second portion 620. This may be due to the process characteristics of the second portion 620 conformally forming the void VD from the inner sidewall of the contact recess PRS to fill at least a portion of the space defined by the contact recess PRS. At this time, as described above, the second width W2 between the two outer surfaces 620_E opposite to each other of the second portion 620 in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) is greater than the third width W3 of the third portion 630 in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)), and the void VD may be easily formed.

[0077] In an embodiment, when an annealing process is performed on the first contact pad 600, the void VD may provide a space that allows the first contact pad 600 to thermally expand. Specifically, when the first contact structure ST1 and the second contact structure ST2 of the semiconductor device according to the embodiment are bonded by hybrid bonding, an annealing process for bonding the first contact pad 600 and the second contact pad 700 may be performed. At this time, the first contact pad 600 and / or the second contact pad 700 may thermally expand. Since the second portion 620 of the semiconductor device according to the embodiment includes the void VD, when the annealing process is performed, the first contact pad 600 may thermally expand toward the inside of the void VD. That is, the void VD may provide a function of limiting and / or preventing the first contact pad 600 from thermally expanding from the upper surface of the first contact structure ST1.

[0078] In an embodiment, the thickness of the second portion 620 surrounding the void VD may be constant. For example, the thickness between the first outer surface 620_E1 and the first inner surface 620_I1 of the second portion 620 may be substantially the same as the thickness between the second outer surface 620_E2 and the second inner surface 620_I2 of the second portion 620. As another example, when the second portion 620 includes a lower portion connected to the first portion 610 to cover a lower region of the void VD and an upper portion connected to the third portion 630 to cover an upper region of the void VD, the thickness of the upper portion may be substantially the same as the thickness of the lower portion. This may be due to the process characteristics of conformally forming the second portion 620 within the contact recess PRS. However, example embodiments are not limited thereto, and the thickness of the upper portion may be thicker than the thickness of the lower portion. This will be described later with reference to Figure 4 Detailed description.

[0079] The third portion 630 may be located on the second portion 620. The third portion 630 may extend in the third direction (Z direction) and penetrate the first bonding insulating layer 450. The third portion 630 may overlap the first bonding insulating layer 450 in a horizontal direction (first direction (X direction) and / or second direction (Y direction)).

[0080] In an embodiment, the upper surface 630_U of the third portion 630 may configure a bonding surface between the first contact structure ST1 and the second contact structure ST2 together with the first bonding insulating layer 450. For example, the third portion 630 may be bonded to the second contact pad 700 of the second contact structure ST2, and the first bonding insulating layer 450 may be bonded to the second bonding insulating layer 350 of the second contact structure. At this time, the upper surface of the third portion 630 may be located at the same or substantially the same level as the upper surface of the first bonding insulating layer 450. That is, the upper surface of the third portion 630 and the upper surface of the first bonding insulating layer 450 may be located at substantially the same distance from the upper surface of the circuit element wiring PTM.

[0081] In an embodiment, the third width W3 of the third portion 630 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be greater than or equal to the first width W1 of the first portion 610 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). In addition, the third width W3 of the third portion 630 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be less than the second width W2 between two outer surfaces 620_E of the second portion 620 that are opposite to each other along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). Here, the second width W2 between two outer surfaces 620_E of the second portion 620 that are opposite to each other along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may represent the maximum width between the first outer surface 620_E1 and the second outer surface 620_E2 of the second portion 620 that face each other. Therefore, during the process of forming the first contact pad 600 , the void VD may be easily formed within the second portion 620 .

[0082] In an embodiment, the central axis of the third portion 630 and the central axis of the second portion 620 may be aligned. Here, the central axis of the third portion 630 may extend in the third direction (Z direction) and may represent an axis passing through the center of the third portion 630. In addition, the central axis of the second portion 620 may extend in the third direction (Z direction) and may represent an axis passing through the center of the second portion 620. This may be due to the fact that the third groove ( Fig.24 TR3 in the figure) to form an extension ( Fig.25 The process characteristics of EN).

[0083] In the embodiment, it is described that a single third portion 630 is located on the second portion 620, but example embodiments are not limited thereto. For example, a plurality of third portions 630 may be provided on the second portion 620. This will be referred to later. Figure 7 Detailed description.

[0084] Return to reference Figure 1 According to the embodiment, the second contact structure ST2 of the semiconductor device may include a second insulating structure 300 located on the first contact structure ST1, an upper contact via UC1 and an upper wiring UM1 penetrating at least a portion of the second insulating structure 300, and a second contact pad 700 electrically connecting the upper wiring UM1 and the first contact pad 600.

[0085] In an implementation, the second insulation structure 300 may include a second bonding insulation layer 350 on the first contact structure ST1 , a plurality of upper interlayer insulation layers 310 , 320 , and 330 on the second bonding insulation layer 350 , and a plurality of upper barrier layers UB.

[0086] The second bonding insulation layer 350 may be located on the first bonding insulation layer 450. The second bonding insulation layer 350 may contact the first bonding insulation layer 450.

[0087] In an embodiment, the bottom surface of the second bonding insulating layer 350 may configure a bonding surface where the first contact structure ST1 and the second contact structure ST2 are bonded. For example, the second bonding insulating layer 350 may be bonded to the first bonding insulating layer 450 by hybrid bonding. Therefore, the bottom surface of the second bonding insulating layer 350 may configure a portion of the bonding surface between the first contact structure ST1 and the second contact structure ST2.

[0088] The second bonding insulating layer 350 may include an insulating material. The second bonding insulating layer 350 may include the same material as the first bonding insulating layer 450. The second bonding insulating layer 350 may include a material having an etching selectivity relative to the plurality of upper interlayer insulating layers 310, 320, and 330, but example embodiments are not limited thereto. For example, the second bonding insulating layer 350 may include silicon carbon nitride, but example embodiments are not limited thereto.

[0089] In an embodiment, the plurality of upper barrier layers UB may include a first upper barrier layer UB1 and a second upper barrier layer UB2. The second upper barrier layer UB2 may be located on the second bonding insulating layer 350. The second upper barrier layer UB2 may be located to be spaced apart from the second bonding insulating layer 350 in a third direction (Z direction). The first upper barrier layer UB1 may be located on the second upper barrier layer UB2. The first upper barrier layer UB1 may be located to be spaced apart from the second upper barrier layer UB2 in a third direction (Z direction).

[0090] The plurality of upper barrier layers UB1 and UB2 may include an insulating material. The plurality of upper barrier layers UB1 and UB2 may include the same material as the plurality of lower barrier layers LB1 and LB2. For example, the plurality of upper barrier layers UB1 and UB2 may include silicon nitride. However, example embodiments are not limited thereto, and each of the plurality of upper barrier layers UB1 and UB2 may include at least one of silicon oxynitride and silicon carbon nitride. In the process of manufacturing the upper wiring UM1 and the upper contact via UC1, the plurality of upper barrier layers UB1 and UB2 may be used as a barrier to limit and / or prevent the material forming the upper wiring UM1 and the upper contact via UC1 from diffusing to the surroundings.

[0091] exist Figure 1 and Figure 2, the number of the plurality of upper barrier layers UB1 and UB2 is shown as 2, but example embodiments are not limited thereto. For example, the second insulating structure 300 may include one upper barrier layer. As another example, the second insulating structure 300 may include three or more upper barrier layers. As yet another example, the second insulating structure 300 may not include the plurality of upper barrier layers UB1 and UB2. This will be described later with reference to Fig.14 Detailed description.

[0092] The plurality of upper interlayer insulating layers 310, 320, and 330 of the semiconductor device according to the embodiment may include a first upper interlayer insulating layer 310, a second upper interlayer insulating layer 320, and a third upper interlayer insulating layer 330. In the embodiment, the upper contact via UC1 may be located in the first upper interlayer insulating layer 310, and the upper wiring UM1 may be located in the second upper interlayer insulating layer 320. However, this is merely an example, and the example embodiment is not limited thereto. For example, the upper contact via UC1 and the upper wiring UM1 may be located in one of the plurality of upper interlayer insulating layers 310, 320, and 330. The description of the plurality of upper interlayer insulating layers 310, 320, and 330 is substantially the same as the description of the plurality of lower interlayer insulating layers 410, 420, and 430 of the first insulating structure 400, and is not included herein.

[0093] In an embodiment, the upper wiring UM1 may be located within the second upper interlayer insulating layer 320. The upper contact via UC1 may penetrate the first upper barrier layer UB1 and the first upper interlayer insulating layer 310 and be connected to the upper wiring UM1. Therefore, the upper wiring UM1 may be electrically connected to an external element and / or device through the upper contact via UC1.

[0094] In an implementation, the second contact pad 700 may be located within the second insulating structure 300 .

[0095] In more detail, the second contact pad 700 may penetrate at least a portion of the plurality of upper interlayer insulating layers 310, 320, and 330 and at least a portion of the plurality of upper barrier layers UB1 and UB2. The second contact pad 700 may be located between the upper wiring UM1 and the first contact structure ST1. For example, the second contact pad 700 may extend in the third direction (Z direction), penetrate the third upper interlayer insulating layer 330 and the second upper barrier layer UB2, and be connected to the upper wiring UM1. However, example embodiments are not limited thereto, and the second contact pad 700 may be positioned to penetrate at least one of the plurality of upper interlayer insulating layers 310, 320, and 330. Alternatively, the second contact pad 700 may not penetrate the plurality of upper barrier layers UB1 and UB2. Hereinafter, as an example, an embodiment in which the second contact pad 700 penetrates the third upper interlayer insulating layer 330 and the second upper barrier layer UB2 will be described in detail.

[0096] In an embodiment, the second contact pad 700 can be bonded to the first contact pad 600 by hybrid bonding. The second contact pad 700 can be bonded to the first contact pad 600 in a direct contact state, and a metal bond can be formed. In addition, the second contact pad 700 can extend in a third direction (Z direction). In this way, the first contact pad 600 of the first contact structure ST1 and the second contact pad 700 of the second contact structure ST2 can be bonded, and an electrical connection path can be provided between the first contact structure ST1 and the second contact structure ST2. For example, an external element connected to the second contact structure ST2 can be electrically connected to a circuit element connected to the circuit element wiring PTM through the first contact pad 600 and the second contact pad 700.

[0097] The side surface of the second contact pad 700 may include a shape that is inclined relative to the upper surface of the circuit element wiring PTM. For example, a portion of the side surface of the second contact pad 700 may include a shape that is inclined relative to the upper surface of the circuit element wiring PTM, and at this time, the inclined surface may have a tapered shape. That is, the second contact pad 700 may include a portion whose width decreases along the horizontal direction (first direction (X direction) and / or second direction (Y direction)) as the distance from the upper surface of the circuit element wiring PTM increases. In other words, the width of a portion of the second contact pad 700 along the horizontal direction (first direction (X direction) and / or second direction (Y direction)) may decrease as the distance from the upper surface of the second bonding insulating layer 350 increases. However, example embodiments are not limited thereto, and the side surface of the second contact pad 700 may have a shape that is inclined relative to the upper surface of the circuit element wiring PTM, and at this time, the inclined surface may have an inverted tapered shape. As another example, the side surface of the second contact pad 700 may have a shape that is perpendicular to the upper surface of the circuit element wiring PTM.

[0098] In an embodiment, the second contact pad 700 may include a third conductive layer 700c, a second conductive layer 700b surrounding the third conductive layer 700c, and a first conductive layer 700a surrounding the second conductive layer 700b. The third conductive layer 700c may contact the third conductive layer 600c of the first contact pad 600. The second conductive layer 700b may contact the second conductive layer 600b of the first contact pad 600, but example embodiments are not limited thereto. For example, the second conductive layer 700b may contact the third conductive layer 600c of the first contact pad 600. The first conductive layer 700a may contact the first conductive layer 600a of the first contact pad 600, but example embodiments are not limited thereto. For example, the first conductive layer 700a may contact the third conductive layer 600c of the first contact pad 600. The first conductive layer 700a to the third conductive layer 700c may include the same material as the first conductive layer 600a to the third conductive layer 600c of the first contact pad 600.

[0099] In the embodiment, it is described that the second contact pad 700 includes the first conductive layer 700a to the third conductive layer 700c, but the example embodiment is not limited thereto. For example, the second contact pad 700 may be formed of two or fewer layers. Alternatively, the second contact pad 700 may be formed of four or more layers.

[0100] In an embodiment, the width of the second contact pad 700 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be greater than the width of the third portion 630 of the first contact pad 600 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). However, example embodiments are not limited thereto, and for example, the width of the second contact pad 700 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be substantially the same as the width of the third portion 630 of the first contact pad 600 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)).

[0101] Figure 1 It is shown that the number of contact structures of the semiconductor device according to the embodiments is 2, but example embodiments are not limited thereto. For example, the semiconductor device according to some embodiments may include three or more contact structures.

[0102] The first contact structure ST1 and the second contact structure ST2 of the semiconductor device according to the embodiment may be joined by hybrid joining. At this time, when the first contact pad 600 and the second contact pad 700 are joined by the annealing process, the first contact pad 600 and / or the second contact pad 700 may thermally expand. For example, the first contact pad 600 may thermally expand so as to protrude from the upper surface of the first contact structure ST1. Meanwhile, during the process of performing the annealing process, in order to limit and / or prevent the first contact structure ST1 and the second contact structure ST2 from being separated, a chemical mechanical polishing process for removing at least a portion of the first contact pad 600 and the second contact pad 700 may be additionally performed before joining the first contact structure ST1 and the second contact structure ST2.

[0103] The first contact pad 600 of the semiconductor device according to the embodiment may include a second portion 620 protruding in a horizontal direction (a first direction (X direction) and / or a second direction (Y direction)). For example, the second portion 620 of the first contact pad 600 may protrude from the third portion 630 in a horizontal direction (a first direction (X direction) and / or a second direction (Y direction)). In addition, the second portion 620 may be provided with a void VD in a central portion. The void VD may provide a space allowing the first contact pad 600 to expand. Therefore, when an annealing process is performed, the first contact pad 600 of the semiconductor device according to the embodiment may thermally expand into the void VD, and the first contact structure ST1 and the second contact structure ST2 may be restricted and / or prevented from being separated.

[0104] In addition, since the first contact pad 600 of the semiconductor device according to the embodiment can be thermally expanded into the void VD, even if the annealing process is performed, the first contact pad 600 may not protrude from the upper surface of the first contact structure ST1. Therefore, the chemical mechanical polishing process of removing at least a portion of the first contact pad 600 and the second contact pad 700 can be simplified or omitted. Therefore, the non-bonding of the first contact pad 600 and the second contact pad 700 due to an excessive chemical mechanical polishing process can be limited and / or prevented, and the reliability of the semiconductor device can be improved.

[0105] In the following, further reference is made to Figures 3 to 10 , the first contact pad 600 of the semiconductor device according to some embodiments will be described in detail.

[0106] Figures 3 to 10 is corresponding to Figure 1 A cross-sectional view of a region A1 of a semiconductor device according to some embodiments is shown.

[0107] according to Figures 3 to 10 The semiconductor device of the embodiment shown in FIG. 1 has many advantages over the semiconductor device according to the embodiment shown in FIG. Figure 1 and Figure 2 The semiconductor device of the embodiment shown in FIG. 1 is the same as the components of the semiconductor device of the embodiment shown in FIG. 2 , therefore, in the following description, the differences are focused on and redundant descriptions of the same components are omitted. In addition, the same reference numerals are used for the same elements as those in the above-mentioned embodiment. In the present embodiment, the shape of the first contact pad 600 is different from that in the above-mentioned embodiment, which will be described below.

[0108] Reference Figure 1 and Figures 3 to 10 , a semiconductor device according to some embodiments may include a circuit element wiring PTM, a first contact structure ST1 located on the circuit element wiring PTM, and a second contact structure ST2 located on the first contact structure ST1.

[0109] The first contact structure ST1 of the semiconductor device according to some embodiments may include a first insulating structure 400 located on the circuit element wiring PTM, a lower contact via LC1 and a lower wiring LM1 penetrating at least a portion of the first insulating structure 400, and a first contact pad 600 electrically connected to the lower wiring LM1. In addition, the first contact pad 600 may include a first portion 610 penetrating the third lower interlayer insulating layer 430, a second portion 620 including a void VD on the first portion 610, and a third portion located on the second portion 620.

[0110] Reference Figure 1 , Figure 3 and Figure 4 , the second portion 620 of the first contact pad 600 according to some embodiments may include portions having different thicknesses. For example, the thickness of the lower portion of the second portion 620 connected to the first portion 610 to cover the lower region of the gap VD may be less than the thickness of the upper portion of the second portion 620 connected to the third portion 630 to cover the upper region of the gap VD.

[0111] As an example, Figure 3 As shown, the second portion 620 of the first contact pad 600 may further include a protrusion pattern EP located in the upper portion of the second portion 620. The protrusion pattern EP may be located between the upper portion of the second portion 620 and the void VD. That is, the upper surface of the void VD may be defined by the protrusion pattern EP. The protrusion pattern EP may be a portion formed as the first contact pad 600 expands when an annealing process is performed on the first contact pad 600. When the annealing process is performed, the first contact pad 600 may thermally expand into the void VD and form the protrusion pattern EP. Therefore, the thickness of the lower portion of the second portion 620 connected to the first portion 610 to cover the lower region of the void VD may be thinner than the thickness of the upper portion of the second portion 620 connected to the third portion 630 to cover the upper region of the void VD.

[0112] As another example, refer to Figure 4 , a first thickness T1 of an upper portion of the second portion 620 connected to the third portion 630 to cover an upper region of the void VD may be thicker than a second thickness T2 of a lower portion of the second portion 620 connected to the first portion 610 to cover a lower region of the void VD. This may be due to process characteristics in a process of conformally forming the first contact pad 600 within the contact recess PRS, in which the upper portion of the second portion 620 is formed thicker than the lower portion of the second portion 620.

[0113] Reference Figure 1 and Figure 5 , the second portion 620 of the first contact pad 600 according to some embodiments may include a plurality of voids VD1 and VD2 .

[0114] Each of the plurality of voids VD1 and VD2 may be surrounded by the second portion 620. That is, each of the plurality of voids VD1 and VD2 may be defined by the inner surface of the second portion 620. Each of the plurality of voids VD1 and VD2 may be positioned adjacent in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). At this time, the second portion 620 may further include a portion extending from between the plurality of voids VD1 and VD2 to between the upper portion of the second portion 620 and the lower portion of the second portion 620.

[0115] Figure 5 The number of the plurality of voids VD1 and VD2 is shown to be 2, but example embodiments are not limited thereto. For example, the void VD located in the second portion 620 may be provided as a single number and may have a toroidal structure. As another example, 3 or more voids VD may be located in the second portion 620.

[0116] Reference Figure 1 and Figure 6 According to some embodiments, the central axis of the third portion 630 and the central axis of the first portion 610 may extend in parallel. That is, a first distance DD1 along the first direction (X direction) may be formed between the central axis of the third portion 630 and the central axis of the first portion 610. The first distance DD1 along the first direction (X direction) between the central axis of the third portion 630 and the central axis of the first portion 610 may be less than the second width W2 between the two outer surfaces 620_E of the second portion 620 that are opposite to each other along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). Here, the central axis of the third portion 630 may extend in the third direction (Z direction) and may represent an axis passing through the center of the third portion 630. In addition, the central axis of the first portion 610 may extend in the third direction (Z direction) and may represent an axis passing through the center of the first portion 610.

[0117] In some embodiments, the central axis of the third portion 630 and the central axis of the second portion 620 may be aligned. Therefore, the central axis of the second portion 620 and the central axis of the first portion 610 may extend in parallel. This may be due to the first portion 610 and the second groove ( Fig.23 Meanwhile, even in this case, since the first contact pad 600 connected to the circuit element wiring PTM can be formed by the extension portion EN, an alignment margin can be ensured.

[0118] Reference Figure 1 and Figure 7, the third portion 630 of the first contact pad 600 according to some embodiments may be provided in plural numbers.

[0119] In an embodiment, the third portion 630 may include a first pattern 631 and a second pattern 632. The first pattern 631 and the second pattern 632 may be positioned to be separated from each other. Figure 7 As shown, the first pattern 631 and the second pattern 632 may be positioned to be spaced apart in the second direction (Y direction). However, example embodiments are not limited thereto, and the first pattern 631 and the second pattern 632 may be positioned to be spaced apart in the first direction (X direction). That is, the first pattern 631 and the second pattern 632 may be positioned to be spaced apart in the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)).

[0120] In an embodiment, the sum of the fourth width W4 of the first pattern 631 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) and the fifth width W5 of the second pattern 632 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be smaller than the second width W2 between the two outer surfaces 620_E of the second portion 620 that are opposite to each other along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). That is, the fourth width W4 of the first pattern 631 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be smaller than the second width W2 between the two outer surfaces 620_E of the second portion 620 that are opposite to each other along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). The fifth width W5 of the second pattern 632 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be smaller than the second width W2 between the two outer surfaces 620_E of the second portion 620 that are opposite to each other along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). In addition, the sum of the fourth width W4 of the first pattern 631 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) and the fifth width W5 of the second pattern 632 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be greater than the first width W1 of the first portion 610 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)). Therefore, during the process of forming the first contact pad 600, the void VD may be easily formed within the second portion 620.

[0121] In an embodiment, each of the first pattern 631 and the second pattern 632 may penetrate the first bonding insulating layer 450. The first pattern 631 and the second pattern 632 may overlap with the first bonding insulating layer 450 in a horizontal direction (a first direction (X direction) and / or a second direction (Y direction)). An upper surface 631_U of the first pattern 631 and an upper surface 632_U of the second pattern 632 may configure a bonding surface between the first contact structure ST1 and the second contact structure ST2 together with the first bonding insulating layer 450. For example, the first pattern 631 and the second pattern 632 may be bonded to the second contact pad 700 of the second contact structure ST2. Therefore, the first pattern 631 and the second pattern 632 may be electrically connected to the second contact pad 700.

[0122] Reference Figure 1 , Figure 8 and Fig. 9 , the side surface 620_S of the second portion 620 according to some embodiments may include a flat portion.

[0123] First, refer to Figure 8 , according to some embodiments, the side surface 620_S of the second portion 620 may have a shape inclined relative to the upper surface of the circuit element wiring PTM, and at this time, the inclined surface may have an inverted cone shape. That is, the width of the second portion 620 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may increase away from the upper surface of the circuit element wiring PTM. In other words, the width of the second portion 620 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may decrease as the distance from the bottom surface of the first bonding insulation layer 450 increases. At this time, the angle formed by the side surface 620_S of the second portion 620 and the bottom surface 620_B of the second portion 620 may be 90 degrees or greater, but example embodiments are not limited thereto. Alternatively, referring to Fig. 9 , a side surface of the second portion 620 may have a shape perpendicular to an upper surface of the circuit element wiring PTM.

[0124] Reference Figure 1 and Fig.10 , a bottom surface 620_B of the second portion 620 according to some embodiments may contact the second lower barrier layer LB2.

[0125] In some embodiments, the first portion 610 may not penetrate the plurality of lower interlayer insulating layers 410, 420, and 430. That is, the first portion 610 may penetrate the second lower barrier layer LB2 and may completely overlap the second lower barrier layer LB2 in a horizontal direction (a first direction (X direction) and / or a second direction (Y direction)).

[0126] In some embodiments, the second portion 620 may be located within the third lower interlayer insulating layer 430. The second portion 620 may completely penetrate the third lower interlayer insulating layer 430. That is, a bottom surface 620_B of the second portion 620 may contact the second lower barrier layer LB2, and an upper surface 620_U of the second portion 620 may contact the first bonding insulating layer 450.

[0127] In the following, reference is made to Fig.11 and Fig.12 Semiconductor devices according to some embodiments are described in detail.

[0128] Fig.11 and Fig.12 is a cross-sectional view showing a semiconductor device according to some embodiments.

[0129] according to Fig.11 and Fig.12 The semiconductor device of the embodiment shown in FIG. 1 has many advantages over the semiconductor device according to the embodiment shown in FIG. Figure 1 and Figure 2 , therefore, in the following description, the differences are focused on and redundant descriptions of the same parts are omitted. In addition, the same reference numerals are used for the same elements as those in the above-described embodiment. In the present embodiment, the shape of the second contact pad 700 of the second contact structure ST2 is different from that in the above-described embodiment, which will be described below.

[0130] Reference Fig.11 and Fig.12 , a semiconductor device according to some embodiments may include a circuit element wiring PTM, a first contact structure ST1 located on the circuit element wiring PTM, and a second contact structure ST2 located on the first contact structure ST1.

[0131] The first contact structure ST1 of the semiconductor device according to some embodiments may include a first insulating structure 400 located on the circuit element wiring PTM, a lower contact via LC1 and a lower wiring LM1 penetrating at least a portion of the first insulating structure 400, and a first contact pad 600 electrically connected to the lower wiring LM1. In addition, the second contact structure ST2 of the semiconductor device according to some embodiments may include a second insulating structure 300 located on the first contact structure ST1, an upper contact via UC1 and an upper wiring UM1 penetrating at least a portion of the second insulating structure 300, and a second contact pad 700 electrically connecting the upper wiring UM1 and the first contact pad 600.

[0132] Reference Fig.11The second contact pad 700 may include a portion penetrating the second bonding insulating layer 350, a portion protruding from the portion penetrating the second bonding insulating layer 350 and including a second gap VDb therein, and a portion extending in a third direction (Z direction) and penetrating the second upper barrier layer UB2.

[0133] In some embodiments, the second contact pad 700 may have a shape symmetrical to the first contact pad 600 with respect to the bottom surface of the second bonding insulating layer 350. That is, the second contact pad 700 includes a second void VDb, and the second void VDb may have a shape symmetrical to the first void VDa of the first contact pad 600 with respect to the bottom surface of the second bonding insulating layer 350. The description of the second contact pad 700 is the same as that of Figure 1 and Figure 2 The description of the first contact pad 600 of the embodiment of FIG. 1 is basically the same and is not presented here again.

[0134] Reference Fig.12 In some embodiments, the side surface of the second contact pad 700 may have a shape inclined relative to the upper surface of the circuit element wiring PTM, and in this case, the inclined surface may have an inverted tapered shape. That is, the width of the second contact pad 700 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may decrease away from the upper surface of the circuit element wiring PTM. In other words, the width of the second contact pad 700 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may decrease away from the upper surface of the second bonding insulation layer 350.

[0135] In the following, reference will be made to Figures 13 to 16 Semiconductor devices according to some embodiments are described in detail.

[0136] Figures 13 to 15 is a cross-sectional view illustrating a semiconductor device according to some embodiments. Fig.16 yes Fig.15 An enlarged cross-sectional view of area A2.

[0137] according to Figures 13 to 16 The semiconductor device of the embodiment shown in FIG. 1 has many advantages over the semiconductor device according to the embodiment shown in FIG. Figure 1 and Figure 2 The semiconductor device of the embodiment shown in FIG. 1 is the same as the components of the semiconductor device of the embodiment shown in FIG. 2 , therefore, in the following description, the differences are focused on and redundant descriptions of the same components are omitted. In addition, the same reference numerals are used for the same elements as those in the above-mentioned embodiment. In the present embodiment, the configuration of the first contact structure ST1 is different from that in the above-mentioned embodiment, which will be described below.

[0138] Reference Figures 13 to 16, a semiconductor device according to some embodiments may include a circuit element wiring PTM, a first contact structure ST1 located on the circuit element wiring PTM, and a second contact structure ST2 located on the first contact structure ST1.

[0139] The first contact structure ST1 of the semiconductor device according to some embodiments may include a first insulating structure 400 located on the circuit element wiring PTM, a lower contact via LC1 and a lower wiring LM1 penetrating at least a portion of the first insulating structure 400, and a first contact pad 600 electrically connected to the lower wiring LM1. In addition, the second contact structure ST2 of the semiconductor device according to some embodiments may include a second insulating structure 300 located on the first contact structure ST1, an upper contact via UC1 and an upper wiring UM1 penetrating at least a portion of the second insulating structure 300, and a second contact pad 700 electrically connecting the upper wiring UM1 and the first contact pad 600.

[0140] In the above-described embodiment, the first insulating structure 400 may include a first bonding insulating layer 450 on the third lower interlayer insulating layer 430. An upper surface of the first bonding insulating layer 450 may constitute a bonding surface to which the first contact structure ST1 and the second contact structure ST2 are bonded.

[0141] However, in some embodiments, the first insulating structure 400 may not include at least one of the plurality of lower barrier layers LB1 and LB2, the plurality of lower interlayer insulating layers 410, 420, and 430, the first bonding insulating layer 450, the lower contact via LC1, and the lower wiring LM1. In addition, the second insulating structure 300 may not include at least one of the plurality of upper barrier layers UB1 and UB2, the plurality of upper interlayer insulating layers 310, 320, and 330, the second bonding insulating layer 350, the upper contact via UC1, and the upper wiring UM1.

[0142] For example, refer to Fig.13 , the first insulating structure 400 of the semiconductor device according to some embodiments may not include the first bonding insulating layer 450. In addition, the second insulating structure 300 may not include the second bonding insulating layer 350. That is, the first insulating structure 400 of the semiconductor device according to some embodiments may include a plurality of lower barrier layers LB1 and LB2 and a plurality of lower interlayer insulating layers 410, 420, and 430. In addition, the second insulating structure 300 may include a plurality of upper barrier layers UB1 and UB2 and a plurality of upper interlayer insulating layers 310, 320, and 330.

[0143] In some embodiments, the upper surface of the third lower interlayer insulating layer 430 and the bottom surface of the third upper interlayer insulating layer 330 may constitute a bonding surface where the first contact structure ST1 and the second contact structure ST2 are bonded. For example, the third lower interlayer insulating layer 430 may be bonded to the third upper interlayer insulating layer 330 to constitute a portion of the bonding surface between the first contact structure ST1 and the second contact structure ST2.

[0144] At this time, the third lower interlayer insulating layer 430 may include the same material as the third upper interlayer insulating layer 330. For example, the third lower interlayer insulating layer 430 and the third upper interlayer insulating layer 330 may include silicon carbon nitride. However, example embodiments are not limited thereto, and the third lower interlayer insulating layer 430 and the third upper interlayer insulating layer 330 may include at least one of silicon oxide, silicon oxynitride, and silicon carbon nitride.

[0145] As another example, refer to Fig.14 , the first contact structure ST1 of the semiconductor device according to some embodiments may not include the lower contact path LC1 and the lower wiring LM1. In addition, the second contact structure ST2 may not include the upper contact path UC1 and the upper wiring UM1. At this time, the first contact pad 600 may penetrate the third lower interlayer insulating layer 430 and the lower barrier layer LB and contact the circuit element wiring PTM.

[0146] As another example, refer to Fig.15 and Fig.16 , the first insulating structure 400 of the semiconductor device according to some embodiments may not include a plurality of lower barrier layers LB1 and LB2. In addition, the second insulating structure 300 may not include a plurality of upper barrier layers UB1 and UB2. That is, the first insulating structure 400 of the semiconductor device according to some embodiments may include a plurality of lower interlayer insulating layers 410, 420, and 430 and a first bonding insulating layer 450. In addition, the second insulating structure 300 may include a plurality of upper interlayer insulating layers 310, 320, and 330 and a second bonding insulating layer 350.

[0147] At this time, the first contact pad 600 may not include the first portion 610. That is, the first contact pad 600 may be located on the second lower interlayer insulating layer 420, and the second portion 620 may be located in the third lower interlayer insulating layer 430, and may include a third portion 630 penetrating the first bonding insulating layer 450. Fig.16 As shown, the second portion 620 may penetrate the third lower interlayer insulating layer 430 and be connected to the lower wiring LM1. That is, the bottom surface of the second portion 620 may contact the lower wiring. The remaining description of the second portion 620 and the third portion 630 of the first contact pad 600 is the same as that of the first contact pad 600. Figure 1 and Figure 2The description of the second portion 620 and the third portion 630 of the first contact pad 600 of the embodiment is substantially the same and is not presented here again.

[0148] In the following, reference will be made to Fig.17 Semiconductor devices according to some embodiments are described in detail.

[0149] Fig.17 is a cross-sectional view showing a semiconductor device according to some embodiments.

[0150] according to Fig.17 The semiconductor device of the embodiment shown in FIG. 1 has many advantages over the semiconductor device according to the embodiment shown in FIG. Figure 1 and Figure 2 The semiconductor device of the embodiment shown in FIG. 1 is the same as the components of the semiconductor device of the embodiment shown in FIG. 2 , therefore, in the following description, the differences are focused on and redundant descriptions of the same components are omitted. In addition, the same reference numerals are used for the same elements as those in the above-mentioned embodiment. In the present embodiment, the shape of the first contact pad 600 is different from that in the above-mentioned embodiment, which will be described below.

[0151] Reference Fig.17 , a semiconductor device according to some embodiments may include a circuit element wiring PTM, a first contact structure ST1 located on the circuit element wiring PTM, and a second contact structure ST2 located on the first contact structure ST1.

[0152] The first contact structure ST1 of the semiconductor device according to some embodiments may include a first insulating structure 400 located on the circuit element wiring PTM, a lower contact via LC1 and a lower wiring LM1 penetrating at least a portion of the first insulating structure 400, and a first contact pad 600 electrically connected to the lower wiring LM1. In addition, the second contact structure ST2 of the semiconductor device according to some embodiments may include a second insulating structure 300 located on the first contact structure ST1, an upper contact via UC1 and an upper wiring UM1 penetrating at least a portion of the second insulating structure 300, and a second contact pad 700 electrically connecting the upper wiring UM1 and the first contact pad 600.

[0153] In the above-described embodiment, the first contact pad 600 may include a first portion 610 penetrating the third lower interlayer insulating layer 430 , a second portion 620 including the void VD on the first portion 610 , and a third portion on the second portion 620 .

[0154] Reference Fig.17 , the first contact pad 600 of the semiconductor device according to some embodiments may not include the third portion 630. That is, may include the first portion 610 penetrating the third lower interlayer insulating layer 430 and the second portion 620 including the void VD on the first portion 610.

[0155] The first portion 610 of the first contact pad 600 may be located on the second lower interlayer insulating layer 420. The first portion 610 may extend in the third direction (Z direction) and penetrate the second lower barrier layer LB2, and may penetrate at least a portion of the third lower interlayer insulating layer 430. The description of the first portion 610 is the same as that of Figure 1 and Figure 2 The description of the first portion 610 of the first contact pad 600 of the embodiment is basically the same and is not presented here again.

[0156] In some embodiments, the second portion 620 of the first contact pad 600 may be located on the first portion 610. The second portion 620 may penetrate at least a portion of the first bonding insulating layer 450 and the third lower interlayer insulating layer 430. That is, the second portion 620 may be located between the second lower barrier layer LB2 and the second bonding insulating layer 350. That is, the second portion 620 may be located on the bottom surface of the second bonding insulating layer 350. For example, the upper surface of the second portion 620 may contact the bottom surface of the second bonding insulating layer 350, but example embodiments are not limited thereto.

[0157] In some embodiments, the second portion 620 may include a void VD located inside the contact recess PRS. The second portion 620 may surround at least a portion of the void VD. For example, the void VD may be located in an upper portion of the second portion 620, and a portion of an upper surface of the void VD may not be surrounded by the second portion 620. That is, the void VD may be defined by an inner surface of the second portion 620 and a bottom surface of the second contact pad 700. This may be due to the process characteristics for removing residues (e.g., sulfuric acid) within the void VD in the process of forming the first contact pad 600 including the void VD within the contact recess PRS.

[0158] In some embodiments, the upper surface of the second portion 620 may configure a bonding surface between the first contact structure ST1 and the second contact structure ST2 together with the first bonding insulating layer 450. For example, the second portion 620 may be bonded to the second contact pad 700, and the first bonding insulating layer 450 may be bonded to the second bonding insulating layer 350. At this time, the upper surface of the second portion 620 may be located at the same or substantially the same level as the upper surface of the first bonding insulating layer 450. That is, the upper surface of the second portion 620 and the upper surface of the first bonding insulating layer 450 may be located at substantially the same distance from the upper surface of the circuit element wiring PTM.

[0159] In the following, reference will be made to Figures 18 to 29 A method of manufacturing a semiconductor device according to an embodiment is described in detail.

[0160] Figures 18 to 29FIG. 1 is a diagram for explaining an intermediate operation of a method for manufacturing a semiconductor memory device according to an embodiment. Figure 1 to Figure 2 Description of those overlapping contents.

[0161] Reference Fig.18 , a first insulating structure 400 , a hard mask pattern HM, and first to third etch stop layers 801 , 802 , and 803 may be formed on the circuit element wiring PTM and the inter-wiring insulating layer 250 .

[0162] First, a first lower barrier layer LB1 may be formed on the circuit element wiring PTM and the inter-wiring insulating layer 250, and a first lower interlayer insulating layer 410 and a second lower interlayer insulating layer 420 may be formed on the first lower barrier layer LB1. Subsequently, a lower contact via LC1 penetrating the first lower interlayer insulating layer 410 may be formed, and a lower wiring LM1 penetrating the second lower interlayer insulating layer 420 may be formed. Subsequently, a second lower barrier layer LB2 may be formed on the second lower interlayer insulating layer 420 and the lower wiring LM1, and a third lower interlayer insulating layer 430 may be formed on the second lower barrier layer LB2.

[0163] In an embodiment, for example, the plurality of lower barrier layers LB1 and LB2 may include silicon nitride. However, example embodiments are not limited thereto, and each of the plurality of lower barrier layers LB1 and LB2 may include at least one of silicon oxynitride and silicon carbon nitride. In addition, in an embodiment, the plurality of lower interlayer insulating layers 410, 420, and 430 may include an insulating material. The plurality of lower interlayer insulating layers 410, 420, and 430 may include the same material, but example embodiments are not limited thereto. The plurality of lower interlayer insulating layers 410, 420, and 430 may include a material having an etching selectivity relative to the plurality of lower barrier layers LB1 and LB2. For example, the plurality of lower interlayer insulating layers 410, 420, and 430 may include silicon oxide. However, example embodiments are not limited thereto, and each of the plurality of lower interlayer insulating layers 410, 420, and 430 may include at least one of silicon oxynitride and silicon carbon nitride.

[0164] Subsequently, the first insulating structure 400 may be formed by forming a first bonding insulating layer 450 on the third lower interlayer insulating layer 430. The first bonding insulating layer 450 may include an insulating material. The first bonding insulating layer 450 may include a material having an etching selectivity relative to the plurality of lower interlayer insulating layers 410, 420, and 430. Specifically, the first bonding insulating layer 450 may include a material having an etching selectivity relative to the third lower interlayer insulating layer 430 in contact with the first bonding insulating layer 450. For example, the first bonding insulating layer 450 may include silicon carbon nitride. However, example embodiments are not limited thereto, and the first bonding insulating layer 450 may be changed in various ways within the range of having an etching selectivity relative to the third lower interlayer insulating layer 430.

[0165] Subsequently, a hard mask pattern HM may be formed on the first bonding insulation layer 450, and first to third etch stop layers 801, 802, and 803 may be formed on the hard mask pattern HM. The hard mask pattern HM may include at least one of silicon oxide, silicon oxynitride, and a spin-on hard mask (SOH). The first etch stop layer 801 and the third etch stop layer 803 may include silicon oxynitride. The second etch stop layer 802 may include a spin-on hard mask (SOH), but example embodiments are not limited thereto.

[0166] Reference Fig.19 , a first photoresist PR1 including a first opening OP1 may be formed on the third etch stop layer 803. The first photoresist PR1 may include a photosensitive material. At this time, the first opening OP1 of the first photoresist PR1 may overlap with the lower wiring LM1 in the third direction (Z direction).

[0167] Reference Fig. 20 At least a portion of the first to third etch stop layers 801 , 802 , and 803 and the first insulating structure 400 may be removed through a photolithography process using the first photoresist PR1 as a mask, thereby forming a first trench TR1 .

[0168] In more detail, the first to third etch stop layers 801, 802, and 803, the hard mask pattern HM, and the third lower interlayer insulating layer 430 exposed by the first opening OP1 may be removed to form a first trench TR1. The process of forming the first trench TR1 may be performed by using a dry etching process, but example embodiments are not limited thereto. The first trench TR1 may overlap the lower wiring LM1 in the third direction (Z direction). When the first trench TR1 is formed, the upper surface of the second lower barrier layer LB2 may be exposed. Subsequently, the first photoresist PR1, the third etch stop layer 803, and the second etch stop layer 802 may be removed to expose the first etch stop layer 801.

[0169] Reference Fig.21 , a fourth etch stop layer 804 and a fifth etch stop layer 805 may be sequentially formed on the first trench TR1 and the first etch stop layer 801. For example, the fourth etch stop layer 804 may include SOH. The fifth etch stop layer 805 may include silicon oxynitride. At this time, the fourth etch stop layer 804 may fill the inside of the first trench TR1.

[0170] Reference Fig. 22 , a second photoresist PR2 including a second opening OP2 may be formed on the fifth etch stop layer 805. The second photoresist PR2 may include a photosensitive material. The second opening OP2 may overlap with the first trench TR1 in the third direction (Z direction), or may partially overlap with the first trench TR1 in the third direction (Z direction) according to an embodiment. For example, as in Figure 1 and Figure 2 In the embodiment of the present invention, the second opening OP2 may overlap with the first trench TR1 in the third direction (Z direction). Figure 6 In the embodiment, when the first portion 610 and the third portion 630 of the first contact pad 600 are not aligned, the second opening OP2 and the first trench TR1 may partially overlap in the third direction (Z direction). At this time, the sixth width W6 of the second opening OP2 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be greater than or equal to the seventh width W7 of the first trench TR1 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)).

[0171] Reference Fig.23 , by a photolithography process using the second photoresist PR2 as a mask, the first etch stop layer 801, the fourth etch stop layer 804, the fifth etch stop layer 805, the hard mask pattern HM, and at least a portion of the first bonding insulation layer 450 may be removed, thereby forming a second trench TR2. Thereafter, the second photoresist PR2 and the fifth etch stop layer 805 may be removed, and through the second trench TR2, the sidewalls of the first etch stop layer 801, the sidewalls of the fourth etch stop layer 804, the sidewalls of the hard mask pattern HM, the sidewalls of the first bonding insulation layer 450, the upper surface of the third lower interlayer insulation layer 430, and the portion of the fourth etch stop layer 804 located within the first trench TR1 may be exposed.

[0172] Reference Fig.24 , at least a portion of the third lower interlayer insulating layer 430 may be removed, thereby forming a third trench TR3.

[0173] For example, according to the sidewall of the second trench TR2, at least a portion of the third lower interlayer insulating layer 430 may be removed to form the third trench TR3. Therefore, the sidewall of the third lower interlayer insulating layer 430 may be additionally exposed. Subsequently, the first etch stop layer 801 and the fourth etch stop layer 804 may be sequentially removed, and the portion located on the first etch stop layer 801. At this time, the portion of the fourth etch stop layer 804 located within the third trench TR3 may be removed together. Therefore, the hard mask pattern HM may be exposed.

[0174] Reference Fig.25 At least a portion of the third lower interlayer insulating layer 430 exposed by the third trench TR3 may be removed through an etch-back process, thereby forming an extension portion EN.

[0175] The process of removing at least a portion of the third lower interlayer insulating layer 430 exposed by the third trench TR3 may be performed by using an etchant having an etching selectivity with respect to the first bonding insulating layer 450, but example embodiments are not limited thereto. Therefore, even if at least a portion of the third lower interlayer insulating layer 430 is removed, the first bonding insulating layer 450 may not be removed. Therefore, the maximum width of the portion of the third trench TR3 in the first bonding insulating layer 450 along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)) may be smaller than the maximum width of the extension portion EN along the horizontal direction (the first direction (X direction) and / or the second direction (Y direction)).

[0176] Reference Fig.26 , at least a portion of the fourth etch stop layer 804 and the second lower barrier layer LB2 exposed by the third trench TR3 may be sequentially removed to form a fourth trench TR4.

[0177] First, the fourth etch stop layer 804 exposed by the third trench TR3 may be removed. Thus, the upper surface of the second lower barrier layer LB2 may be exposed. Subsequently, at least a portion of the exposed second lower barrier layer LB2 may be removed, thereby forming the fourth trench TR4. The process of removing at least a portion of the second lower barrier layer LB2 may be performed by using a dry etching or wet etching process, but example embodiments are not limited thereto. Thus, a portion of the upper surface of the lower wiring LM1 may be exposed.

[0178] Subsequently, the hard mask pattern HM may be removed to expose the first bonding insulation layer 450. In an embodiment, it is described that the hard mask pattern HM may be removed after the fourth etch stop layer 804 is removed, but example embodiments are not limited thereto. For example, the fourth etch stop layer 804 may be removed after the hard mask pattern HM is removed.

[0179] Reference Fig. 27, a first contact pad 600 may be formed in the fourth trench TR4.

[0180] First, the first and second conductive layers 600a and 600b may be conformally and sequentially formed on the upper surface of the fourth trench TR4 and the first bonding insulating layer 450. For example, the first conductive layer 600a may include tantalum and the second conductive layer 600b may include tantalum nitride, but example embodiments are not limited thereto.

[0181] Subsequently, a third conductive layer 600c may be formed on the upper surface of the second conductive layer 600b and on the inner surface of the second conductive layer 600b located within the fourth trench TR4. The third conductive layer 600c may fill at least a portion of the fourth trench TR4. For example, the third conductive layer 600c may fill at least a portion of the fourth trench TR4 along the inner surface of the second conductive layer 600b so that a void VD may be provided in the interior (e.g., the center portion) of the fourth trench TR4. The third conductive layer 600c may include a conductive material. For example, the third conductive layer 600c may include copper, but example embodiments are not limited thereto. Here, the fourth trench TR4 may correspond to Figure 2 The contact depression PRS.

[0182] Reference Fig.28 , at least a portion of the first to third conductive layers 600a to 600c may be removed by using a chemical mechanical polishing process, thereby forming the first contact pad 600. For example, a planarization process (e.g., CMP, chemical mechanical process) may be performed by using a chemical mechanical polishing process so that the upper surfaces of the first to third conductive layers 600a to 600c and the upper surface of the first bonding insulating layer 450 may be located on the same plane, thereby forming the first contact pad 600. At this time, the upper surface 600_U of the first contact pad 600 may be located at the same or substantially the same level as the upper surface 450_U of the first bonding insulating layer.

[0183] Reference Fig.29 , the second contact structure ST2 may be bonded to the first contact structure ST1.

[0184] First, the second contact structure ST2 may be located on the first contact structure ST1 so that the second bonding insulating layer 350 and the second contact pad 700 may contact the first bonding insulating layer 450 and the first contact pad 600, respectively. At this time, the interface between the first bonding insulating layer 450 and the second bonding insulating layer 350 and the interface between the first contact pad 600 and the second contact pad 700 may configure a bonding surface between the first contact structure ST1 and the second contact structure ST2. In an embodiment, a process of forming the second bonding insulating layer 350 of the second contact structure ST2, a plurality of upper interlayer insulating layers 310, 320 and 330 located on the second bonding insulating layer 350, and a plurality of upper barrier layers UB1 and UB2 is substantially the same as the process of forming the first contact structure ST1 and is not included herein.

[0185] Subsequently, the second bonding insulation layer 350 may be bonded to the first bonding insulation layer 450 by hybrid bonding. Thus, a bottom surface of the second bonding insulation layer 350 may configure a portion of a bonding surface between the first contact structure ST1 and the second contact structure ST2.

[0186] Subsequently, by using an annealing process, the first contact pad 600 and the second contact pad 700 may be bonded, thereby bonding the first contact structure ST1 and the second contact structure ST2.

[0187] For example, the second contact pad 700 may be bonded to the first contact pad 600 in a direct contact state, and a metal bond may be formed. Therefore, the first contact pad 600 and the second contact pad 700 may be bonded, and an electrical connection path may be provided between the first contact structure ST1 and the second contact structure ST2. For example, an external element connected to the second contact structure ST2 may be electrically connected to a circuit element connected to the circuit element wiring PTM through the first contact pad 600 and the second contact pad 700.

[0188] At this time, when the first contact pad 600 and the second contact pad 700 are bonded by the annealing process, the first contact pad 600 and / or the second contact pad 700 may thermally expand. The second portion 620 of the semiconductor device according to the embodiment may be provided with a void VD in the central portion. Therefore, when the annealing process is performed, the first contact pad 600 of the semiconductor device according to the embodiment may thermally expand into the void VD. That is, the void VD may provide a space allowing the first contact pad 600 to expand. Therefore, when the annealing process is performed, the first contact structure ST1 and the second contact structure ST2 may be restricted and / or prevented from being separated.

[0189] Since the first contact pad 600 of the semiconductor device according to the embodiment can be thermally expanded into the void VD, the first contact pad 600 may not protrude from the upper surface of the first contact structure ST1 even if the annealing process is performed. Therefore, the chemical mechanical polishing process of removing at least a portion of the first contact pad 600 and the second contact pad 700 can be simplified or omitted. Therefore, the non-bonding of the first contact pad 600 and the second contact pad 700 due to an excessive chemical mechanical polishing process can be limited and / or prevented, and the reliability of the semiconductor device can be improved.

[0190] In the following, reference is made to Figure 30 to Figure 35 , a method for manufacturing a semiconductor device according to some embodiments will be described in detail.

[0191] Figure 30 to Figure 35 FIG. 1 is a diagram for explaining an intermediate operation of a method for manufacturing a semiconductor device according to some embodiments. Figures 18 to 29 Description of the content that the description overlaps.

[0192] Reference Fig.30 , a first contact pad 600 may be formed in the fourth trench TR4.

[0193] First, the first conductive layer 600a and the second conductive layer 600b may be conformally and sequentially formed on the inner sidewall of the fourth trench TR4 and the upper surface of the first bonding insulating layer 450. Subsequently, the third conductive layer 600c may be formed on the upper surface of the second conductive layer 600b and the inner surface of the second conductive layer 600b located in the fourth trench TR4.

[0194] In some embodiments, the third conductive layer 600c may fill at least a portion of the fourth trench TR4. For example, the third conductive layer 600c may fill at least a portion of the fourth trench TR4 along the inner surface of the second conductive layer 600b so that the void VD may be provided in the interior (e.g., the center portion) of the fourth trench TR4. The third conductive layer 600c may include a conductive material. For example, the third conductive layer 600c may include copper, but example embodiments are not limited thereto.

[0195] At this time, during the process of forming the third conductive layer 600c, a residue RM may be formed in the void VD. For example, the residue RM may include sulfuric acid, but example embodiments are not limited thereto. The residue RM may completely fill the void VD, but example embodiments are not limited thereto, and may fill at least a portion of the void VD.

[0196] Reference Fig.31, at least a portion of the first to third conductive layers 600a to 600c, the hard mask pattern HM, the first bonding insulating layer 450, and at least a portion of the third lower interlayer insulating layer 430 may be removed so that the residue RM may be exposed. The process of removing at least a portion of the first to third conductive layers 600a to 600c, the hard mask pattern HM, the first bonding insulating layer 450, and at least a portion of the third lower interlayer insulating layer 430 may be performed by using a chemical mechanical polishing process, but example embodiments are not limited thereto.

[0197] Reference Fig.32 , the exposed residue RM may be removed to expose the void VD. Thus, the inner surface of the third conductive layer 600c may be exposed. Meanwhile, the hole HH of the void VD exposed at substantially the same level as the upper surface of the third lower interlayer insulating layer 430 may have a sufficiently small size.

[0198] Reference Fig.33 , at least a portion of the third lower interlayer insulating layer 430 may be removed. For example, a process of removing at least a portion of the third lower interlayer insulating layer 430 may be performed by using a material having an etching selectivity relative to the first contact pad 600. Therefore, the first contact pad 600 may not be etched. At this time, the upper surface of the first contact pad 600 may be located at a higher level than the upper surface of the third lower interlayer insulating layer 430.

[0199] Reference Fig.34 and Fig.35 , a first bonding insulating layer 450 may be formed on an upper surface of the third lower interlayer insulating layer 430 .

[0200] First, the first bonding insulating layer 450 may be formed on the upper surface of the third lower interlayer insulating layer 430 and the upper surface of the first contact pad 600. The first bonding insulating layer 450 may be formed to a sufficient thickness to cover the upper surface of the third lower interlayer insulating layer 430 and the upper surface of the first contact pad 600. At this time, since the hole HH of the exposed void VD has a sufficiently small size, a material layer constituting the first bonding insulating layer 450 may not be formed within the void VD. However, example embodiments are not limited thereto, and a material layer configuring the first bonding insulating layer 450 may be formed together within the void VD through the hole HH of the exposed void VD.

[0201] Subsequently, by performing a chemical mechanical polishing process, at least a portion of the first bonding insulating layer 450 may be removed. For example, by performing a chemical mechanical polishing process, at least a portion of the first bonding insulating layer 450 may be removed so that the first contact pad 600 may be exposed. Therefore, the hole HH of the void VD may be exposed together.

[0202] Subsequently, a second contact structure ST2 may be formed on the first contact structure ST1 to form a Fig.17 A semiconductor device according to an embodiment of the present invention.

[0203] In the following, reference will be made to Figure 36 to Figure 39 A semiconductor device according to an embodiment is described in detail.

[0204] Fig.36 is a plan view schematically showing a semiconductor device according to an embodiment. Fig.37 is a cross-sectional view schematically showing a semiconductor device according to an embodiment. Fig.38 is a cross-sectional view showing a channel structure of a semiconductor device according to an embodiment. Fig.39 is a cross-sectional view showing a channel structure of a semiconductor device according to some embodiments.

[0205] exist Figure 36 to Figure 39 In the implementation mode, it can be applied Figures 1 to 17 The first contact structure ST1 and the second contact structure ST2 are connected to each other.

[0206] First, refer to Fig.36 and Fig.37 , a semiconductor device according to an embodiment may include a cell structure CELL provided with a memory cell structure and a peripheral structure PERI provided with a peripheral circuit structure for controlling the operation of the memory cell structure. At this time, the cell structure CELL and the peripheral structure PERI may be a bonded semiconductor device of a chip-to-chip (C2C) structure bonded by a wafer bonding method (e.g., hybrid bonding). For example, the peripheral structure PERI and the cell structure CELL may be respectively bonded to Fig.40 The first structure 1100F and the second structure 1100S of the semiconductor device 1100 included in the electronic system 1000 shown in FIG. 1 may be a portion corresponding to the first structure 1100F and the second structure 1100S of the semiconductor device 1100 included in the electronic system 1000 shown in FIG. 1100F and the second structure 1100S of the semiconductor device 1100 included in the electronic system 1000 Fig.42 4. Portions of a first structure 4100 and a second structure 4200 of a semiconductor chip 2200 are shown in FIG.

[0207] Here, the peripheral structure PERI may include a peripheral circuit structure formed on the first substrate 200, and the cell structure CELL may be provided with a gate stack structure 120 and a channel structure CH formed in the cell array region CAR as a memory cell structure. An insulating layer 240 may be between the lower structure LS and the first substrate 200. The insulating layer 240 may also cover the circuit element PTR.

[0208] In an embodiment, the peripheral structure PERI may correspond to Figures 1 to 17 The first contact structure ST1 of the embodiment, and the cell structure CELL may correspond to Figures 1 to 17 That is, a chip-to-chip (C2C) structure of bonding the peripheral structure PERI and the cell structure CELL by a wafer bonding method (eg, hybrid bonding) may be substantially the same as a bonding structure between the first contact structure ST1 and the second contact structure ST2.

[0209] In an embodiment, the cell structure CELL may be located on the peripheral structure PERI. Accordingly, since an area corresponding to the peripheral structure PERI may not be ensured separately from the cell structure CELL, the area of ​​the semiconductor device may be reduced. However, example embodiments are not limited thereto, and many variations are available.

[0210] A semiconductor device according to an embodiment may include a cell array region CAR and an extension region EXT.

[0211] A memory cell array including a plurality of memory cells may be formed on the cell array region CAR. For example, the channel structure CH, a plurality of gate electrodes 130, a bit line BL, etc. described later may be located in the cell array region CAR. In the following description, the surface of the second substrate 100 on which the memory cell array is disposed may be referred to as the first surface or the front side. Conversely, the surface of the second substrate 100 opposite to the front surface of the second substrate 100 may be referred to as the second surface or the back side of the second substrate 100. That is, the first surface of the second substrate 100 may be the surface facing the peripheral structure PERI, and the second surface of the second substrate 100 may be the surface facing away from the first surface of the second substrate 100.

[0212] The extension region EXT may be defined around the cell array region CAR. For example, in a top view, the extension region EXT may surround the cell array region CAR. In the extension region EXT, a structure or wiring for connecting the gate stack structure 120 and / or the channel structure CH located in the cell array region CAR to the peripheral structure PERI or an external circuit may be positioned. In addition, in the extension region EXT, a source contact 186, an input / output contact 188, etc. may be positioned, which will be described later.

[0213] The cell structure CELL according to an embodiment may include a second substrate 100 , a gate stack structure 120 , a channel structure CH, a channel pad 144 , a separation structure 146 , a cell wiring portion 180 , and a second insulating structure 300 .

[0214] The second substrate 100 may include a common source plate 101 and an insulating pattern 102. The common source plate 101 may be provided in a portion of the extension region EXT and the cell array region CAR. The common source plate 101 may be connected to the channel structure CH and the source contact 186. For example, the common source plate 101 may be connected to the channel layer 140 of the channel structure CH in the cell array region CAR. The common source plate 101 may be connected to the source contact 186 in the extension region EXT. The common source plate 101 may be provided as a common source line (e.g., Fig.40 The common source plate 101 may include, for example, polysilicon or a metal doped with impurities, but example embodiments are not limited thereto.

[0215] In an implementation, the common source plate 101 may not overlap the gate contact 184 and the input / output contact 188 in the third direction (Z direction).

[0216] The insulating pattern 102 may be provided in a portion of the extension region EXT. The insulating pattern 102 may not be provided in the cell array region CAR. The insulating pattern 102 may be located around the common source plate 101. For example, the insulating pattern 102 may be located between the common source plate 101 and the common source plate 101. The insulating pattern 102 may surround a portion of the gate contact 184 and a portion of the input / output contact 188. The insulating pattern 102 may overlap the gate contact 184 and the input / output contact 188 in the third direction (Z direction).

[0217] The insulating pattern 102 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, but example embodiments are not limited thereto. Specifically, the insulating pattern 102 may include, for example, flowable oxide (Fox), TOSZ (Tonen Silazen), USG (undoped silica glass), BSG (borosilica glass), PSG (PhosphoSilica glass), BPSG (BoroPhosphossilica glass), PE-TEOS (Plasma Enhanced Tetraethyl Orthosilicate), FSG (Fluoride Silicate Glass), High Density Plasma (HDP), PEOX (Plasma Enhanced Oxide), FCVD (Flowable CVD), or a combination thereof.

[0218] Fig.37 It is shown that the lower surface of the insulating pattern 102 is positioned as a surface coplanar with the lower surface of the common source plate 101 , but this is only an example. As another example, the lower surface of the insulating pattern 102 may be lower than the lower surface of the common source plate 101 .

[0219] The second substrate 100 may include a front side and a rear side facing each other. The front side of the second substrate 100 may face the peripheral structure PERI. Here, the front side of the common source plate 101 and the front side of the insulating pattern 102 may be the front side of the second substrate 100. The rear side of the common source plate 101 and the rear side of the insulating pattern 102 may be the rear side of the second substrate 100.

[0220] The gate stack structure 120 may be located on the front side of the second substrate 100. The gate stack structure 120 may include a plurality of unit insulating layers 132 and a plurality of gate electrodes 130 alternately stacked with each other.

[0221] In the gate stack structure 120, the unit insulating layer 132 may include an interlayer insulating layer 132m located between two adjacent gate electrodes 130 and a pad insulating portion 132i located below the gate stack structure 120. In addition, the unit insulating layer 132 may include a plurality of lower unit insulating layers 132a, 132b, and 132c covering the bottom surface of each of the plurality of gate stack structures 120a, 120b, and 120c. To simplify the description, Fig.37 It is shown that the cell insulating layer 132 is provided as a cell insulating layer without a boundary in the extension region EXT However, the cell insulating layer 132 located in the extension region EXT may have various structures including one or more insulating layers, and example embodiments are not limited thereto.

[0222] In an embodiment, the gate electrode 130 and the interlayer insulating layer 132m of the gate stack structure 120 may extend in a first direction (X direction) and / or a second direction (Y direction). For example, in a direction away from the cell array area CAR, the length of the plurality of gate electrodes 130 may include a step shape sequentially extended toward the second substrate 100. At this time, the plurality of gate electrodes 130 may include a portion having a step shape in one direction or in multiple directions. Therefore, some gate electrodes 130 may extend at different lengths to form steps, and each bottom surface of the gate electrode 130 may include a pad portion PP in contact with the pad insulating portion 132i. The pad portion PP may refer to an area where the gate contact 184 and the gate electrode 130 contact each other.

[0223] A height of the gate electrode 130 in contact with the gate contact 184 in the pad portion PP in the third direction (Z direction) may be higher than another height of the gate electrode 130 in the third direction (Z direction). Here, the third direction (Z direction) may be a direction perpendicular to the front side of the second substrate 100. Therefore, a contact area in which the gate contact 184 and the gate electrode 130 contact each other may be increased, but example embodiments are not limited thereto.

[0224] The gate electrode 130 may include various conductive materials. For example, the gate electrode 130 may include a metal material (such as tungsten (W), copper (Cu), aluminum (Al), etc.), polysilicon, a metal nitride (for example, titanium nitride (TiN), tantalum nitride (TaN), etc.), or a combination thereof. In an embodiment, an insulating material may be further located outside the gate electrode 130. The cell insulating layer 132 may include various insulating materials. For example, the cell insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a lower dielectric constant than silicon oxide, or a combination thereof.

[0225] The channel structure CH may be located within the gate stack structure 120 of the cell array region CAR. The channel structure CH may penetrate the gate stack structure 120 and extend in a cross direction (e.g., a third direction (Z direction)) that crosses (e.g., vertically) the second substrate 100. The channel structure CH may have a columnar shape. For example, the channel structure CH may have an inclined side surface, and when viewed in a cross section, the width of the inclined side surface becomes narrower as it gets closer to the second substrate 100, depending on the aspect ratio. However, example embodiments are not limited thereto, and the structure, shape, etc. of the channel structure CH may be modified in various ways.

[0226] The channel structures CH may respectively form a memory cell string, and in a top view, a plurality of channel structures CH may be positioned to be separated from each other while forming rows and columns. For example, in a top view, a plurality of channel structures CH may be positioned in various forms such as a lattice form or a zigzag form. However, example embodiments are not limited thereto, and the arrangement, shape, etc. of the channel structures CH may be modified in various ways.

[0227] Further references Fig.38 , the channel structure CH may include a gate dielectric layer 150 located on the channel layer 140 between the channel layer 140 and the gate electrode 130, and the channel layer 140. The channel structure CH may also include a core insulating layer 142 located in an inner portion (e.g., a central region) of the channel layer 140, but as a different example, the core insulating layer 142 may not be provided.

[0228] The gate dielectric layer 150 may include a tunneling layer 152, a charge storage layer 154, and a barrier layer 156, which are sequentially formed on the channel layer 140. In an implementation, the channel structure CH may further include a channel pad 144 connected to the channel layer 140.

[0229] The channel layer 140 may include a semiconductor material, such as polysilicon. The core insulating layer 142 may include various insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The tunneling layer 152 may include an insulating material capable of achieving charge tunneling. For example, the tunneling layer 152 may include silicon oxide, silicon oxynitride, or the like. The charge storage layer 154 may be used as a data storage area and may include polysilicon, silicon nitride, or the like. The barrier layer 156 may include an insulating material capable of limiting and / or preventing charges from undesirably flowing into the gate electrode 130. For example, the barrier layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0230] However, materials, stack structures, etc. of the channel layer 140 , the core insulating layer 142 , and the gate dielectric layer 150 may be modified in various ways, and example embodiments are not limited thereto.

[0231] In an embodiment, if Fig.38 As shown, the channel structure CH may include a portion protruding toward the rear side of the second substrate 100 than the first surface of the gate stack structure 120. That is, the first end of the channel structure CH may be located between the front side and the rear side of the common source plate 101. At this time, the portion of the gate dielectric layer 150 located at the first end of the channel structure CH may be removed. The upper surface of the gate dielectric layer 150 may contact the bottom surface of the common source plate 101. The upper surface of the channel layer 140 and / or the core insulating layer 142 may be located between the front side and the rear side of the common source plate 101. Therefore, the channel layer 140 may be connected to the common source plate 101 on the cell array region CAR. The upper surface of the channel layer 140 may be located between the front side and the rear side of the second substrate 100. That is, a portion of the channel layer 140 may be provided in the common source plate 101. The upper surface of the channel layer 140 may contact the common source plate 101.

[0232] However, example embodiments are not limited thereto, and Fig.39 As shown in FIG. 1 , the channel layer 140 may be connected to the horizontal conductive layers 112 and 114 . Specifically, in an embodiment, the cell array region CAR may further include the horizontal conductive layers 112 and 114 between the second substrate 100 and the gate stack structure 120 .

[0233] Horizontal conductive layers 112 and 114 may be connected to channel structure CH and used as a common source line. For example, horizontal conductive layers 112 and 114 may be (eg, directly) connected to channel layer 140 of channel structure CH. At this time, horizontal conductive layers 112 and 114 may be electrically connected to source contact 186.

[0234] The first horizontal conductive layer 112 and the second horizontal conductive layer 114 may include a semiconductor material (e.g., polysilicon). For example, the first horizontal conductive layer 112 may be a polysilicon layer doped with impurities, and the second horizontal conductive layer 114 may be a polysilicon layer doped with impurities or a layer including impurities diffused from the first horizontal conductive layer 112. However, example embodiments are not limited thereto, and the second horizontal conductive layer 114 may be formed of an insulating material. Alternatively, the second horizontal conductive layer 114 may not be provided separately.

[0235] The channel pad 144 may be connected on the bottom surface of the channel structure CH. For example, the channel pad 144 may be located on the bottom surface of the core insulating layer 142 and may be positioned to be connected to the channel layer 140. The channel pad 144 may include a conductive material, polysilicon doped with, for example, impurities, but example embodiments are not limited thereto.

[0236] In an embodiment, the gate stack structure 120 may include a plurality of gate stack structures 120a, 120b, and 120c sequentially stacked on the bottom surface of the second substrate 100, and the channel structure CH may include a plurality of channel structures CH1, CH2, and CH3 penetrating the plurality of gate stack structures 120a, 120b, and 120c. Then, since the number of stacked gate electrodes 130 can be increased, the number of memory cells can be increased with a stable structure. Although the drawings show that the gate stack structure 120 is provided in the number of three, the example embodiments are not limited thereto. Therefore, the gate stack structure 120 may be formed of one or two gate stack structures, and may include four or more gate stack structures.

[0237] In addition, the plurality of channel structures CH1, CH2, and CH3 forming one channel structure CH may also have a form of being connected to each other. Each of the plurality of channel structures CH1, CH2, and CH3 may have an inclined side surface whose width becomes narrower as it is closer to the second substrate 100 depending on the aspect ratio when viewed in cross section. In addition, as Fig.38 As shown, a bent portion may be provided in a portion where the first channel structure CH1 and the second channel structure CH2 are connected according to the width difference. As another example, the plurality of channel structures CH1, CH2, and CH3 may be provided with inclined side surfaces that continuously extend without a bent portion.

[0238] Fig.37 and Fig.38An overall structure is shown in which the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel structures CH1, CH2, and CH3 are continuous with each other. However, example embodiments are not limited thereto, and the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the plurality of channel structures CH1, CH2, and CH3 may be formed separately and then electrically connected to each other. In addition, a separate channel pad may be additionally provided to the connection portions of the plurality of channel structures CH1, CH2, and CH3. In this way, the embodiment is not limited to the shape of the plurality of channel structures CH1, CH2, and CH3.

[0239] Return to reference Fig.37 In an embodiment, the separation structure 146 may penetrate the gate stack structure 120. The separation structure 146 may extend in a direction (e.g., a third direction (Z direction)) that intersects (e.g., is perpendicular) to the second substrate 100. Therefore, in a top view, the gate stack structure 120 may be divided into a plurality of numbers by the separation structure 146. For example, the separation structure 146 is shown as having an inclined side surface, and when viewed in a cross-section, the width of the inclined side surface gradually decreases toward the second substrate 100 due to the high aspect ratio, but the example embodiments are not limited thereto. The side surface of the separation structure 146 may be perpendicular to the second substrate 100, or a curved portion may be provided at a connection portion of the plurality of gate stack structures 120a, 120b, and 120c.

[0240] The semiconductor device according to the embodiment may further include an upper separation region penetrating at least a portion of the gate stack structure 120. In a top view, the separation structure 146 and / or the upper separation region may extend in a first direction (X direction) and may be spaced apart from each other at a desired and / or alternatively predetermined interval in a second direction (Y direction) intersecting therewith. The separation structure 146 and / or the upper separation region may be provided in a plurality of quantities, but example embodiments are not limited thereto.

[0241] The separation structure 146 or the upper separation region may be filled with various insulating materials. For example, the separation structure 146 or the upper separation region may also include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. As another example, the separation structure 146 may also include a semiconductor material, a metal material, etc. In this case, the separation structure 146 may also include a spacer layer including an insulating material and a portion formed on the spacer layer and including a semiconductor material, a metal material, etc. However, the example embodiments are not limited thereto, and the structure, shape, material, etc. of the separation structure 146 or the upper separation region may be modified in various ways.

[0242] In order to connect the gate stack structure 120 and / or the channel structure CH provided in the cell array region CAR to the peripheral structure PERI or an external circuit, a cell wiring portion 180 may be provided in the cell structure CELL.

[0243] Here, the cell wiring portion 180 may include all components that electrically connect the gate electrode 130, the channel structure CH, etc. to the peripheral structure PERI or an external circuit. For example, the cell wiring portion 180 may include a bit line BL, a gate contact 184, an input / output pad IO_PAD, an input / output contact 188, and a contact path 180a connected thereto, respectively. Depending on the embodiment, a connection line 190 connected to the bit line BL, the gate contact 184, and / or the input / output contact 188 may also be included.

[0244] In more detail, the bit line BL may be positioned on the bottom surface of the cell insulating layer 132 of the gate stack structure 120 located in the cell array region CAR. The bit line BL may extend in a direction intersecting the direction in which the gate electrode 130 extends. The bit line BL may be electrically connected to the channel structure CH (e.g., the channel pad 144) through the contact path 180a.

[0245] A member for connecting the gate electrode 130 and the peripheral structure PERI may be provided in the extension region EXT.

[0246] In more detail, the gate contact 184 may be provided in the extension region EXT. The gate contact 184 may extend in the third direction (Z direction) in the extension region EXT and penetrate the cell insulating layer 132 and the mold structure. The gate contact 184 may be connected to one of the plurality of gate electrodes 130 stacked in a step shape in the extension region EXT. For example, the gate contact 184 may contact the sidewall of the connection gate electrode 130c including the pad portion PP. At this time, the pad portion PP of the connection gate electrode 130c may contact the pad insulating portion 132i. For better understanding and ease of description, Fig.37 It is illustrated that the number of gate contacts 184 is eight, but example embodiments are not limited thereto.

[0247] In some embodiments, the upper surface of the gate contact 184 may be located within the insulating pattern 102. That is, the upper surface of the gate contact 184 may be provided between the front side and the back side of the insulating pattern 102. The gate contact 184 may not overlap with the common source plate 101 in the third direction (Z direction). The gate contact 184 may not completely penetrate the second substrate 100. The gate contact 184 may include a conductive material. The gate contact 184 may include, for example, a metal such as copper (Cu), tungsten (W), cobalt (Co), or nickel (Ni), but the type of metal is not limited thereto.

[0248] An insulating ring 184i may be provided within the gate stack structure 120. The insulating ring 184i may be interposed between the gate contact 184 and each of the plurality of gate electrodes 130. The insulating ring 184i may electrically separate the other gate electrodes except the gate electrode 130 including the pad portion PP from the gate contact 184. For example, the insulating ring 184i may restrict and / or prevent the remaining gate electrodes except the connection gate electrode 130c connected to the gate contact 184 from contacting the gate contact 184. For example, the insulating ring 184i may be a ring-shaped structure surrounding the gate contact 184.

[0249] The insulating ring 184i may include an insulating material. The insulating ring 184i may include, for example, an oxide-based insulating material. For example, the insulating ring 184i may include silicon oxide, but example embodiments are not limited thereto.

[0250] The drawings show that the gate contact 184 penetrates the plurality of gate electrodes 130, is electrically connected to one connection gate electrode 130c, and is positioned to be spaced apart from the remaining gate electrodes 130 by the insulation ring 184i. However, example embodiments are not limited thereto, and the gate contact 184 may not penetrate the gate electrode 130 to connect the gate electrode 130 and the connection line 190, but may contact the bottom surface of the gate electrode 130.

[0251] A source contact 186 may be provided in the extension region EXT. The source contact 186 may be formed of a conductive material such as a metal, a metal compound, or polysilicon, and may be electrically connected to the common source plate 101. The source contact 186 may be electrically connected to the bit line BL through a connection line 190. The connection line 190 may include a conductive material. The connection line 190 may include, for example, tungsten (W) or copper (Cu), but example embodiments are not limited thereto.

[0252] In an embodiment, an upper surface of the source contact 186 may be provided between the front side and the back side of the second substrate 100. The source contact 186 may overlap the common source plate 101 in the third direction (Z direction). The source contact 186 may not overlap the insulating pattern 102 in the third direction (Z direction). The source contact 186 does not completely penetrate the common source plate 101.

[0253] The input / output contact 188 may penetrate the unit insulating layer 132 and be connected to the input / output pad IO_PAD described later. The input / output contact 188 may be provided in the extension region EXT. In an embodiment, the common source plate 101 may not be located in the region where the input / output contact 188 is located. The insulating pattern 102 may be located in the region where the input / output contact 188 is provided. The input / output contact 188 may overlap with the insulating pattern 102 in the third direction (Z direction).

[0254] In addition, the input / output contact 188 may not overlap with the plurality of gate electrodes 130 in the third direction (Z direction). The input / output contact 188 may be electrically connected to the bit line BL through the connection line 190.

[0255] The semiconductor device according to the embodiment may further include a first upper insulating layer 103 , a second upper insulating layer 104 , an input / output pad IO_PAD, a cell pad C_PAD, an input / output via IO_VA, and a cell via C_VA.

[0256] The first upper insulating layer 103 may be provided on the back side of the second substrate 100. The first upper insulating layer 103 may include an oxide-based insulating material containing protons (H+). For example, the first upper insulating layer 103 may include a high-density plasma (HDP) oxide. The first upper insulating layer 103 may be referred to as a "hydrogen passivation layer" or a "hydrogen supply layer". However, example embodiments are not limited thereto, and the first upper insulating layer 103 may include, for example, a flowable oxide (Fox) containing protons (H+), TOSZ (Tonen Silazen), USG (undoped silica glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PE-TEOS (plasma-enhanced tetraethyl orthosilicate), FSG (fluoride silicate glass), PEOX (plasma-enhanced oxide) or a combination thereof.

[0257] The second upper insulating layer 104 may be provided on the first upper insulating layer 103. The second upper insulating layer 104 may include a material having an etch selectivity with respect to the first upper insulating layer 103. The second upper insulating layer 104 may include, for example, silicon nitride (SiN), but example embodiments are not limited thereto.

[0258] The input / output pad IO_PAD may be provided on the second upper insulating layer 104 of the extension region EXT. The input / output pad IO_PAD may be connected to the input / output path IO_VA and the input / output contact 188. The input / output pad IO_PAD may be electrically connected to the peripheral structure PERI through the input / output contact 188 and the input / output path IO_VA. In addition, the input / output pad IO_PAD may electrically interconnect an external device and a semiconductor device. The input / output pad IO_PAD may include a conductive material. For example, the input / output pad IO_PAD may include aluminum (Al), but example embodiments are not limited thereto. The input / output path IO_VA may penetrate the second upper insulating layer 104 and the first upper insulating layer 103, and be electrically connected to the input / output pad IO_PAD.

[0259] The cell pad C_PAD may be provided on the second upper insulating layer 104 of the cell array region CAR. The cell pad C_PAD may be connected to the cell via C_VA and the common source plate 101. The cell pad C_PAD may be electrically connected to the common source plate 101 through the cell via C_VA. The cell pad C_PAD may include a conductive material. For example, the cell pad C_PAD may include aluminum (Al), but example embodiments are not limited thereto. The cell via C_VA may penetrate the second upper insulating layer 104 and the first upper insulating layer 103 and be electrically connected to the cell pad C_PAD.

[0260] The cell structure CELL according to an embodiment may include an upper structure US on a bottom surface of the cell wiring portion 180 , upper contact vias UC1 and UC2 penetrating at least a portion of the upper structure US, an upper wiring UM1 , and a second contact pad 700 .

[0261] The upper structure US may be located on the bottom surface of the cell wiring portion 180. For example, the upper structure US may be located on the bottom surface of the bit line BL. The upper structure US may be located between the bit line BL and the lower structure LS. The upper structure US may be connected to the peripheral structure PERI.

[0262] The upper structure US may include a plurality of upper barrier layers UB1 and UB2 , a plurality of upper interlayer insulating layers 301 , 302 , 303 , and 304 , and a second bonding insulating layer 350 sequentially stacked on the bottom surface of the bit line BL in the third direction (Z direction).

[0263] In an embodiment, the superstructure US may correspond to Figures 1 to 17 The second insulating structure 300 of the embodiment of the present invention. That is, Fig.37 As shown in FIG. 1 , the plurality of upper barrier layers UB1 and UB2, the plurality of upper interlayer insulating layers 301, 302, 303, and 304, and the second bonding insulating layer 350 of the upper structure US may correspond to Figures 1 to 17 The second bonding insulation layer 350 , the plurality of upper barrier layers UB1 and UB2 , and the plurality of upper interlayer insulation layers 310 , 320 , and 330 of the second insulation structure 300 of each embodiment.

[0264] Hereinafter, the peripheral structure PERI will be described in detail.

[0265] The peripheral structure PERI may include a first substrate 200 , a circuit element PTR on the first substrate 200 , a lower structure LS on the first substrate 200 , lower contact vias LC1 and LC2 penetrating at least a portion of the lower structure LS, lower wirings LM1 and LM2 , and a first contact pad 600 .

[0266] The lower structure LS may be located on the first substrate 200. For example, the lower structure LS may be located on the front side of the first substrate 200. That is, the lower structure LS may be located between the cell structure CELL and the first substrate 200.

[0267] In an embodiment, the lower structure LS may include a plurality of lower barrier layers LB1, LB2, and LB3, a plurality of lower interlayer insulating layers 401, 402, 403, 404, 405, and 406, and a first bonding insulating layer 450 sequentially stacked on the first substrate 200 in the third direction (Z direction). The plurality of lower barrier layers LB1, LB2, and LB3 and the plurality of lower interlayer insulating layers 401, 402, 403, 404, 405, and 406 may be alternately stacked on the first substrate 200.

[0268] In an embodiment, the lower structure LS may correspond to Figures 1 to 17 The first insulating structure 400 of the embodiment of the present invention. That is, Fig.37 As shown in FIG. 1 , the plurality of lower barrier layers LB1, LB2, and LB3, the plurality of lower interlayer insulating layers 401, 402, 403, 404, 405, and 406, and the first bonding insulating layer 450 of the lower structure LS may correspond to Figures 1 to 17 The first insulating structure 400 of the embodiment of the present invention includes a first bonding insulating layer 450 , a plurality of lower barrier layers LB1 and LB2 , and a plurality of lower interlayer insulating layers 410 , 420 , and 430 .

[0269] In an embodiment, the second bonding insulating layer 350 and the second contact pad 700 of the cell structure CELL and the first bonding insulating layer 450 and the first contact pad 600 of the peripheral structure PERI may be formed by Figures 1 to 17 The mixed joining in the embodiment is used for joining.

[0270] In more detail, the first surface of the peripheral structure PERI adjacent to the cell structure CELL is a bonding surface to the cell structure CELL, and may be configured with a first contact pad 600 and a first bonding insulating layer 450. The first surface of the cell structure CELL adjacent to the peripheral structure PERI is a bonding surface to the peripheral structure PERI, and may be configured with a second contact pad 700 and a second bonding insulating layer 350. The first contact pad 600 may be electrically connected to the circuit element PTR through the lower wirings LM1 and LM2. In addition, the second contact pad 700 may be electrically connected to the cell wiring portion 180 through the upper wiring UM1.

[0271] The first surface of the cell structure CELL and the first surface of the peripheral structure PERI can be bonded by hybrid bonding. Specifically, the first contact pad 600 of the peripheral structure PERI and the second contact pad 700 of the cell structure CELL can be bonded in direct contact to form a metal bond. In addition, the first bonding insulating layer 450 of the peripheral structure PERI and the second bonding insulating layer 350 of the cell structure CELL can be bonded to form a bonding insulating layer.

[0272] In this way, the first contact pad 600 of the peripheral structure PERI and the second contact pad 700 of the cell structure CELL can be bonded, and an electrical connection path can be provided between the peripheral structure PERI and the cell structure CELL. For example, through the upper wiring UM1 and the lower wirings LM1 and LM2, the bit line BL and / or the gate electrode 130 connected to the channel structure CH can be electrically connected to the circuit element PTR of the peripheral structure PERI.

[0273] The first substrate 200 may include a front side and a rear side facing each other. The front side of the first substrate 200 may face the cell structure CELL. The rear side of the first substrate 200 may face away from the cell structure CELL.

[0274] The first substrate 200 may be a semiconductor substrate including a semiconductor material. For example, the first substrate 200 may be a semiconductor substrate formed of a semiconductor material and a semiconductor substrate in which a semiconductor layer is formed on a base substrate. For example, the first substrate 200 may be formed of single crystal or polycrystalline silicon, epitaxial silicon, germanium or silicon germanium, silicon on insulator (SOI), germanium on insulator (GOI), etc.

[0275] The circuit element PTR may be located on the first substrate 200. The circuit element PTR may also include various circuit elements that control the operation of the memory cell structure provided in the cell structure CELL. For example, the circuit element PTR may constitute a decoder circuit ( Fig.40 Reference numeral 1110 in the figure), page buffer ( Fig.40 Reference numeral 1120 in the figure), logic circuit ( Fig.40 The circuit element PTR may include, for example, a transistor, but example embodiments are not limited thereto. For example, the circuit element PTR may include not only active elements such as transistors, but also passive elements such as capacitors, resistors, and inductors.

[0276] In the following, reference will be made to Figure 40 to Figure 42 An electronic system including a semiconductor device according to an embodiment is described in detail.

[0277] Fig.40 is a diagram schematically illustrating an electronic system including a semiconductor device according to an embodiment.

[0278] like Fig.40 As shown, the electronic system 1000 according to the embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, which includes one or more semiconductor devices 1100.

[0279] The semiconductor device 1100 may be a nonvolatile memory device, for example, as described above with reference to Figure 36 to Figure 39 The NAND flash memory device described. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an embodiment, the first structure 1100F may be positioned side by side with the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0280] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT located between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be changed in various ways depending on the implementation.

[0281] In an embodiment, the lower transistors LT1 and LT2 may include ground selection transistors, and the upper transistors UT1 and UT2 may include string selection transistors. The first gate lower line LL1 and the second gate lower line LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be a gate electrode of each of the upper transistors UT1 and UT2.

[0282] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through the first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through the second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0283] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation with respect to at least one memory cell transistor selected from a plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection wiring 1135 extending within the first structure 1100F to the second structure 1100S.

[0284] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . Depending on the implementation, the electronic system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0285] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a desired and / or optionally predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 for processing communication with the semiconductor device 1100. Through the NAND interface 1221, a control command for controlling the semiconductor device 1100, data to be written into the memory cell transistor MCT of the semiconductor device 1100, data to be read from the memory cell transistor MCT of the semiconductor device 1100, etc. may be sent. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. Upon receiving a control command from the external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0286] Fig.41 is a perspective view schematically showing an electronic system including a semiconductor device according to an embodiment.

[0287] like Fig.41As shown, the electronic system 2000 according to the embodiment may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a line pattern 2005 formed in the main substrate 2001.

[0288] The main substrate 2001 may include a connector 2006, which includes a plurality of pins connected to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In an embodiment, the electronic system 2000 may communicate with an external host according to one of the interfaces of a universal serial bus (USB), a peripheral component interconnect (PCI-Express), a serial advanced technology attachment (SATA), an M-Phy for universal flash memory (UFS), etc. In an embodiment, the electronic system 2000 may be operated by power supplied from an external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from an external host to the controller 2002 and the semiconductor package 2003.

[0289] The controller 2002 may record data in the semiconductor package 2003 or read data from the semiconductor package 2003 , and may increase the operation speed of the electronic system 2000 .

[0290] The DRAM 2004 may be a buffer memory for alleviating the speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may also act as a kind of high-speed cache memory and may provide a space for temporarily storing data during a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0291] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 located on each bottom surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0292] The package substrate 2100 may be a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.40 Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include a reference Figure 36 to Figure 39 A semiconductor device is described.

[0293] In an embodiment, the connection structure 2400 may be a bonding wire electrically connecting the input / output pad 2210 and the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. Depending on the embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the connection structure 2400 of the bonding wire method.

[0294] In an embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate other than the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through wires formed in the interposer substrate.

[0295] Fig.42 is a cross-sectional view schematically showing a semiconductor package according to an embodiment.

[0296] Fig.42 Shows Fig.41 2003, and conceptually illustrates an embodiment of a semiconductor package 2003 along Fig.41An area cut off by line II' of the semiconductor package 2003.

[0297] Reference Fig.42 In the semiconductor package 2003A, each semiconductor chip 2200 may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 on the first structure 4100 by a wafer bonding method.

[0298] The first structure 4100 may include a peripheral circuit region including a peripheral wiring 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 and a separation structure 4230 penetrating the gate stack structure 4210, and a word line ( Fig.40 The first structure 4100 and the second structure 4200 may be bonded to each other while being in contact with each other. The portion where the first bonding structure 4150 is bonded to the second bonding structure 4250 may be formed of, for example, copper (Cu).

[0299] In the semiconductor chip 2200 or the semiconductor device according to the embodiment, since the second portion 620 of the first contact pad 600 includes the void VD, when the annealing process is performed, the first contact pad 600 of the semiconductor device according to the embodiment can be thermally expanded into the void VD, and further, the first contact structure ST1 and the second contact structure ST2 can be restricted and / or prevented from being separated, or the first contact pad 600 and the second contact pad 700 can be restricted and / or prevented from being disconnected. Therefore, the reliability of the semiconductor device can be improved.

[0300] Each semiconductor chip 2200 may further include an input / output pad 2210 and an input / output connection wiring 4265 under the input / output pad 2210. The input / output connection wiring 4265 may be electrically connected to a portion of the second bonding structure 4250.

[0301] In an embodiment, a plurality of semiconductor chips 2200 in the semiconductor package 2003A may be electrically connected to each other by a connection structure 2400 in the form of a bonding wire. As another example, a plurality of semiconductor chips 2200 or a plurality of parts constituting the plurality of semiconductor chips 2200 may be electrically connected by a connection structure including a through silicon via. In addition, the semiconductor chip 2200 may be connected to an external element via a solder 2800 through a wiring 2135 and a pad 2125 formed in the package substrate 2100. The wiring 2135 and the pad 2125 are formed in the insulating layer 2120.

[0302] One or more of the elements disclosed above may include or be implemented in a processing circuit, such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0303] While embodiments of the present disclosure have been described in connection with what are presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0304] <Description of symbols>

[0305] ST1: First contact structure

[0306] ST2: Second contact structure

[0307] 400: First insulation structure

[0308] 600: First contact pad

[0309] 610: Part 1

[0310] 620: Part 2

[0311] 630: Part 3

[0312] 300: Second insulation structure

[0313] 700: Second contact pad

[0314] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0156754 filed in the Korean Intellectual Property Office on November 13, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Wiring of circuit components; a lower wiring connected to the circuit element wiring; a lower interlayer insulating layer on the lower wiring; as well as a first contact pad penetrating the lower interlayer insulating layer, wherein The first contact pad includes a first portion, a second portion on the first portion, and a third portion on the second portion, The first portion of the first contact pad is connected to the lower wiring, the second portion of the first contact pad comprises a gap above the first portion of the first contact pad, A maximum width of the second portion of the first contact pad along the horizontal direction is greater than a width of the third portion of the first contact pad along the horizontal direction, and The maximum width of the second portion of the first contact pad along the horizontal direction is a distance from a first outer surface of the second portion of the first contact pad to a second outer surface of the second portion of the first contact pad.

2. The semiconductor device according to claim 1, The maximum width of the third portion of the first contact pad along the horizontal direction is greater than or equal to the maximum width of the first portion of the first contact pad along the horizontal direction.

3. The semiconductor device according to claim 1, further comprising: a first bonding insulating layer on the lower interlayer insulating layer, wherein The third portion of the first contact pad penetrates the first bonding insulating layer, and The second portion of the first contact pad is on a bottom surface of the first bonding insulation layer.

4. The semiconductor device according to claim 3, The upper surface of the second portion of the first contact pad contacts the bottom surface of the first bonding insulation layer.

5. The semiconductor device according to claim 3, in, As a distance of a portion of the second portion of the first contact pad from the bottom surface of the first bonding insulation layer increases, a width of the portion of the second portion of the first contact pad in the horizontal direction decreases.

6. The semiconductor device according to claim 5, in, As the distance of the second portion of the first contact pad from the bottom surface of the first bonding insulation layer increases, the width of the second portion of the first contact pad in the horizontal direction increases and then decreases.

7. The semiconductor device according to claim 3, further comprising: a lower barrier layer, between the lower wiring and the lower interlayer insulating layer, The first portion of the first contact pad penetrates the lower barrier layer.

8. The semiconductor device according to claim 7, wherein: The lower barrier layer includes silicon nitride; and The lower interlayer insulating layer includes at least one of silicon oxide, silicon oxynitride, and silicon carbon nitride.

9. The semiconductor device according to claim 3, wherein a lower portion of the second portion of the first contact pad connected to the first portion of the first contact pad and covering a lower area of ​​the gap; and an upper portion of the second portion of the first contact pad is connected to the third portion of the first contact pad and covers an upper area of ​​the gap, The thickness of the upper portion of the second portion of the first contact pad is thicker than the thickness of the lower portion of the second portion of the first contact pad.

10. The semiconductor device according to claim 9, The second portion of the first contact pad does not overlap with the first bonding insulation layer in the horizontal direction.

11. The semiconductor device according to claim 1, wherein the third portion of the first contact pad includes a first pattern and a second pattern spaced apart from each other on the second portion of the first contact pad, The maximum width of the second portion of the first contact pad in the horizontal direction is greater than the sum of the maximum width of the first pattern in the horizontal direction and the maximum width of the second pattern in the horizontal direction.

12. The semiconductor device according to claim 1, The first contact pad includes a first conductive layer, a second conductive layer and a third conductive layer, The first conductive layer of the first contact pad is in contact with the lower interlayer insulating layer, The second conductive layer of the first contact pad is on an inner surface of the first conductive layer of the first contact pad, and The third conductive layer of the first contact pad is on the inner surface of the second conductive layer of the first contact pad, wherein the second conductive layer of the first contact pad covers an upper surface of the first conductive layer located on the first portion, and In the first portion of the first contact pad, the third conductive layer is on top of the inner surface of the second conductive layer of the first contact pad such that the inner surface of the second conductive layer of the first contact pad is an upper surface of the second conductive layer of the first contact pad.

13. A semiconductor device comprising: A first contact structure includes a lower interlayer insulating layer, a first bonding insulating layer on the lower interlayer insulating layer, and a first contact pad penetrating the lower interlayer insulating layer and the first bonding insulating layer; as well as a second contact structure on the first contact structure, the second contact structure comprising a second bonding insulating layer on the first contact structure and a second contact pad connected to the first contact pad, the second contact pad penetrating the second bonding insulating layer, wherein The first contact pad includes a first portion extending in one direction, a second portion below the first bonding insulating layer, and a third portion penetrating the first bonding insulating layer, the second portion of the first contact pad protrudes further in a horizontal direction than the first portion of the first contact pad, and The second portion of the first contact pad includes an internal buried void.

14. The semiconductor device according to claim 13, The maximum width of the second portion of the first contact pad along the horizontal direction is greater than the maximum width of the third portion of the first contact pad along the horizontal direction.

15. The semiconductor device according to claim 13, wherein: The material in the first bonding insulating layer is the same as the material in the second bonding insulating layer; and The material in the first contact pad is the same as the material in the second contact pad.

16. The semiconductor device according to claim 13, wherein A maximum width of the second portion of the first contact pad along the horizontal direction is greater than a width of the third portion of the first contact pad along the horizontal direction, and The maximum width of the second portion of the first contact pad along the horizontal direction is a distance from a first outer surface of the second portion of the first contact pad to a second outer surface of the second portion of the first contact pad.

17. The semiconductor device according to claim 13, wherein: As the distance between the first portion of the first contact pad and the first bonding insulation layer increases, the width of the first portion of the first contact pad in the horizontal direction decreases.

18. A semiconductor device comprising: a peripheral structure and a unit structure stacked on the peripheral structure, The peripheral structure includes a first substrate, a circuit element on the first substrate, a lower interlayer insulating layer on the first substrate, a first bonding insulating layer on the lower interlayer insulating layer, and a first contact pad penetrating the lower interlayer insulating layer and the first bonding insulating layer. wherein the cell structure comprises a second substrate electrically connected to the first substrate, a gate stack structure, a channel structure penetrating the gate stack structure in a cell array region of the second substrate, a second bonding insulating layer between the gate stack structure and the first bonding insulating layer, and a second contact pad connected to the first contact pad and penetrating the second bonding insulating layer, The second substrate includes the cell array region and the extension region, a first surface of the second substrate faces the peripheral structure, and a second surface of the second substrate is opposite to the first surface, wherein the gate stack structure comprises a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked on the first surface of the second substrate, wherein the first contact pad includes a first portion extending in one direction, a second portion between the first portion and the first bonding insulating layer, and a third portion penetrating the first bonding insulating layer, wherein the second portion of the first contact pad includes an internal buried void, and The second portion of the first contact pad protrudes farther than the third portion of the first contact pad in a horizontal direction.

19. The semiconductor device according to claim 18, wherein a maximum width of the second portion of the first contact pad along the horizontal direction is greater than a width of the third portion of the first contact pad along the horizontal direction, and The maximum width of the second portion of the first contact pad along the horizontal direction is a distance from a first outer surface of the second portion of the first contact pad to a second outer surface of the second portion of the first contact pad.

20. The semiconductor device according to claim 18, further comprising a lower barrier layer below the lower interlayer insulating layer, wherein The first portion of the first contact pad penetrates the lower barrier layer, and The lower interlayer insulating layer overlaps the second portion of the first contact pad in the horizontal direction.

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