Low-resistivity nitride integrated circuit copper interconnection diffusion barrier layer and performance evaluation method
By using low-resistivity vanadium nitride and tungsten nitride as diffusion barrier layer materials in integrated circuit copper interconnects, the problem of diffusion failure of traditional materials under high temperature conditions is solved, lower resistivity and better barrier performance are achieved, and the needs of high-performance interconnects are met.
Patent Information
- Application Number
- CN202510104837.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-13
AI Technical Summary
The prior art is difficult to effectively block Cu diffusion in integrated circuit copper interconnects, especially under high temperature conditions. Traditional diffusion barrier layer materials fail after shrinking their size, which cannot meet the needs of high-performance interconnects.
Low resistivity vanadium nitride (VN) and tungsten nitride (NbN) were used as diffusion barrier materials, and prepared by magnetron sputtering process, and process parameters were optimized to control resistivity and roughness.
It achieves lower resistivity and better diffusion barrier performance in integrated circuit copper interconnects, extends the failure temperature of the diffusion barrier layer, and meets the needs of high-performance interconnects.
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Figure CN119993955A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a low-resistivity nitride integrated circuit copper interconnect diffusion barrier layer and a performance evaluation method, belonging to the technical field of integrated circuit development and preparation. Background Art
[0002] Since 2000, integrated circuits have experienced rapid development. This is due to the growing demand for integrated circuit technology, the ever-decreasing size of microprocessors, and the explosive growth in transistor counts, which have led to resistance and capacitance delays in interconnects. To address diffusion-induced failures, it is necessary to develop a diffusion barrier material to prevent Cu from diffusing into the Si substrate at high temperatures. Currently, the main diffusion barriers used are pure metals and their nitrides, as well as double-layer structures of pure metals and nitrides. These are widely used in Cu interconnects due to their excellent thermal and chemical stability, and their strong bonding with Cu, which reduces electromigration at the interface and is less susceptible to galvanic corrosion.
[0003] As the minimum feature size of copper interconnects has shrunk to 3 nm, the thickness of diffusion barriers has reached its lower limit. Further reduction will render them ineffective in blocking Cu diffusion. Existing traditional diffusion barriers are primarily classified into: pure metals and their nitrides; bilayer structures of pure metals and nitrides, such as Ta and TaN, or Ti and TiN; multi-element alloy barriers, such as CoMo; and dielectric barriers, such as SiCN. However, as interconnect requirements grow, so too do the requirements for diffusion barrier thickness and performance. This has led to the emergence of new diffusion barrier materials: two-dimensional materials, such as hexagonal boron nitride (h-BN) and graphene; and high-entropy alloys and their nitrides. Compared to traditional barrier materials, these new diffusion barrier materials offer lower resistivity and improved diffusion barrier performance. Therefore, these materials hold great potential for reducing the size of Cu interconnects.
[0004] A search revealed that, to date, there are few records on the use of vanadium nitride and other similar low-resistivity, high-diffusion barrier materials in integrated circuit copper interconnects. Summary of the Invention
[0005] The present invention attempts for the first time to use a material with a low resistivity such as vanadium nitride to prepare a diffusion barrier layer with high diffusion barrier performance.
[0006] The present invention discloses a low-resistivity nitride integrated circuit copper interconnect diffusion barrier layer. The copper interconnect diffusion barrier layer is located between copper and a silicon substrate. The copper interconnect diffusion barrier layer contains both M and N elements, wherein M is selected from one of V and Nb. The copper interconnect diffusion barrier layer is prepared by a magnetron sputtering process.
[0007] The present invention provides a low-resistivity nitride integrated circuit copper interconnect diffusion barrier layer. When the VN diffusion barrier layer is prepared by magnetron sputtering, the following steps are controlled: The background vacuum degree is 1~10×10 -4 Pa, preferably 4~6×10 -4 Pa, more preferably 5×10 -4 Pa; The target distance is 10-20 cm, preferably 14-18 cm, and more preferably 16 cm; The sputtering power is 80~150W, preferably 95~105W; The working gas flow rate is 18-22 sccm, preferably 19-21 sccm, and more preferably 20 sccm; The working pressure is 0.4~1.0Pa, preferably 0.5~0.8Pa, more preferably 0.5~0.7Pa; The target material is a V target material with a purity greater than or equal to 99.95%; The working gas consists of argon and nitrogen; The temperature of the substrate is 20~25℃.
[0008] Preferably, when the VN diffusion barrier layer is prepared by magnetron sputtering, the volume ratio of argon to nitrogen in the working gas is 19:1, that is, the flow rate of argon is 18 sccm and the flow rate of nitrogen is 2 sccm. At this time, the sputtering power is preferably 100W.
[0009] The resistivity of the obtained VN diffusion barrier layer is 14~25μΩ•cm, and after optimization it is 14~14.5μΩ•cm.
[0010] The roughness of the optimized VN diffusion barrier layer is 0.983 nm.
[0011] After heat treatment at 700 ℃ for 30 minutes, its resistivity is 2~4 Ω / □.
[0012] Using the optimized process, the sputtering rate can be controlled at 3.8~4.2 nm / min.
[0013] The diffusion barrier performance of the VN diffusion barrier layer with a thickness of 20 nm does not fail after annealing at 550°C.
[0014] The present invention provides a low-resistivity nitride integrated circuit copper interconnect diffusion barrier layer. When the NbN diffusion barrier layer is prepared by magnetron sputtering, the following steps are controlled: The background vacuum degree is 1~10×10 -4 Pa, preferably 4~6×10 -4 Pa, more preferably 5×10 -4 Pa; The target distance is 10-20 cm, preferably 14-18 cm, and more preferably 16 cm; The sputtering power is 25~40W, preferably 28~32W; The working gas flow rate is 18-22 sccm, preferably 19-21 sccm, and more preferably 20 sccm; The working pressure is 0.4~1.0Pa, preferably 0.5~0.8Pa, more preferably 0.5~0.7Pa; The target material is a Nb target material with a purity greater than or equal to 99.95%; The working gas consists of argon and nitrogen; The temperature of the substrate is 20~25℃.
[0015] Preferably, when the NbN diffusion barrier layer is prepared by magnetron sputtering, the volume ratio of argon to nitrogen in the working gas is 19:1, that is, the flow rate of argon is 18 sccm and the flow rate of nitrogen is 2 sccm. At this time, the sputtering power is preferably 30W.
[0016] The resistivity of the obtained NbN diffusion barrier layer is 18~33μΩ•cm and 18~18.5μΩ•cm after optimization.
[0017] After optimization, the roughness of the obtained NbN diffusion barrier layer is 0.768 nm.
[0018] After heat treatment at 700 ℃ for 30 minutes, its resistivity is only 56 Ω / □.
[0019] Using the optimized process, the sputtering rate can be controlled at 1.8~2.2 nm / min.
[0020] The present invention provides a performance evaluation method for a low-resistivity nitride integrated circuit copper interconnect diffusion barrier layer; the method includes the following two schemes. Scheme 1 is a conventional heat treatment scheme, which determines the failure temperature of the diffusion barrier layer by performing heat treatment at different temperatures and analyzing whether a CuSi phase is generated.
[0021] Option 2: Simulation calculation evaluation The second solution includes: calculating the diffusion activation energy of Cu in different diffusion barrier layers, and performing performance evaluation according to the principle that the greater the diffusion activation energy, the better the diffusion barrier performance.
[0022] The failure temperature of the diffusion barrier layer is estimated based on the theoretical formation temperature of the tetragonal Cu3Si phase in the diffusion barrier layer being 200-250° C. The theory includes thermodynamic theory.
[0023] Specifically, they may include: Step 1: First principles modeling and geometry optimization The calculations are all performed based on the DFT method, and the calculation tool is the Cambridge Sequential Total Energy Package (CASTEP) module in Materials studio (MS).
[0024] Before the calculation, all parameters were reviewed and tested, with the K point set to 12. The calculation quality was divided into four levels: coarse, medium, fine, and ultrafine; the corresponding energy cutoffs were 250 eV, 351 eV, 400 eV, and 440 eV, respectively. To ensure accuracy, this paper selected the calculation quality with an energy cutoff of 400 eV. Once the energy cutoff was determined, the corresponding values for energy convergence tolerance, maximum displacement, and maximum stress were also determined. In order to study the diffusion of Cu in V and VN, a heterojunction structure is used to simulate the diffusion between interfaces; the modeling includes the crystal structures of Cu, V, and VN, three heterojunction structures of Cu-V (110), Cu-VN (111)-N, and Cu-VN (111)-V, two heterojunction structures in which the N or V atomic plane contacts the Cu atom, and three crystal structures of Cu3Si after the diffusion of Cu and Si, which are hexagonal, tetragonal, and trigonal, respectively.
[0025] Before each calculation, all crystal structures and models must be geometrically optimized to ensure structural stability. The optimization functional used is the generalized gradient approximation (GGA) within the Perdew-Burke-Ernzerhof (PBE) algorithm, employing the Broyden-Fletcher-Goldfarb-Shanno (BFGS) algorithm. Ultrasoft pseudopotentials are chosen, and spin polarization is considered. For the electronic parameters, an energy cutoff of 400 eV is used, resulting in convergence tolerances of 1.0 × 10−5 eV / atom, a maximum interatomic force of 0.03 eV / Å, a maximum stress of 0.05 GPa, and a maximum displacement of 0.001 Å. Furthermore, the K-point settings for the three heterojunction structures are 3×3×1, 5×5×1, and 5×5×1, respectively; the K-point settings for the rhombohedral, hexagonal, and tetragonal Cu3Si phases are 7×7×4, 6×6×6, and 7×7×3, respectively.
[0026] Step 2: Transition state search calculation The main calculation principle of the transition state search in the CASTEP module is to establish a model before and after the reaction and match other atoms except for diffusion. The diffusion of Cu is mainly divided into two diffusion mechanisms, namely vacancy diffusion and interstitial diffusion. For vacancy diffusion, an atom can be deleted in the product to simulate the vacancy defect, and then a single Cu atom can be moved to a pre-set vacancy. For interstitial diffusion, it refers to the diffusion of Cu atoms into the unit cell gap of V and VN, which can be simulated by moving a single Cu atom to the equilibrium interstitial position. The diffused Cu atoms are determined by geometric optimization and the proximity principle. The diffusion activation energy refers to the difference between the peak value of the total energy of the system after the Cu atom moves from the initial position to the final position and the initial energy of the reactants. In this invention, a complete LST / QST search protocol is used, and other settings are the same as the geometric optimization; through the transition state search calculation, the diffusion activation energy of Cu in different diffusion barriers is obtained, and the performance evaluation is carried out according to the principle that the larger the diffusion activation energy, the better the diffusion barrier performance.
[0027] In practical applications, the stability of Cu3Si can also be calculated; specifically: Using the CASTEP module in Materials Studio to calculate elastic constants, important mechanical properties such as Young's modulus (E), Vickers hardness (HV), Poisson's ratio (V), and elastic stiffness matrix (C) can be directly and indirectly derived. This paper primarily examines the stiffness coefficients (Cij) of three Cu3Si lattice structures. Different crystal structures must meet different stiffness coefficient conditions to determine their mechanical stability. The calculations for all three crystal structures were performed to a fine level of accuracy, thus defining energy convergence tolerances, maximum interatomic forces, and maximum displacements.
[0028] Lattice stability requires phonon calculations for detailed analysis. Energy calculations yield the density of states (DOS) and phonon properties of Cu3Si. The density of states is further divided into the total density of states (TDOS) and the partial density of states (PDOS). For phonon properties, the unit cell must be expanded before calculation, as phonon properties are closely related to atomic lattice vibrations. The trigonal, hexagonal, and tetragonal unit cells were expanded to 2×2×1, 2×2×3, and 3×3×3, respectively. Other calculation parameters remain the same as for geometry optimization. Based on the theoretical formation temperature of the tetragonal Cu3Si phase in the diffusion barrier, which is approximately 250°C, a preliminary estimate of the failure temperature of the diffusion barrier was made. This theory includes thermodynamics: From a thermodynamic perspective, tetragonal Cu3Si exhibits excellent mechanical stability, a key indicator of its thermodynamic stability. Mechanical stability is generally related to the material's elastic constants, which the tetragonal Cu3Si crystal meets the mechanical stability criteria. The dense packing and strong interatomic bonding of this structure make it thermodynamically more stable. Secondly, the presence of imaginary frequencies in a material's phonon spectrum is often used to determine its lattice stability. The presence of imaginary frequencies in the phonon spectrum often indicates material instability, whereas the absence of imaginary frequencies in the phonon graph of the tetragonal structure suggests that these two crystal structures are relatively stable in terms of lattice stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 The surface morphology of the film after annealing at different temperatures of the product obtained in Example 1; Figure 2 This is a diagram showing the change in sheet resistance of the products obtained in Example 1 and Comparative Example 1 after annealing at different temperatures; Figure 3 The surface morphology of the film of the product obtained in Comparative Example 1 after annealing at different temperatures; Figure 4 The surface morphology of the film obtained from Example 2 after annealing at different temperatures; Figure 5 This is a diagram showing the change in sheet resistance of the products obtained in Example 2 and Comparative Example 2 after annealing at different temperatures; Figure 6 The surface morphology of the film of the product obtained in Comparative Example 2 after annealing at different temperatures; Figure 7 Surface morphology of the product obtained to explore case series 2-1.
[0030] Figure 8 Surface morphology of the product obtained to explore case series 2-2. DETAILED DESCRIPTION
[0031] In the embodiments and comparative examples of the present invention, a V layer, a VN layer, a Nb layer, a NbN barrier layer film with a thickness of about 20 nm and a simulated Cu interconnect layer with a thickness of about 150 nm are prepared on an N-type single crystal silicon (100) substrate. The resistivity of the N-type single crystal silicon (100) substrate is 0.05-0.1Ω.CM; The purity of the target material used is greater than 99.95%, and the purity of the argon and nitrogen used is 5N grade or above.
[0032] The main equipment used are SB-5200DTD ultrasonic cleaner, TRP-450 magnetron sputtering coater and SLG1000-60 tube furnace.
[0033] Pre-treatment: First, the silicon wafer was ultrasonically cleaned in an acetone solution for 10 minutes to remove organic pollutants on the surface of the silicon wafer. After taking it out, it was rinsed with deionized water and blown dry with nitrogen. Then, the silicon wafer was ultrasonically cleaned in anhydrous ethanol for 5 minutes to remove grease on the surface of the substrate and ensure that the film adheres better to the silicon substrate. After taking it out, it was rinsed with deionized water and blown dry with nitrogen. Then, the silicon wafer was immersed in a 5% concentration HF solution for 2 minutes to remove the surface oxide layer. The silicon oxide (SiO2) layer on the silicon surface will hinder the deposition of the thin film, resulting in poor uniformity. After taking it out, it was rinsed with deionized water and blown dry with nitrogen. Finally, it was ultrasonically cleaned in anhydrous ethanol for 5 minutes. After taking it out, it was blown dry with nitrogen for later use.
[0034] When depositing the copper layer, control: Background vacuum degree 5×10 -4 Pa, target distance was 16 cm, sputtering power was 60 W, working gas flow rate was 20 sccm, and working pressure was 0.5 Pa. The target material used was a Cu target with a purity greater than or equal to 99.95%; the working gas used was argon with a flow rate of 20 sccm; and the substrate temperature was 25°C.
[0035] Example 1 On a spare N-type single crystal silicon (100) substrate, a vanadium nitride layer was deposited by magnetron sputtering, and then a 250 nm thick copper layer was deposited to obtain a Cu (250 nm) / VN (15 nm) / Si deposited sample; wherein the resistivity of the VN film was 14.26 μΩ·cm; When depositing the VN layer, control: Background vacuum degree 5×10 -4Pa, target distance of 16 cm, sputtering power of 100 W, working gas flow rate of 20 sccm, and operating pressure of 0.5 Pa. The target used was a V target with a purity greater than or equal to 99.95%. The working gas used was composed of argon and nitrogen, with an argon flow rate of 18 sccm and a nitrogen flow rate of 2 sccm. The substrate temperature was 25°C. Sputtering lasted for 10 minutes.
[0036] Failure temperature test experiment: Annealing test was carried out at 400℃-800℃ in nitrogen atmosphere (test time 30min). The surface morphology of the film after annealing at different temperatures is shown in Figure 2. Figure 1 ; The change of sheet resistance after annealing at different temperatures is shown in Figure 2 ,Depend on Figure 1 、 2 It can be seen that the diffusion barrier aging temperature of the Cu (250 nm) / VN (15 nm) / Si deposited sample prepared in Example 1 is about 700°C.
[0037] Comparative Example 1 Other conditions were the same as those in Example 1, except that the working gas was argon only, the pressure was 0.5 Pa, and the sputtering power was 20 W; a Cu (250 nm) / V (15 nm) / Si deposited sample was obtained; Failure temperature test experiment: Annealing test was carried out at 400℃-800℃ in nitrogen atmosphere (test time 30min). The surface morphology of the film after annealing at different temperatures is shown in Figure 2. Figure 3 The change of sheet resistance after annealing at the same temperature is shown in Figure 2 ,It can be seen from 2 and 3 that the diffusion barrier failure temperature of the Cu(250nm) / VN(15nm) / Si deposited sample prepared in Comparative Example 1 is about 600°C.
[0038] Exploration Case Series 1 Other conditions are the same as those in Example 1, except that the nitrogen flow rate is different. The resistivity of the obtained product is shown in Table 1:
[0039] Through exploratory experiments, it can be seen that the product with 2sccm has the best performance.
[0040] Prediction experiment of the products obtained in Example 1 and Comparative Example 1: Step 1: First principles modeling and geometry optimization The calculations are all performed based on the DFT method, and the calculation tool is the Cambridge Sequential Total Energy Package (CASTEP) module in Materials studio (MS).
[0041] Before the calculation, all parameters were reviewed and tested, with the K point set to 12. The calculation quality was divided into four levels: coarse, medium, fine, and ultrafine; the corresponding energy cutoffs were 250 eV, 351 eV, 400 eV, and 440 eV, respectively. To ensure accuracy, this paper selected the calculation quality with an energy cutoff of 400 eV. Once the energy cutoff was determined, the corresponding values for energy convergence tolerance, maximum displacement, and maximum stress were also determined. In order to study the diffusion of Cu in V and VN, a heterojunction structure is used to simulate the diffusion between interfaces; the modeling includes the crystal structures of Cu, V, and VN, three heterojunction structures of Cu-V (110), Cu-VN (111)-N, and Cu-VN (111)-V, two heterojunction structures in which the N or V atomic plane contacts the Cu atom, and three crystal structures of Cu3Si after the diffusion of Cu and Si, which are hexagonal, tetragonal, and trigonal, respectively.
[0042] Before each calculation, all crystal structures and models must be geometrically optimized to ensure structural stability. The optimization functional used is the generalized gradient approximation (GGA) within the Perdew-Burke-Ernzerhof (PBE) algorithm, employing the Broyden-Fletcher-Goldfarb-Shanno (BFGS) algorithm. Ultrasoft pseudopotentials are chosen, and spin polarization is considered. For the electronic parameters, an energy cutoff of 400 eV is used, resulting in convergence tolerances of 1.0 × 10−5 eV / atom, a maximum interatomic force of 0.03 eV / Å, a maximum stress of 0.05 GPa, and a maximum displacement of 0.001 Å. Furthermore, the K-point settings for the three heterojunction structures are 3×3×1, 5×5×1, and 5×5×1, respectively; the K-point settings for the rhombohedral, hexagonal, and tetragonal Cu3Si phases are 7×7×4, 6×6×6, and 7×7×3, respectively.
[0043] Step 2: Transition state search calculation The main calculation principle of the transition state search in the CASTEP module is to establish a model before and after the reaction and match other atoms except for diffusion. The diffusion of Cu is mainly divided into two diffusion mechanisms, namely vacancy diffusion and interstitial diffusion. For vacancy diffusion, an atom can be deleted in the product to simulate the vacancy defect, and then a single Cu atom can be moved to a pre-set vacancy. For interstitial diffusion, it refers to the diffusion of Cu atoms into the unit cell gaps of V and VN, which can be simulated by moving a single Cu atom to the equilibrium interstitial position. The diffused Cu atoms are determined by geometric optimization and the proximity principle. The diffusion activation energy refers to the difference between the peak value of the total energy of the system after the Cu atom moves from the initial position to the final position and the initial energy of the reactants. The present invention uses a complete LST / QST search protocol, and the other settings are the same as the geometric optimization; through the transition state search calculation, the diffusion activation energy of Cu in different diffusion barriers is obtained, and the performance evaluation is carried out according to the principle that the greater the diffusion activation energy, the better the diffusion barrier performance; By calculation, we get: 1. The minimum diffusion barrier for Cu diffusion through vacancies on the surface of metal V is 0.2309 eV; 2. When Cu atoms diffuse in the VN (111) system with the N atoms facing upward, the lowest diffusion barrier is as high as 1.4467 eV; Therefore, it can be determined that the VN developed by the present invention has significantly excellent diffusion barrier performance.
[0044] Example 2 On a spare N-type single crystal silicon (100) substrate, a vanadium nitride layer is deposited by magnetron sputtering, and then a 250nm thick copper layer is deposited to obtain a Cu (250nm) / NbN (15nm) / Si deposited sample; wherein the resistivity of the NbN film is 18.5μΩ·cm; When depositing the NbN layer, control: Background vacuum degree 5×10 -4 Pa, target distance 16 cm, sputtering power 30 W, working gas flow rate 20 sccm, working pressure 0.5 Pa. The target used was Nb with a purity greater than or equal to 99.95%. The working gas used consisted of argon and nitrogen, with an argon flow rate of 18 sccm and a nitrogen flow rate of 2 sccm. The substrate temperature was 25°C. Sputtering lasted 10 minutes.
[0045] Failure temperature test experiment: Annealing test was carried out at 400℃-800℃ in nitrogen atmosphere (test time 30min). The surface morphology of the film after annealing at different temperatures is shown in Figure 2. Figure 4; The change of sheet resistance after annealing at different temperatures is shown in Figure 5 ,Depend on Figure 4 、 5 It can be seen that the aging temperature of the diffusion barrier of the Cu (250 nm) / NbN (15 nm) / Si deposited sample prepared in Example 2 is about 700°C.
[0046] Comparative Example 2 Other conditions are the same as those in Example 2, except that the working gas is only argon.
[0047] Failure temperature test experiment: Annealing test was carried out at 400℃-800℃ in nitrogen atmosphere (test time 30min). The surface morphology of the film after annealing at different temperatures is shown in Figure 2. Figure 6 The change of sheet resistance after annealing at the same temperature is shown in Figure 5 ,It can be seen from Figures 5 and 6 that the aging temperature of the diffusion barrier of the Cu(250nm) / VN(15nm) / Si deposited sample prepared in Comparative Example 2 is about 600℃.
[0048] Exploration Case Series 2-1 Other conditions were the same as those in Example 2, except that the nitrogen flow rate was different, the sputtering power was 100 W, and the sputtering time was 10 min. The resistivity of the obtained product is shown in Table 2:
[0049] For NbN thin films, we first considered the effect of nitrogen flow rate on the film. Figure 7The following graphs show the surface quality of the films when the nitrogen flow rate is varied from (a) 2 sccm, (b) 4 sccm, and (c) 6 sccm, while keeping all other sputtering conditions unchanged (sputtering power of 100 W, sputtering time of 10 min). As can be seen, with increasing nitrogen flow rate, the surface quality of the films gradually improves, with fewer cracks and finer grains. This is due to the reduction in the mean free path length of the ions bombarding the Nb target caused by the introduction of the reactive gas, which reduces the sputtering rate and film thickness for the same sputtering time. Furthermore, the increased number of nitrogen atoms may cause chemical reactions between the Nb target and the target, poisoning the target and reducing the sputtering rate. Furthermore, with increasing nitrogen flow rate, white clusters on the film surface gradually increase. The increasing amount of nitrides causes the film to transition from metallic to non-metallic properties, eliminating internal stress while also increasing resistance. As shown in Table 2, as the nitrogen flow rate increases, the film resistivity also increases, while the carrier mobility also decreases. Too low mobility indicates that when the current passes through the film, the power consumption is large, and the resulting thermal effect will affect the operating frequency of the device. Similarly, we also characterized the crystallization behavior of the film under different sputtering powers, such as Figure 7 As shown in (b), it is clear that the NbN film is preferentially grown on the (111) plane, and the diffraction peak is low and broad, also tending towards the amorphous state. Therefore, to ensure the performance of the interconnect layer, an NbN film with a nitrogen flow rate of 2 sccm was selected. However, cracks appeared on the film surface at a sputtering power of 100 W. Further optimization of the sputtering power parameters will be carried out to ensure the quality of the film.
[0050] Exploration Case Series 2-2 Other conditions were the same as those in Example 2, except for the following: nitrogen flow rate (N2 = 2 sccm), different sputtering powers (a) 100 W, (b) 60 W, (c) 50 W, (d) 40 W, and (e) 30 W; The surface quality of the obtained product can be seen in Figure 8 , Figure 8 (a) is the surface quality map of the product obtained with a sputtering power of 100 W, (b) is the surface quality map of the product obtained with a sputtering power of 60 W, (c) is the surface quality map of the product obtained with a sputtering power of 50 W, (d) is the surface quality map of the product obtained with a sputtering power of 40 W, and (e) is the surface quality map of the product obtained with a sputtering power of 30 W.
[0051] It can be seen that when the sputtering power is high, obvious grooves appear on the film surface. This is because the energy of the sputtered atoms increases. High-energy sputtered atoms can cause defects in the substrate, resulting in more pores in the film structure. When the deposition time increases, cracks form. When the power is reduced to 40 W and 30 W, the particles on the film surface are relatively uniform and there are no obvious large cracks. However, careful observation shows that at 40 W, a few small gaps of shorter length still exist. At the same time, as the sputtering power decreases, the grain diameter also decreases, and the NbN film becomes denser and less rough, creating good conditions for subsequent sputtering. It was found that reducing the sputtering power can effectively eliminate cracks on the film surface, but it is worth noting that the lower the power, the better. If the power is too low, the plasma will be unstable, which will lead to loose structure, rough surface and uneven particle size of the sputtered film. Therefore, in the present invention, the optimal sputtering power for preparing NbN is 30 W, and the prefabricated nitrogen flow rate is 2 sccm.
Claims
1. A low resistivity nitride integrated circuit copper interconnect diffusion barrier layer, characterized in that: The copper interconnect diffusion barrier layer is located between copper and a silicon substrate, the copper interconnect diffusion barrier layer contains both M and N elements, the M is selected from one of V and Nb, and the copper interconnect diffusion barrier layer is prepared by a magnetron sputtering process.
2. The low resistivity nitride integrated circuit copper interconnect diffusion barrier layer according to claim 1, characterized in that: When the VN diffusion barrier layer is prepared by magnetron sputtering, control: The background vacuum degree is 1~10×10 -4 Pa, preferably 4~6×10 -4 Pa, more preferably 5×10 -4 Pa; The target distance is 10-20 cm, preferably 14-18 cm, and more preferably 16 cm; The sputtering power is 80~150W, preferably 95~105W; The working gas flow rate is 18-22 sccm, preferably 19-21 sccm, and more preferably 20 sccm; The working pressure is 0.4~1.0Pa, preferably 0.5~0.8Pa, and more preferably 0.5~0.7Pa; The target material is a V target material with a purity greater than or equal to 99.95%; The working gas is composed of argon and nitrogen; The temperature of the substrate is 20~25℃; Preferably, when the VN diffusion barrier layer is prepared by magnetron sputtering, the volume ratio of argon to nitrogen in the working gas is 19:1, that is, the flow rate of argon is 18 sccm and the flow rate of nitrogen is 2 sccm, and the sputtering power is preferably 100 W; The resistivity of the obtained VN diffusion barrier layer is 14~25μΩ•cm and 14~14.5μΩ•cm after optimization; The roughness of the optimized VN diffusion barrier layer is 0.983nm; After optimization, the roughness of the obtained VN diffusion barrier layer was 0.983 nm; After heat treatment at 700 ℃ for 30 minutes, its resistivity is 2~4 Ω / □.
3. The low resistivity nitride integrated circuit copper interconnect diffusion barrier layer according to claim 1, characterized in that: The diffusion barrier performance of the VN diffusion barrier layer with a thickness of 20 nm does not fail after annealing at 550°C.
4. The low resistivity nitride integrated circuit copper interconnect diffusion barrier layer according to claim 1, characterized in that: When the NbN diffusion barrier layer is prepared by magnetron sputtering, control: The background vacuum degree is 1~10×10 -4 Pa, preferably 4~6×10 -4 Pa, more preferably 5×10 -4 Pa; The target distance is 10-20 cm, preferably 14-18 cm, and more preferably 16 cm; The sputtering power is 25~40W, preferably 28~32W; The working gas flow rate is 18-22 sccm, preferably 19-21 sccm, and more preferably 20 sccm; The working pressure is 0.4~1.0Pa, preferably 0.5~0.8Pa, and more preferably 0.5~0.7Pa; The target material is a Nb target material with a purity greater than or equal to 99.95%; The working gas is composed of argon and nitrogen; The temperature of the substrate is 20~25℃.
5. The low resistivity nitride integrated circuit copper interconnect diffusion barrier layer according to claim 4, characterized in that: When the NbN diffusion barrier layer is prepared by magnetron sputtering, the volume ratio of argon and nitrogen in the working gas is 19:1, that is, the flow rate of argon is 18 sccm and the flow rate of nitrogen is 2 sccm. At this time, the sputtering power is preferably 30W.
6. The low resistivity nitride integrated circuit copper interconnect diffusion barrier layer according to claim 1, characterized in that: The resistivity of the obtained NbN diffusion barrier layer is 18~33μΩ•cm and 18~18.5μΩ•cm after optimization.
7. The low resistivity nitride integrated circuit copper interconnect diffusion barrier layer according to claim 6, characterized in that: The roughness of the obtained NbN diffusion barrier layer is 0.768 nm; After heat treatment at 700 °C for 30 min, the resistivity of the obtained NbN diffusion barrier layer is 56 Ω / □.
8. The low resistivity nitride integrated circuit copper interconnect diffusion barrier layer according to claim 1, characterized in that: The sputtering rate was controlled at 1.8~2.2 nm / min.
9. A method for evaluating the performance of a low resistivity nitride integrated circuit copper interconnect diffusion barrier layer; characterized in that: The following two schemes are included: Scheme 1 is a heat treatment scheme, which determines the failure temperature of the diffusion barrier layer by performing heat treatment at different temperatures and analyzing whether a CuSi phase is generated; Option 2: Simulation calculation evaluation The second scheme includes: calculating the diffusion activation energy of Cu in different diffusion barrier layers, and evaluating the performance according to the principle that the greater the diffusion activation energy, the better the diffusion barrier performance.
10. A method for evaluating the performance of a low resistivity nitride integrated circuit copper interconnect diffusion barrier layer; characterized in that: The evaluation methods include: Step 1: First principles modeling and geometry optimization The calculations are all based on the DFT method, and the calculation tool is the Cambridge Sequential Total Energy Package module in Materials studio; Before the calculation, all parameters were reviewed and tested, and the K point was set to 12. The calculation quality was divided into four levels: coarse, medium, fine, and ultrafine. The corresponding energy cutoffs were 250 eV, 351 eV, 400 eV, and 440 eV, respectively. The calculation quality with an energy cutoff of 400 eV was selected. Once the energy cutoff was determined, the corresponding energy convergence tolerance, maximum displacement, maximum stress, and other values were determined. In order to study the diffusion of Cu in V and VN, a heterojunction structure is used to simulate the diffusion between interfaces. The modeling includes the crystal structures of Cu, V, and VN, three heterojunction structures of Cu-V (110), Cu-VN (111)-N, and Cu-VN (111)-V, two heterojunction structures in which the N or V atomic plane contacts the Cu atom, and three crystal structures of Cu3Si, the product of the diffusion of Cu and Si, which are hexagonal, tetragonal, and trigonal, respectively. Before each calculation, all crystal structures and models must be geometrically optimized to ensure the stability of the structure. The functional used for structural optimization is the generalized gradient approximation in perdew-burke-ernzerhof, the BFGS algorithm is used, the pseudopotential is ultrasoft and spin polarization is considered; for the electronic parameters, the energy cutoff is 400 eV, so the corresponding convergence tolerance energy is 1.0 × 10−5 eV / atom, the maximum force between atoms is 0.03 eV / Å, the maximum stress is 0.05 GPa, and the maximum displacement is 0.001Å. In addition, the K-point settings of the three heterojunction structures are 3×3 ×1, 5×5×1, and 5×5×1 respectively; the k-point settings of the rhombohedral phase, hexagonal phase, and tetragonal phase of Cu3Si are 7×7×4, 6×6×6, and 7×7×3 respectively; Step 2: Transition state search calculation The main calculation principle of transition state search in the CASTEP module is achieved by establishing models before and after the reaction and matching other atoms except diffusion. The diffusion of Cu is mainly divided into two diffusion mechanisms, namely vacancy diffusion and interstitial diffusion. For vacancy diffusion, an atom can be deleted in the product to simulate the vacancy defect, and then a single Cu atom can be moved to the pre-set vacancy; for interstitial diffusion, it refers to the diffusion of Cu atoms into the unit cell gaps of V and VN, which can be simulated by moving a single Cu atom to the equilibrium interstitial position; the diffused Cu atoms are determined by geometric optimization and the proximity principle; the diffusion activation energy refers to the difference between the peak value of the total energy of the system after the Cu atom moves from the initial position to the final position and the initial energy of the reactants; transition state search calculation; The complete LST / QST search protocol was used in the transition state search calculation, and the other settings were the same as the geometry optimization. Through the transition state search calculation, the diffusion activation energy of Cu in different diffusion barriers was obtained, and the performance evaluation was carried out according to the principle that the larger the diffusion activation energy, the better the diffusion barrier performance.