Method for inhibiting generation of copper void defect
By increasing the compressive stress of the intermediate film layer of the protective layer in the copper interconnection process, the problem of copper void defects is solved and the performance and reliability of the device are improved.
Patent Information
- Application Number
- CN202510782504.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-10-17
AI Technical Summary
In the copper interconnection process, thermal and mechanical stresses introduced by subsequent thin film processes and etching processes lead to copper migration, resulting in copper void defects and affecting device performance.
By forming a protective layer on the interlayer dielectric layer and increasing the compressive stress of the intermediate film layer, the residual stress on the surface of the copper interconnect metal layer is reduced and the generation of copper void defects is suppressed.
It effectively reduces the generation of copper void defects and improves the performance stability and reliability of the device.
Smart Images
Figure CN120809674A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a method for inhibiting copper cavity defect. BACKGROUND
[0002] With the integrated circuit entering the era of very large scale integration, copper becomes the main interconnection metal of integrated circuit because of its smaller resistivity, good anti-electric migration performance and anti-stress migration ability; but copper interconnection technology is easy to cause copper migration because of the introduction of thermal stress, mechanical stress and other reasons in subsequent thin film process and etching process, which seriously affects the performance of the device. SUMMARY
[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for inhibiting copper cavity defect, which is used to solve the problem that the subsequent process after the formation of the copper interconnection metal layer causes copper cavity defect in the prior art.
[0004] To achieve the above object and other related objects, the present application provides a method for inhibiting copper cavity defect, comprising:
[0005] Step one, providing a substrate, forming an interlayer dielectric layer on the substrate, and forming a copper interconnection metal layer in the interlayer dielectric layer;
[0006] Step two, forming a protective layer on the interlayer dielectric layer, and increasing the compressive stress of the intermediate film layer in the protective layer;
[0007] Step three, forming a trench in the protective layer to expose part of the copper interconnection metal layer.
[0008] Preferably, the increase of the compressive stress is not less than 120 MPa.
[0009] Preferably, the protective layer is formed on the interlayer dielectric layer by a deposition process.
[0010] Preferably, the deposition mode or process parameters of the deposition process are adjusted to change the compressive stress of the intermediate film layer.
[0011] Preferably, the thickness of the intermediate film layer remains unchanged while the compressive stress of the intermediate film layer increases.
[0012] Preferably, the material of the intermediate film layer includes TEOS, the material of the film layer below the intermediate film layer includes silicon carbonitride, and the material of the film layer above the intermediate film layer includes silicon nitride.
[0013] Preferably, the step of forming the copper interconnection metal layer in the interlayer dielectric layer comprises: forming a patterned mask layer on the interlayer dielectric layer by photolithography and etching process; forming a via in the interlayer dielectric layer by etching process with the mask layer as a mask; and filling the via with the copper interconnection metal layer after removing the mask layer.
[0014] Preferably, the copper interconnection metal layer is filled in the via hole by a process of electroplating and then polishing.
[0015] As described above, the method for inhibiting the generation of copper void defects provided by the present application has the following beneficial effects: the generation of copper void defects is inhibited by reducing the residual stress on the surface of the copper interconnection metal layer by increasing the compressive stress of the intermediate film layer in the passivation layer. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings described below are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0017] Figure 1 A cross-sectional structure schematic diagram showing copper void defects;
[0018] Figure 2 A flowchart showing the method for inhibiting the generation of copper void defects provided by the embodiments of the present application;
[0019] Figures 3A-3C A cross-sectional structure schematic diagram showing the device formed after each step in the method for inhibiting the generation of copper void defects provided by the embodiments of the present application;
[0020] Figure 4 A comparative schematic diagram showing that the method for inhibiting the generation of copper void defects provided by the embodiments of the present application greatly reduces the copper void defects in the wafer compared with the prior art. DETAILED DESCRIPTION
[0021] The embodiments of the present application will be described in detail below with specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied by different specific embodiments, and various modifications or changes can be made to the details in the present specification based on different views and applications without departing from the spirit of the present application.
[0022] The technical solutions in the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0023] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0024] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0025] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict.
[0026] In the copper interconnection process, copper migration is prone to occur due to the introduction of thermal stress, mechanical stress and the like in subsequent thin film process, etching process, etc., resulting in the generation of void defects as shown in Figure 1 The stress remaining in the previous process leads to strain recrystallization at the copper grain boundary. Under the high temperature environment of the process, copper recrystallization migration occurs. Due to the existence of a large stress at the copper grain boundary, new crystal nuclei are easily formed under external causes and develop into voids and copper hills, thereby forming void defects.
[0027] In order to solve this problem, the present application provides a method for inhibiting the generation of copper void defects.
[0028] Please refer to Figure 2 which shows the method for inhibiting the generation of copper void defects provided by the embodiments of the present application.
[0029] As shown in Figure 2 , the method for inhibiting the generation of copper void defects comprises the following steps:
[0030] Step one, providing a substrate, forming an interlayer dielectric layer on the substrate, and forming a copper interconnection metal layer in the interlayer dielectric layer;
[0031] Step two, forming a protective layer on the interlayer dielectric layer, and increasing the compressive stress of the intermediate film layer in the protective layer;
[0032] Step three, form a trench in the protective layer to expose part of the copper interconnection metal layer.
[0033] In step one, the substrate can be a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or the like. Alternatively, the substrate can be made of other materials, such as a gallium arsenide or other III-V compound. Those skilled in the art can select the material of the substrate according to the type of the device structure formed on the substrate, and thus the type of the substrate should not limit the scope of the present application.
[0034] The substrate is formed with a plurality of isolation components, which divide the substrate into a plurality of regions. The isolation components can be made of any insulating material, such as silicon dioxide (SiO2), or a "high-K" dielectric having a high dielectric constant, for example, higher than 3.9. In some cases, the isolation components can be made of an oxide material. The materials suitable for making the isolation components can include, for example, silicon dioxide (SiO2), hafnium oxide (HfO2), alumina (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials having similar properties that are currently known or later developed.
[0035] The isolation components are formed, for example, by a shallow trench isolation (STI) process, which includes, but is not limited to, a shallow trench etching, an oxide filling, and an oxide planarization.
[0036] The shallow trench etching includes, but is not limited to, an isolation oxide layer, a nitride deposition, a shallow trench isolation using a mask, and an STI shallow trench etching. The STI oxide filling includes, but is not limited to, a trench liner oxide silicon, a trench CVD (chemical vapor deposition) oxide filling, or a PVD (physical vapor deposition) oxide filling. The planarization of the surface of the silicon wafer can be achieved by various methods. The planarization of the silicon wafer can be achieved by filling the gap using SOG (spin-on-glass), which can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked to evaporate the solvent and leave the silicon dioxide in the gap. The entire surface can also be etched back to reduce the thickness of the entire silicon wafer. The planarization can also be effectively achieved by a CMP process (also known as a chemical mechanical polishing process), which includes, but is not limited to, polishing the trench oxide (which can be achieved by chemical mechanical polishing) and removing the nitride.
[0037] The different regions of the substrate are formed with various semiconductor devices, such as MOS transistors, diodes, or the like. For simplicity, the substrate, the isolation components, and the various semiconductor devices are not shown in the figure.
[0038] As shown in Figure 3A As an example, an interlayer dielectric layer 301 is formed on the substrate by a deposition process, the material of the interlayer dielectric layer 301 includes, but is not limited to, silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, boron phosphorus silicon glass (BPSG), silsesquioxane, carbon (C) doped oxide including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms (i.e. organosilicate), thermoset polyarylene ether, or other low dielectric constant (<3.9) material.
[0039] As an example, the step of forming the copper interconnection metal layer 302 in the interlayer dielectric layer 301 includes: forming a patterned mask layer on the interlayer dielectric layer 301 by a photolithography and etching process; forming a via in the interlayer dielectric layer 301 by an etching process with the mask layer as a mask; and filling the via with the copper interconnection metal layer 302 after removing the mask layer.
[0040] In step two, as shown in Figure 3B An etching process is performed on the interlayer dielectric layer 301 to form a via in the interlayer dielectric layer 301, and a deposition process is performed on the interlayer dielectric layer 301 to form a protective layer 303 on the interlayer dielectric layer 301, the protective layer 303 is stacked by three film layers, the material of the film layer below the middle film layer 305 includes silicon carbon nitride (SiCN), and the material of the film layer above the middle film layer 305 includes silicon nitride.
[0041] The process of forming the copper interconnection metal layer 302 causes residual stress on the surface of the copper interconnection metal layer, in order to reduce the residual stress, the compressive stress of the middle film layer 305 is increased by no less than 120 MPa. Those skilled in the art can know that different deposition processes can be used to form the middle film layer 305 with different values of compressive stress, and the deposition method and the change of process parameters of the deposition process all fall within the protection scope of the claims of the present application.
[0042] As an example, the compressive stress of the middle film layer 305 is increased while the thickness remains unchanged.
[0043] As an example, the material of the middle film layer 305 includes tetraethoxysilane (TEOS), and the TEOS layer is formed by a plasma enhanced chemical vapor deposition process.
[0044] In step three, as shown in Figure 3C The step of forming the trench 306 in the protective layer 303 includes: forming a mask layer with an opening pattern of the trench 306 on the protective layer 303 by a photolithography and etching process; forming the trench 306 in the protective layer 303 by an etching process with the mask layer as a mask; and removing the mask layer by an ashing or etching process.
[0045] For example, when the compressive stress of TEOS is increased from -65 MPa to -1850 MPa, the bottom warpage of the protective layer 303 is reduced by about 35 μm, i.e. the surface void defects of the copper interconnection metal layer 302 are reduced.
[0046] As shown in Figure 4 Compared with the prior art, the copper void defects in the wafer are greatly reduced by using the method for inhibiting the generation of copper void defects provided in the present application.
[0047] It should be noted that the diagrams provided in the present embodiment only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the diagrams, rather than the number, shape and size of the components when actually implemented. The shape, number and proportion of the components when actually implemented can be arbitrarily changed, and the layout pattern of the components can be more complex.
[0048] In summary, the method for inhibiting the generation of copper void defects provided in the present application reduces the residual stress on the surface of the copper interconnection metal layer by increasing the compressive stress of the intermediate film layer in the protective layer, thereby inhibiting the generation of copper void defects. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.
[0049] The above-described embodiments only illustratively explain the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.
Claims
1. A method for suppressing the generation of copper void defects, characterized in that: The method comprises: Step 1: providing a substrate, forming an interlayer dielectric layer on the substrate, and forming a copper interconnect metal layer in the interlayer dielectric layer; Step 2: forming a protective layer on the interlayer dielectric layer, wherein the compressive stress of the intermediate film layer in the protective layer is increased; Step three: forming a groove in the protective layer to expose a portion of the copper interconnect metal layer.
2. The method according to claim 1, characterized in that The increase in the compressive stress is not less than 120 MPa.
3. The method according to claim 1, characterized in that A protection layer is formed on the interlayer dielectric layer through a deposition process.
4. The method according to claim 3, characterized in that The compressive stress of the intermediate film layer is changed by adjusting the deposition method or process parameters of the deposition process.
5. The method according to claim 1, wherein The compressive stress of the intermediate film layer increases while the thickness remains unchanged.
6. The method according to claim 1, characterized in that The material of the middle film layer includes TEOS, the material of the film layer below the middle film layer includes silicon carbonitride, and the material of the film layer above the middle film layer includes silicon nitride.
7. The method according to claim 1, characterized in that The steps of forming a copper interconnect metal layer in the interlayer dielectric layer include: forming a patterned mask layer on the interlayer dielectric layer by photolithography and etching processes; using the mask layer as a mask, forming a through hole in the interlayer dielectric layer by etching processes; after removing the mask layer, filling the through hole with a copper interconnect metal layer.
8. The method according to claim 7, characterized in that The through hole is filled with a copper interconnect metal layer by a process of electroplating followed by grinding.