Linear charging circuit integrated with communication interface and control method thereof

Abstract

The invention discloses a linear charging circuit integrated with a communication interface and a control method thereof.The linear charging circuit comprises a linear charging module, a communication link module, an overvoltage protection module REG, a power supply selection module CMP1 and a universal circuit module, and the input end of the linear charging module, the input end of the communication link module and the input end of the overvoltage protection module REG are connected with an input signal VIN; the output end of the linear charging module is connected with a battery end BAT and the first input end of the power supply selection module CMP1, the output end of the overvoltage protection module REG is connected with the second input end of the power supply selection module CMP1 and generates a signal VINREG, and the output end of the power supply selection module CMP1 is connected with the general circuit module and provides a power supply AVCC for the general circuit module. According to the invention, the problems of electric leakage, logic dead zone and oscillation in a traditional dual-power circuit system are effectively solved, and the stability and reliability of the system are improved.

Description

Technical Field

[0001] The present invention relates to a linear charging circuit and a control method thereof, in particular to a linear charging circuit with an integrated communication interface and a control method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] The linear charging circuit is a circuit design widely used in battery charging management. It adjusts the output voltage and current by adjusting the conduction degree (impedance) of the internal transistor, thereby achieving safe and stable constant voltage / constant current charging of the battery. It has the advantages of simple structure, low cost, and easy control. At this stage, the linear charging circuit is relatively mature in technology. In the application field, allowing data exchange with external devices, such as status reporting, fault diagnosis, etc., real-time detection of battery status and timely adjustment of charging parameters through the MCU host have gradually become customer application trends. Therefore, it is necessary to design a linear charging circuit with an integrated communication interface. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a linear charging circuit with an integrated communication interface and a control method thereof, so as to realize the dual functions of charging and communication of the circuit under different voltage conditions.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A linear charging circuit with an integrated communication interface comprises a linear charging module, a communication link module, an overvoltage protection module REG, a power supply selection module CMP1 and a general circuit module. The input end of the linear charging module, the input end of the communication link module and the input end of the overvoltage protection module REG are connected to an input signal VIN. The output end of the linear charging module is connected to a battery end BAT and a first input end of the power supply selection module CMP1. The output end of the overvoltage protection module REG is connected to a second input end of the power supply selection module CMP1 and generates a signal VIN_REG. The output end of the power supply selection module CMP1 is connected to the general circuit module to provide a power supply AVCC for the general circuit module.

[0005] Furthermore, the linear charging module includes a high-voltage resistant NMOS tube M1 and a high-voltage resistant NMOS tube M2, the drain of the high-voltage resistant NMOS tube M1 serves as the input end of the linear charging module, the source of the high-voltage resistant NMOS tube M1 is connected to the drain of the high-voltage resistant NMOS tube M2, the source of the high-voltage resistant NMOS tube M2 serves as the output end of the linear charging module, and the gate of the high-voltage resistant NMOS tube M1 and the gate of the high-voltage resistant NMOS tube M2 are connected to the control signal ctl1.

[0006] Furthermore, the communication link module includes a high-voltage resistant NMOS tube M3, the drain of the high-voltage resistant NMOS tube M3 serves as the input end of the communication link module, the source of the high-voltage resistant NMOS tube M3 serves as the output end of the communication link module, and the gate of the high-voltage resistant NMOS tube M3 is connected to the control signal ctl2, and the control signal ctl1 and the control signal ctl2 are reverse signals.

[0007] Furthermore, the control signal ctl1 and the control signal ctl2 are generated by a first control signal circuit, which includes a comparator CMP2 and an inverter INV1, a first input terminal of the comparator CMP2 is connected to an input signal VIN, a second input terminal of the comparator CMP2 is connected to a reference voltage REF1, an output terminal of the comparator CMP2 is connected to an input terminal of the inverter INV1 and generates a control signal ctl1, and an output terminal of the inverter INV1 generates a control signal ctl2.

[0008] Furthermore, the overvoltage protection module REG comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, an NMOS tube M4, a PMOS tube M5, an NMOS tube M6, an NMOS tube M7 and a reverse biased PN junction D1, one end of the resistor R1 and one end of the resistor R2, a source of the PMOS tube M6 and one end of the resistor R3 are connected as input ends of the overvoltage protection module REG to the input signal VIN, the other end of the resistor R1 is connected to the cathode of the reverse biased PN junction D1 and the gate of the NMOS tube M4, the other end of the resistor R2 is connected to the drain of the NMOS tube M4, and the NMOS tube M The source of the resistor R4 is connected to one end of the resistor R4 and the drain of the PMOS tube M5 and serves as the output end of the overvoltage protection module REG to generate a signal VIN_REG. The other end of the resistor R4 is connected to the drain of the NMOS tube M6 and the gate of the NMOS tube M6 to generate a bias voltage BIAS. The other end of the resistor R3 is connected to the gate of the PMOS tube M5 and one end of the resistor R5. The other end of the resistor R5 is connected to one end of the NMOS tube M7. The gate of the NMOS tube M7 is connected to the control signal OVP. The anode of the reverse biased PN junction D1, the source of the NMOS tube M6 and the source of the NMOS tube M7 are grounded.

[0009] Furthermore, the control signal OVP is generated by a second control signal circuit, which includes a comparator CMP3 and an inverter INV4, a first input terminal of the comparator CMP3 is connected to an input signal VIN, a second input terminal of the comparator CMP3 is connected to a reference voltage REF2, an output terminal of the comparator CMP3 is connected to an input terminal of the inverter INV4, and an output terminal of the inverter INV4 generates the control signal OVP.

[0010] Further, the power supply selection module CMP1 includes a PMOS tube M8, a PMOS tube M9, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, an NMOS tube M13, an NMOS tube M14, a PMOS tube M5, a Schmitt trigger SMIT1, an inverter INV2 and an inverter INV3, the source of the PMOS tube M8 is connected to the signal VIN_REG, the source of the MOS tube M9 is connected to the battery terminal BAT, the gate of the PMOS tube M8 is connected to the drain of the PMOS tube M8, the drain of the NMOS tube M10 and the gate of the PMOS tube M9, the gate of the NMOS tube M10, the gate of the NMOS tube M11 and the gate of the NMOS tube M13 are connected to the bias voltage BIAS, the source of the NMOS tube M10, the source of the NMOS tube M11 and the source of the NMOS tube M13 are grounded, and the PMOS tube M The source of the PMOS tube M9 is connected to the power supply terminal BAT, the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M11, the drain of the NMOS tube M12 and the input terminal of the Schmitt trigger SMIT1, the output terminal of the Schmitt trigger SMIT1 is connected to the input terminal of the inverter INV2 and the gate of the NMOS tube M12, the source of the NMOS tube M12 is connected to the drain of the NMOS tube M13, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3 and the gate of the PMOS tube M15, the output terminal of the inverter INV3 is connected to the gate of the NMOS tube M14, the drain of the NMOS tube M14 is connected to the battery terminal BAT, the source of the NMOS tube M14 is connected to the source of the PMOS tube M15 and serves as the output terminal of the power supply selection module CMP1 to generate the power supply AVCC, and the drain of the PMOS tube M15 is connected to the signal VIN_REG.

[0011] A control method for a linear charging circuit with an integrated communication interface comprises the following steps: The reference voltage REF1 is equal to the battery terminal BAT voltage; When the voltage of the input signal VIN is less than the reference voltage REF1, the output of the comparator CMP2 in the first control signal circuit is low level, at this time the control signal ctl1 is low level, the control signal ctl2 is high level, then the linear charging module is turned off, the communication link module is turned on, and at this time the linear charging circuit can exchange data with the external device or the main control unit through the communication link module; at the same time, the control signal OVP in the second control signal circuit is high level, then the NMOS tube M7 in the overvoltage protection module REG is turned on, the gate of the PMOS tube M5 is low level, the PMOS tube M5 is turned on, the signal VIN_REG voltage is equal to the input signal VIN, at this time the signal VIN_REG voltage is lower than the battery terminal BAT voltage, and the power supply AVCC at the output end of the power supply selection module CMP1 is equal to the battery terminal BAT voltage; When the voltage of the input signal VIN is greater than the reference voltage REF1 and less than the reference voltage REF2, the output of the comparator CMP2 in the first control signal circuit is high level, at this time the control signal ctl1 is high level, the control signal ctl2 is low level, then the linear charging module is turned on, the communication link module is turned off, and at the same time the control signal OVP in the second control signal circuit is high level, then the NMOS tube M7 in the overvoltage protection module REG is turned on, the gate of the PMOS tube M5 is low level, the PMOS tube M5 is turned on, the signal VIN_REG voltage is equal to the input signal VIN, at this time the signal VIN_REG voltage is higher than or equal to the battery terminal BAT voltage, the power supply AVCC at the output end of the power supply selection module CMP1 is equal to the input signal VIN voltage; When the voltage of the input signal VIN is greater than the reference voltage REF2, the control signal OVP in the second control signal circuit is at a low level, the NMOS tube M7 in the overvoltage protection module REG is turned off, the gate of the PMOS tube M5 is at a high level, the PMOS tube M5 is turned off, and the voltage of the signal VIN_REG is equal to 0. At this time, the reverse biased PN junction D1 in the overvoltage protection module REG is turned on, the gate of the NMOS tube M4 is at a low level, the NMOS tube M4 is turned off, the bias voltage BIAS is 0, and the power supply selection module CMP1 does not work.

[0012] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a linear charging circuit with an integrated communication interface and a control method thereof, which effectively solves the leakage, logic dead zone and oscillation problems existing in the traditional dual power supply circuit system, and improves the stability and reliability of the system; at the same time, the design of multiplexing the VIN port further simplifies the circuit structure and improves the overall integration and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of a linear charging circuit with an integrated communication interface of the present invention.

[0014] Figure 2 Schematic diagram of the overvoltage protection module REG of the present invention.

[0015] Figure 3 is a schematic diagram of the power supply selection module CMP1 of the present invention.

[0016] Figure 4 is a schematic diagram of a first control signal circuit of the present invention.

[0017] Figure 5 is a schematic diagram of a second control signal circuit of the present invention. DETAILED DESCRIPTION

[0018] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0019] like Figure 1 As shown, a linear charging circuit with an integrated communication interface of the present invention comprises a linear charging module, a communication link module, an overvoltage protection module REG, a power supply selection module CMP1 and a general circuit module, the input end of the linear charging module, the input end of the communication link module and the input end of the overvoltage protection module REG are connected to an input signal VIN, the output end of the linear charging module is connected to a battery end BAT and a first input end of the power supply selection module CMP1, the output end of the overvoltage protection module REG is connected to a second input end of the power supply selection module CMP1 and generates a signal VIN_REG, and the output end of the power supply selection module CMP1 is connected to the general circuit module to provide a power supply AVCC for the general circuit module.

[0020] The linear charging module includes a high-voltage resistant NMOS tube M1 and a high-voltage resistant NMOS tube M2. The drain of the high-voltage resistant NMOS tube M1 serves as the input end of the linear charging module. The source of the high-voltage resistant NMOS tube M1 is connected to the drain of the high-voltage resistant NMOS tube M2. The source of the high-voltage resistant NMOS tube M2 serves as the output end of the linear charging module. The gate of the high-voltage resistant NMOS tube M1 and the gate of the high-voltage resistant NMOS tube M2 are connected to the control signal ctl1.

[0021] The communication link module includes a high-voltage resistant NMOS tube M3, the drain of which serves as the input end of the communication link module, the source of which serves as the output end of the communication link module, and the gate of which is connected to the control signal ctl2. The control signal ctl1 and the control signal ctl2 are reverse signals.

[0022] like Figure 4 As shown, the control signal ctl1 and the control signal ctl2 are generated by a first control signal circuit, which includes a comparator CMP2 and an inverter INV1. The first input terminal of the comparator CMP2 is connected to the input signal VIN, the second input terminal of the comparator CMP2 is connected to the reference voltage REF1, the output terminal of the comparator CMP2 is connected to the input terminal of the inverter INV1 and generates the control signal ctl1, and the output terminal of the inverter INV1 generates the control signal ctl2.

[0023] like Figure 2As shown, the overvoltage protection module REG includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, an NMOS tube M4, a PMOS tube M5, an NMOS tube M6, an NMOS tube M7 and a reverse biased PN junction D1. One end of the resistor R1, one end of the resistor R2, the source of the PMOS tube M6 and one end of the resistor R3 are connected to the input signal VIN as the input end of the overvoltage protection module REG. The other end of the resistor R1 is connected to the cathode of the reverse biased PN junction D1 and the gate of the NMOS tube M4. The other end of the resistor R2 is connected to the drain of the NMOS tube M4. The source is connected to one end of the resistor R4 and the drain of the PMOS tube M5 and serves as the output end of the overvoltage protection module REG to generate a signal VIN_REG. The other end of the resistor R4 is connected to the drain of the NMOS tube M6 and the gate of the NMOS tube M6 and generates a bias voltage BIAS. The other end of the resistor R3 is connected to the gate of the PMOS tube M5 and one end of the resistor R5. The other end of the resistor R5 is connected to one end of the NMOS tube M7. The gate of the NMOS tube M7 is connected to the control signal OVP. The anode of the reverse biased PN junction D1, the source of the NMOS tube M6 and the source of the NMOS tube M7 are grounded. The resistance values ​​of the resistors R2 and R4 are relatively large. When the NMOS tube M4 is turned on, the maximum current passing through the NMOS tube M6 is (VIN-GND) / (R2+R4). It is ensured to be less than 1uA during design. This current always remains in the turned-on state and provides the bias voltage BIAS. The maximum bias current of the comparator is set to a 1uA constant current source to ensure that the comparator can maintain basic working conditions even when a suitable power supply is not selected, avoiding logic dead zones and oscillation problems.

[0024] like Figure 5 As shown, the control signal OVP is generated by a second control signal circuit, which includes a comparator CMP3 and an inverter INV4. The first input terminal of the comparator CMP3 is connected to the input signal VIN, the second input terminal of the comparator CMP3 is connected to the reference voltage REF2, the output terminal of the comparator CMP3 is connected to the input terminal of the inverter INV4, and the output terminal of the inverter INV4 generates the control signal OVP.

[0025] like Figure 3As shown, the power supply selection module CMP1 includes a PMOS tube M8, a PMOS tube M9, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, an NMOS tube M13, an NMOS tube M14, a PMOS tube M5, a Schmitt trigger SMIT1, an inverter INV2 and an inverter INV3, the source of the PMOS tube M8 is connected to the signal VIN_REG, the source of the MOS tube M9 is connected to the battery terminal BAT, the gate of the PMOS tube M8 is connected to the drain of the PMOS tube M8, the drain of the NMOS tube M10 and the gate of the PMOS tube M9, the gate of the NMOS tube M10, the gate of the NMOS tube M11 and the gate of the NMOS tube M13 are connected to the bias voltage BIAS, the source of the NMOS tube M10, the source of the NMOS tube M11 and the source of the NMOS tube M13 are grounded, and the source of the PMOS tube M9 is grounded. The source is connected to the power supply terminal BAT, the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M11, the drain of the NMOS tube M12 and the input terminal of the Schmitt trigger SMIT1, the output terminal of the Schmitt trigger SMIT1 is connected to the input terminal of the inverter INV2 and the gate of the NMOS tube M12, the source of the NMOS tube M12 is connected to the drain of the NMOS tube M13, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3 and the gate of the PMOS tube M15, the output terminal of the inverter INV3 is connected to the gate of the NMOS tube M14, the drain of the NMOS tube M14 is connected to the battery terminal BAT, the source of the NMOS tube M14 is connected to the source of the PMOS tube M15 and serves as the output terminal of the power supply selection module CMP1 to generate the power supply AVCC, and the drain of the PMOS tube M15 is connected to the signal VIN_REG. The present invention adopts a power supply selection module CMP1 to avoid leakage problems caused by the high impedance state of the power supply when the system is not enabled. NMOS tube M12, NMOS tube M13 and Schmitt trigger SMIT1 jointly form a voltage hysteresis function to prevent the comparator from generating an oscillating output when the input voltage is close. The logic signal after the Schmitt trigger SMIT1 is enhanced through a cascade inverter to enhance the driving capability to turn on the NMOS tube M14 or the PMOS tube M15, thereby realizing the function of selecting a higher voltage. This design ensures the stability and reliability of the power supply selection and avoids unnecessary repeated switching caused by input voltage fluctuations.

[0026] A linear charging circuit with an integrated communication interface of the present invention not only reduces the number of ports required, improves the overall integration and efficiency of the chip, but also solves the leakage problem commonly seen in traditional dual power supply circuit systems by multiplexing the design of the VIN port. In traditional dual power supply circuits, it is usually necessary to select a suitable power supply through a comparator. However, the comparator itself also requires current to provide bias. When a suitable power supply is not selected, the comparator may not work properly, and it is easy to form a logical dead zone or generate an oscillating output. In contrast, the power comparison selection module in the present invention can ensure that the power supply does not enter a high-impedance state when the system is not enabled, thereby avoiding the leakage problem caused by this. A current-type comparator is used to distinguish the voltages of the VIN_REG and BAT terminals, and a voltage hysteresis function is formed by a Smith trigger to prevent oscillating outputs when the input voltage is close. The driving capability of the logic signal is enhanced by a cascade inverter to turn on M14 or M15 to ensure that a higher voltage can be correctly selected as the power supply.

[0027] A control method for a linear charging circuit with an integrated communication interface comprises the following steps: The reference voltage REF1 is equal to the battery terminal BAT voltage.

[0028] When the voltage of the input signal VIN is less than the reference voltage REF1, the output of the comparator CMP2 in the first control signal circuit is low level. At this time, the control signal ctl1 is low level, and the control signal ctl2 is high level, then the linear charging module is turned off, and the communication link module is turned on. At this time, the linear charging circuit can exchange data with the external device or the main control unit through the communication link module; at the same time, the control signal OVP in the second control signal circuit is high level, then the NMOS tube M7 in the overvoltage protection module REG is turned on, the gate of the PMOS tube M5 is low level, the PMOS tube M5 is turned on, and the signal VIN_REG voltage is equal to the input signal VIN. At this time, the signal VIN_REG voltage is lower than the battery terminal BAT voltage, and the power supply AVCC at the output end of the power supply selection module CMP1 is equal to the battery terminal BAT voltage.

[0029] When the voltage of the input signal VIN is greater than the reference voltage REF1 and less than the reference voltage REF2, the output of the comparator CMP2 in the first control signal circuit is high level. At this time, the control signal ctl1 is high level and the control signal ctl2 is low level, then the linear charging module is turned on and the communication link module is turned off. At the same time, the control signal OVP in the second control signal circuit is high level, then the NMOS tube M7 in the overvoltage protection module REG is turned on, the gate of the PMOS tube M5 is low level, the PMOS tube M5 is turned on, and the signal VIN_REG voltage is equal to the input signal VIN. At this time, the signal VIN_REG voltage is higher than or equal to the battery terminal BAT voltage, and the power supply AVCC at the output end of the power supply selection module CMP1 is equal to the input signal VIN voltage.

[0030] When the voltage of the input signal VIN is greater than the reference voltage REF2, the control signal OVP in the second control signal circuit is at a low level, the NMOS tube M7 in the overvoltage protection module REG is turned off, the gate of the PMOS tube M5 is at a high level, the PMOS tube M5 is turned off, and the signal VIN_REG voltage is equal to 0. At this time, the reverse biased PN junction D1 in the overvoltage protection module REG is turned on, the gate of the NMOS tube M4 is at a low level, and the NMOS tube M4 is turned off. The bias voltage BIAS is 0, and the power supply selection module CMP1 does not work. The bias voltage BIAS also provides a bias voltage for the comparators of the first control signal circuit and the second control signal circuit. In this state, the two control signal circuits do not work, and the corresponding linear charging module and communication link module do not work.

[0031] The present invention provides a linear charging circuit with integrated communication interface and a control method thereof, which effectively solves the leakage, logic dead zone and oscillation problems existing in the traditional dual power supply circuit system and improves the stability and reliability of the system; at the same time, the design of multiplexing the VIN port further simplifies the circuit structure and improves the overall integration and efficiency.

[0032] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A linear charging circuit with integrated communication interface, characterized in that: It includes a linear charging module, a communication link module, an overvoltage protection module REG, a power supply selection module CMP1 and a general circuit module. The input end of the linear charging module, the input end of the communication link module and the input end of the overvoltage protection module REG are connected to the input signal VIN, the output end of the linear charging module is connected to the battery end BAT and the first input end of the power supply selection module CMP1, the output end of the overvoltage protection module REG is connected to the second input end of the power supply selection module CMP1 and generates a signal VIN_REG, and the output end of the power supply selection module CMP1 is connected to the general circuit module to provide power AVCC for the general circuit module.

2. The linear charging circuit with integrated communication interface according to claim 1, characterized in that: The linear charging module includes a high-voltage resistant NMOS tube M1 and a high-voltage resistant NMOS tube M2. The drain of the high-voltage resistant NMOS tube M1 serves as the input end of the linear charging module. The source of the high-voltage resistant NMOS tube M1 is connected to the drain of the high-voltage resistant NMOS tube M2. The source of the high-voltage resistant NMOS tube M2 serves as the output end of the linear charging module. The gate of the high-voltage resistant NMOS tube M1 and the gate of the high-voltage resistant NMOS tube M2 are connected to the control signal ctl1.

3. The linear charging circuit with integrated communication interface according to claim 2, characterized in that: The communication link module includes a high-voltage resistant NMOS tube M3, the drain of the high-voltage resistant NMOS tube M3 serves as the input end of the communication link module, the source of the high-voltage resistant NMOS tube M3 serves as the output end of the communication link module, the gate of the high-voltage resistant NMOS tube M3 is connected to the control signal ctl2, and the control signal ctl1 and the control signal ctl2 are reverse signals.

4. The linear charging circuit with integrated communication interface according to claim 3, characterized in that: The control signal ctl1 and the control signal ctl2 are generated by a first control signal circuit, which includes a comparator CMP2 and an inverter INV1. The first input end of the comparator CMP2 is connected to the input signal VIN, the second input end of the comparator CMP2 is connected to the reference voltage REF1, the output end of the comparator CMP2 is connected to the input end of the inverter INV1 and generates the control signal ctl1, and the output end of the inverter INV1 generates the control signal ctl2.

5. The linear charging circuit with integrated communication interface according to claim 1, characterized in that: The overvoltage protection module REG comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, an NMOS tube M4, a PMOS tube M5, an NMOS tube M6, an NMOS tube M7 and a reverse biased PN junction D1. One end of the resistor R1, one end of the resistor R2, the source of the PMOS tube M6 and one end of the resistor R3 are connected to the input signal VIN as the input end of the overvoltage protection module REG. The other end of the resistor R1 is connected to the cathode of the reverse biased PN junction D1 and the gate of the NMOS tube M4. The other end of the resistor R2 is connected to the drain of the NMOS tube M4. The source of the NMOS tube M4 is connected to the drain of the NMOS tube M4. The first electrode is connected to one end of the resistor R4 and the drain of the PMOS tube M5 and serves as the output end of the overvoltage protection module REG to generate a signal VIN_REG. The other end of the resistor R4 is connected to the drain of the NMOS tube M6 and the gate of the NMOS tube M6 to generate a bias voltage BIAS. The other end of the resistor R3 is connected to the gate of the PMOS tube M5 and one end of the resistor R5. The other end of the resistor R5 is connected to one end of the NMOS tube M7. The gate of the NMOS tube M7 is connected to the control signal OVP. The anode of the reverse biased PN junction D1, the source of the NMOS tube M6 and the source of the NMOS tube M7 are grounded.

6. The linear charging circuit with integrated communication interface according to claim 5, characterized in that: The control signal OVP is generated by a second control signal circuit, which includes a comparator CMP3 and an inverter INV4. The first input terminal of the comparator CMP3 is connected to the input signal VIN, the second input terminal of the comparator CMP3 is connected to the reference voltage REF2, the output terminal of the comparator CMP3 is connected to the input terminal of the inverter INV4, and the output terminal of the inverter INV4 generates the control signal OVP.

7. The linear charging circuit with integrated communication interface according to claim 5, characterized in that: The power supply selection module CMP1 includes a PMOS tube M8, a PMOS tube M9, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, an NMOS tube M13, an NMOS tube M14, a PMOS tube M5, a Schmitt trigger SMIT1, an inverter INV2 and an inverter INV3, the source of the PMOS tube M8 is connected to the signal VIN_REG, the source of the MOS tube M9 is connected to the battery terminal BAT, the gate of the PMOS tube M8 is connected to the drain of the PMOS tube M8, the drain of the NMOS tube M10 and the gate of the PMOS tube M9, the gate of the NMOS tube M10, the gate of the NMOS tube M11 and the gate of the NMOS tube M13 are connected to the bias voltage BIAS, the source of the NMOS tube M10, the source of the NMOS tube M11 and the source of the NMOS tube M13 are grounded, and the The source is connected to the power supply terminal BAT, the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M11, the drain of the NMOS tube M12 and the input terminal of the Schmitt trigger SMIT1, the output terminal of the Schmitt trigger SMIT1 is connected to the input terminal of the inverter INV2 and the gate of the NMOS tube M12, the source of the NMOS tube M12 is connected to the drain of the NMOS tube M13, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3 and the gate of the PMOS tube M15, the output terminal of the inverter INV3 is connected to the gate of the NMOS tube M14, the drain of the NMOS tube M14 is connected to the battery terminal BAT, the source of the NMOS tube M14 is connected to the source of the PMOS tube M15 and serves as the output terminal of the power supply selection module CMP1 to generate the power supply AVCC, and the drain of the PMOS tube M15 is connected to the signal VIN_REG.

8. A control method for a linear charging circuit with an integrated communication interface according to any one of claims 1 to 7, characterized in that The following steps are involved: The reference voltage REF1 is equal to the battery terminal BAT voltage; When the voltage of the input signal VIN is less than the reference voltage REF1, the output of the comparator CMP2 in the first control signal circuit is low level, at this time the control signal ctl1 is low level, the control signal ctl2 is high level, then the linear charging module is turned off, the communication link module is turned on, and at this time the linear charging circuit can exchange data with the external device or the main control unit through the communication link module; at the same time, the control signal OVP in the second control signal circuit is high level, then the NMOS tube M7 in the overvoltage protection module REG is turned on, the gate of the PMOS tube M5 is low level, the PMOS tube M5 is turned on, the signal VIN_REG voltage is equal to the input signal VIN, at this time the signal VIN_REG voltage is lower than the battery terminal BAT voltage, and the power supply AVCC at the output end of the power supply selection module CMP1 is equal to the battery terminal BAT voltage; When the voltage of the input signal VIN is greater than the reference voltage REF1 and less than the reference voltage REF2, the output of the comparator CMP2 in the first control signal circuit is high level, at this time the control signal ctl1 is high level, the control signal ctl2 is low level, then the linear charging module is turned on, the communication link module is turned off, and at the same time the control signal OVP in the second control signal circuit is high level, then the NMOS tube M7 in the overvoltage protection module REG is turned on, the gate of the PMOS tube M5 is low level, the PMOS tube M5 is turned on, the signal VIN_REG voltage is equal to the input signal VIN, at this time the signal VIN_REG voltage is higher than or equal to the battery terminal BAT voltage, the power supply AVCC at the output end of the power supply selection module CMP1 is equal to the input signal VIN voltage; When the voltage of the input signal VIN is greater than the reference voltage REF2, the control signal OVP in the second control signal circuit is at a low level, the NMOS tube M7 in the overvoltage protection module REG is turned off, the gate of the PMOS tube M5 is at a high level, the PMOS tube M5 is turned off, and the voltage of the signal VIN_REG is equal to 0. At this time, the reverse biased PN junction D1 in the overvoltage protection module REG is turned on, the gate of the NMOS tube M4 is at a low level, the NMOS tube M4 is turned off, the bias voltage BIAS is 0, and the power supply selection module CMP1 does not work.

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