Driving circuit for inhibiting crosstalk of GaN HEMT bridge arm

Abstract

The invention discloses a driving circuit for inhibiting crosstalk of a GaN HEMT (High Electron Mobility Transistor) bridge arm. An upper bridge arm crosstalk suppression circuit and a lower bridge arm crosstalk suppression circuit are arranged in a high-side drive circuit and a low-side drive circuit respectively; the upper bridge arm crosstalk suppression circuit absorbs (forward) voltage spike crosstalk in the high-side driving circuit when the power tube is turned on, and absorbs (negative) voltage spike crosstalk in the high-side driving circuit when the power tube is turned off; the lower bridge arm crosstalk suppression circuit absorbs (forward) voltage spike crosstalk in the low-side driving circuit when the power tube is turned on, and absorbs (negative) voltage spike crosstalk in the low-side driving circuit when the power tube is turned off. According to the GaN HEMT half-bridge driving circuit, crosstalk of the upper bridge arm and the lower bridge arm is effectively restrained, the grid electrode of the GaN HEMT power device is protected, and the reliability of the GaN HEMT half-bridge driving circuit is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronics, and in particular relates to a driving circuit for suppressing crosstalk of a GaN HEMT bridge arm. Background Art

[0002] With the rapid development of semiconductor technology, the third-generation wide bandgap power semiconductor devices represented by GaN (gallium nitride) HEMT (high electron mobility transistor) have demonstrated excellent performance in high-speed switching applications due to their significant advantages of low on-resistance and low parasitic capacitance, significantly reducing the switching loss and conduction loss of power devices, and opening up broad application prospects in the field of high power density converters.

[0003] In the half-bridge drive circuit composed of GaN HEMT, this device is the core switching unit. Its fast turn-on characteristics promote the improvement of system efficiency, but it is also accompanied by potential problems. Specifically, the tiny parasitic capacitance of GaN HEMT accelerates its conduction process, but it also causes a sharp rise in the drain-source voltage of the GaNHEMT on the opposite side when one side of the GaN HEMT is quickly hard-turned on in the half-bridge circuit. The rapidly rising voltage is coupled to the drive shutdown loop through the transfer capacitance, and due to the impedance in the loop, it causes an unexpected increase in the gate voltage. When the voltage rise exceeds the threshold voltage, the GaN HEMT that should be in the off state will cause crosstalk conduction, significantly increasing the conduction loss, and even causing a shoot-through phenomenon under high voltage conditions, endangering the device reliability and system stability.

[0004] On the other hand, when one side of the GaN HEMT in the half-bridge circuit performs a hard turn-off operation, the GaN HEMT on the opposite side enters a reverse freewheeling state, accompanied by a rapid drop in the drain-source voltage. In this process, the current extraction effect of the transfer capacitor generates a reverse current flow in the turn-off loop, which is also affected by the loop impedance, forming a negative voltage at the gate. If the negative voltage exceeds the tolerance limit of the HEMT gate, it will cause reverse overvoltage breakdown, posing a direct threat to device safety.

[0005] Traditional coping strategies, such as slowing down the switching speed of devices, can suppress crosstalk conduction to a certain extent, but sacrifice switching efficiency; directly reducing the turn-off loop impedance is effective, but it is easy to cause turn-off overvoltage and EMI (electromagnetic interference) noise problems; and the use of negative voltage shutdown technology may increase the risk of reverse overvoltage breakdown. Summary of the invention

[0006] The present invention aims to provide a driving circuit for suppressing the crosstalk of the bridge arm of GaN HEMT without affecting the switching speed of the GaN power tube, increasing the switching loss and adding an extra control signal, which can effectively suppress the crosstalk problem caused by the gate-source voltage of the GaN power tube in the half-bridge circuit, so that the positive crosstalk voltage and the negative crosstalk voltage are kept within the safety threshold, so as to solve the technical problems mentioned in the background technology.

[0007] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0008] A driving circuit for suppressing crosstalk in a GaN HEMT bridge arm, wherein the driving circuit is connected to a GaN HEMT bridge arm, wherein the GaN HEMT bridge arm comprises an upper bridge arm circuit and a lower bridge arm circuit, and the upper bridge arm circuit has the same structure as the lower bridge arm circuit;

[0009] The driving circuit includes two crosstalk suppression circuits. The crosstalk suppression circuit in the upper bridge arm is used to suppress the crosstalk peak voltage in the high-side driving circuit; the crosstalk suppression circuit in the lower bridge arm is used to suppress the crosstalk peak voltage in the low-side driving circuit.

[0010] The high-side driving circuit and the crosstalk suppression circuit in the lower bridge arm share a dual-channel isolation chip 1;

[0011] The low-side driving circuit and the crosstalk suppression circuit in the upper bridge arm share a dual-channel isolation chip 2;

[0012] The first signal output HOUT1 of the dual-channel isolation chip 1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the gate of the power tube M1;

[0013] The second signal output LOUT2 of the dual-channel isolation chip 2 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the gate of the power tube M2.

[0014] Furthermore, the upper bridge arm circuit includes a power tube M1 gate circuit, and the power tube M1 gate circuit includes a dual-channel isolation chip 1, a power tube M1, and a resistor R1;

[0015] The first signal output HOUT1 of the dual-channel isolation chip 1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the gate of the power tube M1;

[0016] The lower bridge arm circuit includes a power tube M2 gate circuit, and the power tube M2 gate circuit includes a dual-channel isolation chip 2, a power tube M2, and a resistor R5;

[0017] The second signal output LOUT2 of the dual-channel isolation chip 2 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the gate of the power tube M2;

[0018] Furthermore, the crosstalk suppression circuit arranged in the upper bridge arm is a first crosstalk suppression circuit, and the first crosstalk suppression circuit includes a dual-channel isolation chip 2, an auxiliary transistor Q1, a diode D1, a resistor R2, a resistor R3, and a capacitor C1;

[0019] The first signal output LOUT1 of the dual-channel isolation chip 2 is connected to one end of the resistor R2 and the resistor R3, the other end of the resistor R3 is connected to the anode of the diode D1, and the cathode of the diode D1 and the other end of the resistor R2 are commonly connected to the gate of the auxiliary transistor Q1;

[0020] The drain of the auxiliary transistor Q1 is connected to the capacitor C1, and the other end of the capacitor C1 is connected to the gate of the power tube M1;

[0021] The source of the auxiliary transistor Q1 is connected to the source of the power transistor M1;

[0022] One end of the resistor R4 is connected to the gate of the power tube M1, and the other end is connected to the source of the power tube M1;

[0023] The crosstalk suppression circuit arranged in the lower bridge arm is a second crosstalk suppression circuit, and the second crosstalk suppression circuit includes a dual-channel isolation chip 1, an auxiliary transistor Q2, a diode D2, a resistor R6, a resistor R7, and a capacitor C2;

[0024] The second signal output HOUT2 of the dual-channel isolation chip 2 is connected to one end of the resistor R6 and the resistor R7, the other end of the resistor R7 is connected to the anode of the diode D2, and the cathode of the diode D2 and the other end of the resistor R6 are commonly connected to the gate of the auxiliary transistor Q2;

[0025] The drain of the auxiliary transistor Q2 is connected to the capacitor C2, and the other end of the capacitor C2 is connected to the gate of the power transistor M2;

[0026] The source of the auxiliary transistor Q2 is connected to the source of the power transistor M2;

[0027] One end of the resistor R8 is connected to the gate of the power tube M2, and the other end is connected to the source of the power tube M2;

[0028] Further, the logic input of the dual-channel isolation chip 1 includes signal input terminals IN1-A and IN1-B, and the input terminals IN1-A and IN1-B are commonly connected to the first control signal PWM1;

[0029] The logic input of the dual-channel isolation chip 2 includes signal input terminals IN2-A and IN2-B, and the input terminals IN2-A and IN2-B are commonly connected to the second control signal PWM2;

[0030] The first output ground VEEH1 of the dual-channel isolation chip 1 and the first output ground VEEL1 of the dual-channel isolation chip 2 are connected to the high-side reference ground GNDH;

[0031] The second output ground VEEH2 of the dual-channel isolation chip 1 and the second output ground VEEL2 of the dual-channel isolation chip 2 are connected to the low-side reference ground GNDL;

[0032] Furthermore, the dual-channel isolation chip 1 and the dual-channel isolation chip 2 used are both isolated dual-channel gate drive chips. On the one hand, the chip logic input and output are isolated, and on the other hand, the two output channels are isolated from each other;

[0033] Since the diode D1 is connected in series with the resistor R3, the gate resistance when the auxiliary transistor Q1 is turned on is the parallel connection of the resistors R2 and R3, and the gate resistance when the auxiliary transistor Q1 is turned off is R2;

[0034] Since the diode D2 is connected in series with the resistor R7, the gate resistance when the auxiliary transistor Q2 is turned on is the parallel connection of the resistors R6 and R7, and the gate resistance when the auxiliary transistor Q1 is turned off is R6;

[0035] The gate resistance of the power tube M1 when it is turned on and off is R1; the gate resistance of the power tube M2 when it is turned on and off is R5;

[0036] By selecting the resistance values ​​of resistors R1, R2, R3, R5, R6 and R7, the switching speed of the auxiliary transistor and the power tubes of the upper bridge arm and the lower bridge arm in the circuit is controlled;

[0037] The auxiliary transistor Q1 conducts faster than the power tube M2 turns off, and turns off slower than the power tube M2 conducts;

[0038] The auxiliary transistor Q2 conducts faster than the power tube M1 and turns off slower than the power tube M1 conducts;

[0039] Furthermore, the auxiliary transistors Q1 and Q2 are both low-voltage GaN switch tubes, and the switching speed of the auxiliary transistors should be faster than the switching speed of the power tubes;

[0040] Furthermore, the resistance values ​​of resistors R1, R2, R3, R5, R6, and R7 should satisfy the following formula:

[0041]

[0042] Furthermore, the working cycle of the driving circuit for suppressing the crosstalk of the GaN HEMT bridge arm is divided into four stages:

[0043] In the first stage, the first control signal PWM1 maintains a low level, and the second control signal PWM2 sends a shutdown signal; the power tube M1 is in the off state, the power tube M2 is turned off, the auxiliary transistor Q1 is turned off, and the auxiliary transistor Q2 is in the off state; the auxiliary transistor Q1 is turned off slowly, and when the power tube M2 is turned off, the auxiliary transistor Q1 is still in the on state, so that a first crosstalk suppression path is formed between the gate of the power tube M1 and the high-side reference ground GNDH, suppressing the crosstalk caused by the instant when the power tube M2 is turned off;

[0044] In the second stage, the first control signal PWM1 sends a start signal, and the second control signal PWM2 maintains a low level; the power tube M1 is turned on, the power tube M2 is in the off state, the auxiliary transistor Q1 is in the off state, and the auxiliary transistor Q2 is turned on; the auxiliary transistor Q2 is turned on quickly, and when the power tube M1 is turned on, the auxiliary transistor Q2 is already turned on, so that a second crosstalk suppression path is formed between the gate of the power tube M2 and the low-side reference ground GNDL, suppressing the crosstalk caused by the moment the power tube M1 is turned on;

[0045] In the third stage, the first control signal PWM1 sends a shutdown signal, and the second control signal PWM2 maintains a low level; the power tube M1 is turned off, the power tube M2 is in the off state, the auxiliary transistor Q1 is in the off state, and the auxiliary transistor Q2 is turned off; the auxiliary transistor Q2 is turned off slowly, and when the power tube M1 is turned off, the auxiliary transistor Q2 is still in the on state, so that a first crosstalk suppression path is formed between the gate of the power tube M2 and the low-side reference ground GNDL, suppressing the crosstalk caused by the moment when the power tube M1 is turned off;

[0046] In the fourth stage, the first control signal PWM1 maintains a low level, and the second control signal PWM2 sends a start signal; the power tube M1 is in the off state, the power tube M2 is turned on, the auxiliary transistor Q1 is turned on, and the auxiliary transistor Q2 is in the off state; the auxiliary transistor Q1 is turned on quickly, and when the power tube M2 is turned on, the auxiliary transistor Q1 is already turned on, so that a second crosstalk suppression path is formed between the gate of the power tube M1 and the high-side reference ground GNDH, suppressing the crosstalk caused by the moment when the power tube M2 is turned on.

[0047] A driving circuit for suppressing GaN HEMT bridge arm crosstalk of the present invention has the following advantages:

[0048] The present invention enables the lower bridge arm crosstalk suppression circuit or the upper bridge arm crosstalk suppression circuit to be alternately turned on before the crosstalk phenomenon occurs in the upper bridge arm or the lower bridge arm, and absorbs the crosstalk caused by the upper and lower bridge arms being turned on or off at the moment by the capacitor in the circuit. Under the premise of not affecting the switching speed and switching loss of the upper and lower bridge arm switching devices and not increasing any extra control signals, the active suppression of the crosstalk phenomenon of the upper bridge arm and the lower bridge arm is realized efficiently and reliably, thereby improving the reliability of the switching devices. From the perspective of the overall structure of the circuit implementation, only the crosstalk suppression circuit needs to be designed to achieve the above-mentioned invention purpose, which is easy to implement and low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of the structure of a driving circuit for suppressing GaN HEMT half-bridge crosstalk in an embodiment of the present invention;

[0050] Figure 2 This is a working timing diagram of a driving circuit for suppressing GaN HEMT half-bridge crosstalk in an embodiment of the present invention;

[0051] Figure 3 A diagram showing a simulation circuit structure in an embodiment of the present invention;

[0052] Figure 4 The gate-source voltage Vgs waveform of the high / side power tube without adding the crosstalk suppression circuit;

[0053] Figure 5 This is the gate-source voltage Vgs waveform of the high / side power tube with the crosstalk suppression circuit added. DETAILED DESCRIPTION

[0054] In order to better understand the purpose, structure and function of the present invention, a driving circuit for suppressing GaN HEMT bridge arm crosstalk of the present invention is further described in detail below with reference to the accompanying drawings.

[0055] like Figure 1 As shown, this embodiment provides a driving circuit for suppressing crosstalk of a GaN HEMT bridge arm, characterized in that the driving circuit is connected to a GaN HEMT bridge arm, the GaN HEMT bridge arm includes an upper bridge arm circuit and a lower bridge arm circuit, and the upper bridge arm circuit has the same structure as the lower bridge arm circuit;

[0056] The driving circuit includes two crosstalk suppression circuits. The crosstalk suppression circuit in the upper bridge arm is used to suppress the crosstalk peak voltage in the high-side driving circuit; the crosstalk suppression circuit in the lower bridge arm is used to suppress the crosstalk peak voltage in the low-side driving circuit.

[0057] The high-side driving circuit and the crosstalk suppression circuit in the lower bridge arm share a dual-channel isolation chip 1;

[0058] The low-side driving circuit and the crosstalk suppression circuit in the upper bridge arm share a dual-channel isolation chip 2;

[0059] The upper bridge arm circuit includes a power tube M1 gate circuit, and the power tube M1 gate circuit includes a dual-channel isolation chip 1, a power tube M1, and a resistor R1;

[0060] The first signal output HOUT1 of the dual-channel isolation chip 1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the gate of the power tube M1;

[0061] The lower bridge arm circuit includes a power tube M2 gate circuit, and the power tube M2 gate circuit includes a dual-channel isolation chip 2, a power tube M2, and a resistor R5;

[0062] The second signal output LOUT2 of the dual-channel isolation chip 2 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the gate of the power tube M2;

[0063] The crosstalk suppression circuit arranged in the upper bridge arm is a first crosstalk suppression circuit, and the first crosstalk suppression circuit includes a dual-channel isolation chip 2, an auxiliary transistor Q1, a diode D1, a resistor R2, a resistor R3, and a capacitor C1;

[0064] The first signal output LOUT1 of the dual-channel isolation chip 2 is connected to one end of the resistor R2 and the resistor R3, the other end of the resistor R3 is connected to the anode of the diode D1, and the cathode of the diode D1 and the other end of the resistor R2 are commonly connected to the gate of the auxiliary transistor Q1;

[0065] The drain of the auxiliary transistor Q1 is connected to the capacitor C1, and the other end of the capacitor C1 is connected to the gate of the power tube M1;

[0066] The source of the auxiliary transistor Q1 is connected to the source of the power transistor M1;

[0067] One end of the resistor R4 is connected to the gate of the power tube M1, and the other end is connected to the source of the power tube M1;

[0068] The crosstalk suppression circuit arranged in the lower bridge arm is a second crosstalk suppression circuit, and the second crosstalk suppression circuit includes a dual-channel isolation chip 1, an auxiliary transistor Q2, a diode D2, a resistor R6, a resistor R7, and a capacitor C2;

[0069] The second signal output HOUT2 of the dual-channel isolation chip 2 is connected to one end of the resistor R6 and the resistor R7, the other end of the resistor R7 is connected to the anode of the diode D2, and the cathode of the diode D2 and the other end of the resistor R6 are commonly connected to the gate of the auxiliary transistor Q2;

[0070] The drain of the auxiliary transistor Q2 is connected to the capacitor C2, and the other end of the capacitor C2 is connected to the gate of the power transistor M2;

[0071] The source of the auxiliary transistor Q2 is connected to the source of the power transistor M2;

[0072] One end of the resistor R8 is connected to the gate of the power tube M2, and the other end is connected to the source of the power tube M2;

[0073] The logic input of the dual-channel isolation chip 1 includes signal input terminals IN1-A and IN1-B, and the input terminals IN1-A and IN1-B are commonly connected to the first control signal PWM1;

[0074] The logic input of the dual-channel isolation chip 2 includes signal input terminals IN2-A and IN2-B, and the input terminals IN2-A and IN2-B are commonly connected to the second control signal PWM2;

[0075] The first output ground VEEH1 of the dual-channel isolation chip 1 and the first output ground VEEL1 of the dual-channel isolation chip 2 are connected to the high-side reference ground GNDH;

[0076] The second output ground VEEH2 of the dual-channel isolation chip 1 and the second output ground VEEL2 of the dual-channel isolation chip 2 are connected to the low-side reference ground GNDL;

[0077] The dual-channel isolation chip 1 and dual-channel isolation chip 2 used are both isolated dual-channel gate drive chips. On the one hand, the chip logic input and output are isolated, and on the other hand, the two output channels are isolated from each other;

[0078] By selecting the resistance values ​​of resistors R1, R2, R3, R5, R6, and R7, the switching speed of the auxiliary transistor and the high-power tube in the circuit is controlled;

[0079] Since the diode D1 is connected in series with the resistor R3, the gate resistance when the auxiliary transistor Q1 is turned on is the parallel connection of the resistors R2 and R3, and the gate resistance when the auxiliary transistor Q1 is turned off is R2;

[0080] Since the diode D2 is connected in series with the resistor R7, the gate resistance when the auxiliary transistor Q2 is turned on is the parallel connection of the resistors R6 and R7, and the gate resistance when the auxiliary transistor Q1 is turned off is R6;

[0081] The gate resistance of the power tube M1 when it is turned on and off is R1; the gate resistance of the power tube M2 when it is turned on and off is R5;

[0082] The auxiliary transistor Q1 conducts faster than the power tube M2 turns off, and turns off slower than the power tube M2 conducts;

[0083] The auxiliary transistor Q2 conducts faster than the power tube M1 and turns off slower than the power tube M1 conducts;

[0084] The auxiliary transistors Q1 and Q2 are both low-voltage GaN switch tubes, and the switching speed of the auxiliary transistors should be faster than that of the power tubes;

[0085] The resistance values ​​of resistors R1, R2, R3, R5, R6, and R7 should satisfy the following formula:

[0086]

[0087] Figure 2 The driving circuit control operation timing diagram for suppressing GaN HEMT half-bridge crosstalk in this embodiment is shown below. Figure 2 The working principle of this embodiment is described as follows:

[0088] Before time t0, the power tube M1 is in the off state, the power tube M2 is in the on state, the auxiliary transistor Q1 is in the off state, and the auxiliary transistor Q2 is in the on state;

[0089] At time t0, the second control signal PWM2 sends a shutdown signal, and the shutdown signal controls the power transistor M2 and the auxiliary transistor Q1 simultaneously through the dual-channel isolation chip 2;

[0090] During the period t0-t1, the power tube M1 is in the off state, the power tube M2 is off, the auxiliary transistor Q1 is on, and the auxiliary transistor Q2 is in the on state; when the auxiliary transistor Q1 is off, the gate resistance is R2, and the turn-off speed of the auxiliary transistor Q1 is controlled by matching the gate resistance R2 with a larger resistance value to the auxiliary transistor Q1, so that the turn-off speed of the auxiliary transistor Q1 is slower than the turn-off speed of the power tube M2. When the power tube M2 is turned off, the auxiliary transistor Q1 is still in the on state, and a first crosstalk suppression path is formed between the gate of the power tube M1 and the high-side reference ground GNDH;

[0091] When the power tube M2 starts to shut down, the drain-source voltage of the power tube M1 suddenly changes, causing a negative dV / dt change. The dV / dt change acts on both ends of the Miller capacitor of the power tube M1, thereby generating a negative displacement current. If the crosstalk suppression circuit is not introduced, the displacement current will generate additional gate-source negative crosstalk voltage spikes through the lower drive loop. The gate-source negative crosstalk voltage spike may exceed the maximum gate-source breakdown negative voltage of the GaN tube, causing the GaN tube to break down. Due to the introduction of the crosstalk suppression circuit, the auxiliary transistor Q1 will be turned on to provide a low-resistance path, and the capacitor C1 will absorb the negative crosstalk voltage spike energy, suppressing the crosstalk caused by the power tube M2 being turned off.

[0092] During the period t1-t2, the auxiliary transistor Q1 is turned off;

[0093] During the period t2-t3, the high side and power tube are both in the off state, and the auxiliary transistors Q1 and Q2 are both in the off state;

[0094] At time t3, the first control signal PWM1 sends a start signal, and the start signal controls the power transistor M1 and the auxiliary transistor Q2 simultaneously through the dual-channel isolation chip 1;

[0095] During the period t3-t4, the power tube M1 is turned on, the power tube M2 is in the off state, the auxiliary transistor Q1 is in the off state, and the auxiliary transistor Q2 is turned on; when the auxiliary transistor Q2 is turned on, the gate resistance is the parallel connection of the resistors R6 and R7, and its turn-on speed is controlled by matching the resistor R7 with a smaller resistance value, so that the turn-on speed of the auxiliary transistor Q2 is faster than that of the power tube M1. Before the power tube M1 is turned on, the auxiliary transistor Q2 is already in the on state, and a second crosstalk suppression path is formed between the gate of the power tube M2 and the low-side reference ground GNDL;

[0096] During the period t4-t5, the power tube M1 starts to conduct, and the drain-source voltage of the power tube M2 suddenly changes, causing a positive dV / dt change. The dV / dt change acts on both ends of the Miller capacitor of the power tube M2, thereby generating a positive displacement current. If the crosstalk suppression circuit is not introduced, the displacement current will generate additional gate-source positive crosstalk voltage spikes through the upper drive loop. The gate-source positive crosstalk voltage spike may exceed its threshold voltage VTH and cause false start. Due to the introduction of the crosstalk suppression circuit, the auxiliary transistor Q2 will conduct to provide a low-resistance path, and the capacitor C2 absorbs the energy of the positive crosstalk voltage spike, suppressing the crosstalk caused by the power tube M1 being turned on at the moment of conduction;

[0097] During the period t5-t6, the power tube M1 is in the on state, the power tube M2 is in the off state, the auxiliary transistor Q1 is in the off state, and the auxiliary transistor Q2 is in the on state;

[0098] At time t6, the first control signal PWM1 sends a shutdown signal, and the startup signal controls the power transistor M1 and the auxiliary transistor Q2 simultaneously through the dual-channel isolation chip 1;

[0099] During the period t6-t7, the power tube M1 is turned off, the power tube M2 is in the off state, the auxiliary transistor Q1 is in the off state, and the auxiliary transistor Q2 is turned off; when the auxiliary transistor Q2 is turned off, the gate resistance is R6, and the turn-off speed of the auxiliary transistor Q6 is controlled by matching the gate resistance R6 with a larger resistance value, so that the turn-off speed of the auxiliary transistor Q2 is slower than the turn-off speed of the power tube M1. When the power tube M1 is turned off, the auxiliary transistor Q2 is still in the on state, and a second crosstalk suppression path is formed between the gate of the power tube M2 and the low-side reference ground GNDL;

[0100] When the power tube M1 starts to shut down, the drain-source voltage of the power tube M2 suddenly changes, causing a negative dV / dt change. The dV / dt change acts on both ends of the Miller capacitor of the power tube M2, thereby generating a negative displacement current. If the crosstalk suppression circuit is not introduced, the displacement current will generate additional gate-source negative crosstalk voltage spikes through the lower drive circuit. The gate-source negative crosstalk voltage spike may exceed the maximum gate-source breakdown negative voltage of the GaN tube, causing the GaN tube to break down. Due to the introduction of the crosstalk suppression circuit, the auxiliary transistor Q2 will be turned on to provide a low-resistance path, and the capacitor C2 will absorb the positive crosstalk voltage spike energy, suppressing the crosstalk caused by the moment when the power tube M1 is turned off;

[0101] During the period t7-t8, the auxiliary transistor Q2 is turned off;

[0102] During the period t8-t9, the high side and power tubes are both in the off state, and the auxiliary transistors Q1 and Q2 are both in the off state;

[0103] At time t9, the second control signal PWM2 sends a start signal, and the start signal controls the power transistor M2 and the auxiliary transistor Q1 simultaneously through the dual-channel isolation chip 2;

[0104] During the period t9-t10, the power tube M1 is in the off state, the power tube M2 is turned on, the auxiliary transistor Q1 is turned on, and the auxiliary transistor Q2 is in the off state; when the auxiliary transistor Q1 is turned on, the gate resistance is the parallel connection of the resistors R2 and R3, and its turn-on speed is controlled by matching the resistor R3 with a smaller resistance value, so that the turn-on speed of the auxiliary transistor Q1 is faster than that of the power tube M2. Before the power tube M2 is turned on, the auxiliary transistor Q1 is already in the on state, and a first crosstalk suppression path is formed between the gate of the power tube M1 and the high-side reference ground GNDH.

[0105] During the t10-t11 period, the power tube M2 begins to conduct, and the drain-source voltage of the power tube M1 suddenly changes, causing a positive dV / dt change. The dV / dt change acts on both ends of the Miller capacitor of the power tube M1, thereby generating a positive displacement current. If the crosstalk suppression circuit is not introduced, the displacement current will generate additional gate-source positive crosstalk voltage spikes through the upper drive loop. The gate-source positive crosstalk voltage spike may exceed its threshold voltage VTH and cause false start. Due to the introduction of the crosstalk suppression circuit, the auxiliary transistor Q1 will conduct to provide a low-resistance path, and the capacitor C1 absorbs the energy of the positive crosstalk voltage spike, suppressing the crosstalk caused by the power tube M2 being turned on at the moment;

[0106] After time t11, the power tube M2 starts to conduct, the power tube M1 is in the off state, and the half-bridge circuit starts the next cycle.

[0107] In order to compare the crosstalk suppression effect of the present invention in the half-bridge circuit, this embodiment builds a simulation circuit model based on LTspice software. The simulation circuit structure diagram is as follows: Figure 3 As shown. Among them, the power tube M1 and M2 models adopt the TP65H150G4LSG model provided by Transform, the Schottky diodes D1 and D2 in the crosstalk suppression circuit adopt the 1N5817 model, the auxiliary transistors Q1 and Q2 adopt the GS61008P model, and the capacitors C1 and C2 are 5uF. Compared with the traditional circuit without crosstalk suppression, the load inductance L0 of the simulation circuit model of this embodiment is 500uH, the load resistance R0 is 20Ω, the filter capacitor C0 is 5uF, and the DC input voltage VDC is 400V. The driving resistors R1 and R2 are 5Ω, the absorption capacitors C1 and C2 in the crosstalk suppression circuit are 5uF, the resistors R2 and R5 are 15Ω, the resistors R3 and R7 are 15Ω, and the resistors R4 and R8 are 10kΩ. The comparison results are shown in Figure 4 and Figure 5 As shown, according to the waveform, it can be known that when the conventional half-bridge driving circuit is not added with a crosstalk suppression circuit, affected by the crosstalk, the positive crosstalk voltage peak value of the gate-source voltage Vgs of the power tube M2 can reach 4V, and the negative crosstalk voltage peak value can reach -8V, and there are large oscillations at the moment of turning on and off the power tube M1; when the bridge arm crosstalk suppression circuit of the present invention is added, the positive and negative crosstalk voltages of the gate-source voltage Vgs of the power tube Q2 almost completely disappear.

[0108] The invention patent focuses on optimizing the performance of GaN HEMT half-bridge circuits, especially through innovative circuit design and control strategies, which effectively suppresses crosstalk conduction and gate reverse overshoot without sacrificing the normal shutdown speed of the device and without adding extra control signals, providing an innovative solution for improving the overall efficiency and reliability of GaN HEMT half-bridge circuits.

[0109] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A driving circuit for suppressing GaN HEMT bridge arm crosstalk, characterized in that: The driving circuit is connected to the GaN HEMT bridge arm, the GaN HEMT bridge arm includes an upper bridge arm circuit and a lower bridge arm circuit, and the upper bridge arm circuit has the same structure as the lower bridge arm circuit; The driving circuit comprises two crosstalk suppression circuits, namely a crosstalk suppression circuit in an upper bridge arm and a crosstalk suppression circuit in a lower bridge arm; the crosstalk suppression circuit in the upper bridge arm is used to suppress the crosstalk spike voltage in the high-side driving circuit; the crosstalk suppression circuit in the lower bridge arm is used to suppress the crosstalk spike voltage in the low-side driving circuit; The high-side driving circuit and the lower bridge arm crosstalk suppression circuit share a dual-channel isolation chip 1; The low-side driving circuit and the upper bridge arm crosstalk suppression circuit share a dual-channel isolation chip 2; The upper bridge arm circuit includes a power tube M1 gate circuit, and the power tube M1 gate circuit includes a dual-channel isolation chip 1, a power tube M1, and a resistor R1; The first signal output HOUT1 of the dual-channel isolation chip 1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the gate of the power tube M1; The lower bridge arm circuit includes a power tube M2 gate circuit, and the power tube M2 gate circuit includes a dual-channel isolation chip 2, a power tube M2, and a resistor R5; The second signal output LOUT2 of the dual-channel isolation chip 2 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the gate of the power tube M2. The crosstalk suppression circuit arranged in the upper bridge arm is a first crosstalk suppression circuit, and the first crosstalk suppression circuit includes a dual-channel isolation chip 2, an auxiliary transistor Q1, a diode D1, a resistor R2, a resistor R3, and a capacitor C1; The first signal output LOUT1 of the dual-channel isolation chip 2 is connected to one end of the resistor R2 and the resistor R3, the other end of the resistor R3 is connected to the anode of the diode D1, and the cathode of the diode D1 and the other end of the resistor R2 are commonly connected to the gate of the auxiliary transistor Q1; The drain of the auxiliary transistor Q1 is connected to the capacitor C1, and the other end of the capacitor C1 is connected to the gate of the power tube M1; The source of the auxiliary transistor Q1 is connected to the source of the power transistor M1; One end of the resistor R4 is connected to the gate of the power tube M1, and the other end is connected to the source of the power tube M1; The crosstalk suppression circuit arranged in the lower bridge arm is a second crosstalk suppression circuit, and the second crosstalk suppression circuit includes a dual-channel isolation chip 1, an auxiliary transistor Q2, a diode D2, a resistor R6, a resistor R7, and a capacitor C2; The second signal output HOUT2 of the dual-channel isolation chip 1 is connected to one end of the resistor R6 and the resistor R7, the other end of the resistor R7 is connected to the anode of the diode D2, and the cathode of the diode D2 and the other end of the resistor R6 are commonly connected to the gate of the auxiliary transistor Q2; The drain of the auxiliary transistor Q2 is connected to the capacitor C2, and the other end of the capacitor C2 is connected to the gate of the power transistor M2; The source of the auxiliary transistor Q2 is connected to the source of the power transistor M2; One end of the resistor R8 is connected to the gate of the power tube M2 , and the other end of the resistor R8 is connected to the source of the power tube M2 .

2. The driving circuit for suppressing GaN HEMT bridge arm crosstalk according to claim 1, characterized in that: The logic input of the dual-channel isolation chip 1 includes signal input terminals IN1-A and IN1-B, and the input terminals IN1-A and IN1-B are commonly connected to the first control signal PWM1; The logic input of the dual-channel isolation chip 2 includes signal input terminals IN2-A and IN2-B, and the input terminals IN2-A and IN2-B are commonly connected to the second control signal PWM2; The first output ground VEEH1 of the dual-channel isolation chip 1 and the first output ground VEEL1 of the dual-channel isolation chip 2 are connected to the high-side reference ground GNDH; The second output ground VEEH2 of the dual-channel isolation chip 1 and the second output ground VEEL2 of the dual-channel isolation chip 2 are connected to the low-side reference ground GNDL; The dual-channel isolation chip 1 and the dual-channel isolation chip 2 used are both isolated dual-channel gate drive chips. On the one hand, the chip logic input and output are isolated, and on the other hand, the two output channels are isolated from each other.

3. The driving circuit for suppressing GaN HEMT bridge arm crosstalk according to claim 1, characterized in that: By selecting the resistance values ​​of resistors R1, R2, R3, R5, R6 and R7, the switching speed of the auxiliary transistor and the power tubes of the upper bridge arm and the lower bridge arm in the circuit is controlled; The auxiliary transistor Q1 conducts faster than the power tube M2 turns off, and turns off slower than the power tube M2 conducts; The auxiliary transistor Q2 conducts faster than the power tube M1 and turns off slower than the power tube M1 conducts; The auxiliary transistors Q1 and Q2 are both low-voltage GaN switch tubes, and the switching speed of the auxiliary transistors should be faster than that of the power tubes; The resistance values ​​of resistors R1, R2, R3, R5, R6, and R7 should satisfy the following formula: R1≤R6, R5≤R2。 4. The driving circuit for suppressing GaN HEMT bridge arm crosstalk according to claim 3, characterized in that: The circuit's working cycle is divided into four stages: In the first stage, the first control signal PWM1 maintains a low level, and the second control signal PWM2 sends a shutdown signal; the power tube M1 is in the off state, the power tube M2 is turned off, the auxiliary transistor Q1 is turned off, and the auxiliary transistor Q2 is in the off state; the auxiliary transistor Q1 is turned off slowly, and when the power tube M2 is turned off, the auxiliary transistor Q1 is still in the on state, so that a first crosstalk suppression path is formed between the gate of the power tube M1 and the high-side reference ground GNDH, suppressing the crosstalk caused by the instant when the power tube M2 is turned off; In the second stage, the first control signal PWM1 sends a start signal, and the second control signal PWM2 maintains a low level; the power tube M1 is turned on, the power tube M2 is in the off state, the auxiliary transistor Q1 is in the off state, and the auxiliary transistor Q2 is turned on; the auxiliary transistor Q2 is turned on quickly, and when the power tube M1 is turned on, the auxiliary transistor Q2 is already turned on, so that a second crosstalk suppression path is formed between the gate of the power tube M2 and the low-side reference ground GNDL, suppressing the crosstalk caused by the moment the power tube M1 is turned on; In the third stage, the first control signal PWM1 sends a shutdown signal, and the second control signal PWM2 maintains a low level; the power tube M1 is turned off, the power tube M2 is in the off state, the auxiliary transistor Q1 is in the off state, and the auxiliary transistor Q2 is turned off; the auxiliary transistor Q2 is turned off slowly, and when the power tube M1 is turned off, the auxiliary transistor Q2 is still in the on state, so that a first crosstalk suppression path is formed between the gate of the power tube M2 and the low-side reference ground GNDL, suppressing the crosstalk caused by the moment when the power tube M1 is turned off; In the fourth stage, the first control signal PWM1 maintains a low level, and the second control signal PWM2 sends a start signal; the power tube M1 is in the off state, the power tube M2 is turned on, the auxiliary transistor Q1 is turned on, and the auxiliary transistor Q2 is in the off state; the auxiliary transistor Q1 is turned on quickly, and when the power tube M2 is turned on, the auxiliary transistor Q1 is already turned on, so that a second crosstalk suppression path is formed between the gate of the power tube M1 and the high-side reference ground GNDH, suppressing the crosstalk caused by the moment when the power tube M2 is turned on.

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