Cooperative suppression device and method for common-mode noise and neutral current of multi-level inverter

Abstract

The invention relates to the field of power electronics, and discloses a common-mode noise and neutral current collaborative suppression device and method for a multi-level inverter, and the device comprises a parallel 3L-NPC inverter, a common-mode conducted noise suppression circuit, a DC side linear impedance stabilization network, an AC side feed-through capacitor, and a load. The common-mode conducted noise suppression circuit comprises a direct-current side suppression circuit and an alternating-current side suppression circuit; one side of the parallel inverter is electrically connected with the DC power supply after passing through the DC suppression circuit and the DCLISN; the other side of the parallel inverter is electrically connected with a load after passing through an alternating current suppression circuit and an alternating current side feed-through capacitor; the method is mainly used for solving equivalent inductance equivalent to a circuit model and modulating carrier wave staggering. The technical defect that common-mode noise and neutral current of the parallel inverter cannot be obtained at the same time is overcome, the method is simple and easy to implement, the size of an EMI filter in a parallel inverter scene can be reduced, and the power density of equipment is increased.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and in particular to a device and method for cooperatively suppressing common-mode noise and neutral current of a multi-level inverter. Background Art

[0002] Since integrated power systems such as ships and aircraft do not have the conditions to connect to the large power grid, most of them use independent DC power supply systems to improve the endurance of ships. As the power of equipment becomes larger and larger, the transmission power of a single inverter can no longer meet the requirements of high-power inverter power supply systems. Modular multi-inverter parallel systems are widely used due to their flexibility in expanding system capacity, high reliability of redundant systems, and easy production and maintenance of modular equipment. The first diode midpoint clamped converter was invented by A. Nabae, I. Takahashi and H. Akagi in 1979 and was experimentally verified.

[0003] The invention of the three-level neutral point clamped (3L-NPC) converter marks the beginning of a new era in the field of power electronic inverter topology, known as the "multi-level inverter". The three-level inverter can output three levels of positive voltage, zero voltage and negative voltage. With its advantages of small switch tube voltage stress and low total harmonic distortion (THD), it has become the main topology of modular parallel inverter power supply.

[0004] Due to the limited space on the ship, the investment of a large number of power electronic equipment has also created an extremely complex electromagnetic environment. In the parallel inverter power supply using pulse width modulation technology (PWM), when the switch tube is turned on and off at high frequency and high speed, a large voltage jump (d v / dt) and current jump (d i / dt), these fast-changing voltages and currents contain abundant high-frequency harmonics, and will propagate through the conduction paths such as stray capacitance and stray inductance in the system, causing serious electromagnetic interference (EMI) problems. For example, serious electromagnetic interference will lead to equipment malfunction, motor shaft distortion and vibration, relay protection device failure or malfunction, sensitive equipment disconnection and failure, and other accidents.

[0005] The common-mode conducted electromagnetic interference problem of modular parallel inverters is studied. The existing suppression schemes can be divided into two categories: one is software-based suppression, which usually includes improved modulation and control methods. The modulation algorithm usually needs to sacrifice the total harmonic distortion of the converter, and the closed-loop control has very high requirements on the response speed of the system, and the ability to suppress high-frequency interference of MHz is limited.

[0006] The other type is based on hardware modification, which blocks the conduction path by improving the circuit topology and adding EMI filters. Among them, since the balanced bridge technology only requires the addition of passive devices and has a simple structure, domestic and foreign scholars often use it to suppress the electromagnetic interference of the converter. However, it only suppresses the common-mode interference on the AC side of the three-phase inverter, and does not take into account the common-mode interference suppression on both the DC and AC sides. Therefore, scholars are urgently needed to conduct in-depth research on the common-mode electromagnetic interference and neutral current problems of modular parallel-type mid-point clamped three-level inverter power supply. Summary of the invention

[0007] The purpose of the present invention is to propose a common-mode noise and neutral current collaborative suppression device and method for a multi-level inverter, so as to solve the technical problem that the common-mode noise and neutral current of a parallel NPC inverter cannot be eliminated simultaneously in the common-mode conducted electromagnetic interference of an existing modular parallel inverter.

[0008] Specifically, the present invention provides a common-mode noise and neutral current cooperative suppression device for a multi-level inverter, comprising: a parallel-type 3L-NPC inverter, a common-mode conduction noise suppression circuit, a DC-side linear impedance stabilization network DC_LISN, an AC-side through-hole capacitor and a load; The common mode conduction noise suppression circuit includes a DC side suppression circuit and an AC side suppression circuit; One side of the parallel 3L-NPC inverter is electrically connected to the DC power supply through the DC suppression circuit and the DC side linear impedance stabilization network DC_LISN; The other side of the parallel 3L-NPC inverter is electrically connected to the load through an AC suppression circuit and an AC measurement through-hole capacitor.

[0009] A method for cooperatively suppressing common-mode noise and neutral current of a multi-level inverter, applied to the suppression device, comprises the following steps: S1: Based on the circuit principle, the common-mode time-domain model of the parallel 3L-NPC inverter is simplified to obtain the common-mode equivalent frequency-domain model; S2: Based on the Wheatstone bridge principle, the common-mode equivalent frequency domain model is again equivalent to obtain the calibrated bridge model; S3: According to the superposition principle and the parameters of each component, the bridge model is further simplified to obtain the final equivalent circuit; S4: Based on the theoretical balance condition and the final equivalent circuit, the inductance value of the common mode inductor Ldc is solved; based on the solved inductance value, the common mode noise current is suppressed; S5: Stagger the modulated carriers of the two inverters in the parallel 3L-NPC inverter by 180° to eliminate the neutral current.

[0010] The beneficial effects provided by the present invention are: 1. By adding common-mode inductance on the DC side of the parallel-type midpoint clamped three-level inverter L dc , differential mode capacitance C x Construct the neutral point of the DC side and connect the neutral point of the AC and DC sides. First, establish the common-mode frequency domain model of the inverter and simplify it. Secondly, based on the balanced bridge theory, design the common-mode inductor of the DC side L dc The inductance of the AC and DC sides is used to suppress the common mode noise. At the same time, the addition of common mode inductance on the DC side effectively increases the impedance value of the neutral current loop, which is beneficial to reduce the neutral current.

[0011] 2. Through theoretical analysis of the neutral current component and voltage source, the modulation method of carrier staggered 180° is adopted to not only reduce the common mode voltage d v / dt, and at the same time, the odd-order components of the switching frequency in the neutral current cancel each other out, effectively reducing the neutral current value. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the structure of the device of the present invention; Figure 2 This is the schematic diagram of the 3L-NPC inverter; Figure 3 It is the schematic diagram of the DC side linear impedance network; Figure 4 It is the common-mode equivalent frequency domain model of the parallel 3L-NPC inverter; Figure 5 It is a schematic diagram of the bridge model; Figure 6 is the equivalent circuit diagram; Figure 7 This is a schematic diagram of the common mode voltage corresponding to the mutual interference of the working principle of the carrier in-phase stacking modulation method; Figure 8 This is a schematic diagram of the common mode voltage corresponding to the mutual interference of the working principle of the carrier anti-phase stacking modulation method; Fig. 9 It is a schematic diagram of carrier control signal; Fig.10 This is a schematic diagram of Fourier spectrum analysis of carrier inversion stacking modulation; Fig.11 The neutral current is 3 with carrier interleaving 180° i o Schematic diagram of the analysis spectrum for Fourier analysis; Fig.12 This is a comparison chart of the common-mode conducted electromagnetic interference spectrum on the DC side of a parallel-type midpoint clamped three-level inverter; Fig.13 This is a comparison chart of the common-mode conducted electromagnetic interference spectrum on the AC side of a parallel-type midpoint clamped three-level inverter; Fig.14 It is a neutral current diagram of a parallel type neutral point clamped three-level inverter using a carrier staggered 180° neutral line directly connected; Fig.15 The present invention discloses a neutral line current diagram of a parallel-type neutral point clamped three-level inverter using the common mode noise and neutral line circulating current coordinated suppression method proposed by the present invention. DETAILED DESCRIPTION

[0013] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0014] Before formally describing the present invention, the scheme of the present invention is first generally described for easy understanding.

[0015] Please refer to Figure 1 The present invention provides a common mode noise and neutral current cooperative suppression device for a multi-level inverter, comprising: Parallel 3L-NPC inverter, common mode conduction noise suppression circuit, DC side linear impedance stabilization network DC_LISN, AC side through-hole capacitor and load; The common mode conduction noise suppression circuit includes a DC side suppression circuit and an AC side suppression circuit; One side of the parallel 3L-NPC inverter is electrically connected to the DC power supply through the DC suppression circuit and the DC side linear impedance stabilization network DC_LISN; The other side of the parallel 3L-NPC inverter is electrically connected to the load through an AC suppression circuit and an AC measurement through-hole capacitor.

[0016] It should be noted that the parallel 3L-NPC inverter includes two, namely NPC inverter 1 and NPC inverter 2. The two inverters are connected in parallel, and before the other side of the parallel 3L-NPC inverter is connected to the AC suppression circuit, it also passes through the filter inductor L ac , where NPC inverter 1 corresponds to three inductors L of the three phases ac1 NPC inverter 2 corresponds to three inductors L of three phases ac2 .

[0017] Please refer to Figure 2 , Figure 2 This is the schematic diagram of the 3L-NPC inverter.

[0018] Each phase of each inverter contains 4 switching tubes S X1 ~S X4 and 2 diodes D X1 , D X2 And 6 parasitic capacitors C p1 -C p6 ; Where S X1 ~S X4 Insert them in series in the DC side; x1 and S x3 The emitter leads to a branch, and a diode D is connected in series on the branch. x1 and D x2 , where S x3 The emitter of the diode D x2 The positive pole of the diode D is electrically connected to x2 The negative electrode and D x1 The positive pole of the diode D is electrically connected to x1 The negative electrode and S x1 The emitter of the diode D is electrically connected to x2 The negative pole leads to the center point N; After the above connection method, the principle is as follows: When S X1 and S X2 When turned on, the inverter outputs a high level V dc / 2; when S X2 and D X1 , or, S X3 and D X2 When it is turned on, the inverter outputs zero level; when S X3 and S X4 When turned on, the inverter outputs a negative level -V dc / 2.

[0019] Please refer to Figure 1 , Figure 1 The bold part in the figure shows the common-mode conducted noise suppression circuit diagram of the present invention.

[0020] The common mode conduction noise suppression circuit includes a DC side suppression circuit and an AC side suppression circuit; It should be noted that the DC side suppression circuit includes: a common mode inductor L dc , 2 differential mode capacitors C x1 and C x2 , the differential mode capacitance Cx1 and C x2 One end is connected to the positive and negative busbars respectively, and the other ends are connected to each other to form the DC side neutral point N1; Common mode inductor L dc It is a whole body surrounded by a magnetic ring; the common mode inductor L dc One end is connected to the DC power supply, and the other end is connected to the input end of the parallel type 3L-NPC inverter.

[0021] It should be noted that the AC suppression circuit includes three filter capacitors C ac ; Among them, 3 filter capacitors C ac Use star connection to connect to the three-phase output bus respectively, and connect the other ends together to construct the neutral point O on the AC side; then directly connect the DC side neutral point N1 and the AC side neutral point O through conduction to construct a low-impedance return path.

[0022] The present invention mainly uses the Wheatstone bridge principle to design the DC side common mode inductor L dc value, theoretically, the common-mode current flowing through the linear impedance stabilization network on the DC side and the through-hole capacitor on the AC side is 0, thus achieving the suppression of common-mode noise in hardware.

[0023] For further information, please refer to Figure 3 , Figure 3 As shown, it is a schematic diagram of the DC side linear impedance network. It mainly measures the interference voltage emitted by the equipment under test (Equipment Under Test, EUT) along the power line to the power grid through the line impedance stabilization network. The measurement frequency is 10kHz-30MHz.

[0024] The specific principle of common-mode noise suppression for the parallel 3L-NPC inverter is described below.

[0025] Measuring the stray parameters of the 3L-NPC inverter, where Figure 2 C shown in p1 -C p6 are the relative parasitic capacitances of the NPC inverter, Figure 1 C shown in bus is the parasitic capacitance of the DC bus to ground.

[0026] A method for cooperatively suppressing common mode noise and neutral current of a multi-level inverter is applied to the suppression device, and the method comprises the following steps: S1: Based on the circuit principle, the common-mode time-domain model of the parallel 3L-NPC inverter is simplified to obtain the common-mode equivalent frequency-domain model; It should be noted that the common-mode time domain model of the parallel 3L-NPC inverter is simplified based on the circuit principle in the present invention. Figure 4 The common-mode equivalent frequency domain model of the proposed parallel 3L-NPC inverter is shown; specifically, the common-mode equivalent frequency domain model includes: capacitor C J1 , C J2 , C N , C g , differential mode capacitance C x (i.e. Figure 1 Middle C x1 or C x2 )、Equivalent common mode interference source V CM1 、V CM2 , the parasitic inductance L of the neutral line N1O o , Neutral line inductance L ac1 , L ac2 ; The equivalent common mode interference source V CM1 The positive electrode and capacitor C J1 One end of the inductor L ac1 One end of the inductor is electrically connected; ac The other end of the capacitor C g One end of the inductor L ac2 One end of the capacitor C is electrically connected; g The other end of the inductor L is grounded; ac2 The other end of the capacitor C J2 One end of the equivalent common mode interference source V CM2 The positive pole of the equivalent common mode interference source V CM2 The negative pole of the equivalent common mode interference source V CM1 The negative electrode, capacitor C N One end of the inductor L dc One end of the capacitor C is electrically connected; N The other end of the inductor is grounded; L dc The other end of the DC side linear impedance stabilization network DC_LISN, capacitor C x One end of the capacitor C is electrically connected; x The other end of the inductor L o One end of the inductor is electrically connected; o The other end of the capacitor C ac One end of the capacitor C is electrically connected; ac The other end of the capacitor C g One end is electrically connected.

[0027] Further references Figure 4 , Figure 4 The relevant equivalent parameters in are as follows: a) CapacitanceC J1 , C J2 : The output-side ground capacitance of two 3L-NPC inverters is composed of the ground capacitance of the IGBT (insulated gate bipolar transistor) in the NPC inverter. C p2 , C p3 , C p4 constitute: (1) b) Capacitance C N : It is the DC side ground capacitance of the parallel type 3L-NPC inverter, which is composed of the DC bus itself ground capacitance C bus And IGBT to ground capacitance C p1 , C p5 , C p6 constitute: (2) c) V CM1 、V CM2 : Equivalent common mode interference source, composed of three-phase output voltage V AN 、V BN 、V CN constitute: (3).

[0028] S2: Based on the Wheatstone bridge principle, the common-mode equivalent frequency domain model is again equivalent to obtain the calibrated bridge model; It should be noted that in order to apply the Wheatstone bridge principle, Figure 4 Equivalent conversion to Figure 5 The bridge model shown.

[0029] The equivalent bridge model is as follows: Equivalent common mode interference source V CM2 The positive electrode and the inductor L ac2 One end of the capacitor C J2 One end of the inductor is electrically connected; ac2 The other end of the inductor L ac1 One end of the capacitor C g One end of the capacitor C ac One end of the inductor is electrically connected; ac1 The other end of the capacitor C J1 One end of the equivalent common mode interference source V CM1 The positive pole of capacitor C is electrically connected;J1 The other end of the capacitor C J2 The other end of the capacitor C g The other end of the capacitor C N The other end of the DC side linear impedance stabilization network DC_LISN is electrically connected to the inductor. L dc The other end of the capacitor C x One end of the capacitor C is electrically connected; x The other end of the inductor L o One end of the inductor is electrically connected; o The other end of the capacitor C ac The other end of the inductor is electrically connected; L dc The other end is connected to the equivalent common mode interference source V CM1 Negative pole, equivalent common mode interference source V CM2 The negative pole is electrically connected.

[0030] S3: According to the superposition principle and the parameters of each component, the bridge model is further simplified to obtain the final equivalent circuit; It should be noted that according to the superposition theorem, the common-mode noise current flowing through the DC side impedance characteristic network and the AC side through-hole capacitor can be considered as V CM1 and V CM2 Act separately and then add up.

[0031] Due to the capacitance C x1 , C x2 , C ac They are all in the order of uF, and the parasitic inductance L of the neutral line N1O is o It is of nH order of magnitude. In the range of 10kHz-30MHz, branch N1O can be regarded as a short circuit, and its Wheatstone bridge circuit can be simplified to an equivalent circuit. Figure 6 shown.

[0032] Figure 6 The final equivalent circuit is as follows: Equivalent common mode interference source V CM1 The positive electrode of capacitor C J1 One end of the inductor L ac1 One end of the inductor is electrically connected; ac1 The other end of the capacitor C g 、Inductance L ac2 ,inductance L dc , DC side linear impedance stabilization network DC_LISN in parallel; capacitor C gThe other end of the capacitor C J1 The other end of the capacitor C is electrically connected to J1 The other end of the capacitor is C N With capacitor C J2 After the capacitors with the sum of the two are connected in series, the equivalent common mode interference source V CM1 of the negative electrode.

[0033] S4: Based on the theoretical balance conditions and the final equivalent circuit, solve the common mode inductance L dc The inductance value of the inductor is determined; the common mode noise current is suppressed based on the solved inductance value; By designing the DC side common mode inductor L dc The inductance value makes the balanced bridge balanced. Theoretically, the current flowing through DC_LISN and C g The common-mode current of the parallel-type 3L-NPC inverter can be suppressed by reducing the common-mode current to 0.

[0034] The theoretical balance condition is shown in formula (4), so the common mode inductance can be calculated in reverse L dc The inductance value.

[0035] (4) The hardware circuit part of the present invention can theoretically realize that the common mode noise current forms a circulation current inside the parallel type 3L-NPC inverter through the neutral line, thereby avoiding flowing to the port.

[0036] S5: Stagger the modulated carriers of the two inverters in the parallel 3L-NPC inverter by 180° to reduce the neutral line current.

[0037] It should be noted that the magnitude of the common-mode noise current is not only related to the noise source, but also depends on the conduction path impedance, which may cause the neutral current to i o Too large.

[0038] Neutral current 3 i o As shown in formula (5): (5).

[0039] The equivalent voltage source of the neutral current is the common-mode voltage source, as shown in formula (6): (6).

[0040] In actual engineering, in order to reduce the calculation amount of the signal processing chip (Digital Signal Processor, DSP), the parallel 3L-NPC inverter usually adopts carrier stacking modulation instead of space vector modulation.

[0041] Carrier stacking PWM modulation is to stack the triangular carrier in layers and compare it with the sine wave to generate rectangular pulses that change according to the sine law to control the opening and closing of the switch tube. According to the different carrier phases, it can be further divided into phase disposition PWM (PD PWM) and phase opposition disposition PWM (POD PWM). For diode clamped inverters, the upper carrier controls the switch tube. S x1 and S x3 When the modulation wave is larger than the upper carrier wave, S x1 Conductivity, S x3 Turn off; when it is less than the upper carrier, S x1 Shutdown, S x3 Similarly, when the modulation wave is larger than the download wave, S x2 Open, S x4 Shutdown; when the modulation wave is smaller than the download wave, S x2 Shutdown, S x4 Turned on to generate a driving signal.

[0042] The working principle of the carrier co-phase stacking modulation method is that the common mode voltage corresponding to the mutual interference is as follows Figure 7 As shown, the solid line U a1 ~ U c1 They are the modulation waves of the three phases of inverter 1, C 1 and C 2 are the two carriers of inverter 1, S a1 ~ S c1 They are the switching sequences of the three phases in the carrier cycle of inverter 1; the dotted lines U a2 ~ U c2 They are the modulation waves of the three phases of inverter 2, C 1 and C 2 are the two carrier waves of inverter 1. S a2 ~ S c2They are the switching sequences of the three phases in the carrier cycle of inverter 2. The bolded ones are the common-mode voltages of the parallel 3L-NPC inverters. It can be seen that the common-mode voltage peak value of the carrier in-phase stacked modulation method is the DC side voltage V dc / 3.

[0043] The working principle of carrier reverse stack modulation is as follows: Figure 8 As shown, the solid line U a1 ~ U c1 They are the modulation waves of the three phases of inverter 1, C 1 and C 2 are the two carriers of inverter 1, S a1 ~ S c1 They are the switching sequences of the three phases in the carrier cycle of inverter 1; the dotted lines U a2 ~ U c2 They are the modulation waves of the three phases of inverter 2, C 1 and C 2 are the two carrier waves of inverter 1. S a2 ~ S c2 They are the switching sequences of the three phases in the carrier cycle of inverter 2. The bolded ones are the common-mode voltages of the parallel 3L-NPC inverters. It can be seen that the common-mode voltage peak value of the carrier reverse stack modulation method is the DC side voltage V dc / 6. The common mode voltage peak of the carrier anti-phase stack is 1 / 2 of that of the in-phase stack, which helps to reduce the common mode noise, that is, helps to reduce the neutral current 3 i o size.

[0044] Neutral current of carrier reverse stack modulation method 3 i o Perform Fourier analysis to analyze the spectrum such as Fig.10 As shown, it can be seen that the main component of the neutral line current is the switching frequency sideband current of 15kHz (carrier frequency is 15kHz). The currents of the two inverter switching frequencies are superimposed on the neutral line, resulting in excessive current on the neutral line.

[0045] Therefore, as an embodiment, the carriers of inverter 1 and inverter 2 are staggered by 180° in the present invention. Fig. 9 , Fig. 9 is a schematic diagram of a carrier signal; specifically described as a solid line U a1 ~U c1 They are the modulation waves of the three phases of inverter 1, C 1 and C 2 are the two carriers of inverter 1, S a1 ~ S c1 They are the switching sequences of the three phases in the carrier cycle of inverter 1; the dotted lines U a2 ~ U c2 They are the modulation waves of the three phases of inverter 2, C 1 and C 2 are the two carrier waves of inverter 1. S a2 ~ S c2 They are the switching sequences of the three phases in the carrier cycle of inverter 2. The bolded ones are the common-mode voltages of the parallel 3L-NPC inverters. The common-mode voltage peak value of the carrier staggered 180° modulation method is the DC side voltage V dc / 3, but the voltage jump is only V dc / 12, which helps to reduce d v / dt.

[0046] Since the carriers are staggered 180°, the odd-numbered carrier currents of inverter 1 and inverter 2 have equal amplitudes and opposite phases, and the vector sum is 0, thus achieving neutral current 3 i o The odd-numbered components of 15kHz cancel each other out, and the even-numbered components are doubled.

[0047] Neutral current of carrier wave staggered 180°3 i o Perform Fourier analysis to analyze the spectrum such as Fig.11 As shown, it can be seen that the switching frequency sideband currents of 15kHz (carrier frequency is 15kHz) in the neutral current have canceled each other out, leaving only the 3 times frequency component introduced by controlling the midpoint potential and the even-multiple frequency sideband current of 30kHz.

[0048] Example: In order to verify the effect of the common-mode noise and neutral line circulating current collaborative suppression method of parallel-type neutral point clamped three-level inverters, a simulation model was built in ANSYS Electronics Desktop software using two 3L-NPC inverters as examples. In the simulation, the DC input is 800V, the AC output is 380V, and the three-phase resistive inductive load is 200kW. The inverter adopts carrier anti-phase cascade modulation and the proposed method for comparative analysis.

[0049] Fig.12 The comparison diagram of the common-mode conducted electromagnetic interference spectrum on the DC side of the parallel-type midpoint clamped three-level inverter is shown. Among them, the light gray solid line is the common-mode conducted interference spectrum on the DC side with carrier inversion stacking, and the dark gray dotted line is the common-mode conducted interference spectrum on the DC side with carrier staggered 180°. It can be seen that the equivalent frequency of carrier staggered 180° is 30kHz, and increasing the switching frequency is helpful for subsequent filter design. The black implementation is the common-mode conducted interference spectrum on the DC side using the common-mode noise and neutral line circulating current collaborative suppression method proposed in the present invention, which not only can have an equivalent switching frequency of 30kHz, but also in the range of 10kHz-10MHz, the common-mode conducted electromagnetic interference spectrum on the DC side is attenuated by 10-30dBμV.

[0050] Fig.13 The comparison diagram of the common-mode conducted electromagnetic interference spectrum of the AC side of the parallel-type midpoint clamped three-level inverter is shown. Among them, the light gray solid line is the common-mode conducted interference spectrum of the DC side with carrier anti-phase stacking, and the dark gray dotted line is the common-mode conducted interference spectrum of the DC side with carrier staggered 180°. It can be seen that the equivalent frequency of the carrier staggered 180° is 30kHz, and increasing the switching frequency is helpful for the subsequent filter design. The black implementation is the common-mode conducted interference spectrum of the DC side using the common-mode noise and neutral line circulating current collaborative suppression method proposed in the present invention. Not only can the equivalent switching frequency be 30kHz, but also in the range of 10kHz-10MHz, the common-mode conducted electromagnetic interference spectrum of the AC side is attenuated by 10-30dBμV.

[0051] Fig.13 The neutral line current diagram of a parallel-type neutral point clamped three-level inverter directly connected to the neutral line using a carrier anti-phase stacked neutral line is shown.

[0052] It can be seen that without any measures being taken, the peak current of the neutral line is as high as 180A when the neutral line is directly connected.

[0053] Fig.14 The figure shows the neutral current diagram of the parallel type neutral point clamped three-level inverter with carrier staggered 180° and neutral line directly connected. It can be seen that when the carrier is staggered 180° and the neutral line is directly connected, the odd harmonics of the switching frequency in the neutral current cancel each other out, and the current peak is 75A, which is only Fig.13 42% of the neutral current.

[0054] Fig.15 The figure shows the neutral line current diagram of the parallel type neutral point clamped three-level inverter using the common mode noise and neutral line circulating current collaborative suppression method proposed by the present invention. It can be seen that the current peak is 20A, which is only Fig.13 11% of the neutral current is Fig.14 27% of the neutral current.

[0055] The beneficial effects of the present invention are as follows: the software part of the device and method proposed in the present invention is based on carrier modulation, which is simpler than the background technology solution, easy to implement in DSP, and effectively reduces the amount of digital calculation; the present invention simultaneously suppresses the common-mode noise on the AC and DC sides of the parallel-type neutral-point clamped three-level inverter, which takes more into account than the single-ended noise suppression in the background technology, and is helpful for the subsequent design of filters at both ends of the AC and DC; the present invention realizes the coordinated suppression of common-mode noise and neutral line circulating current, which is more comprehensive than the background technology that only suppresses common-mode noise, and effectively reduces the neutral line current.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A common mode noise and neutral current cooperative suppression device for a multi-level inverter, characterized in that: include: Parallel 3L-NPC inverter, common mode conduction noise suppression circuit, DC side linear impedance stabilization network DC_LISN, AC side through-hole capacitor and load; The common mode conduction noise suppression circuit includes a DC side suppression circuit and an AC side suppression circuit; One side of the parallel 3L-NPC inverter is electrically connected to the DC power supply through the DC suppression circuit and the DC side linear impedance stabilization network DC_LISN; The other side of the parallel 3L-NPC inverter is electrically connected to the load through an AC suppression circuit and an AC measurement through-hole capacitor.

2. The common mode noise and neutral current cooperative suppression device of a multi-level inverter according to claim 1, characterized in that: The DC side suppression circuit includes: a common mode inductor L dc , 2 differential mode capacitors C x1 and C x2 , the differential mode capacitance C x1 and C x2 One end is connected to the positive and negative busbars respectively, and the other end is connected to each other to form a DC side neutral point N1; the common mode inductor L dc One end is connected to the DC power supply, and the other end is connected to the input end of the parallel type 3L-NPC inverter.

3. The common mode noise and neutral current cooperative suppression device of a multi-level inverter according to claim 2, characterized in that: The AC suppression circuit includes three filter capacitors C ac ; Among them, 3 filter capacitors C ac Use star connection to connect to the three-phase output bus respectively, and connect the other ends together to construct the neutral point O on the AC side; then directly connect the DC side neutral point N1 and the AC side neutral point O through conduction to construct a low-impedance return path.

4. The common mode noise and neutral current cooperative suppression device of a multi-level inverter according to claim 3, characterized in that: In the parallel 3L-NPC inverter, each phase of each inverter contains 4 switch tubes S X1 ~S X4 and 2 diodes D X1 , D X2 And 6 parasitic capacitors C p1 -C p6 ; Where S X1 ~S X4 Insert them in series in the DC side; x1 and S x3 The emitter leads to a branch, and a diode D is connected in series on the branch. x1 and D x2 , where S x3 The emitter of the diode D x2 The positive pole of the diode D is electrically connected to x2 The negative electrode and D x1 The positive pole of the diode D is electrically connected to x1 The negative electrode and S x1 The emitter of the diode D is electrically connected to x2 The negative pole leads to the center point N; When S X1 and S X2 When turned on, the inverter outputs a high level V dc / 2; when S X2 and D X1 , or, S X3 and D X2 When it is turned on, the inverter outputs zero level; when S X3 and S X4 When turned on, the inverter outputs a negative level -V dc / 2.

5. A method for cooperatively suppressing common mode noise and neutral current of a multi-level inverter, applied to the suppression device according to any one of claims 1 to 4, characterized in that: The method comprises the following steps: S1: Based on the circuit principle, the common-mode time-domain model of the parallel 3L-NPC inverter is simplified to obtain the common-mode equivalent frequency-domain model; S2: Based on the Wheatstone bridge principle, the common-mode equivalent frequency domain model is again equivalent to obtain the calibrated bridge model; S3: According to the superposition principle and the parameters of each component, the bridge model is further simplified to obtain the final equivalent circuit; S4: Based on the theoretical balance conditions and the final equivalent circuit, solve the common mode inductance L dc The inductance value of the inductor is determined; the common mode noise current is suppressed based on the solved inductance value; S5: Stagger the modulated carriers of the two inverters in the parallel 3L-NPC inverter by 180° to reduce the neutral line current.

6. The method for cooperatively suppressing common mode noise and neutral current of a multi-level inverter according to claim 5, characterized in that: The common-mode equivalent frequency domain model in step S1 includes: capacitor C J1 , C J2 , C N , C g , differential mode capacitance C x , equivalent common mode interference source V CM1 、V CM2 , the parasitic inductance L of the neutral line N1O o , AC side filter inductor L ac1 , L ac2 ; The equivalent common mode interference source V CM1 The positive electrode and capacitor C J1 One end of the inductor L ac1 One end of the inductor is electrically connected; ac1 The other end of the capacitor C g One end of the inductor L ac2 One end of the capacitor C is electrically connected; g The other end of the inductor L is grounded; ac2 The other end of the capacitor C J2 One end of the equivalent common mode interference source V CM2 The positive pole of the equivalent common mode interference source V CM2 The negative pole of the equivalent common mode interference source V CM1 The negative electrode, capacitor C N One end of the inductor L dc One end of the capacitor C is electrically connected; N The other end of the inductor is grounded; L dc The other end of the DC side linear impedance stabilization network DC_LISN, capacitor C x One end of the capacitor C is electrically connected; x The other end of the inductor L o One end of the inductor is electrically connected; o The other end of the capacitor C ac One end of the capacitor C is electrically connected; ac The other end of the capacitor C g One end of the device is electrically connected to the other end; The capacitance C J1 , C J2 The calculation formula is as follows: (1)， Capacitor C N The calculation formula is as follows: (2)， V CM1 、V CM2 The three-phase output voltage V AN 、V BN 、V CN The calculation formula is as follows: (3).

7. A method for cooperatively suppressing common mode noise and neutral current of a multi-level inverter according to claim 6, characterized in that: In step S2, the equivalent bridge model is as follows: Equivalent common mode interference source V CM2 The positive electrode and the inductor L ac2 One end of the capacitor C J2 One end of the inductor is electrically connected; ac2 The other end of the inductor L ac1 One end of the capacitor C g One end of the capacitor C ac One end of the inductor is electrically connected; ac1 The other end of the capacitor C J1 One end of the equivalent common mode interference source V CM1 The positive pole of capacitor C is electrically connected; J1 The other end of the capacitor C J2 The other end of the capacitor C g The other end of the capacitor C N The other end of the DC side linear impedance stabilization network DC_LISN is electrically connected to the inductor. L dc The other end of the capacitor C x One end of the capacitor C is electrically connected; x The other end of the inductor L o One end of the inductor is electrically connected; o The other end of the capacitor C ac The other end of the inductor is electrically connected; L dc The other end is connected to the equivalent common mode interference source V CM1 Negative pole, equivalent common mode interference source V CM2 The negative pole is electrically connected.

8. The method for cooperatively suppressing common mode noise and neutral current of a multi-level inverter according to claim 7, characterized in that: The final equivalent circuit in step S3 is as follows: Equivalent common mode interference source V CM1 The positive electrode of capacitor C J1 One end of the inductor L ac1 One end of the inductor is electrically connected; ac1 The other end of the capacitor C g 、Inductance L ac2 ,inductance L dc , DC side linear impedance stabilization network DC_LISN in parallel; capacitor C g The other end of the capacitor C J1 The other end of the capacitor C is electrically connected; J1 The other end of the capacitor is C N With capacitor C J2 After the capacitors with the sum of the two are connected in series, the equivalent common mode interference source V CM1 of the negative electrode.

9. A method for collaboratively suppressing common mode noise and neutral current of a multi-level inverter, characterized in that: In step S4, the common mode inductance is solved L dc The formula for the inductance value is as follows: .

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