Fractional order second harmonic current suppression method of single-phase dual-mode boost inverter

Abstract

The invention discloses a fractional order second harmonic current suppression method for a single-phase dual-mode boost inverter, and the method comprises the steps: regulating and controlling the bus voltage of the single-phase inverter into a partial sine waveform and a constant direct waveform through dual-mode control, and enabling a front-stage Boost circuit to work at a high frequency and a rear-stage inverter to work at a low frequency in a partial sine waveform interval of the bus; and in a bus constant direct waveform interval, the front-stage Boost circuit works at low frequency, and the rear-stage inverter works at high frequency. The dual-mode control does not need to maintain the bus voltage at a relatively high constant value, so that the required bus capacitance is greatly reduced, the size of the device is reduced, and meanwhile, the switching and conduction loss is reduced. In addition, the fractional order second harmonic current suppression branch circuit is formed by connecting virtual capacitors Cfoc and C1 in series, the virtual capacitor Cfoc is composed of an inductor Lb, a capacitor C2 and half-bridge switching tubes Sb and Sc, and when the instantaneous power of the fractional order suppression branch circuit and the secondary pulsating power output by the inverter are equal in amplitude and complementary in phase, the inverter is switched on. And the complete suppression of the input second harmonic current can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of electric energy conversion and control and electric energy quality, and in particular to a fractional-order second harmonic current suppression method of a single-phase dual-mode boost inverter. Background Art

[0002] Under the background of "dual carbon", the two-stage single-phase Boost inverter (BI) serves as an important interface link for connecting new energy power generation and distributed energy storage equipment such as solar energy and fuel cells to the power grid. It has the advantages of wide input voltage range and flexible control of front and rear circuits. However, this structure requires a large electrolytic capacitor for the DC bus and has two-stage energy conversion links, resulting in a large system size, complex structure and low efficiency. In addition, the secondary pulsating power in the inverter output power will bring secondary harmonic current components to the input DC power supply, reducing power supply utilization and service life.

[0003] In response to the above-mentioned problems of low efficiency and power density, scholars have studied dual-mode inverters in recent years, such as "dual-mode time-sharing sinusoidal modulation inverter (DMI)", "Aalborg inverter", etc. Such achievements have improved efficiency and power density, but have not mentioned the problem of second harmonic current suppression. Of course, there are more studies on the suppression of second harmonic current of input DC power supply, such as "suppression method based on passive components", "suppression method based on DC-DC converter control", "suppression method using second harmonic current compensator", "suppression method based on fractional order capacitor (foc) theory", etc. In summary, the suppression methods of second harmonic current can be roughly divided into two categories: one is to suppress second harmonic current from the perspective of system control, and the other is to absorb second harmonic current by adding additional auxiliary circuits on the DC side or AC side; these methods can suppress second harmonic current to varying degrees, but the power switch tubes of the front and rear circuits are always in high-frequency working state, which is not conducive to the improvement of efficiency and power density. The following are common solutions:

[0004] Option 1: As attached Figure 1As shown in the figure, a two-stage time-sharing dual-mode sinusoidal modulation inverter (DMI) circuit topology is adopted. Compared with the traditional two-stage single-phase Boost inverter, the difference between this structure and the previous stage Boost circuit is that a bypass diode is connected in parallel. When the subsequent stage inverter is PWM modulated, the previous stage Boost circuit is bypassed by the diode, further reducing the conduction loss of the inductor. In addition, the front and rear stages realize high-frequency and low-frequency dual-mode operation according to the selective time-sharing sinusoidal PWM modulation strategy. The power switch tube does not need to be in the high-frequency state all the time, which reduces the switching and conduction losses, but cannot suppress the second harmonic current of the input power supply.

[0005] Option 2: As attached Figure 2 As shown in the figure, a differential boost inverter (DBI) circuit topology is adopted. DBI is actually composed of two Boost converters, which can operate in differential mode (DM) and common mode (CM) dual modes. The differential mode (DM) mode is used for sinusoidal AC output voltage regulation and active power conversion, and the common mode (CM) mode is used for power decoupling, thereby achieving the suppression of second harmonic current; but two input inductors and two bus capacitors are required, and it is easy to generate circulating current between the input and output, which reduces the power conversion efficiency and the control strategy is relatively complicated.

[0006] Option 3: As attached Figure 3 As shown, an additional topological structure of a second harmonic suppression branch based on fractional-order capacitors is adopted, and a fractional-order suppression branch is connected in parallel on the DC bus side to absorb the second harmonic current; by adjusting the port voltage of the fractional-order capacitor and the AC component of the actual capacitor port voltage connected in series, the amplitude of the second harmonic is equal and the phase is opposite, so that the fractional-order suppression branch presents zero impedance to the second harmonic current, and the absorption of the second harmonic current is achieved while the bus capacitance is relatively reduced, thus avoiding the harm of the secondary current to the DC power supply. However, this method adds an additional auxiliary circuit, increases the size of the device, and the power switch tube in the circuit is always in a high-frequency working state, which is not conducive to reducing losses. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a method for suppressing fractional-order second harmonic current of a single-phase dual-mode boost inverter, and adopt high-frequency-low-frequency dual-mode control for a traditional two-stage single-phase Boost inverter to solve the problems of low inverter efficiency and power density. At the same time, a suppression branch based on fractional-order capacitors is adopted on the DC bus side to absorb the second harmonic current on the DC side, so as to overcome the problem of harm caused by the second harmonic current being connected to the DC power supply.

[0008] In order to solve the above technical problems, the present invention provides a method for suppressing fractional-order second harmonic current of a single-phase dual-mode boost inverter, including high-frequency-low-frequency dual-mode control of a two-stage single-phase Boost inverter and power decoupling control of a bus-side parallel fractional-order second harmonic current suppression branch.

[0009] In a preferred embodiment: the method is applied to a second harmonic current suppression circuit of a single-phase dual-mode boost inverter, the second harmonic current suppression circuit of the single-phase dual-mode boost inverter comprises a two-stage single-phase Boost boost inverter and a fractional-order second harmonic current suppression branch connected in parallel with a busbar;

[0010] The two-stage single-phase Boost inverter is composed of a front-stage Boost circuit and a rear-stage full-bridge inverter. The front-stage Boost circuit consists of an energy storage inductor L a , freewheeling diode VD, power switch tube S a , energy storage capacitor C a The inductor L a One end is connected to the input DC power supply U i The positive pole, the other end is connected to the anode of the freewheeling diode VD, and the power switch tube S a The drain is connected to the VD anode, and the capacitor C a The positive electrode is connected to the cathode of VD, and the capacitor C a Negative electrode and S a The source is connected to the DC power supply U i Negative pole. The rear full-bridge inverter consists of four power switch tubes S1, S2, S3, and S4 and an LC filter circuit. The complementary power switch tubes S1 and S2 form one bridge arm, and the other bridge arm consists of the complementary power switch tubes S3 and S4. The two ends of the two bridge arms are connected to the capacitor C a The positive and negative electrodes of the bridge arm are connected to the filter inductor L and one end of the filter capacitor C, and the output load R is connected to the common point of the filter inductor L and the filter capacitor C and the other end of the capacitor C;

[0011] The fractional-order second harmonic current suppression branch is composed of two power switch tubes S which are complementary turned on in a half-bridge form. b , S c With inductance L b , capacitor C2 forms a fractional capacitor C foc , and then connected in series with capacitor C1. Power switch tube S b , S c One end of the half-bridge arm is connected to the positive pole of the DC bus, and the other end is connected to the negative pole of the DC bus. The negative pole of capacitor C1 is connected to the positive pole of capacitor C2, that is, the negative pole of C1 is connected to the fractional-order virtual capacitor C foc The positive poles of capacitor C1 are connected to the positive pole of the DC bus, and the fractional-order virtual capacitor C focThe negative pole is connected to the negative pole of the DC bus, and the inductor L b One end is connected to the midpoint of the half bridge arm, and the other end is connected to C1 and C foc Connect the midpoint and control S b , S c The on-off of C1 and C foc The port voltage amplitudes are equal and the phases are complementary.

[0012] In a preferred embodiment: the two-stage single-phase Boost inverter high-frequency-low-frequency dual-mode control includes the front-stage Boost circuit control and the rear-stage single-phase inverter control, and the bus voltage is regulated into two waveforms: partial sine and constant direct.

[0013] Specifically, according to the input DC power supply voltage U i and the actual desired single-phase full-bridge inverter output sinusoidal voltage By comparing the size of the bus voltage, the bus voltage is adjusted to two waveforms, partial sine and constant value, through the voltage single closed-loop PI control, to achieve dual-mode switching of high-frequency and low-frequency operation of the front-stage Boost circuit and the rear-stage full-bridge inverter.

[0014] In a preferred embodiment: When the bus voltage is adjusted to correspond to The peak and trough of the partial sine waveform are calculated by the program The bus reference command voltage signal u of the sinusoidal waveform of the peak and trough parts aref , by collecting the DC side capacitor C a Port voltage u a With reference command voltage u aref The difference is input into the front-stage Boost voltage loop PI controller, and the power switch tube S is controlled through sinusoidal pulse width modulation. a In the peak part, the power switch tubes S1 and S4 of the rear inverter are always on, and the power switch tubes S2 and S3 are always off. In the trough part, the power switch tubes S1 and S4 of the rear inverter are always off, and the power switch tubes S2 and S3 are always on, which reduces the switching loss of the inverter power devices. At this time, the front-stage Boost circuit works at a high frequency, and the rear-stage inverter works at a low frequency.

[0015] In a preferred embodiment: When the bus voltage is regulated to a constant waveform, the program calculates Reference command voltage signal u of the middle waveform oref , by collecting the output load R port voltage u o With reference command voltage u orefThe difference is input into the voltage loop PI controller of the subsequent inverter, and the on and off of the four power switch tubes S1, S2, S3, and S4 are controlled through sinusoidal pulse width modulation. a It is always off, which reduces the switching and conduction losses of the power devices in the Boost circuit and improves efficiency. At this time, the front-stage Boost circuit works at a low frequency, and the rear-stage inverter works at a high frequency.

[0016] In a preferred embodiment: the power decoupling control of the fractional-order second harmonic current suppression branch is specifically divided into using capacitors C1 and C foc Voltage outer loop, inductance L b Double closed-loop PI control of the current inner loop;

[0017] By collecting the sinusoidal AC voltage u at the output load R port of the subsequent full-bridge inverter o and current i o , calculate the secondary pulsation power P in the output power o-2nd , according to the fractional-order branch instantaneous power P foc With P o-2nd The amplitude is equal, the phase is complementary, and the power decoupling is used to calculate the reference voltage signal u of capacitor C2. C2-ref , we can know that the terminal voltage u of C2 C2 With the fractional virtual capacitor C foc The port voltage u Cfoc Equal, reference voltage u Cfoc-ref It is also equal to u C2-ref；

[0018] By collecting the voltage u at the C2 port C2 , which is the fractional-order virtual capacitance C foc The port voltage u Cfoc , and the fractional virtual capacitor reference voltage u Cfoc-ref The difference is sent to the voltage outer loop PI controller, and its output is used as the inductor L b The reference current signal of the current inner loop is then compared with the collected inductance L b Current i Lb The difference is sent to the current inner loop PI controller, and the PWM wave is generated through sinusoidal pulse width modulation to control the power switch tube S b , S c The turn-on and turn-off of

[0019] When the capacitance C2 of the fractional-order second harmonic current suppression branch is equal to the series capacitance C1, a very small capacitance value can be selected theoretically at the double frequency, and power decoupling control is used to achieve that the instantaneous power of the fractional-order second harmonic current suppression branch is equal to the secondary pulsating power amplitude output by the subsequent full-bridge inverter, and the phases are complementary.

[0020] In a preferred embodiment: According to the high-frequency-low-frequency dual-mode control, the fractional-order virtual capacitor C is solved piecewise. foc The modulation voltage.

[0021] In a preferred embodiment: the voltage u1 of the capacitor C1 of the fractional-order second harmonic current suppression branch C1 and fractional-order virtual capacitance C foc The terminal voltage u Cfoc It is an AC signal with DC bias. Its AC component shows secondary pulsating power balance to the second harmonic current. It is necessary to satisfy the voltage amplitude equality and phase complementarity, and at the same time satisfy the capacitors C1 and C foc The terminal voltage u C1 、u Cfoc The sum is equal to the DC bus voltage.

[0022] In a preferred embodiment: the high-frequency-low-frequency dual-mode control segmented solution of the fractional-order virtual capacitor C foc The modulation voltage is calculated by solving the fractional capacitor C in the high-frequency and low-frequency regions according to the power constraint and DC bus voltage constraint. foc Port voltage u Cfoc The numerical solution of the first-order differential equation is used to calculate the fractional virtual capacitance C foc The port reference voltage u Cfoc-ref The modulation voltage.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1) High-frequency-low-frequency dual-mode control adjusts the inverter bus voltage into two waveforms: partial sine and constant DC. It does not need to be maintained at a higher constant DC voltage. The bus capacitance is greatly reduced, the device size is reduced, and the device power density is improved.

[0025] 2) When the front-stage Boost circuit works at a low frequency, the power switch tube Sa is in the cut-off state; when the rear-stage inverter works at a low frequency, it only relies on a pair of power switch tubes to be directly turned on, which reduces switching and conduction losses and improves efficiency.

[0026] 3) The front-stage Boost circuit has completed the control of the peaks and troughs of the output sinusoidal AC voltage, while the rear-stage full-bridge inverter mainly completes the pulse width modulation control of the waveform in the middle section of the sinusoidal voltage. It does not require a higher DC inverter voltage, reducing the power required for inverter.

[0027] 4) The second harmonic current suppression branch of the busbar portable plug-in fractional capacitor absorbs the second harmonic current on the DC side, which is easy to control and improves the power supply efficiency and service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a circuit schematic diagram of a time-sharing dual-mode sinusoidal modulation inverter (DMI) in solution 1 of the background technology;

[0029] Figure 2 It is a circuit schematic diagram of a differential boost inverter DB I in solution 2 of the background technology;

[0030] Figure 3 It is the second harmonic suppression branch topology of the three-fractional-order capacitor in the background technology solution;

[0031] Figure 4 It is a circuit schematic diagram of a single-phase dual-mode boost inverter with a fractional-order second harmonic current suppression branch;

[0032] Figure 5 It is a control block diagram of the second harmonic current suppression method of the single-phase dual-mode boost inverter according to the present invention;

[0033] Figure 6 The switch drive waveform of the high-frequency-low-frequency dual-mode control of the single-phase dual-mode boost inverter of the present invention and the corresponding Boost circuit inductor L a Current and Capacitance C a Voltage waveform diagram;

[0034] Figure 7 It is a working mode analysis diagram of high-frequency-low-frequency dual-mode control of the single-phase dual-mode boost inverter of the present invention;

[0035] Figure 8 It is the basic working waveform diagram of the fractional-order second harmonic current suppression branch of the present invention;

[0036] Fig. 9 It is a working modal analysis diagram of the fractional-order second harmonic current suppression branch described in the present invention;

[0037] Fig.10 It is a bus voltage, output voltage and current waveform diagram of the single-phase dual-mode boost inverter described in the present invention;

[0038] Fig.11 It is the input current waveform and FFT spectrum diagram before and after the fractional-order second harmonic current suppression branch is added as described in the present invention;

[0039] Fig.12 This is a comparison chart of the efficiency of the single-phase dual-mode controlled boost inverter of the present invention and the single-phase boost inverter of the traditional control method. DETAILED DESCRIPTION

[0041] In order to make the technical solutions and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific examples. It should be understood that these examples are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0042] This embodiment proposes a method for suppressing fractional second harmonic current of a single-phase dual-mode inverter. Aiming at the problems of large size, low power density, low efficiency and second harmonic interference of input power supply of the traditional two-stage single-phase Boost inverter, the improvement is mainly that the single-phase Boost inverter adopts high-frequency-low-frequency dual-mode control, and according to the input DC power supply voltage U i And the actual desired output sinusoidal AC voltage u o * Comparison of size, the front-stage Boost circuit regulates the DC bus voltage into two waveforms: partial sine and constant DC. When the bus is a sinusoidal curve section, the front-stage Boost circuit switch tube works at high frequency, and the rear-stage full-bridge inverter selects the signal according to the sinusoidal half-cycle, relying only on a pair of power switch tubes to work at low frequency, reducing switching losses. In the constant DC section of the bus voltage, the front-stage Boost circuit is in the cut-off state, and the four power switch tubes of the rear-stage full-bridge inverter work at high frequency modulation, reducing conduction losses. The bus voltage of the inverter controlled by high-frequency-low-frequency dual-mode does not need to be maintained at a relatively high constant DC voltage. The bus capacitor C a The device volume is greatly reduced, and the power density is improved. At the same time, a fractional-order second harmonic current suppression branch is connected in parallel on the bus side, and a fractional-order virtual capacitor C is used. foc The voltage outer loop of the series capacitor C1 and the inductor L b The double closed-loop PI control of the current inner loop makes the capacitor C foc and the terminal voltage u of capacitor C1 Cfoc and u C1 The AC components of the busbars have equal amplitudes and complementary phases, and satisfy the busbar voltage constraints in both the busbar sinusoidal curve and the constant DC section, and also satisfy the fractional-order branch instantaneous power P foc And the output secondary pulsation power P o-2nd The power decoupling constraints of equal amplitude and complementary phase enable the second harmonic current on the DC side to be absorbed by the fractional-order suppression branch, avoiding it from flowing into the DC power supply, thereby improving the power supply efficiency and service life.

[0043] As attached Figure 4 As shown, the single-phase dual-mode boost inverter with a fractional-order second harmonic current suppression branch of the present invention comprises a front-stage Boost boost circuit, a rear-stage single-phase full-bridge inverter and a busbar-connected fractional-order second harmonic current suppression branch, wherein the front-stage Boost boost circuit is composed of an energy storage inductor La , freewheeling diode VD, power switch tube S a , energy storage capacitor C a The inductor L a One end is connected to the input DC power supply U i The positive pole, the other end is connected to the anode of the freewheeling diode VD, and the power switch tube S a The drain is connected to the VD anode, and the capacitor C a The positive electrode is connected to the cathode of VD, and the capacitor C a Negative electrode and S a The source is connected to the DC power supply U i negative electrode;

[0044] The post-stage single-phase inverter is composed of four power switch tubes S1, S2, S3, and S4 and an LC filter circuit, wherein the complementary power switch tubes S1 and S2 form a bridge arm, and the other bridge arm is composed of the complementary power switch tubes S3 and S4, thereby forming a single-phase full bridge, and the two ends of the two bridge arms are respectively connected to the bus capacitor C a The positive and negative poles of the bridge arm are connected to the filter inductor L and one end of the filter capacitor C, and the output load R is connected to the common point of the filter inductor L and the filter capacitor C and the other end of the capacitor C.

[0045] The fractional-order second harmonic current suppression branch is composed of a pair of complementary conducting power switch tubes S b , S c With inductance L b , capacitor C2 forms a fractional-order virtual capacitor C foc , and then connected in series with capacitor C1, capacitor C2 and fractional virtual capacitor C foc The port voltages are consistent. b , S c One end of the half-bridge arm formed by the power switch tube is connected to the positive electrode of the DC bus, and the other end is connected to the negative electrode of the DC bus. The negative electrode of capacitor C1 is connected to the fractional virtual capacitor C foc The positive poles of capacitor C1 are connected to the positive pole of the DC bus, and the fractional-order virtual capacitor C foc The negative pole is connected to the negative pole of the DC bus, and the inductor L b One end is connected to the midpoint of the half bridge arm, and the other end is connected to C1 and C foc Connect the midpoints.

[0046] The present invention adopts the following control method:

[0047] The control block diagram of the fractional-order second harmonic current suppression method of a single-phase dual-mode boost inverter is shown in the attached figure. Figure 5 As shown in Figure 1, the entire system is divided into high-frequency-low-frequency dual-mode control of the single-phase boost inverter and power decoupling control of the fractional-order second harmonic current suppression branch. iand the actual desired single-phase full-bridge inverter output sinusoidal voltage The high-frequency or low-frequency control of the front-stage Boost circuit and the rear-stage full-bridge inverter is selected based on the size comparison.

[0048] when When the DC bus capacitance C a Port voltage u Ca With reference command voltage u aref The difference is input into the front-stage Boost voltage loop PI controller, and a PWM drive signal is generated through sinusoidal pulse width modulation, and then sent to the front-stage signal selector. with U i The pre-stage signal selector sends the PWM signal output by the pre-stage Boost circuit PI controller to the pre-stage Boost circuit power switch tube S. a Between the gate and the source, the corresponding The bus voltage output of the peak and trough parts of the sine wave. At the same time, the rear-stage signal selector gives the corresponding sine half-cycle square wave signal to the gate and source of the four power switch tubes S1, S2, S3, and S4 of the rear-stage single-phase inverter. Among them, S1 and S4 are turned on in the positive half cycle, S2 and S3 are turned off, and S1 and S4 are turned off in the negative half cycle, and S2 and S3 are turned on. At this time, the rear-stage inverter only forms a path through a pair of conducting switch tubes, and does not regulate the output voltage; at this time, the front-stage Boost circuit works at high frequency, and the rear-stage full-bridge inverter works at low frequency.

[0049] when When the front-stage signal selector sends the low level to the front-stage Boost circuit power switch tube S a Between gate and source, S a Cut off, at this time the bus voltage is directly taken from the input DC power supply voltage U i . Collect the voltage u at the output load R port of the full-bridge inverter o With reference command voltage u oref The difference is input into the voltage loop PI controller of the rear full-bridge inverter, and 4 PWM drive signals are generated through sinusoidal pulse width modulation, and then sent to the rear signal selector. with U i The 4-way PWM signals output by the rear voltage loop PI controller are respectively given to the gate and source of the four power switch tubes S1, S2, S3, and S4 of the rear full-bridge inverter, where the drive signals of S1 and S2, S3 and S4 are complementary, the drive signals of S1 and S4, S2 and S3 are the same, and the rising edges of the drive signals of S1 and S3 differ by 180°, so as to realize the regulation of the middle section of the sinusoidal AC voltage. At this time, the front-stage Boost circuit works at a low frequency, and the rear-stage full-bridge inverter works at a high frequency.

[0050] The actual expected single-phase inverter output sinusoidal voltage It can be expressed as

[0051] Among them, U o is the peak value of the desired output voltage, and ω is the angular frequency of the desired output voltage.

[0052] pass with U i By comparing the size of the previous stage Boost circuit output voltage, the reference command voltage of the single closed-loop PI controller is

[0053]

[0054] pass with U i By comparing the size of the following single-phase inverter output voltage single closed-loop PI controller, the reference command voltage is:

[0055]

[0056] The power decoupling control of the fractional-order second harmonic current suppression branch first collects the output voltage u of the subsequent full-bridge inverter o 、Current i o , and the DC bus voltage u Ca According to the fractional-order branch instantaneous power P foc And the output secondary pulsation power P o-2nd Decoupling constraints for power balance with equal amplitude and complementary phase, and fractional-order virtual capacitor C foc The voltage u between capacitor C1 Cfoc and u C1 The AC components of the two phases are equal in amplitude and complementary in phase, and u Cfoc and u C1 The sum is equal to the bus voltage u Ca The total constraint of the fractional-order virtual capacitance C is calculated foc The reference voltage u Cfoc-ref Then, the detected terminal voltage of capacitor C2, i.e., fractional-order virtual capacitor C foc The port voltage u Cfoc The difference is sent to the voltage outer loop PI controller, and its output is used as the fractional-order branch resonant inductor L b The reference command current signal i Lb-ref , and then with the inductor feedback current i Lb The difference is sent to the current inner loop PI controller, and two PWM signals are generated through sinusoidal pulse width modulation to drive the power switch tube S b With S c , to achieve the absorption of second harmonic current.

[0057] The power balance decoupling constraint is determined by the inverter output voltage and current.

[0058] Among them U o is the peak value of the inverter output voltage, ω is the angular frequency of the inverter output, I o is the peak value of the inverter output current, and θ is the phase shift angle of the inverter output current.

[0059] The calculated output power The secondary pulsation power is

[0060]

[0061] According to the power balance, when the instantaneous power p in the foc fractional-order capacitor branch connected in parallel to the DC bus foc and secondary pulsation power P o-2nd The amplitudes are equal, the phases are complementary, and u Cfoc and u C1 The sum satisfies the DC bus voltage u Ca When the total constraint is met, the second harmonic current can be completely suppressed. Take C1 = C2 = C, the foc branch energy storage capacitor is in the microfarad level, the inductor is in the microhenry level, and the inductor L b The power p Lb << is much smaller than the power of the two capacitors in the FOC branch, and the inductor L can be ignored. b The power in the foc branch is p foc The constraint and branch capacitance voltage constraint equations are:

[0062]

[0063] The DC bus voltage

[0064] Simplifying the above equations, we can get the voltage u at the terminal of capacitor C2: C2 , that is, the fractional capacitance C foc The port voltage u Cfoc The quadratic equation of

[0065] when When the foc branch power and capacitor voltage constraint equations are simplified to

[0066] Here, λ is an arbitrary constant term generated when solving the first-order differential equation for power balance.

[0067] If this quadratic equation is to have real solutions, then its discriminant must be greater than or equal to 0, that is, it satisfies

[0068]

[0069] If the discriminant is to satisfy the above conditions throughout the entire period, then

[0070]

[0071] That is, any constant term λ must satisfy

[0072]

[0073] When λ directly takes this lower limit value, the foc suppression branch can choose a smaller capacitance value

[0074] At this time, the fractional-order virtual capacitor C foc The voltage u between capacitor C1 Cfoc and u C1 The expression is

[0075]

[0076] Using the same method, we can find When Cfoc and u C1 The expression is

[0077] in,

[0078]

[0079] Observation Cfoc and u C1 And bus voltage u Ca The expression of fractional-order virtual capacitance C foc The voltage u between capacitor C1 Cfoc and u C1 The satisfied DC bus voltage constraint can be rewritten as

[0080] Among them, u h is the modulation voltage, U h is the amplitude of the modulation voltage, and β is the phase shift angle of the modulation voltage.

[0081] when When u Cfoc and u C1 The simplified expression can be obtained as follows: h The expression is

[0082]

[0083] Since the capacitor voltage cannot be negative, it must satisfy

[0084] By u Cfoc and u C1 From the expression, we can see that in order to satisfy the condition that the voltage is greater than 0 during the entire cycle,

[0085]

[0086] Available Where M is the transformation ratio of the subsequent full-bridge inverter, and R is the inverter output load. The foc branch capacitance value parameter can be obtained according to this formula.

[0087] In order to reduce the inductance L b The resonance effect of capacitor C2 should make the resonance frequency at least 10 times of the inverter output operating frequency. The international power quality requirement IEEE 519 requires that the first 11 harmonics should not be greater than 4% of the DC component. The foc branch inductance L b Maximum value possible

[0088] In order to obtain the optimal second harmonic current absorption capability, in practice the inductance value needs to be fine-tuned according to the obtained value.

[0089] When a pure resistive load is used, the same method as above can be used to obtain The modulation voltage u h The expression is

[0090] in,

[0091] Obtain the modulation voltage u of the full cycle h The expression can be used to obtain the fractional-order virtual capacitance C foc The reference voltage u Cfoc-ref Thus, dual closed-loop decoupling control of voltage and current is performed to achieve absorption of second harmonic current.

[0092] As attached Figure 6 As shown, according to the input DC power supply voltage U i and the actual desired single-phase inverter output sinusoidal voltage The size comparison, combined with the capacitor C of the Boost circuit a Voltage u Ca and inductor L a Current i La The waveform changes in the positive and negative half cycles. In one switching cycle, the single-phase dual-mode boost inverter can be divided into four working areas, each of which contains two working modes.

[0093] Region D1: corresponds to sinusoidal voltage positive half cycle, and When the input DC power supply maintains the capacitor voltage uCa in U i Left and right, La The waveform is close to the zero axis, that is, the inductance L a A small current flows through the circuit. At this time, the middle part of the sinusoidal voltage is mainly controlled by the subsequent inverter, and there are two modes: I and III.

[0094] Region D2: corresponds to sinusoidal voltage positive half cycle, and When Ca and i La The waveforms all change according to the peak trend of the output AC sinusoidal voltage. At this time, the control of the sinusoidal voltage peak part is mainly completed by the front-stage Boost circuit, and there are two modes, I and IV.

[0095] Region D3: corresponds to sinusoidal voltage Negative half cycle, and When the input DC power supply maintains the capacitor voltage u Ca in U i Left and right, La The waveform is close to the zero axis, that is, the inductance L a A small current flows through the circuit. At this time, the middle part of the sinusoidal voltage is mainly controlled by the subsequent inverter, and there are two modes, II and III.

[0096] Region D4: corresponds to sinusoidal voltage Negative half cycle, and When Ca and i La The waveforms all change according to the trend of the output AC sinusoidal voltage trough. At this time, the control of the trough part of the sinusoidal voltage is mainly completed by the front-stage Boost circuit, and there are two modes, II and V.

[0097] Mode I: As attached Figure 7 As shown in (a), S a , S2, S3 are turned off, S1 and S4 are turned on, the DC power supply and inductor L a Through VD to capacitor C a Charging, inductance L a The current decreases; at the same time, the capacitor C a Power is supplied to the load R through S1 and S4, C a Voltage rises.

[0098] Mode II: As attached Figure 7 As shown in (b), S a , S1, S4 are turned off, S2 and S3 are turned on, the DC power supply and inductor L a Through VD to capacitor C a Charging, inductance L a The current decreases; at the same time, the capacitor C a Power is supplied to the load R through S2 and S3, Ca Voltage rises.

[0099] Mode III: As attached Figure 7 (c) As shown in a , S1, S2, S3, S4 are all turned off, and the DC power supply passes through L a and VD to capacitor C a Charging, inductance L a Current rises, voltage C a rise.

[0100] Mode IV: As attached Figure 7 As shown in (d), S a , S1, S4 are turned on, S2 and S3 are turned off, and the DC power supply is a Give inductor L a Charging, inductance L a The current rises; at the same time, the capacitor C a Power is supplied to the load R through S1 and S4, C a Voltage drops.

[0101] Mode V: As attached Figure 7 As shown in (e), S a , S2, S3 are turned on, S1 and S4 are turned off, and the DC power supply is a Give inductor L a Charging, inductance L a The current rises; at the same time, the capacitor C a Power is supplied to the load R through S2 and S3, C a Voltage drops.

[0102] like Figure 8 The figure shows the basic working waveform of the foc second harmonic current suppression branch. In one switching cycle, according to the inductor L b Current i Lb changes, such as Figure 8 As shown in (a), the working conditions of the foc second harmonic current suppression branch can be divided into three regions. In each region, the foc branch contains two working modes. The specific modal analysis is as follows.

[0103] Area d1: Figure 8 (c) shows that the foc branch inductance L b Current i Lb >0, capacitor C2 voltage u C2 There are two modes: I and II.

[0104] Area d2: Figure 8 As shown in (b), the foc branch inductance L b Current i Lb There are positive and negative, changing direction within one switching cycle, and there are two modes: II and III.

[0105] Area d3: Figure 8 As shown in (d), the foc branch inductance L b Current i Lb <0, capacitor C2 voltage u C2 There are two modes, III and IV.

[0106] Mode I: Fig. 9 As shown in (a), S b On, S c Turn off, inductor L b Current i Lb >0, the DC bus passes through the switch tube S b Give inductor L b and capacitor C2 is charged, inductor L b Current i Lb The capacitor C2 voltage u C2 rise.

[0107] Mode II: If Fig. 9 As shown in (b), S b Shutdown, S c On, inductance L b Current i Lb >0, inductance L b By S c The body diode charges the capacitor C2, and the inductor L b Current i Lb The voltage u of capacitor C2 decreases C2 rise.

[0108] Mode III: If Fig. 9 (c) As shown in b On, S c Turn off, inductor L b Current i Lb <0, inductance L b and capacitor C2 through S b The body diode feeds back energy to the DC bus, and the inductor L b Current i Lb Reduce, capacitor C2 voltage u C2 reduce.

[0109] Mode IV: If Fig. 9 As shown in (d), S b Shutdown, S c On, inductance L b Current i Lb <0,C2 through S c Give inductor L b Charging, inductance L b Current i Lb The capacitor C2 voltage uC2 reduce.

[0110] Based on the above analysis and parameter selection, a single-phase dual-mode boost inverter with a foc suppression branch is simulated. The specific parameter settings are shown in the following table:

[0111]

[0112] Attached Fig.10 (a) is the DC bus voltage waveform of the single-phase dual-mode controlled boost inverter of the present invention. It can be seen that except for a slight upward fluctuation in the constant DC part, it can basically track the shape of the peaks and troughs of the output sinusoidal AC voltage without affecting the sinusoidal output of the subsequent inverter.

[0113] Attached Fig.10 (b) is the output voltage and current waveforms of the single-phase dual-mode boost inverter of the present invention. It can be seen that the voltage waveform on the load can basically maintain a sinusoidal AC waveform with a peak value of 311V.

[0114] Attached Fig.10 (c) is the FFT Fourier analysis spectrum of the inverter output load voltage waveform. It can be seen that after the output sinusoidal AC voltage stabilizes, the FFT spectrum of 3 cycles is analyzed starting from 0.03 seconds, and its harmonic distortion rate THD value is 1.73%, which is lower than the national standard of 5%.

[0115] Attached Fig.11 (a) is the power input current waveform and FFT spectrum of the single-phase dual-mode boost inverter of the present invention. Due to the dual-mode control, the input current is similar to the bus voltage and presents a secondary pulsation form. Of course, it also includes the secondary harmonic current component caused by the secondary pulsation of the inverter output power, of which the two higher harmonic components, the second harmonic current component reaches 160.8%, and the fourth harmonic current component reaches 83.9%.

[0116] Attached Fig.11 (b) is the input current waveform and FFT spectrum of the power supply after adding the foc fractional-order suppression branch. It can be seen that the second harmonic current is reduced to 9.7%, and the fourth harmonic current component is 75.5%, which is also reduced accordingly. Since the output secondary pulsating power will only cause the input second harmonic current, and the fourth harmonic component is caused by dual-mode regulation, it is impossible to completely eliminate it.

[0117] In order to verify the characteristics of the dual-mode control method described in the present invention, a comparative simulation was performed on the traditional control method of the DC bus voltage outputting a constant DC voltage, and the simulation parameter design was completely consistent with the simulation circuit parameters described in the present invention.

[0118] The conventional control method also adopts voltage closed-loop PI control. At this time, the PI controller of the front-stage Boost circuit refers to the command voltage u aref The reference voltage u of the PI controller of the subsequent single-phase inverter is 350V. oref for u o * , collect the DC side capacitance C a Port voltage u Ca Perform single closed-loop PI control of the front stage, generate a PWM drive signal through sinusoidal pulse width modulation, and give it to the power switch tube S of the front stage Boost circuit a Between the gate and the source, the DC bus voltage is constant at 350V output. Collect the voltage u at the output load R port of the inverter o The subsequent single closed-loop PI control is carried out, and four PWM drive signals are generated by sinusoidal pulse width modulation, which are respectively given to the gate and source of the four power switch tubes S1, S2, S3, and S4 of the subsequent single-phase inverter. The drive signals of S1 and S2, S3 and S4 are complementary, the drive signals of S1 and S4, S2 and S3 are the same, and the rising edges of the drive signals of S1 and S3 differ by 180°, so as to realize full-cycle regulation of the sinusoidal output voltage.

[0119] The single-phase boost inverter outputs a sinusoidal AC voltage waveform and FFT Fourier analysis spectrum under the traditional control method. It can be seen that after the system is stable, it can maintain a sinusoidal AC voltage output with a peak value of 311V, and its THD value is 0.81%, which is 5% lower than the national standard.

[0120] Attached Fig.12 This is a comparison diagram of the input-output efficiency curves of the single-phase Boost inverter of the high-frequency-low-frequency dual-mode control method described in the present invention and the traditional control method. It can be seen that under the effect of almost the same output sinusoidal AC voltage waveform, the efficiency of the single-phase dual-mode boost inverter of the present invention is always better than the efficiency of the single-phase inverter of the traditional control method.

[0121] The above is only a specific implementation of the present invention, but the design concept of the present invention is not limited to this. Any non-substantial changes to the present invention using this concept shall be deemed as an infringement of the protection scope of the present invention.

Claims

1. A fractional-order second harmonic current suppression method for a single-phase dual-mode boost inverter, characterized in that: It includes high-frequency-low-frequency dual-mode control of a two-stage single-phase Boost inverter and power decoupling control of a bus-side parallel fractional-order second harmonic current suppression branch.

2. The fractional-order second harmonic current suppression method of the single-phase dual-mode boost inverter according to claim 1, characterized in that: The method is applied to a second harmonic current suppression circuit of a single-phase dual-mode boost inverter, wherein the second harmonic current suppression circuit of the single-phase dual-mode boost inverter comprises a two-stage single-phase Boost boost inverter and a fractional-order second harmonic current suppression branch connected in parallel with a busbar; The two-stage single-phase Boost inverter is composed of a front-stage Boost circuit and a rear-stage full-bridge inverter. The front-stage Boost circuit consists of an energy storage inductor L a , freewheeling diode VD, power switch tube S a , energy storage capacitor C a The inductor L a One end is connected to the input DC power supply U i The positive pole, the other end is connected to the anode of the freewheeling diode VD, and the power switch tube S a The drain is connected to the VD anode, and the capacitor C a The positive electrode is connected to the cathode of VD, and the capacitor C a Negative electrode and S a The source is connected to the DC power supply U i Negative pole; the rear full-bridge inverter consists of four power switch tubes S1, S2, S3, and S4 and an LC filter circuit; the complementary power switch tubes S1 and S2 form a bridge arm, and the other bridge arm consists of complementary power switch tubes S3 and S4. The two ends of the two bridge arms are connected to capacitors C a The positive and negative electrodes of the bridge arm are connected to the filter inductor L and one end of the filter capacitor C, and the output load R is connected to the common point of the filter inductor L and the filter capacitor C and the other end of the capacitor C; The fractional-order second harmonic current suppression branch is composed of two power switch tubes S which are complementary turned on in a half-bridge form. b , S c With inductance L b , capacitor C2 forms a fractional capacitor C foc , and then connected in series with capacitor C1. Power switch tube S b , S c One end of the half-bridge arm is connected to the positive pole of the DC bus, and the other end is connected to the negative pole of the DC bus. The negative pole of capacitor C1 is connected to the positive pole of capacitor C2, that is, the negative pole of C1 is connected to the fractional-order virtual capacitor C foc The positive poles of capacitor C1 are connected to the positive pole of the DC bus, and the fractional-order virtual capacitor C foc The negative pole is connected to the negative pole of the DC bus, and the inductor L b One end is connected to the midpoint of the half bridge arm, and the other end is connected to C1 and C foc Connect the midpoint and control S b , S c The on-off of C1 and C foc The port voltage amplitudes are equal and the phases are complementary.

3. The fractional-order second harmonic current suppression method of the single-phase dual-mode boost inverter according to claim 2, characterized in that: The two-stage single-phase Boost inverter high-frequency-low-frequency dual-mode control includes the front-stage Boost circuit control and the rear-stage single-phase inverter control, and the bus voltage is regulated into two waveforms: partial sine and constant direct. Specifically, according to the input DC power supply voltage U i and the actual desired single-phase full-bridge inverter output sinusoidal voltage u o * By comparing the size of the bus voltage, the bus voltage is adjusted to two waveforms, partial sine and constant value, through the voltage single closed-loop PI control, to achieve dual-mode switching of high-frequency and low-frequency operation of the front-stage Boost circuit and the rear-stage full-bridge inverter.

4. The fractional-order second harmonic current suppression method of the single-phase dual-mode boost inverter according to claim 3, characterized in that: When|u o * |≥U i When the bus voltage is adjusted to correspond to u o * The peak and trough of the sine wave are calculated by the program to obtain u o * The bus reference command voltage signal u of the sinusoidal waveform of the peak and trough parts aref , by collecting the DC side capacitor C a Port voltage u a With reference command voltage u aref The difference is input into the front-stage Boost voltage loop PI controller, and the power switch tube S is controlled through sinusoidal pulse width modulation. a In the peak part, the power switch tubes S1 and S4 of the rear inverter are always on, and the power switch tubes S2 and S3 are always off. In the trough part, the power switch tubes S1 and S4 of the rear inverter are always off, and the power switch tubes S2 and S3 are always on, which reduces the switching loss of the inverter power devices. At this time, the front-stage Boost circuit works at a high frequency, and the rear-stage inverter works at a low frequency.

5. The fractional-order second harmonic current suppression method of the single-phase dual-mode boost inverter according to claim 3, characterized in that: when|u o * |<U i When the bus voltage is regulated to a constant waveform, u o * Reference command voltage signal u of the middle waveform oref , by collecting the output load R port voltage u o With reference command voltage u oref The difference is input into the voltage loop PI controller of the subsequent inverter, and the on and off of the four power switch tubes S1, S2, S3, and S4 are controlled through sinusoidal pulse width modulation. a It is always off, which reduces the switching and conduction losses of the power devices in the Boost circuit and improves efficiency. At this time, the front-stage Boost circuit works at a low frequency, and the rear-stage inverter works at a high frequency.

6. The fractional-order second harmonic current suppression method of the single-phase dual-mode boost inverter according to claim 2, characterized in that: The power decoupling control of the fractional-order second harmonic current suppression branch is specifically divided into the following steps: using capacitors C1 and C2 to suppress the fractional-order second harmonic current. foc Voltage outer loop, inductance L b Double closed-loop PI control of the current inner loop; By collecting the sinusoidal AC voltage u at the output load R port of the subsequent full-bridge inverter o and current i o , calculate the secondary pulsation power P in the output power o-2nd , according to the fractional-order branch instantaneous power P foc With P o-2nd The amplitude is equal, the phase is complementary, and the power decoupling is used to calculate the reference voltage signal u of capacitor C2. C2-ref , we can know that the terminal voltage u of C2 C2 With the fractional order virtual capacitor C foc The port voltage u Cfoc Equal, reference voltage u Cfoc-ref It is also equal to u C2-ref； By collecting the voltage u at the C2 port C2 , which is the fractional-order virtual capacitance C foc The port voltage u Cfoc , and the fractional virtual capacitor reference voltage u Cfoc-ref The difference is sent to the voltage outer loop PI controller, and its output is used as the inductor L b The reference current signal of the current inner loop is then compared with the collected inductance L b Current i Lb The difference is sent to the current inner loop PI controller, and the PWM wave is generated through sinusoidal pulse width modulation to control the power switch tube S b , S c The turn-on and turn-off of When the capacitance C2 of the fractional-order second harmonic current suppression branch is equal to the series capacitance C1, at the double frequency, power decoupling control is used to achieve that the instantaneous power of the fractional-order second harmonic current suppression branch is equal to the secondary pulsating power amplitude output by the subsequent full-bridge inverter, and the phases are complementary.

7. The fractional-order second harmonic current suppression method of the single-phase dual-mode boost inverter according to claim 2, characterized in that: Solve the fractional-order virtual capacitor C piecewise based on high-frequency-low-frequency dual-mode control foc The modulation voltage.

8. The fractional-order second harmonic current suppression method of the single-phase dual-mode boost inverter according to claim 7, characterized in that: The voltage u at the capacitor C1 of the fractional-order second harmonic current suppression branch C1 and fractional-order virtual capacitance C foc The terminal voltage u Cfoc It is an AC signal with DC bias. Its AC component shows secondary pulsating power balance to the second harmonic current. It is necessary to satisfy the voltage amplitude equality and phase complementarity, and at the same time satisfy the capacitors C1 and C foc The terminal voltage u C1 、u Cfoc The sum is equal to the DC bus voltage.

9. The fractional-order second harmonic current suppression method of the single-phase dual-mode boost inverter according to claim 8, characterized in that: The high-frequency-low-frequency dual-mode control solves the fractional-order virtual capacitance C piecewise. foc The modulation voltage is calculated by solving the fractional capacitor C in the high-frequency and low-frequency regions according to the power constraint and DC bus voltage constraint. foc Port voltage u Cfoc The numerical solution of the first-order differential equation is used to calculate the fractional virtual capacitance C foc The port reference voltage u Cfoc-ref The modulation voltage.

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