A Ring Oscillator with Adjustable Phase Noise and Maximum Oscillation Frequency and Its Control Method

Abstract

The object of the present invention is to provide a phase noise and maximum oscillation frequency adjustable ring oscillator and a control method. The oscillator includes: a main path and a third auxiliary path; the third auxiliary path is connected to the main path for increasing the oscillation frequency; by inserting an adjustable inverter, when the frequency of the ring oscillator does not meet the requirements under extreme corner conditions, the oscillation frequency can be increased by sacrificing some phase noise by adjusting the inverter.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a ring oscillator with adjustable phase noise and maximum oscillation frequency and a control method therefor. Background Art

[0002] A ring oscillator is a ring circuit composed of an odd number of NOT gates, whose output terminal and input terminal are connected end to end to form a ring structure. The ring oscillator is characterized by a simple circuit, easy startup, and no need for additional resistor-capacitor elements, which is convenient for integration. Its working principle is to generate periodic high and low level changes through the delay effect of the NOT gates, thereby realizing oscillation. The basic working principle of the ring oscillator is to achieve oscillation through the delay effect of an odd number of NOT gates. Taking three NOT gates as an example, the output of NOT gate A is connected to the input of NOT gate B, the output of NOT gate B is connected to the input of NOT gate C, and the output of NOT gate C is connected back to the input of NOT gate A to form a closed loop. When the input terminal of NOT gate A becomes high level, its output terminal becomes low level, and so on, forming a periodic high and low level change, thereby realizing oscillation. The ring oscillator is mainly applied to high-frequency oscillations with low requirements for internal integration in integrated circuits, as well as simple oscillators in ordinary digital circuits. Due to its simple circuit, easy startup and no need for additional resistor-capacitor elements, the ring oscillator has certain advantages in integrated circuit design. In addition, the ring oscillator can also change the oscillation period by adding a resistor-capacitor delay network, which is suitable for application scenarios that require flexible frequency adjustment.

[0003] Different process corners represent different extreme cases of process parameters. For example, in the fastest process corner, all process deviations increase the drive current of the transistors, so the speed is the fastest; while in the slowest process corner, the device speed is slowed down by the process deviations. These changes in process parameters will cause parameters such as the threshold voltage and transconductance of the transistors to change, thereby affecting the delay time of basic units such as inverters in the ring oscillator, and ultimately resulting in the oscillation frequency not meeting the requirements. Summary of the Invention

[0004] The object of the present invention is to provide a ring oscillator with adjustable phase noise and maximum oscillation frequency and a control method therefor. The oscillator inserts adjustable inverters to achieve that when the frequency of the ring oscillator does not meet the requirements under extreme corner conditions, the oscillation frequency can be increased by sacrificing some phase noise through adjusting the inverters.

[0005] A ring oscillator with adjustable phase noise and maximum oscillation frequency includes: a main path and a third auxiliary path;

[0006] The third auxiliary path is connected to the main path and is used to increase the oscillation frequency;

[0007] The third auxiliary path includes: the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter;

[0008] The input end of the twenty-fourth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter;

[0009] The input end of the twenty-fifth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the second inverter and the input end of the third inverter;

[0010] The input end of the twenty-sixth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter;

[0011] The input end of the twenty-seventh inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter;

[0012] The input end of the twenty-eighth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter;

[0013] The input end of the twenty-ninth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter;

[0014] The input end of the thirtieth inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter, and the output end is connected to the output end of the seventh inverter and the input end of the zeroth inverter;

[0015] The input end of the thirty-first inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter.

[0016] Preferably, the main path includes: the zeroth inverter, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, and the seventh inverter;

[0017] The input end of the zeroth inverter is connected to the output end of the seventh inverter, and the output end is connected to the input end of the first inverter;

[0018] The output end of the first inverter is connected to the input end of the second inverter;

[0019] The output terminal of the second inverter is connected to the input terminal of the third inverter;

[0020] The output terminal of the third inverter is connected to the input terminal of the fourth inverter;

[0021] The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter;

[0022] The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter;

[0023] The output terminal of the sixth inverter is connected to the input terminal of the seventh inverter;

[0024] The output terminal of the seventh inverter is connected to the input terminal of the zero-th inverter.

[0025] Preferably, it further includes: a first auxiliary path;

[0026] The first auxiliary path includes: an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, and a fifteenth inverter;

[0027] The input terminal of the eighth inverter is connected to the output terminal of the zero-th inverter and the input terminal of the first inverter, and the output terminal is connected to the output terminal of the sixth inverter and the input terminal of the seventh inverter;

[0028] The input terminal of the ninth inverter is connected to the output terminal of the seventh inverter and the input terminal of the zero-th inverter, and the output terminal is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter;

[0029] The input terminal of the tenth inverter is connected to the output terminal of the sixth inverter and the input terminal of the seventh inverter, and the output terminal is connected to the output terminal of the fourth inverter and the input terminal of the fifth inverter;

[0030] The input terminal of the eleventh inverter is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter, and the output terminal is connected to the output terminal of the third inverter and the input terminal of the fourth inverter;

[0031] The input terminal of the twelfth inverter is connected to the output terminal of the fourth inverter and the input terminal of the fifth inverter, and the output terminal is connected to the output terminal of the second inverter and the input terminal of the third inverter;

[0032] The input terminal of the thirteenth inverter is connected to the output terminal of the third inverter and the input terminal of the fourth inverter, and the output terminal is connected to the output terminal of the first inverter and the input terminal of the second inverter;

[0033] The input terminal of the fourteenth inverter is connected to the output terminal of the second inverter and the input terminal of the third inverter, and the output terminal is connected to the output terminal of the zero-th inverter and the input terminal of the first inverter;

[0034] The input terminal of the fifteenth inverter is connected to the output terminal of the first inverter and the input terminal of the second inverter, and the output terminal is connected to the output terminal of the seventh inverter and the input terminal of the zero-th inverter.

[0035] Preferably, it further includes: a second auxiliary path;

[0036] The second auxiliary path includes: a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a twentieth inverter, a twenty-first inverter, a twenty-second inverter, and a twenty-third inverter;

[0037] The input terminal of the sixteenth inverter is connected to the output terminal of the first inverter and the input terminal of the second inverter, and the output terminal is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter;

[0038] The input terminal of the seventeenth inverter is connected to the output terminal of the second inverter and the input terminal of the third inverter, and the output terminal is connected to the output terminal of the sixth inverter and the input terminal of the seventh inverter;

[0039] The input terminal of the eighteenth inverter is connected to the output terminal of the seventh inverter and the input terminal of the zero-th inverter, and the output terminal is connected to the output terminal of the third inverter and the input terminal of the fourth inverter;

[0040] The input terminal of the nineteenth inverter is connected to the output terminal of the zero-th inverter and the input terminal of the first inverter, and the output terminal is connected to the output terminal of the fourth inverter and the input terminal of the fifth inverter;

[0041] The input terminal of the twentieth inverter is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter, and the output terminal is connected to the output terminal of the first inverter and the input terminal of the second inverter;

[0042] The input terminal of the twenty-first inverter is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter, and the output terminal is connected to the output terminal of the first inverter and the input terminal of the second inverter;

[0043] The input terminal of the twenty-second inverter is connected to the output terminal of the fourth inverter and the input terminal of the fifth inverter, and the output terminal is connected to the output terminal of the zero-th inverter and the input terminal of the first inverter;

[0044] The input terminal of the twenty-third inverter is connected to the output terminal of the third inverter and the input terminal of the fourth inverter, and the output terminal is connected to the output terminal of the seventh inverter and the input terminal of the zero-th inverter.

[0045] Preferably, the zero-th inverter has the same structure as the second inverter, third inverter, fourth inverter, fifth inverter, sixth inverter, seventh inverter, eighth inverter, ninth inverter, tenth inverter, eleventh inverter, twelfth inverter, thirteenth inverter, fourteenth inverter, fifteenth inverter, sixteenth inverter, seventeenth inverter, eighteenth inverter, nineteenth inverter, twentieth inverter, twenty-first inverter, twenty-second inverter, and twenty-third inverter;

[0046] The zero-th inverter includes: a first NMOS transistor and a first PMOS transistor;

[0047] The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the source of the first NMOS transistor, the source is connected to a high level, and the gate is connected to the gate of the first PMOS transistor;

[0048] The source of the first NMOS transistor is grounded.

[0049] Preferably, the structure of the twenty-fourth inverter is the same as that of the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter;

[0050] The twenty-fourth inverter includes: a plurality of switch branches;

[0051] Each of the switch branches is connected in parallel;

[0052] Each switch branch includes: a second NMOS transistor, a second PMOS transistor, a first switch, and a second switch;

[0053] The drain of the second PMOS transistor is connected to the first switch, the gate is connected to the gate of the second NMOS transistor, and the source is connected to a high level;

[0054] The drain of the second NMOS transistor is connected to the second switch, and the source is grounded.

[0055] Preferably, the driving capabilities of the zero-th inverter, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, and the seventh inverter are 2 to 3 times that of the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter, and the fifteenth inverter.

[0056] Preferably, the driving capabilities of the eighth inverter, ninth inverter, tenth inverter, eleventh inverter, twelfth inverter, thirteenth inverter, fourteenth inverter, and fifteenth inverter are 3-4 times that of the sixteenth inverter, seventeenth inverter, eighteenth inverter, nineteenth inverter, twentieth inverter, twenty-first inverter, twenty-second inverter, and twenty-third inverter.

[0057] Preferably, the driving capabilities of the sixteenth inverter, seventeenth inverter, eighteenth inverter, nineteenth inverter, twentieth inverter, twenty-first inverter, twenty-second inverter, and twenty-third inverter are 1.2-1.6 times that of the twenty-fourth inverter, twenty-fifth inverter, twenty-sixth inverter, twenty-seventh inverter, twenty-eighth inverter, twenty-ninth inverter, thirtieth inverter, and thirty-first inverter.

[0058] A control method for a phase noise and maximum oscillation frequency adjustable ring oscillator, applied to a phase noise and maximum oscillation frequency adjustable ring oscillator, includes:

[0059] Under TT and FF corner conditions, the switches inside the twenty-fourth inverter, twenty-fifth inverter, twenty-sixth inverter, twenty-seventh inverter, twenty-eighth inverter, twenty-ninth inverter, thirtieth inverter, and thirty-first inverter are turned off, that is, the third auxiliary path of the oscillator is disconnected. At this time, the oscillation frequency and phase noise of the oscillator both meet the regulations;

[0060] Under SS corner conditions, gradually turn on the switches inside the twenty-fourth inverter, twenty-fifth inverter, twenty-sixth inverter, twenty-seventh inverter, twenty-eighth inverter, twenty-ninth inverter, thirtieth inverter, and thirty-first inverter to increase the frequency to the specified value.

[0061] The beneficial effects of the present invention are as follows: Compared with the existing 8-phase output ring oscillator, under the condition of the same power consumption, by inserting adjustable inverters: the twenty-fourth inverter, twenty-fifth inverter, twenty-sixth inverter, twenty-seventh inverter, twenty-eighth inverter, twenty-ninth inverter, thirtieth inverter, and thirty-first inverter, when the frequency of the ring oscillator does not meet the regulations under extreme corner conditions, the oscillation frequency can be increased by sacrificing some phase noise by adjusting the adjustable inverters to meet the working requirements. Description of the Drawings

[0062] The drawings here are incorporated into the specification and form a part of this specification, marking the embodiments that conform to the present invention, and are used together with the specification to explain the principles of the present invention.

[0063] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0064] Figure 1 It is a structural diagram of a ring oscillator with adjustable phase noise and maximum oscillation frequency according to the present invention;

[0065] Figure 2 It is a schematic diagram of the structure of an unadjustable inverter according to the present invention;

[0066] Figure 3 It is a schematic diagram of the structure of an adjustable inverter according to the present invention. Specific embodiments

[0067] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0068] It should be noted that all the directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0069] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0070] Different process corners represent different extreme cases of process parameters. For example, in the fastest process corner, all process deviations increase the drive current of the transistor, so the speed is the fastest; while in the slowest process corner, the device speed is slowed down by the process deviations. These changes in process parameters will cause parameters such as the threshold voltage and transconductance of the transistor to change, thereby affecting the delay time of basic units such as inverters in the ring oscillator, and ultimately resulting in the oscillation frequency not meeting the requirements.

[0071] Compared with the existing 8-phase output ring oscillator, under the condition of the same power consumption, by inserting adjustable inverters: the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter, when the frequency of the ring oscillator does not meet the requirements under extreme corner conditions, the oscillation frequency can be increased by adjusting the adjustable inverters at the cost of some phase noise to meet the working requirements.

[0072] Embodiment 1

[0073] A ring oscillator with adjustable phase noise and maximum oscillation frequency, referring to Figure 1 , includes: a main path and a third auxiliary path;

[0074] The third auxiliary path is connected to the main path and is used to increase the oscillation frequency;

[0075] The third auxiliary path includes: the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter;

[0076] The input end of the twenty-fourth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter;

[0077] The input end of the twenty-fifth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the second inverter and the input end of the third inverter;

[0078] The input end of the twenty-sixth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter;

[0079] The input end of the twenty-seventh inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter;

[0080] The input end of the twenty-eighth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter;

[0081] The input end of the twenty-ninth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter;

[0082] The input terminal of the thirtieth inverter is connected to the output terminal of the fourth inverter and the input terminal of the fifth inverter, and the output terminal is connected to the output terminal of the seventh inverter and the input terminal of the zeroth inverter;

[0083] The input terminal of the thirty-first inverter is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter, and the output terminal is connected to the output terminal of the zeroth inverter and the input terminal of the first inverter.

[0084] As Figure 1 shown, eight inverters D0 to D7 form the main path of the ring oscillator, and inverters D24 to D31 constitute the third auxiliary path of the ring oscillator. Figure 1 Among them, P0 to P3 and N0 to N3 are eight phase oscillation waveforms output by the ring oscillator.

[0085] In the embodiment of the present invention, in the third auxiliary path, a feedback inverter is inserted every five inverters, and the transistor size of the inverter is set smaller than that of the first and second auxiliary paths, and the frequency improvement effect is the weakest.

[0086] For the main path, the first auxiliary path, and the second auxiliary path of the present invention, the internal inverters do not use enable control. Only the internal inverters of the third auxiliary path use enable adjustable control. When the maximum output frequency of the oscillator does not meet the requirements under extreme corner conditions, by inserting the third adjustable auxiliary path, some phase noise is sacrificed to further improve the frequency.

[0087] Preferably, the main path includes: a zeroth inverter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, and a seventh inverter;

[0088] The input terminal of the zeroth inverter is connected to the output terminal of the seventh inverter, and the output terminal is connected to the input terminal of the first inverter;

[0089] The output terminal of the first inverter is connected to the input terminal of the second inverter;

[0090] The output terminal of the second inverter is connected to the input terminal of the third inverter;

[0091] The output terminal of the third inverter is connected to the input terminal of the fourth inverter;

[0092] The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter;

[0093] The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter;

[0094] The output terminal of the sixth inverter is connected to the input terminal of the seventh inverter;

[0095] The output terminal of the seventh inverter is connected to the input terminal of the zeroth inverter.

[0096] Preferably, it further includes: a first auxiliary path;

[0097] The first auxiliary path includes: an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, and a fifteenth inverter;

[0098] The input end of the eighth inverter is connected to the output end of the zero - th inverter and the input end of the first inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter;

[0099] The input end of the ninth inverter is connected to the output end of the seventh inverter and the input end of the zero - th inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter;

[0100] The input end of the tenth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter;

[0101] The input end of the eleventh inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter;

[0102] The input end of the twelfth inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter, and the output end is connected to the output end of the second inverter and the input end of the third inverter;

[0103] The input end of the thirteenth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter;

[0104] The input end of the fourteenth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the zero - th inverter and the input end of the first inverter;

[0105] The input end of the fifteenth inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the seventh inverter and the input end of the zero - th inverter.

[0106] As Figure 1 shown, the inverters D8 - D15 form the first auxiliary path of the ring oscillator.

[0107] In the embodiment of the present invention, for the first auxiliary path, a feedback inverter is inserted every two inverters, and the transistor size of the inverters is set larger than that of the second and third auxiliary paths, with the strongest frequency - enhancing effect.

[0108] Preferably, it further includes: a second auxiliary path;

[0109] The second auxiliary path includes: the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty - first inverter, the twenty - second inverter, and the twenty - third inverter;

[0110] The input terminal of the sixteenth inverter is connected to the output terminal of the first inverter and the input terminal of the second inverter, and the output terminal is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter;

[0111] The input terminal of the seventeenth inverter is connected to the output terminal of the second inverter and the input terminal of the third inverter, and the output terminal is connected to the output terminal of the sixth inverter and the input terminal of the seventh inverter;

[0112] The input terminal of the eighteenth inverter is connected to the output terminal of the seventh inverter and the input terminal of the zeroth inverter, and the output terminal is connected to the output terminal of the third inverter and the input terminal of the fourth inverter;

[0113] The input terminal of the nineteenth inverter is connected to the output terminal of the zeroth inverter and the input terminal of the first inverter, and the output terminal is connected to the output terminal of the fourth inverter and the input terminal of the fifth inverter;

[0114] The input terminal of the twentieth inverter is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter, and the output terminal is connected to the output terminal of the first inverter and the input terminal of the second inverter;

[0115] The input terminal of the twenty - first inverter is connected to the output terminal of the fifth inverter and the input terminal of the sixth inverter, and the output terminal is connected to the output terminal of the first inverter and the input terminal of the second inverter;

[0116] The input terminal of the twenty - second inverter is connected to the output terminal of the fourth inverter and the input terminal of the fifth inverter, and the output terminal is connected to the output terminal of the zeroth inverter and the input terminal of the first inverter;

[0117] The input terminal of the twenty - third inverter is connected to the output terminal of the third inverter and the input terminal of the fourth inverter, and the output terminal is connected to the output terminal of the seventh inverter and the input terminal of the zeroth inverter.

[0118] In the embodiment of the present invention, in the second auxiliary path, a feedback inverter is inserted every 4 inverters. The transistor size of the inverter is set smaller than that of the first auxiliary path and larger than that of the third auxiliary path, and the frequency - boosting effect is the second best.

[0119] Preferably, refer to Figure 2, the structure of the zero-th inverter is the same as that of the second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, eighteenth, nineteenth, twentieth, twenty-first, twenty-second, and twenty-third inverters;

[0120] The zero-th inverter includes: a first NMOS transistor and a first PMOS transistor;

[0121] The drain of the first PMOS transistor is connected to the drain and the source of the first NMOS transistor, the source is connected to a high level, and the gate is connected to the gate of the first PMOS transistor;

[0122] The source of the first NMOS transistor is grounded.

[0123] Preferably, referring to Figure 3 , the structure of the twenty-fourth inverter is the same as that of the twenty-fifth, twenty-sixth, twenty-seventh, twenty-eighth, twenty-ninth, thirtieth, and thirty-first inverters;

[0124] The twenty-fourth inverter includes: a plurality of switch branches;

[0125] Each switch branch is in parallel;

[0126] The switch branch includes: a second NMOS transistor, a second PMOS transistor, a first switch, and a second switch;

[0127] The drain of the second PMOS transistor is connected to the first switch, the gate is connected to the gate of the second NMOS transistor, and the source is connected to a high level;

[0128] The drain of the second NMOS transistor is connected to the second switch, and the source is grounded.

[0129] In the embodiment of the present invention, one switch branch has two switches. The upper one is the switch of the PMOS transistor, and the lower one is the switch of the NMOS transistor. The parasitic capacitance introduced at the oscillation node by the switch position arranged in the present invention is smaller.

[0130] Preferably, the driving capabilities of the zero-th, first, second, third, fourth, fifth, sixth, and seventh inverters are 2-3 times that of the eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth inverters.

[0131] In the embodiments of the present invention, when the driving ability of the inverter increases, the oscillation frequency output by the ring oscillator will also increase. Inverters D0 to D23 are general inverters, and inverters D24 to D31 are composed of 5 groups of inverters inside. S1 to S5 are used as switches to control the opening and closing of the inverters; the driving ability of inverters D0 to D7 is 2 to 3 times stronger than that of inverters D8 to D15, the driving ability of inverters D8 to D15 is 3 to 4 times stronger than that of inverters D16 to D23, and the driving ability of inverters D16 to D23 is 1.2 to 1.6 times stronger than that of D24 to D31.

[0132] Preferably, the driving ability of the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter, and the fifteenth inverter is 3-4 times that of the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter, and the twenty-third inverter.

[0133] Preferably, the driving ability of the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter, and the twenty-third inverter is 1.2-1.6 times that of the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter.

[0134] In the embodiments of the present invention, in the third auxiliary path composed of the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter, since the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter are all adjustable inverters, the driving ability of the third auxiliary path inverter is adjustable, and the effect of improving the oscillation frequency will be adjustable. In order to meet the requirements of different corners for the maximum frequency, for example: in the ff corner, the oscillation frequency is very high and the highest frequency meets the requirements, then the inverters in the third auxiliary path can be completely turned off; in the ss corner, the oscillation frequency is very small and the highest frequency does not meet the requirements, then the inverters in the third auxiliary path can be completely turned on.

[0135] Embodiment 2

[0136] A control method for a phase noise and maximum oscillation frequency adjustable ring oscillator, which is applied to a phase noise and maximum oscillation frequency adjustable ring oscillator, includes:

[0137] Under the TT and FF corner conditions, the switches inside the 24th inverter, 25th inverter, 26th inverter, 27th inverter, 28th inverter, 29th inverter, 30th inverter, and 31st inverter are turned off, that is, the third auxiliary path of the oscillator is disconnected. At this time, both the oscillation frequency and phase noise of the oscillator meet the requirements.

[0138] Under the TT and FF corner conditions, the S1 - S5 switches inside the inverters D24 - D31 are turned off, which is equivalent to disconnecting the third auxiliary path of the oscillator. At this time, both the oscillation frequency and phase noise of the oscillator meet the spec.

[0139] Under the SS corner condition, gradually turn on the switches inside the 24th inverter, 25th inverter, 26th inverter, 27th inverter, 28th inverter, 29th inverter, 30th inverter, and 31st inverter to increase the frequency to the specified value.

[0140] However, under the SS corner condition, if the S1 - S5 switches inside the inverters D24 - D31 are turned off, the oscillation frequency of the oscillator cannot meet the spec, but the phase noise is better than the spec and has a certain margin. At this time, gradually turn on the S1 - S5 switches inside the inverters D24 - D31, sacrificing some phase noise to meet the requirement of increasing the frequency to the spec.

[0141] Compared with the existing 8 - phase output ring oscillator, under the condition of the same power consumption, by inserting adjustable inverters: the 24th inverter, 25th inverter, 26th inverter, 27th inverter, 28th inverter, 29th inverter, 30th inverter, and 31st inverter, when the frequency of the ring oscillator does not meet the requirements under extreme corner conditions, the oscillation frequency can be increased by sacrificing some phase noise through adjusting the adjustable inverters to meet the working requirements.

[0142] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather will be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A ring oscillator with adjustable phase noise and maximum oscillation frequency, characterized in that: include: Main access and third auxiliary access; The third auxiliary path is connected to the main path and is used to increase the oscillation frequency; The third auxiliary path includes: a twenty-fourth inverter, a twenty-fifth inverter, a twenty-sixth inverter, a twenty-seventh inverter, a twenty-eighth inverter, a twenty-ninth inverter, a thirtieth inverter and a thirty-first inverter; The input end of the twenty-fourth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-fifth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the second inverter and the input end of the third inverter; The input end of the twenty-sixth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the twenty-seventh inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the twenty-eighth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the twenty-ninth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the 30th inverter is connected to the output end of the 4th inverter and the input end of the 5th inverter, and the output end is connected to the output end of the 7th inverter and the input end of the 0th inverter; The input end of the thirty-first inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter; Also included: a first auxiliary pathway; The first auxiliary path includes: an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter and a fifteenth inverter; The input end of the eighth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the ninth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the tenth inverter is connected to the output end of the sixth inverter and the input end of the seventh inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the eleventh inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the twelfth inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter, and the output end is connected to the output end of the second inverter and the input end of the third inverter; The input end of the thirteenth inverter is connected to the output end of the third inverter and the input end of the fourth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the fourteenth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter; The input end of the fifteenth inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the seventh inverter and the input end of the zeroth inverter; Also included: a second auxiliary pathway; The second auxiliary path includes: a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a twentieth inverter, a twenty-first inverter, a twenty-second inverter and a twenty-third inverter; The input end of the sixteenth inverter is connected to the output end of the first inverter and the input end of the second inverter, and the output end is connected to the output end of the fifth inverter and the input end of the sixth inverter; The input end of the seventeenth inverter is connected to the output end of the second inverter and the input end of the third inverter, and the output end is connected to the output end of the sixth inverter and the input end of the seventh inverter; The input end of the eighteenth inverter is connected to the output end of the seventh inverter and the input end of the zeroth inverter, and the output end is connected to the output end of the third inverter and the input end of the fourth inverter; The input end of the nineteenth inverter is connected to the output end of the zeroth inverter and the input end of the first inverter, and the output end is connected to the output end of the fourth inverter and the input end of the fifth inverter; The input end of the 20th inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-first inverter is connected to the output end of the fifth inverter and the input end of the sixth inverter, and the output end is connected to the output end of the first inverter and the input end of the second inverter; The input end of the twenty-second inverter is connected to the output end of the fourth inverter and the input end of the fifth inverter, and the output end is connected to the output end of the zeroth inverter and the input end of the first inverter; The input terminal of the twenty-third inverter is connected to the output terminal of the third inverter and the input terminal of the fourth inverter, and the output terminal of the twenty-third inverter is connected to the output terminal of the seventh inverter and the input terminal of the zeroth inverter.

2. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 1, characterized in that: The main path includes: a zeroth inverter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a seventh inverter; The input end of the zeroth inverter is connected to the output end of the seventh inverter, and the output end is connected to the input end of the first inverter; The output terminal of the first inverter is connected to the input terminal of the second inverter; The output terminal of the second inverter is connected to the input terminal of the third inverter; The output terminal of the third inverter is connected to the input terminal of the fourth inverter; The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter; The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter; The output terminal of the sixth inverter is connected to the input terminal of the seventh inverter; The output terminal of the seventh inverter is connected to the input terminal of the zeroth inverter.

3. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 1, characterized in that: The zeroth inverter has the same structure as the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter, the fifteenth inverter, the sixteenth inverter, the seventeenth inverter, the tenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter; The zeroth inverter comprises: a first NMOS tube and a first PMOS tube; The drain of the first PMOS tube is connected to the drain of the first NMOS tube and the source of the first NMOS tube, the source is connected to a high level, and the gate is connected to the gate of the first PMOS tube; The source of the first NMOS tube is grounded.

4. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 1, characterized in that: The structure of the twenty-fourth inverter is consistent with the structures of the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter and the thirty-first inverter; The twenty-four inverters include: a plurality of switch branches; Each of the switch branches is connected in parallel; The switch branch includes: a second NMOS transistor, a second PMOS transistor, a first switch and a second switch; The drain of the second PMOS tube is connected to the first switch, the gate is connected to the gate of the second NMOS tube, and the source is connected to a high level; The drain of the second NMOS tube is connected to the second switch, and the source is grounded.

5. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 1, characterized in that: The driving capabilities of the zeroth inverter, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter and the seventh inverter are 2-3 times that of the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter and the fifteenth inverter.

6. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 5, characterized in that: The driving capabilities of the eighth inverter, the ninth inverter, the tenth inverter, the eleventh inverter, the twelfth inverter, the thirteenth inverter, the fourteenth inverter and the fifteenth inverter are 3-4 times that of the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter.

7. The phase noise and maximum oscillation frequency adjustable ring oscillator according to claim 6, characterized in that: The driving capabilities of the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twentieth inverter, the twenty-first inverter, the twenty-second inverter and the twenty-third inverter are 1.2-1.6 times the driving capabilities of the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter and the thirty-first inverter.

8. A method for controlling a ring oscillator with adjustable phase noise and maximum oscillation frequency, applied to a ring oscillator with adjustable phase noise and maximum oscillation frequency as claimed in any one of claims 1 to 7, characterized in that: include: Under the TT, FF corner conditions, the switches inside the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter are disconnected, that is, the third auxiliary path of the oscillator is disconnected. At this time, the oscillation frequency and phase noise of the oscillator meet the requirements; Under the SS corner condition, switches inside the twenty-fourth inverter, the twenty-fifth inverter, the twenty-sixth inverter, the twenty-seventh inverter, the twenty-eighth inverter, the twenty-ninth inverter, the thirtieth inverter, and the thirty-first inverter are gradually turned on to increase the frequency to a specified value.

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