Silicon carbide driving circuit and control method thereof

Abstract

The invention discloses a silicon carbide drive circuit and a control method thereof, relates to the technical field of power electronics, and solves the problems of failure of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and reduction of circuit reliability caused by high rising speed of interference current and too slow action of a protection circuit in the silicon carbide drive circuit. The circuit comprises an upper tube driving circuit and a lower tube driving circuit, the upper tube driving circuit comprises an upper tube conduction driving circuit and an upper tube turn-off driving circuit with a first bypass semiconductor switch, and the lower tube driving circuit comprises a lower tube conduction driving circuit and a lower tube turn-off driving circuit with a second bypass semiconductor switch. An upper tube driving control signal is input to the second bypass semiconductor switch after being isolated by the second isolation circuit, and a lower tube driving control signal is input to the first bypass semiconductor switch after being isolated by the first isolation circuit, so that the anti-interference capability of the silicon carbide driving circuit is improved, and the application range of the high-frequency and high-power carbonizer is expanded; and the reliability of the silicon carbide MOSFET circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a silicon carbide drive circuit and a control method thereof. Background Art

[0002] With the development of power electronics technology, the application of power MOSFET has made great progress. Silicon carbide semiconductor technology belongs to the third generation of semiconductor technology. Silicon carbide MOSFET devices are typical representatives of the third generation of semiconductor technology. With their wide bandgap characteristics, high breakdown electric field, high thermal conductivity and high switching speed, they show significant advantages in high-frequency, high-power and high-efficiency applications. At present, silicon carbide MOSFET devices have begun to be widely used in electric vehicles, charging piles, new energy, data center power supplies, 5G base stations, etc. With the advancement of silicon carbide semiconductor manufacturing technology and the reduction of costs, silicon carbide MOSFET devices will replace silicon semiconductor devices in more fields in the future.

[0003] Improving the operating voltage and current of silicon carbide MOSFET circuits will help to increase the power output of products and expand the scope of high-power applications. Increasing the operating frequency of silicon carbide MOSFET circuits will help to achieve high-density integration of small-volume products, reduce material costs, and reduce product weight. However, it also has adverse effects. When the operating frequency is increased, the device voltage change rate dv / dt increases when the silicon carbide MOSFET device is turned on and off, which can be as high as 100V / ns. The operating frequency of the circuit depends on the device characteristics, drive circuit design and working conditions. Under high-frequency conditions, the requirements for device characteristics should be reduced as much as possible to reduce the parasitic distributed parameters of silicon carbide MOSFET devices, such as parasitic capacitance (Cgd, Cgs, Cds) and other effects on the circuit. The smaller the parasitic parameters, the higher the allowed dv / dt, and the greater the room for improving the operating frequency. However, in actual applications, the device characteristics are limited by the current semiconductor technology conditions, and it is difficult to quickly break through and improve. It is necessary to improve the operating frequency of the circuit from the drive circuit design and improve the working conditions.

[0004] To increase the operating frequency, it is necessary to reduce the parasitic distribution parameters of SiC MOSFET devices. However, to increase the circuit power, it is necessary to increase the operating voltage and current of SiC MOSFET devices. SiC MOSFET devices require a larger volume, and the increased volume affects the parasitic distribution parameters of SiC MOSFET devices. For example, the parasitic capacitance input capacitance Ciss (Cgd + Cgs) of SiC MOSFET 1200V 60A is 2.3nF, the output capacitance Coss (Cgd + Cds) is 0.25nF, and the reverse transfer capacitance Crss (Cgd) is 0.01nF. The parasitic capacitance input capacitance Ciss (Cgd + Cgs) of SiC MOSFET 1200V 600A is 47.2nF, the output capacitance Coss (Cgd + Cds) is 2.6nF, and the reverse transfer capacitance Crss (Cgd) is 0.11nF. Comparing the distributed parameters of SiC MOSFET 1200V 60A and 1200V 600A, the parasitic distributed parameters of high-current SiC MOSFET increase dramatically. High-power SiC MOSFET, high voltage and high current, has large parasitic parameters, which seriously restricts the increase of operating frequency. Under high power, in order to improve the reliability of SiC MOSFET, it is usually used to increase the gate resistance (Rg) of SiC MOSFET, sacrifice the speed of opening, and reduce the dv / dt voltage change rate, but it leads to increased switching loss and reduced operating frequency. The gate of SiC MOSFET can also be turned off with a higher negative voltage to prevent the gate from mis-turning the device on, but the gate oxide layer of SiC MOSFET is thin and has limited voltage resistance. Excessive negative voltage may cause the gate oxide layer to break down and damage the device, and long-term application of excessive negative voltage will accelerate the aging of the gate oxide layer and reduce the reliability of the device.

[0005] In high-frequency and high-power applications, the dv / dt voltage change rate of SiC MOSFET is high, and the parasitic distributed parameters of SiC MOSFET are large. In typical applications of SiC half-bridge circuits, serious crosstalk will occur during the opening of the upper SiC MOSFET module and the lower SiC MOSFET module. Crosstalk refers to the interference caused by one signal path in the circuit to another signal path. In SiC MOSFET, crosstalk mainly occurs during the switching process, mainly caused by the device parasitic reverse transfer capacitance Crss (also commonly called Miller Capacitance). The reverse transfer capacitance Crss will couple the change of the drain voltage to the gate, affecting the stability of the gate voltage. The voltage change rate dv / dt is high, the parasitic distributed parameters are large, and the current generated by the reverse transfer capacitance Crss is very large. After interference coupling, the switching action of one SiC MOSFET will affect the working state of another SiC MOSFET. When the other one is turned on incorrectly, the two SiC MOSFETs are turned on at the same time, causing a short circuit in the circuit. It may also cause the gate voltage of SiC MOSFET to be too high and break down the gate. In the application of silicon carbide MOSFET circuits, in order to improve the anti-interference ability and reduce the impact of crosstalk, the solution is to add a voltage comparator to the drive circuit to compare the gate voltage. When the gate voltage exceeds the preset protection voltage, the gate voltage protection circuit is triggered to limit the gate voltage change. However, since the protection is based on the amplitude of the interference voltage, the protection circuit takes effect after the interference is generated. Under high frequency and high power conditions, the dv / dt voltage change rate is high, the interference current rises rapidly, and the protection circuit acts too slowly, resulting in the failure of the silicon carbide MOSFET and reduced circuit reliability. Summary of the invention

[0006] The purpose of the present application is to overcome the problem that the interference current rises quickly and the protection circuit acts too slowly in the silicon carbide drive circuit, resulting in failure of the silicon carbide MOSFET device and reduced circuit reliability, and to provide a silicon carbide drive circuit and its control method.

[0007] In a first aspect, a silicon carbide driving circuit is provided, comprising:

[0008] An upper tube driving circuit, the upper tube driving circuit comprising an upper tube conduction driving circuit and an upper tube shutoff driving circuit having a first bypass semiconductor switch, the input ends of the upper tube conduction driving circuit and the upper tube shutoff driving circuit being used to connect the upper tube driving control signal isolated by the first isolation circuit, and the output ends of the upper tube conduction driving circuit and the upper tube shutoff driving circuit being connected to the gate of the first silicon carbide MOS module;

[0009] A lower tube driving circuit, wherein the lower tube driving circuit comprises a lower tube conduction driving circuit and a lower tube shutoff driving circuit having a second bypass semiconductor switch, wherein input ends of the lower tube conduction driving circuit and the lower tube shutoff driving circuit are used to connect the lower tube driving control signal isolated by the second isolation circuit, and output ends of the lower tube conduction driving circuit and the lower tube shutoff driving circuit are connected to the gate of the second silicon carbide MOS module;

[0010] Among them, the upper tube drive control signal is isolated by the second isolation circuit and input into the second bypass semiconductor switch for adjusting the impedance of the lower tube drive circuit during the period when the lower tube drive circuit is turned off. The lower tube drive control signal is isolated by the first isolation circuit and input into the first bypass semiconductor switch for adjusting the impedance of the upper tube drive circuit during the period when the upper tube drive circuit is turned off. The source of the first silicon carbide MOS module and the drain D of the second silicon carbide MOS module are interconnected to form an AC output electrode.

[0011] The upper tube driving circuit is powered by a first isolated DC power supply, and the lower tube driving circuit is powered by a second isolated DC power supply 600. The drain D of the first silicon carbide MOS module is connected to the positive pole of the DC bus of the main circuit, and the source S of the second silicon carbide MOS module is connected to the negative pole of the DC bus of the main circuit. The gate of the first silicon carbide MOS module is electrically connected to a first voltage source, and the gate of the second silicon carbide MOS module is electrically connected to a second voltage source.

[0012] In some possible implementations, the upper tube conduction drive circuit includes a first conduction control level converter, the upper tube drive control signal is isolated by a first isolation circuit and then input to the input end of the first conduction control level converter, the output end of the first conduction control level converter is electrically connected to the gate of the first semiconductor switch tube, the drain of the first semiconductor switch tube is electrically connected to the positive power supply output end of the first isolated DC power supply, the drain of the first semiconductor switch tube is also electrically connected to the first capacitor, the second capacitor and the third capacitor, the other ends of the first capacitor, the second capacitor and the third capacitor are all grounded, and the source of the first semiconductor switch tube is electrically connected to the gate of the first silicon carbide MOS module through a first on-resistance.

[0013] In some possible implementations, the upper tube shutdown drive circuit includes a first shutdown control level converter, the upper tube drive control signal is isolated by the first isolation circuit and then input to the input end of the first shutdown control level converter, the output end of the first shutdown control level converter is electrically connected to the gate of the second semiconductor switch tube, the source of the second semiconductor switch tube is electrically connected to the negative power supply output end of the first isolated DC power supply, the source of the second semiconductor switch tube is also electrically connected to a fourth capacitor, a fifth capacitor and a sixth capacitor, the other ends of the fourth capacitor, the fifth capacitor and the sixth capacitor are all grounded, the drain of the second semiconductor switch tube is electrically connected to the gate of the first silicon carbide MOS module through a first shutdown resistor, the source of the second semiconductor switch tube is also electrically connected to the source of the first bypass semiconductor switch, the drain of the first bypass semiconductor switch is electrically connected to the gate of the first silicon carbide MOS module, the lower tube drive control signal is isolated by the first isolation circuit and then converted by the second conduction control level converter and then input to the gate of the first bypass semiconductor switch, and a first resistor is electrically connected between the gate and the source of the first silicon carbide MOS module.

[0014] In some possible implementations, it also includes Schottky diode 1 and Schottky diode 2, the positive electrode of Schottky diode 1 is electrically connected to the gate of the first silicon carbide MOS module, the negative electrode of Schottky diode 1 is electrically connected to the positive power output terminal of the first isolated DC power supply, the negative electrode of Schottky diode 2 is electrically connected to the gate of the first silicon carbide MOS module, and the positive electrode of Schottky diode 2 is electrically connected to the negative power output terminal of the first isolated DC power supply. Schottky diode 1 and Schottky diode 2 perform voltage stabilization and clamping between the gate of the first silicon carbide MOS module and the first isolated DC power supply, further improving the anti-interference performance.

[0015] In some possible implementations, the lower tube conduction drive circuit includes a third conduction control level converter, the lower tube drive control signal is isolated by the second isolation circuit and then input to the input end of the third conduction control level converter, the output end of the third conduction control level converter is electrically connected to the gate of the third semiconductor switch tube, the drain of the third semiconductor switch tube is electrically connected to the positive power supply output end of the second isolated DC power supply 600, the drain of the third semiconductor switch tube is also electrically connected to the seventh capacitor, the eighth capacitor and the ninth capacitor, the other ends of the seventh capacitor, the eighth capacitor and the ninth capacitor are all grounded, and the source of the third semiconductor switch tube is electrically connected to the gate of the second silicon carbide MOS module through the second on-resistance.

[0016] In some possible implementations, the lower tube shutdown drive circuit includes a second shutdown control level converter, the lower tube drive control signal is isolated by the second isolation circuit and then input to the input end of the second shutdown control level converter, the output end of the second shutdown control level converter is electrically connected to the gate of the fourth semiconductor switch tube, the source of the fourth semiconductor switch tube is electrically connected to the negative power supply output end of the second isolated DC power supply 600, the source of the fourth semiconductor switch tube is also electrically connected to the tenth capacitor, the eleventh capacitor and the twelfth capacitor, the tenth capacitor, the eleventh capacitor and the twelfth capacitor The other ends of the capacitors are grounded, the drain of the fourth semiconductor switch tube is electrically connected to the gate of the second silicon carbide MOS module through the second turn-off resistor, the source of the fourth semiconductor switch tube is also electrically connected to the source of the second bypass semiconductor switch, the drain of the second bypass semiconductor switch is electrically connected to the gate of the second silicon carbide MOS module, the upper tube drive control signal is isolated by the second isolation circuit and then converted by the fourth conduction control level converter and input to the gate of the second bypass semiconductor switch, and a second resistor is electrically connected between the gate and the source of the second silicon carbide MOS module.

[0017] In some possible implementations, Schottky diode three and Schottky diode four are also included, the positive electrode of Schottky diode three is electrically connected to the gate of the second silicon carbide MOS module, the negative electrode of Schottky diode three is electrically connected to the positive power output terminal of the second isolated DC power supply 600, the negative electrode of Schottky diode four is electrically connected to the gate of the second silicon carbide MOS module, and the positive electrode of Schottky diode four is electrically connected to the negative power output terminal of the second isolated DC power supply 600. Schottky diode three and Schottky diode four perform voltage stabilization and clamping between the gate of the second silicon carbide MOS module and the second isolated DC power supply 600, thereby further improving the anti-interference performance.

[0018] In some possible implementations, a first transient overvoltage suppression diode and a first transient overvoltage suppression diode connected in reverse series are electrically connected between the gate and the source of the first silicon carbide MOS module, and a third transient overvoltage suppression diode and a fourth transient overvoltage suppression diode connected in reverse series are electrically connected between the gate and the source of the second silicon carbide MOS module. By setting the first transient overvoltage suppression diode and the first transient overvoltage suppression diode connected in reverse series, the risk of gate and source breakdown of the first silicon carbide MOS module and the first silicon carbide MOS module is reduced.

[0019] In a second aspect, a control method for a silicon carbide driving circuit is provided, comprising:

[0020] Using a first isolated DC power supply and a second isolated DC power supply 600 which are independent of each other to respectively power the upper tube driving circuit and the lower tube driving circuit;

[0021] After the upper tube drive control signal is isolated by the first isolation circuit, the upper tube drive circuit is used to drive and control the on and off of the first silicon carbide MOS module;

[0022] The upper tube drive control signal is isolated by the second isolation circuit and then input to the second bypass semiconductor switch for adjusting the impedance of the lower tube shutdown drive circuit during the shutdown period of the lower tube drive circuit;

[0023] After the lower tube driving control signal is isolated by the second isolation circuit, the lower tube driving circuit is used to drive and control the on and off of the second silicon carbide MOS module;

[0024] The lower tube driving control signal is isolated by the first isolation circuit and then input into the first bypass semiconductor switch for adjusting the impedance of the upper tube shut-down driving circuit during the shut-down period of the upper tube driving circuit.

[0025] In some possible implementations, the maximum allowable peak current of the first bypass semiconductor switch and the second bypass semiconductor switch should satisfy the following formula:

[0026]

[0027] Among them, I p is the maximum allowable peak current of the first bypass semiconductor switch or the second bypass semiconductor switch; C GD is the capacitance value between the gate and drain of the silicon carbide MOSFET module in the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube; dU is the voltage change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on; dt is the time change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on.

[0028] In some possible implementations, the conduction equivalent resistance of the first bypass semiconductor switch and the second bypass semiconductor switch should satisfy the following formula:

[0029]

[0030] Among them, R on is the conduction equivalent resistance of the first bypass semiconductor switch or the second bypass semiconductor switch; C GD is the capacitance value between the gate and drain of the silicon carbide MOSFET module in the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube; dU is the voltage change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on; dt is the time change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on.

[0031] In some possible implementations, the time from turning off to turning on of the first bypass semiconductor switch and the second bypass semiconductor switch is less than one tenth of the time from turning off to turning on of the silicon carbide MOSFET modules in the silicon carbide half-bridge upper tube and the silicon carbide half-bridge lower tube.

[0032] This application has the following beneficial effects:

[0033] 1. The silicon carbide drive circuit of the present application is suitable for drive control containing a silicon carbide half-bridge. In addition to the conventional on-off drive control of the upper tube and the lower tube of the silicon carbide half-bridge, the upper tube drive control signal and the lower tube drive control signal are also introduced into the lower tube for lower tube drive protection, and the lower tube drive control signal is introduced into the upper tube for upper tube drive protection, thereby improving the anti-interference ability of the silicon carbide drive circuit, expanding the application range of high-frequency and high-power carbides, improving the reliability of the silicon carbide MOSFET circuit, and reducing the voltage value of the negative voltage turned off by the silicon carbide drive circuit, preventing the gate oxide layer from being damaged by excessive negative voltage breakdown, and avoiding the long-term application of excessive negative voltage to accelerate the aging of the gate oxide layer and reduce the service life of the device;

[0034] 2. The silicon carbide drive circuit of the present application uses the original upper tube drive control signal and the lower tube drive control signal in the drive circuit for protection control, and can be directly connected to the original interface in the external control system without the need for additional control signals. When upgrading, only the drive circuit itself needs to be upgraded and replaced, and the upgrade cost is low and the method is simple;

[0035] 3. The control method of the present application introduces the upper tube drive control signal into the lower tube for lower tube drive protection, and introduces the lower tube drive control signal into the upper tube for upper tube drive protection, so that the protection circuit is actuated before the upper tube or lower tube of the silicon carbide half-bridge is turned on, and the anti-interference protection of the silicon carbide half-bridge lower tube drive is turned on in advance, avoiding the lag and delay of the traditional silicon carbide drive Miller clamp protection action, thereby improving the protection capability of high-frequency and high-power silicon carbide and improving the reliability of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application.

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1is a circuit block diagram of a silicon carbide driving circuit of Example 1 of the present application;

[0039] Figure 2 The circuit is the silicon carbide driving circuit of Example 1 of the present application;

[0040] Figure 3 This is the schematic diagram of the silicon carbide half-bridge circuit used for motor drive control;

[0041] Figure 4 It is the equivalent circuit of the parasitic distribution parameters of SiC MOSFET;

[0042] Figure 5 This is the driving waveform diagram of the upper tube and lower tube of the existing silicon carbide half-bridge circuit;

[0043] Figure 6 This is a driving waveform diagram of the upper tube and the lower tube of the silicon carbide half-bridge circuit after the silicon carbide driving circuit of Example 1 of the present application is adopted;

[0044] Figure 7 This is a protection principle diagram of turning off the drive of the upper tube when the lower tube of the silicon carbide half-bridge circuit is turned on after the silicon carbide driving circuit of Example 1 of the present application is adopted;

[0045] Figure 8 This is a protection principle diagram of turning off the drive of the lower tube when the upper tube of the silicon carbide half-bridge circuit is turned on after the silicon carbide driving circuit of Example 1 of the present application is adopted;

[0046] Fig. 9 This is a protection waveform diagram of turning off the upper tube when the lower tube of the silicon carbide half-bridge circuit is turned on after the silicon carbide driving circuit of Example 1 of the present application is adopted;

[0047] Fig.10 This is a protection waveform diagram of the lower tube being turned off when the upper tube of the silicon carbide half-bridge circuit is turned on after the silicon carbide driving circuit of Example 1 of the present application is adopted.

[0048] Reference numerals:

[0049] 100, upper tube driving circuit; 101, upper tube conduction driving circuit; 102, first bypass semiconductor switch; 103, upper tube shutdown driving circuit; 200, first silicon carbide MOS module; 300, lower tube driving circuit; 301, lower tube conduction driving circuit; 302, second bypass semiconductor switch; 303, lower tube shutdown driving circuit; 400, second silicon carbide MOS module; 500, first isolated DC power supply; 600, second isolated DC power supply 600. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] Example 1

[0052] like Figure 1 As shown, a silicon carbide drive circuit involved in Example 1 of the present application includes: an upper tube drive circuit 100, the upper tube drive circuit 100 includes an upper tube conduction drive circuit 101 and an upper tube shutdown drive circuit 103 having a first bypass semiconductor switch 102, the input ends of the upper tube conduction drive circuit 101 and the upper tube shutdown drive circuit 103 are used to connect the upper tube drive control signal isolated by the first isolation circuit, and the output ends of the upper tube conduction drive circuit 101 and the upper tube shutdown drive circuit 103 are connected to the first silicon carbide The gate of the MOS module 200 is connected; the lower tube driving circuit 300, the lower tube driving circuit 300 includes a lower tube conduction driving circuit 301 and a lower tube shutdown driving circuit 303 having a second bypass semiconductor switch 302, the input ends of the lower tube conduction driving circuit 301 and the lower tube shutdown driving circuit 303 are used to connect the lower tube drive control signal isolated by the second isolation circuit, and the output ends of the lower tube conduction driving circuit 301 and the lower tube shutdown driving circuit 303 are connected to the gate of the second silicon carbide MOS module 400;

[0053] Among them, the upper tube drive control signal is isolated by the second isolation circuit and input into the second bypass semiconductor switch 302 for adjusting the impedance of the lower tube shutdown drive circuit 303 during the shutdown period of the lower tube drive circuit 300. The lower tube drive control signal is isolated by the first isolation circuit and input into the first bypass semiconductor switch 102 for adjusting the impedance of the upper tube drive circuit 100 during the shutdown period of the upper tube. The source of the first silicon carbide MOS module 200 and the drain D of the second silicon carbide MOS module 400 are interconnected to form an AC output pole.

[0054] like Figure 2 As shown, the silicon carbide half-bridge circuit includes two silicon carbide modules, namely the first silicon carbide MOS module and the second silicon carbide MOS module. The first silicon carbide MOS module whose drain D is connected to the positive pole of the DC bus of the main circuit is called the upper tube, and the second silicon carbide MOS module whose source S is connected to the negative pole of the DC bus of the main circuit is called the lower tube. The source S of the upper tube and the drain D of the lower tube are connected to each other to form an AC output pole. The upper tube includes an independent gate G for drive control, and the lower tube also includes an independent gate G for drive control. See the typical circuit for details. Figure 3Schematic diagram of silicon carbide half-bridge circuit for motor drive control. Figure 3 1, 2, and 3 are three silicon carbide half-bridge circuits.

[0055] The silicon carbide driving circuit of this embodiment includes two sets of independent high-voltage isolated DC power supplies U1 and U2. The first isolated DC power supply U1 is used to power the upper tube driving circuit 100 of the first silicon carbide MOS tube MOS_A of the silicon carbide half-bridge circuit, and the first isolated DC power supply 500U2 is used to power the lower tube driving circuit 300 of the second silicon carbide MOS tube MOS_B of the silicon carbide half-bridge circuit. Vin and GND are external power inputs of the silicon carbide driving circuit, and the DC power supply is generally 15~36V. After the DC / DC isolation conversion, the first isolated DC power supply U1 generally outputs positive and negative DC. The positive power supply is S1+ and GND1, and the typical value of S1+ is 15V~20V. The negative power supply is S1- and GND1, and the typical value of S1- is -3V~-5V. After the DC / DC isolation conversion, the second isolated DC power supply U2 generally outputs positive and negative DC. The positive power supply is S2+ and GND2, and the typical value of S2+ is 15V~20V. The negative power supply is S2- and GND2, and the typical value of S2- is -3V~-5V. The first silicon carbide MOS module 200 includes a first silicon carbide MOS tube MOS_A, and the second silicon carbide MOS module 400 includes a second silicon carbide MOS tube MOS_B. A diode is connected between the drain D and the source S of the first silicon carbide MOS tube MOS_A and the second silicon carbide MOS tube MOS_B. The drain D of the first silicon carbide MOS tube MOS_A is connected to the positive pole of the DC bus of the main circuit, and the source S of the second silicon carbide MOS tube MOS_B is connected to the negative pole of the DC bus of the main circuit. The gate of the first silicon carbide MOS tube MOS_A is electrically connected to the first voltage source V GSA The gate of the second silicon carbide MOS tube MOS_B is electrically connected to a second voltage source V GSB .

[0056] The upper tube conduction driving circuit 101 includes a first conduction control level converter Q11. The upper tube driving control signal PWM_A is isolated by the first isolation circuit M1 and then input to the input end of the first conduction control level converter Q11. The output end of the first conduction control level converter Q11 is connected to the first semiconductor switch tube VT ON1 The gate of the first semiconductor switch tube VT is electrically connected to ON1 The drain of the first semiconductor switch tube VT is electrically connected to the positive power supply S1+ of the first isolated DC power supply U1. ON1 The drain of the first semiconductor switch tube VT is also electrically connected to the first capacitor C11, the second capacitor C12 and the third capacitor C13. The other ends of the first capacitor C11, the second capacitor C12 and the third capacitor C13 are all grounded.ON1 The source of the ON1 The gate of the first silicon carbide MOS tube MOS_A is electrically connected.

[0057] The upper tube shutdown driving circuit 103 includes a first shutdown control level converter Q12. The upper tube driving control signal PWM_A is isolated by the first isolation circuit M1 and then input to the input end of the first shutdown control level converter Q12. The output end of the first shutdown control level converter Q12 is connected to the second semiconductor switch tube VT OFF1 The gate of the second semiconductor switch tube VT is electrically connected to OFF1 The source of the first isolated DC power supply U1 is electrically connected to the negative power supply S1-, and the second semiconductor switch tube VT OFF1 The source of the second semiconductor switch VT is also electrically connected to the fourth capacitor C14, the fifth capacitor C15 and the sixth capacitor C16, the other ends of the fourth capacitor C14, the fifth capacitor C15 and the sixth capacitor C16 are all grounded, and the second semiconductor switch VT OFF1 The drain of the OFF1 The gate of the first silicon carbide MOS tube MOS_A is electrically connected to the second semiconductor switch tube VT OFF1 The source of the first bypass semiconductor switch VT P1 The source of the first bypass semiconductor switch VT is electrically connected to P1 The drain of the first silicon carbide MOS tube MOS_A is electrically connected, and the lower tube drive control signal PWM_B is isolated by the first isolation circuit M1 and then converted by the second conduction control level converter Q13 and input to the first bypass semiconductor switch VT P1 A first resistor R11 is electrically connected between the gate and the source of the first silicon carbide MOS tube MOS_A.

[0058] The lower tube conduction driving circuit 301 includes a third conduction control level converter Q21. The lower tube driving control signal PWM_B is isolated by the second isolation circuit M2 and then input to the input end of the third conduction control level converter Q21. The output end of the third conduction control level converter Q21 is connected to the third semiconductor switch tube VT ON2 The gate of the third semiconductor switch tube VT is electrically connected to ON2 The drain of the third semiconductor switch tube VT is electrically connected to the positive power supply S2+ of the second isolated DC power supply U2. ON2 The drain of the third semiconductor switch tube VT is also electrically connected to the seventh capacitor C21, the eighth capacitor C22 and the ninth capacitor C23, the other ends of the seventh capacitor C21, the eighth capacitor C22 and the ninth capacitor C23 are all grounded, and the third semiconductor switch tube VT ON2 The source of the ON2 The gate of the second silicon carbide MOS transistor MOS_B is electrically connected.

[0059] The lower tube shutdown driving circuit 303 includes a second shutdown control level converter Q22. The lower tube driving control signal PWM_B is isolated by the second isolation circuit M2 and then input to the input end of the second shutdown control level converter Q22. The output end of the second shutdown control level converter Q22 is connected to the fourth semiconductor switch tube VT OFF2 The gate of the fourth semiconductor switch tube VT is electrically connected to OFF2 The source of the fourth semiconductor switch tube VT is electrically connected to the negative power supply S2- of the second isolated DC power supply U2. OFF2 The source of the fourth semiconductor switch tube VT is also electrically connected to the tenth capacitor C24, the eleventh capacitor C25 and the twelfth capacitor C26, the other ends of the tenth capacitor C24, the eleventh capacitor C25 and the twelfth capacitor C26 are all grounded, and the fourth semiconductor switch tube VT OFF2 The drain of the OFF2 The fourth semiconductor switch tube VT is electrically connected to the gate of the second silicon carbide MOS tube MOS_B. OFF2 The source of the second bypass semiconductor switch VT P2 The source of the second bypass semiconductor switch VT is electrically connected to P2 The drain of the upper tube is electrically connected to the gate of the second silicon carbide MOS tube MOS_B, and the upper tube driving control signal PWM_A is isolated by the second isolation circuit M2 and then converted by the fourth conduction control level converter Q23 and input to the second bypass semiconductor switch VT P2 A second resistor R12 is electrically connected between the gate and the source of the second silicon carbide MOS tube MOS_B.

[0060] In a further embodiment, a Schottky diode D11 and a Schottky diode D12 are further included. The positive electrode of the Schottky diode D11 is electrically connected to the gate of the first silicon carbide MOS tube MOS_A, and the negative electrode of the Schottky diode D11 is electrically connected to the positive power supply S1+ of the first isolated DC power supply 500. The voltage of the positive power supply output S1+ capacitor (C11, C12, C13) is clamped to prevent the positive voltage of the insulated gate of silicon carbide from exceeding the positive voltage allowed by the device itself and damaging the first silicon carbide MOS tube MOS_A. The negative electrode of the Schottky diode D12 is electrically connected to the gate of the first silicon carbide MOS tube MOS_A, and the positive electrode of the Schottky diode D12 is electrically connected to the positive power supply S1- of the first isolated DC power supply 500. The voltage of the negative power supply output S1- capacitor (C14, C15, C16) is clamped to prevent the negative voltage of the insulated gate of silicon carbide from exceeding the negative voltage allowed by the device itself and damaging the first silicon carbide MOS tube MOS_A.

[0061] In a further embodiment, a Schottky diode D21 and a Schottky diode D22 are also included. The positive electrode of the Schottky diode D21 is electrically connected to the gate of the second silicon carbide MOS tube MOS_B, and the negative electrode of the Schottky diode D21 is electrically connected to the positive power supply S2+ of the second isolated DC power supply 600. The voltage clamping of the positive power supply S2+ capacitor (C21, C22, C23) prevents the positive voltage of the insulated gate of silicon carbide from exceeding the positive voltage allowed by the device itself and damaging the second silicon carbide MOS tube MOS_B. The negative electrode of the Schottky diode D22 is electrically connected to the gate of the second silicon carbide MOS tube MOS_B, and the positive electrode of the Schottky diode D22 is electrically connected to the positive power supply S2- of the second isolated DC power supply 600. The voltage clamping of the negative power supply S2- capacitor (C24, C25, C26) prevents the negative voltage of the insulated gate of silicon carbide from exceeding the negative voltage allowed by the device itself and damaging the second silicon carbide MOS tube MOS_B.

[0062] A first transient overvoltage suppression diode D13 and a first transient overvoltage suppression diode D14 connected in reverse series are electrically connected between the gate and the source of the first silicon carbide MOS tube MOS_A, and a third transient overvoltage suppression diode D23 and a fourth transient overvoltage suppression diode D24 connected in reverse series are electrically connected between the gate and the source of the second silicon carbide MOS tube MOS_B.

[0063] After the upper tube drive control signal PWM_A of the first silicon carbide MOS tube MOS_A of the upper tube is isolated and converted by the isolation conversion circuit M1, the high level signal of the upper tube drive control signal PWM_A is converted by the first conduction control level converter Q11 circuit level to drive the first semiconductor switch tube VT ON1 , connect the positive power supply S1+ of the first isolated DC power supply U1, and the positive power supply S1+ is connected to the positive power supply S1+ through the on-resistance R ON1 The gate G of the first silicon carbide MOS tube MOS_A connected to the upper tube, the source of the first silicon carbide MOS tube MOS_A is connected to the GND1 of the first isolated DC power supply U1, and the V GSA The voltage rises toward the S1+ voltage value, controlling the first silicon carbide MOS tube MOS_A to be turned on.

[0064] At the same time, after the upper tube driving control signal PWM_A of the first silicon carbide MOS tube MOS_A of the upper tube is isolated and converted by another isolation conversion circuit M2, the PWM_A level signal is converted by the Q23 circuit level to drive the lower tube of the second silicon carbide MOS tube MOS_B of the lower tube to turn off the second bypass semiconductor switch VT of the driving circuit 303. P2, used to adjust the impedance of the lower tube shutdown drive circuit 303 during the shutdown period of the second silicon carbide MOS tube MOS_B, when the upper tube drive control signal PWM_A of the first silicon carbide MOS tube MOS_A is at a low level, the second bypass semiconductor switch VT of the lower tube shutdown drive circuit 303 P2 Turn off, the second turn-off resistor R OFF2 When the upper tube drive control signal PWM_A of the first silicon carbide MOS tube MOS_A is at a high level, the second bypass semiconductor switch VT of the lower tube drive circuit 303 of the second silicon carbide MOS tube MOS_B is turned off. P2 On, the second off resistor R OFF2 The second silicon carbide MOS tube MOS_B is short-circuited, and the impedance of the lower tube shutdown driving circuit 303 of the second silicon carbide MOS tube MOS_B becomes smaller, thereby stabilizing the shutdown voltage of the gate G of the second silicon carbide MOS tube MOS_B, thereby preventing the shutdown voltage of the second silicon carbide MOS tube MOS_B from being affected by the conduction of the first silicon carbide MOS tube MOS_A during the shutdown period of the second silicon carbide MOS tube MOS_B, thereby causing the second silicon carbide MOS tube MOS_A to be mis-turned on.

[0065] The upper tube drive control signal PWM_A low level signal is converted by the first off control level converter Q12 circuit level to drive the second semiconductor switch tube VT OFF1 , connect the negative power supply S1- of the first isolated DC power supply U1, and the negative power supply S1- is connected to the first off resistor R OFF1 The gate G of the first silicon carbide MOS tube MOS_A is connected, the source of the first silicon carbide MOS tube MOS_A is connected to the GND1 of the first isolated DC power supply U1, and the V GSA The voltage drops toward the S1-voltage value, controlling the first silicon carbide MOS tube MOS_A to be turned off.

[0066] After the lower tube drive control signal PWM_B is isolated and transformed by the second isolation conversion circuit M2, the high level signal of the lower tube drive control signal PWM_B is converted by the third conduction control level converter Q21 circuit level to drive the third semiconductor switch tube VT ON2 , connect the positive power supply S2+ of the second isolated DC power supply U2, and the positive power supply S2+ passes through the second on-resistance R ON2 The gate G of the second silicon carbide MOS tube MOS_B is connected, the source of the second silicon carbide MOS tube MOS_B is connected to the GND2 of the second isolated DC power supply U2, and the V GSB The voltage rises toward the S2+ voltage value, controlling the second silicon carbide MOS tube MOS_B of the lower tube to be turned on.

[0067] At the same time, after the lower tube drive control signal PWM_B of the second silicon carbide MOS tube MOS_B is isolated and converted by another first isolation conversion circuit M1, the level signal of the lower tube drive control signal PWM_B is converted by the second conduction control level converter Q13 circuit level conversion, driving the first bypass semiconductor switch VT of the upper tube turn-off drive circuit 103 of the first silicon carbide MOS tube MOS_A. P1 , used to adjust the impedance of the upper tube shutdown drive circuit 103 during the shutdown period of the first silicon carbide MOS tube MOS_A, when the lower tube drive control signal PWM_B of the second silicon carbide MOS tube MOS_B is at a low level, the first bypass semiconductor switch VT of the upper tube shutdown drive circuit 103 P1 Turn off, the first turn-off resistor R OFF1 When the lower tube drive control signal PWM_B of the second silicon carbide MOS tube MOS_B is at a high level, the first bypass semiconductor switch VT of the upper tube drive circuit 103 of the first silicon carbide MOS tube MOS_A is turned off. P1 On, the first off resistance R OFF1 The first silicon carbide MOS tube MOS_A is short-circuited, and the impedance of the upper tube shutdown drive circuit 103 of the first silicon carbide MOS tube MOS_A becomes smaller, thereby stabilizing the shutdown voltage of the gate G of the first silicon carbide MOS tube MOS_A, thereby preventing the shutdown voltage of the first silicon carbide MOS tube MOS_A from being affected by the conduction of the second silicon carbide MOS tube MOS_B during the shutdown period of the first silicon carbide MOS tube MOS_A, thereby causing the first silicon carbide MOS tube MOS_A to be mis-turned on.

[0068] The low level signal of the lower tube drive control signal PWM_B is converted by the second shutdown control level converter Q22 circuit to drive the second semiconductor switch tube VT OFF2 , connect the negative power supply S2- of the second isolated DC power supply U2, and the negative power supply S2- is connected to the negative power supply S2- through the second turn-off resistor R OFF2 The gate G of the second silicon carbide MOS tube MOS_B is connected, the source of the second silicon carbide MOS tube MOS_B is connected to the GND2 of the second isolated DC power supply U2, and the V GSB The voltage drops toward the S2-voltage value, controlling the second silicon carbide MOS tube MOS_B to turn off.

[0069] In high-frequency and high-power applications, the performance of SiC MOSFET devices is greatly affected by the device's own parasitic distribution parameters. The equivalent circuit is as follows: Figure 4 As shown:

[0070] RDS on-resistance: The equivalent resistance between the drain and the source in the on-state, in ohms ( );

[0071] LS drain-source inductance: the equivalent internal inductance between the drain and the source, in henry (H);

[0072] MOSideal ideal switch: Silicon carbide MOSFET ideal switch, on-resistance is 0, off-resistance is ∞;

[0073] RG Gate internal resistance: Gate equivalent internal resistance, in ohms ( );

[0074] LG gate inductance: gate equivalent internal inductance, unit is Henry (H);

[0075] CGS gate-source capacitance: the capacitance between the gate and the source, in Farad (F);

[0076] CGD gate-drain capacitance: the capacitance between the gate and the drain, in farads (F);

[0077] CDS drain-source capacitance: the capacitance between the drain and the source, in farads (F);

[0078] DBD equivalent body diode: includes forward conduction voltage and reverse breakdown voltage, in volts (V);

[0079] The parasitic distributed parameters that affect the SiC MOSFET drive circuit are RG gate internal resistance, LG gate inductance, CGS gate-source capacitance and CGD gate-drain capacitance.

[0080] like Figure 5 As shown in the figure, it is a driving waveform diagram of the upper tube and lower tube of the silicon carbide half-bridge circuit in the prior art in high-frequency and high-power applications. The driving control signal PWM_A of the first silicon carbide MOS tube MOS_A and the driving control signal PWM_B of the upper tube MOS_B are both from the control system. The typical low level value of PWM_A and PWM_B is 0V, which is used to control the silicon carbide MOSFET to turn off. The typical high level value of PWM_A and PWM_B is 5V, which is used to control the silicon carbide MOSFET to turn on. The driving control signals PWM_A and PWM_B are isolated by the isolation circuit and converted by the level conversion circuit. The gate voltage V GSA , the gate voltage of the lower tube MOS_A is V GSB The actual gate G voltage corresponding to the control of the silicon carbide MOSFET to turn off is typically -3V, and the gate G voltage corresponding to the control of the silicon carbide MOSFET to turn on is typically +18V.

[0081] from Figure 5 It can be seen that when the PWM_A voltage rises from 0V to +5V, Figure 5 The gate voltage V of the first silicon carbide MOS tube MOS_A at a1 GSAFrom -3V to +18V, that is, during the period when the first silicon carbide MOS tube MOS_A is turned on, PWM_B is kept at 0V, but Figure 5 The gate voltage V of the second silicon carbide MOS tube MOS_B at b2 GSB The -3V off voltage cannot be maintained, and interference occurs, resulting in an abnormal change from -3V to +5V. The +5V voltage exceeds the threshold voltage of the gate of the second silicon carbide MOS tube MOS_B, causing the second silicon carbide MOS tube MOS_B to be mis-conducted. When the PWM_B voltage rises from 0V to +5V, Figure 5 The gate voltage V of the second silicon carbide MOS tube MOS_B at b1 GSB From -3V to +18V, that is, during the period when the second silicon carbide MOS tube MOS_B is turned on, the PWM_A voltage remains at 0V, but Figure 5 The gate voltage V of the first silicon carbide MOS tube MOS_A at a2 GSA The -3V off voltage cannot be maintained, and interference occurs, resulting in an abnormal change from -3V to +5V. The +5V voltage exceeds the threshold voltage for the gate of the first silicon carbide MOS tube MOS_A to be turned on, resulting in mis-conduction of the first silicon carbide MOS tube MOS_A.

[0082] In high-frequency and high-power applications, after adopting the silicon carbide driving circuit of this example, the driving waveforms of the upper and lower tubes of the silicon carbide half-bridge circuit are as follows: Figure 6 shown.

[0083] The first drive control signal PWM_A of the first silicon carbide MOS tube MOS_A and the second drive control signal PWM_B of the upper tube MOS_B are both from the control system. The typical low level value of PWM_A and PWM_B is 0V, which is used to control the silicon carbide MOSFET to turn off. The typical high level value of PWM_A and PWM_B is 5V, which is used to control the silicon carbide MOSFET to turn on. The drive control signals PWM_A and PWM_B are isolated by the isolation circuit and converted by the level conversion circuit. The gate voltage V GSA , the gate voltage of the lower tube MOS_A is V GSB The actual gate G voltage corresponding to the control of the silicon carbide MOSFET to turn off is typically -3V, and the gate G voltage corresponding to the control of the silicon carbide MOSFET to turn on is typically +18V.

[0084] from Figure 6 It can be seen that when the PWM_A voltage rises from 0V to +5V, Figure 6 The gate voltage V of the first silicon carbide MOS tube MOS_A at a1 GSA From -3V to +18V, that is, during the period when the first silicon carbide MOS tube MOS_A is turned on, PWM_B is kept at 0V. Figure 6 The gate voltage V of the second silicon carbide MOS tube MOS_B at b2 GSB The -3V turn-off voltage of the PWM_B is slightly changed due to interference. The voltage rises from -3V to -2.5V. The voltage does not exceed the threshold voltage of the gate of the second silicon carbide MOS tube MOS_B, and the second silicon carbide MOS tube MOS_B will not be misled. When the PWM_B voltage rises from 0V to +5V, Figure 6 The gate voltage V of the second silicon carbide MOS tube MOS_B at b1 GSB From -3V to +18V, that is, during the period when the second silicon carbide MOS tube MOS_B is turned on, the PWM_A voltage remains at 0V. Figure 6 The gate voltage V of the first silicon carbide MOS tube MOS_A at a2 GSA The turn-off voltage has a slight change caused by interference, from -3V to -2.5V. The voltage does not exceed the threshold voltage of the gate of the first silicon carbide MOS tube MOS_A for conduction, and the first silicon carbide MOS tube MOS_A will not be mis-turned on.

[0085] In this embodiment, when the lower tube of the silicon carbide half-bridge circuit is turned on, the protection principle diagram of the upper tube is turned off and driven, as shown in FIG. Figure 7 shown.

[0086] Before the second silicon carbide MOS tube MOS_B is turned on, the PWM_A voltage is 0V, and the gate voltage of the first silicon carbide MOS tube MOS_A is V GSA The first silicon carbide MOS tube MOS_A is kept at a -3V off voltage to keep it off. When the PWM_B voltage rises from 0V to +5V, it is used to drive the third semiconductor switch tube VT after isolation conversion by the second isolation conversion circuit M2. ON2 , the gate voltage of the second silicon carbide MOS tube MOS_B is V GSB The voltage of PWM_B rises from -3V to +18V, controlling the second silicon carbide MOS tube MOS_B from off to on, and the midpoint AC1 of the half bridge drops rapidly to DC-. After the PWM_B voltage is isolated and transformed by the first isolation conversion circuit M1, it simultaneously enters the drive circuit of the first silicon carbide MOS tube MOS_A. The voltage of PWM_B rises from 0V to +5V, and the first silicon carbide MOS tube MOS_A turns off the first bypass semiconductor switch VT of the drive circuit. P1 The first turn-off resistor R OFF1 The first bypass semiconductor switch VT is short-circuited, and the impedance of the upper tube of the first silicon carbide MOS tube MOS_A is reduced. P1 The working voltage and current are much smaller than the working voltage and current of the second silicon carbide MOS tube MOS_B in the main circuit, and the first bypass semiconductor switch VT P1The parasitic distributed parameter CGS gate-source capacitance value of the second silicon carbide MOS tube MOS_B in the main circuit is also much smaller than the parasitic distributed parameter CGS gate-source capacitance value of the second silicon carbide MOS tube MOS_B. Although the same control signal PWM_B is used, the first bypass semiconductor switch VT P1 It will be turned on before the second silicon carbide MOS tube MOS_B is turned on, and the driving anti-interference protection of the first silicon carbide MOS tube MOS_A is turned on in advance, reducing the impedance of the upper tube shutdown drive circuit 103 of the first silicon carbide MOS tube MOS_A. During the period when the second silicon carbide MOS tube MOS_B is turned off and on, and the midpoint AC1 of the half bridge drops rapidly to DC-, the DC bus DC+ passes through the CGD gate-drain capacitance of the first silicon carbide MOS tube MOS_A and the first bypass semiconductor switch VT P1 , negative power supply S1-filter capacitor (C14, C15, C16), half-bridge midpoint AC1, second silicon carbide MOS tube MOS_B reaches DC bus DC-, forming an interference loop. IDG is the current of the interference loop, and the current IDG flows through the first bypass semiconductor switch VT P1 , the negative power supply S1-filter capacitor (C14, C15, C16) forms interference. At this time, the gate of the first silicon carbide MOS tube MOS_A and the negative power supply S1-filter capacitor (C14, C15, C16) are connected through the first bypass semiconductor switch VT P1 Connection, ideally first bypass semiconductor switch VT P1 The on-resistance is zero, and the gate voltage of the first silicon carbide MOS tube MOS_A is V GSA The voltage of the negative power supply S1-filter capacitor (C14, C15, C16) is clamped to maintain the -3V turn-off voltage. However, the actual first bypass semiconductor switch VT P1 The on-resistance cannot be zero. The first bypass semiconductor switch VT P1 When turned on, the gate of the first silicon carbide MOS tube MOS_A is V GSA The turn-off voltage shows a slight change due to interference, and the first bypass semiconductor switch VT is selected. P1 The appropriate on-resistance can make the gate V of the first silicon carbide MOS tube MOS_A GSA The turn-off voltage is controlled to change slightly from -3V to -2.5V, so that the first silicon carbide MOS tube MOS_A remains turned off, and does not cause the first silicon carbide MOS tube MOS_A and the second silicon carbide MOS tube MOS_B to be turned on at the same time, thereby preventing a short circuit fault of the DC bus DC+ and DC-.

[0087] After the PWM_B voltage drops from +5V to 0V, the second silicon carbide MOS tube MOS_B is turned off, and the bypass semiconductor switch VTP1 is turned off.

[0088] When the lower tube of the silicon carbide half-bridge circuit is turned on, the protection waveform of the upper tube is turned off, as shown in Fig. 9 As shown, when the PWM_B voltage rises from 0V to +5V, it is used to drive the third semiconductor switch tube VT ON2 , the gate voltage of the second silicon carbide MOS tube MOS_B is V GSB The voltage rises from -3V to +18V, controlling the second silicon carbide MOS tube MOS_B to conduct. The first bypass semiconductor switch VT used to protect the first silicon carbide MOS tube MOS_A P1 Gate voltage VT P1 _GS rises from -3V to +18V, controlling the first bypass semiconductor switch VT P1 Comparison Fig. 9 VT P1 _GS and V GSB It can be seen from the driving waveform used to control the conduction that the first bypass semiconductor switch VT used to protect the first silicon carbide MOS tube MOS_A P1 After the first one is turned on, the second silicon carbide MOS tube MOS_B starts to be turned on, and the protection is turned on before the interference occurs.

[0089] After adopting the driving anti-interference scheme, when the upper tube of the silicon carbide half-bridge circuit is turned on, the protection principle diagram of the lower tube is turned off, as shown in the figure. Figure 8 shown.

[0090] Before the first silicon carbide MOS tube MOS_A is turned on, the PWM_B voltage is 0V and the gate voltage of the second silicon carbide MOS tube MOS_B is V GSB The off voltage is maintained at -3V, so that the second silicon carbide MOS tube MOS_B remains off. When the PWM_A voltage rises from 0V to +5V, it is used to drive the first semiconductor switch tube VT after isolation conversion by the first isolation conversion circuit M1. ON1 , the gate voltage of the first silicon carbide MOS tube MOS_A is V GSA The voltage rises from -3V to +18V, controlling the first silicon carbide MOS tube MOS_A from off to on, and the midpoint AC1 of the half bridge rises quickly to DC+. After the PWM_A voltage is isolated and transformed by the second isolation conversion circuit M2, it enters the drive circuit of the second silicon carbide MOS tube MOS_B at the same time. The PWM_A voltage rises from 0V to +5V, and the second silicon carbide MOS tube MOS_B turns off the second bypass semiconductor switch VT of the drive circuit. P2 The second turn-off resistor R OFF2 The second silicon carbide MOS tube MOS_B turns off the impedance of the drive circuit and becomes smaller. P2 The working voltage and current are much smaller than the working voltage and current of the first silicon carbide MOS tube MOS_A in the main circuit, and the second bypass semiconductor switch VT P2The parasitic distributed parameter CGS gate-source capacitance value of the first silicon carbide MOS tube MOS_A in the main circuit is also much smaller than the parasitic distributed parameter CGS gate-source capacitance value of the first silicon carbide MOS tube MOS_A in the main circuit. Although the same control signal PWM_A is used, the second bypass semiconductor switch VT P2 It will be turned on before the first silicon carbide MOS tube MOS_A is turned on, and the second silicon carbide MOS tube MOS_B will be turned on in advance to drive anti-interference protection, reducing the impedance of the second silicon carbide MOS tube MOS_B shutdown drive circuit. When the first silicon carbide MOS tube MOS_A is turned on from off, and the half-bridge midpoint AC1 quickly rises to DC+, the DC bus DC+ passes through the first silicon carbide MOS tube MOS_A, the half-bridge midpoint AC1, the CGD gate-drain capacitance of the second silicon carbide MOS tube MOS_B, and the second bypass semiconductor switch VT P2 , the negative power supply S2-filter capacitor (C24, C25, C26) reaches the DC bus DC-, forming an interference loop. IDG is the current of the interference loop, and the current IDG flows through the second bypass semiconductor switch VT P2 , the negative power supply S2-filter capacitor (C24, C25, C26) forms interference. At this time, the gate of the second silicon carbide MOS tube MOS_B and the negative power supply S2-filter capacitor (C24, C25, C26) are connected through the second bypass semiconductor switch VT P2 Connect, ideally the second bypass semiconductor switch VT P2 The on-resistance is zero, and the gate voltage of the second silicon carbide MOS tube MOS_B is V GSB The voltage of the negative power supply S2-filter capacitor (C24, C25, C26) is clamped to maintain the -3V turn-off voltage. However, the actual second bypass semiconductor switch VT P2 The on-resistance cannot be zero, and the second bypass semiconductor switch VT P2 When turned on, the gate of the second silicon carbide MOS tube MOS_B is V GSB The turn-off voltage has a small change caused by interference, and the second bypass semiconductor switch VT is selected P2 The appropriate on-resistance can make the gate V GSB The turn-off voltage is controlled to change slightly from -3V to -2.5V, so that the second silicon carbide MOS tube MOS_B remains turned off, and the first silicon carbide MOS tube MOS_A and the second silicon carbide MOS tube MOS_B are not turned on at the same time, which will not cause a short circuit fault between the DC bus DC+ and DC-.

[0091] After the PWM_A voltage drops from +5V to 0V, the first silicon carbide MOS tube MOS_A is turned off, and the second bypass semiconductor switch VT P2 Shut down.

[0092] When the upper tube of the silicon carbide half-bridge circuit is turned on, the protection waveform of the lower tube is turned off, as shown in Fig.10 As shown:

[0093] When the PWM_A voltage rises from 0V to +5V, it is used to drive the first semiconductor switch tube VT ON1 , the gate voltage of the first silicon carbide MOS tube MOS_A is V GSA The voltage rises from -3V to +18V, controlling the first silicon carbide MOS tube MOS_A to conduct. The second bypass semiconductor switch VT used to protect the second silicon carbide MOS tube MOS_B P2 Gate voltage VT P2 _GS rises from -3V to +18V, controlling the second bypass semiconductor switch VT P2 Comparison Fig.10 VT P2 _GS and V GSA It can be seen from the drive waveform used to control the conduction that the second bypass semiconductor switch VT used to protect the second silicon carbide MOS tube MOS_B P2 After the first is turned on, the first silicon carbide MOS tube MOS_A starts to be turned on, and the protection is turned on before the interference occurs.

[0094] The silicon carbide drive circuit of the present embodiment is suitable for drive control containing a silicon carbide half-bridge. In addition to the conventional on-off and on-off drive control of the upper and lower tubes of the silicon carbide half-bridge, the upper tube drive control signal and the lower tube drive control signal also introduce the upper tube drive control signal into the lower tube for lower tube drive protection, and the lower tube drive control signal is introduced into the upper tube for upper tube drive protection, thereby improving the anti-interference ability of the silicon carbide drive circuit, expanding the application range of high-frequency and high-power carbides, improving the reliability of the silicon carbide MOSFET circuit, and reducing the voltage value of the negative voltage turned off by the silicon carbide drive circuit, preventing the gate oxide layer from being damaged by excessive negative voltage breakdown, and avoiding long-term application of excessive negative voltage to accelerate the aging of the gate oxide layer and reduce the service life of the device. In the present embodiment, In the silicon carbide driving circuit of the example, the original upper tube driving control signal and the lower tube driving control signal in the driving circuit are used for protection control, and can be directly connected to the original interface in the external control system without the need for additional control signals. When upgrading, only the driving circuit itself needs to be upgraded and replaced. The upgrade cost is low and the method is simple. In addition, by introducing the upper tube driving control signal into the lower tube for lower tube driving protection, and introducing the lower tube driving control signal into the upper tube for upper tube driving protection, the protection circuit is actuated before the upper tube or lower tube of the silicon carbide half-bridge is turned on, and the anti-interference protection of the silicon carbide half-bridge lower tube drive is turned on in advance, avoiding the lag and delay of the traditional silicon carbide drive Miller clamp protection action, thereby improving the protection capability of high-frequency and high-power silicon carbide and improving the reliability of the equipment.

[0095] Example 2

[0096] A control method of a silicon carbide driving circuit according to Embodiment 2 of the present application includes:

[0097] The upper tube driving circuit 100 and the lower tube driving circuit 300 are powered by a first isolated DC power supply 500 and a second isolated DC power supply 600 which are independent of each other, wherein the first isolated DC power supply 500 and the second isolated DC power supply 600 are independent of each other, the first isolated DC power supply 500 is used for powering the upper tube driving circuit 100, and the second isolated DC power supply 600 is used for powering the lower tube driving circuit 300;

[0098] The two PWM drive control signals are respectively an upper tube drive control signal PWM_A and a lower tube drive control signal PWM_B. The upper tube drive control signal PWM_A is used to drive and control the first silicon carbide MOS tube MOS_A to turn on and off after being isolated and converted by the first isolation circuit M1, and the lower tube drive control signal PWM_B is used to drive and control the second silicon carbide MOS tube MOS_B to turn on and off after being isolated and converted by the second isolation circuit M2. After the upper tube drive control signal PWM_A is isolated and converted by the second isolation circuit M2, the lower tube shutdown drive circuit 303 of the second silicon carbide MOS tube MOS_B is introduced at the same time to control the second bypass semiconductor switch VT in the lower tube shutdown drive circuit 303. P2 , protecting the second silicon carbide MOS tube MOS_B from being mis-turned on due to the interference generated by the first silicon carbide MOS tube MOS_A from being disconnected to being turned on. After the lower tube drive control signal PWM_B is isolated and converted by the first isolation circuit M1, it is simultaneously introduced into the upper tube shutdown drive circuit 103 of the first silicon carbide MOS tube MOS_A to control the first bypass semiconductor switch VT in the upper tube shutdown drive circuit 103 P1 , protecting the first silicon carbide MOS tube MOS_A from being mis-turned on due to interference generated by the second silicon carbide MOS tube MOS_B switching from disconnection to conduction.

[0099] After the upper tube drive control signal PWM_A is converted by the isolation and level conversion circuit, the low level signal is used to drive and control the first silicon carbide MOS tube MOS_A to turn off, and the high level signal is used to drive and control the first silicon carbide MOS tube MOS_A to turn on. At the same time, after the upper tube drive control signal PWM_A is converted by another isolation and level conversion circuit, it drives the lower tube of the second silicon carbide MOS tube MOS_B to turn off the second bypass semiconductor switch VT of the driving circuit 303. P2, used to adjust the impedance of the lower tube shutdown drive circuit 303 during the shutdown period of the second silicon carbide MOS tube MOS_B. Select appropriate device parameters of the second bypass semiconductor switch 302, so that the second bypass semiconductor switch 302 using the same upper tube drive control signal PWM_A as the second silicon carbide MOS tube MOS_B is turned on before the first silicon carbide MOS tube MOS_A, and the anti-interference protection driven by the second silicon carbide MOS tube MOS_B is turned on in advance, reducing the impedance of the lower tube shutdown drive circuit 303 of the second silicon carbide MOS tube MOS_B. When the upper tube drive control signal PWM_A is a low-level signal, the second bypass semiconductor switch VT of the lower tube shutdown drive circuit 303 of the second silicon carbide MOS tube MOS_B P2 When the upper tube driving control signal PWM_A is high level, the lower tube of the second silicon carbide MOS tube MOS_B turns off the second bypass semiconductor switch VT of the driving circuit 303. P2 The impedance of the lower tube turn-off driving circuit 303 of the second silicon carbide MOS tube MOS_B becomes smaller, thereby stabilizing the gate turn-off voltage of the second silicon carbide MOS tube MOS_B, and preventing the turn-off voltage of the second silicon carbide MOS tube MOS_B from being affected by the conduction of the first silicon carbide MOS tube MOS_A during the turn-off period of the second silicon carbide MOS tube MOS_B, thereby causing the second silicon carbide MOS tube MOS_B to be mis-turned on.

[0100] After the lower tube drive control signal PWM_B is converted by the isolation and level conversion circuit, the low level signal is used to drive the second silicon carbide MOS tube MOS_B to turn off, and the high level signal is used to drive the second silicon carbide MOS tube MOS_B to turn on. At the same time, after the lower tube drive control signal PWM_B is converted by another isolation and level conversion circuit, it drives the first silicon carbide MOS tube MOS_A to turn off the first bypass semiconductor switch VT of the drive circuit. P1 , used to adjust the impedance of the upper tube shutdown drive circuit 103 of the first silicon carbide MOS tube MOS_A during the shutdown period of the first silicon carbide MOS tube MOS_A. Select the first bypass semiconductor switch VT P1 Appropriate device parameters enable the first bypass semiconductor switch VT to use the same lower tube drive control signal PWM_B as the second silicon carbide MOS tube MOS_B P1 Before the second silicon carbide MOS tube MOS_B is turned on, the anti-interference protection of the first silicon carbide MOS tube MOS_A is turned on in advance, reducing the impedance of the first silicon carbide MOS tube MOS_A turning off the drive circuit. When the lower tube drive control signal PWM_B is a low level signal, the first silicon carbide MOS tube MOS_A turns off the first bypass semiconductor switch VT of the drive circuit P1When the upper tube of the first silicon carbide MOS tube MOS_A turns off, the impedance of the driving circuit 103 remains unchanged. When the lower tube driving control signal PWM_B is a high level signal, the upper tube of the first silicon carbide MOS tube MOS_A turns off the first bypass semiconductor switch VT of the driving circuit 103. P1 The impedance of the upper tube turn-off drive circuit 103 of the first silicon carbide MOS tube MOS_A becomes smaller, thereby stabilizing the gate turn-off voltage of the first silicon carbide MOS tube MOS_A, and preventing the turn-off voltage of the first silicon carbide MOS tube MOS_A from being affected by the conduction of the second silicon carbide MOS tube MOS_B during the turn-off period of the first silicon carbide MOS tube MOS_A, thereby causing the first silicon carbide MOS tube MOS_A to be mis-turned on.

[0101] In some possible implementations, the maximum allowable peak current of the first bypass semiconductor switch 102 and the second bypass semiconductor switch 302 should satisfy the following formula:

[0102]

[0103] Among them, I p is the maximum allowable peak current of the first bypass semiconductor switch 102 or the second bypass semiconductor switch 302; C GD is the capacitance value between the gate and drain of the silicon carbide MOSFET module in the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube; dU is the voltage change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on; dt is the time change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on.

[0104] In some possible implementations, the on-state equivalent resistance of the first bypass semiconductor switch 102 and the second bypass semiconductor switch 302 should satisfy the following formula:

[0105]

[0106] Among them, R on is the conduction equivalent resistance of the first bypass semiconductor switch 102 or the second bypass semiconductor switch 302; C GD is the capacitance value between the gate and drain of the silicon carbide MOSFET module in the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube; dU is the voltage change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on; dt is the time change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on.

[0107] In some possible implementations, the time from turning off to turning on of the first bypass semiconductor switch 102 and the second bypass semiconductor switch 302 is less than one tenth of the time from turning off to turning on of the silicon carbide MOSFET modules in the silicon carbide half-bridge upper tube and the silicon carbide half-bridge lower tube.

[0108] In this embodiment, the upper tube drive control signal is introduced into the lower tube for lower tube drive protection, and the lower tube drive control signal is introduced into the upper tube for upper tube drive protection, so that the protection circuit is actuated before the upper tube or lower tube of the silicon carbide half-bridge is turned on, and the anti-interference protection of the silicon carbide half-bridge lower tube drive is turned on in advance, avoiding the lag and delay of the traditional silicon carbide drive Miller clamp protection action, thereby improving the protection capability of high-frequency and high-power silicon carbide and improving the reliability of the equipment.

[0109] It should be noted that other specific implementations of the control method of the silicon carbide driving circuit in this embodiment can refer to the specific implementations of the silicon carbide driving circuit mentioned above, and will not be described again here to avoid redundancy.

[0110] The above are only preferred specific implementations of the present application; however, the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solution and its improved ideas of the present application within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A silicon carbide driving circuit, characterized in that: include: An upper tube driving circuit, the upper tube driving circuit comprising an upper tube conduction driving circuit and an upper tube shutoff driving circuit having a first bypass semiconductor switch, the input ends of the upper tube conduction driving circuit and the upper tube shutoff driving circuit being used to connect the upper tube driving control signal isolated by the first isolation circuit, and the output ends of the upper tube conduction driving circuit and the upper tube shutoff driving circuit being connected to the gate of the first silicon carbide MOS module; A lower tube driving circuit, wherein the lower tube driving circuit comprises a lower tube conduction driving circuit and a lower tube shutoff driving circuit having a second bypass semiconductor switch, wherein input ends of the lower tube conduction driving circuit and the lower tube shutoff driving circuit are used to connect the lower tube driving control signal isolated by the second isolation circuit, and output ends of the lower tube conduction driving circuit and the lower tube shutoff driving circuit are connected to the gate of the second silicon carbide MOS module; Among them, the upper tube drive control signal is isolated by the second isolation circuit and input to the second bypass semiconductor switch for adjusting the impedance of the lower tube shutdown drive circuit during the shutdown period of the lower tube drive circuit; the lower tube drive control signal is isolated by the first isolation circuit and input to the first bypass semiconductor switch for adjusting the impedance of the upper tube drive circuit during the shutdown period of the upper tube drive circuit; the source of the first silicon carbide MOS module and the drain of the second silicon carbide MOS module are connected to each other to form an AC output pole, the drain of the first silicon carbide MOS module is connected to the positive pole of the DC bus of the main circuit, and the source of the second silicon carbide MOS module is connected to the negative pole of the DC bus of the main circuit; the upper tube drive circuit is powered by a first isolated DC power supply, and the lower tube drive circuit is powered by a second isolated DC power supply.

2. The silicon carbide driving circuit according to claim 1, characterized in that: The upper tube conduction drive circuit includes a first conduction control level converter, the upper tube drive control signal is isolated by the first isolation circuit and then input to the input end of the first conduction control level converter, the output end of the first conduction control level converter is electrically connected to the gate of the first semiconductor switch tube, the drain of the first semiconductor switch tube is electrically connected to the positive power supply output end of the first isolated DC power supply, the drain of the first semiconductor switch tube is also electrically connected to the first capacitor, the second capacitor and the third capacitor, the other ends of the first capacitor, the second capacitor and the third capacitor are all grounded, and the source of the first semiconductor switch tube is electrically connected to the gate of the first silicon carbide MOS module through the first on-resistance; The upper tube shutdown drive circuit includes a first shutdown control level converter, the upper tube drive control signal is isolated by the first isolation circuit and then input to the input end of the first shutdown control level converter, the output end of the first shutdown control level converter is electrically connected to the gate of the second semiconductor switch tube, the source of the second semiconductor switch tube is electrically connected to the negative power supply output end of the first isolated DC power supply, the source of the second semiconductor switch tube is also electrically connected to a fourth capacitor, a fifth capacitor and a sixth capacitor, the other ends of the fourth capacitor, the fifth capacitor and the sixth capacitor are all grounded, the drain of the second semiconductor switch tube is electrically connected to the gate of the first silicon carbide MOS module through a first shutdown resistor, the source of the second semiconductor switch tube is also electrically connected to the source of the first bypass semiconductor switch, the drain of the first bypass semiconductor switch is electrically connected to the gate of the first silicon carbide MOS module, the lower tube drive control signal is isolated by the first isolation circuit and then converted by the second conduction control level converter and then input to the gate of the first bypass semiconductor switch, and a first resistor is electrically connected between the gate and the source of the first silicon carbide MOS module.

3. The silicon carbide driving circuit according to claim 2, characterized in that: It also includes Schottky diode 1 and Schottky diode 2, the anode of Schottky diode 1 is electrically connected to the gate of the first silicon carbide MOS module, the cathode of Schottky diode 1 is electrically connected to the positive power output terminal of the first isolated DC power supply, the cathode of Schottky diode 2 is electrically connected to the gate of the first silicon carbide MOS module, and the anode of Schottky diode 2 is electrically connected to the negative power output terminal of the first isolated DC power supply.

4. The silicon carbide driving circuit according to claim 1, characterized in that: The lower tube conduction drive circuit includes a third conduction control level converter, the lower tube drive control signal is input to the input end of the third conduction control level converter after being isolated by the second isolation circuit, the output end of the third conduction control level converter is electrically connected to the gate of the third semiconductor switch tube, the drain of the third semiconductor switch tube is electrically connected to the positive power supply output end of the second isolated DC power supply, the drain of the third semiconductor switch tube is also electrically connected to the seventh capacitor, the eighth capacitor and the ninth capacitor, the other ends of the seventh capacitor, the eighth capacitor and the ninth capacitor are all grounded, and the source of the third semiconductor switch tube is electrically connected to the gate of the second silicon carbide MOS module through the second on-resistance; The lower tube shutdown driving circuit includes a second shutdown control level converter, the lower tube driving control signal is isolated by the second isolation circuit and then input to the input end of the second shutdown control level converter, the output end of the second shutdown control level converter is electrically connected to the gate of the fourth semiconductor switch tube, the source of the fourth semiconductor switch tube is electrically connected to the negative power supply output end of the second isolated DC power supply, the source of the fourth semiconductor switch tube is also electrically connected to the tenth capacitor, the eleventh capacitor and the twelfth capacitor, the other ends of the tenth capacitor, the eleventh capacitor and the twelfth capacitor are all grounded, the drain of the fourth semiconductor switch tube is electrically connected to the gate of the second silicon carbide MOS module through the second shutdown resistor, the source of the fourth semiconductor switch tube is also electrically connected to the source of the second bypass semiconductor switch, the drain of the second bypass semiconductor switch is electrically connected to the gate of the second silicon carbide MOS module, the upper tube driving control signal is isolated by the second isolation circuit and then converted by the fourth conduction control level converter and then input to the gate of the second bypass semiconductor switch, and a second resistor is electrically connected between the gate and the source of the second silicon carbide MOS module.

5. The silicon carbide driving circuit according to claim 4, characterized in that: It also includes Schottky diode three and Schottky diode four, the anode of Schottky diode three is electrically connected to the gate of the second silicon carbide MOS module, the cathode of Schottky diode three is electrically connected to the positive power output terminal of the second isolated DC power supply, the cathode of Schottky diode four is electrically connected to the gate of the second silicon carbide MOS module, and the anode of Schottky diode four is electrically connected to the negative power output terminal of the second isolated DC power supply.

6. The silicon carbide driving circuit according to any one of claims 1 to 5, characterized in that: A first transient overvoltage suppression diode and a first transient overvoltage suppression diode connected in reverse series are also electrically connected between the gate and the source of the first silicon carbide MOS module, and a third transient overvoltage suppression diode and a fourth transient overvoltage suppression diode connected in reverse series are also electrically connected between the gate and the source of the second silicon carbide MOS module.

7. A control method for a silicon carbide drive circuit, characterized in that: include: Using a first isolated DC power supply and a second isolated DC power supply independent of each other to supply power to the upper tube driving circuit and the lower tube driving circuit respectively; After the upper tube drive control signal is isolated by the first isolation circuit, the upper tube drive circuit is used to drive and control the on and off of the first silicon carbide MOS module; The upper tube drive control signal is isolated by the second isolation circuit and then input to the second bypass semiconductor switch for adjusting the impedance of the lower tube shutdown drive circuit during the shutdown period of the lower tube drive circuit; After the lower tube driving control signal is isolated by the second isolation circuit, the lower tube driving circuit is used to drive and control the on and off of the second silicon carbide MOS module; The lower tube driving control signal is isolated by the first isolation circuit and then input into the first bypass semiconductor switch for adjusting the impedance of the upper tube shut-down driving circuit during the shut-down period of the upper tube driving circuit.

8. The control method of the silicon carbide driving circuit according to claim 7, characterized in that: The maximum allowable peak current of the first bypass semiconductor switch and the second bypass semiconductor switch should satisfy the following formula: ; Among them, I p is the maximum allowable peak current of the first bypass semiconductor switch or the second bypass semiconductor switch; C GD is the capacitance value between the gate and drain of the silicon carbide MOSFET module in the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube; dU is the voltage change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on; dt is the time change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on.

9. The control method of the silicon carbide driving circuit according to claim 8, characterized in that: The conduction equivalent resistance of the first bypass semiconductor switch and the second bypass semiconductor switch should satisfy the following formula: ; Among them, R on is the conduction equivalent resistance of the first bypass semiconductor switch or the second bypass semiconductor switch; C GD is the capacitance value between the gate and drain of the silicon carbide MOSFET module in the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube; dU is the voltage change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on; dt is the time change value of the silicon carbide half-bridge upper tube or the silicon carbide half-bridge lower tube from off to on.

10. The control method of the silicon carbide driving circuit according to any one of claims 7 to 9, characterized in that: The time from turning off to turning on of the first bypass semiconductor switch is less than one tenth of the time from turning off to turning on of the silicon carbide MOSFET module in the silicon carbide half-bridge lower tube, and the time from turning off to turning on of the second bypass semiconductor switch is less than one tenth of the time from turning off to turning on of the silicon carbide MOSFET module in the silicon carbide half-bridge upper tube.

Images