High-speed SubLVDS (Substrate Low Voltage Differential Signaling) transmitting end circuit with adjustable output swing

Abstract

The invention relates to a high-speed SubLVDS (Substrate Low Voltage Differential Signaling) transmitting end circuit with adjustable output swing. The circuit comprises a control circuit, a single-ended to differential circuit, a common-mode feedback circuit, a biasing circuit and a driver circuit. Wherein the control circuit controls the starting and mode switching of the whole circuit, and the single-ended to differential circuit is used for converting an input single-ended signal into a differential signal and further inputting the differential signal into the driver circuit; a resistance voltage division circuit formed by the resistors R1, R2, R3 and R4 provides a reference voltage VCM for the common-mode feedback circuit; the common-mode feedback circuit is used for controlling the common-mode voltage of the driver circuit so as to ensure the stability of output; the bias circuit is used for providing mirror current and voltage for the driver circuit. The finally output common-mode voltage meets the requirements of the SubLVDS protocol, and the output swing of the differential signal is adjustable.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuit design, and in particular relates to a high-speed SubLVDS transmitting end circuit with adjustable output swing. Background Art

[0002] In today's information age, more and more data needs to be transmitted in real time, the transmission speed is getting faster and faster, and the amount of data transmission is getting larger and larger. Therefore, the performance requirements for the chip's input and output transmission interface are getting higher and higher. Since the traditional parallel transmission interface has a large number of interfaces, occupies a large chip area, and has a relatively complex layout and wiring, it is difficult to meet the design requirements of small-size chips. Therefore, a new I / O interface circuit with high speed, low power consumption and strong anti-interference ability is particularly important.

[0003] There are some I / O transmission interface circuits for high-speed digital signal transmission, such as CML (Current Mode Logic) interface circuit, LVPECL (Low Voltage Positive Emitter Coupled Logic) interface circuit, LVDS (Low Voltage Differential Signaling) interface circuit, etc. In practical applications, it is necessary to balance power consumption and speed. Among them, LVDS is an effective way to achieve a balance between high-speed and low-power data transmission. The emergence of this technology provides a possibility to solve the bottleneck problem of data transmission.

[0004] Sub Low Voltage Differential Signaling (SubLVDS) is a serial transmission interface with a very low output voltage swing. It is an effective way to achieve high-speed data transmission inside and outside the chip. It has the advantages of fast transmission speed, low power consumption, and low noise. Sub LVDS technology is a new technology developed from LVDS. Compared with LVDS, its operating voltage is further reduced, and it can work at a lower operating voltage, with relatively lower power consumption. Summary of the invention

[0005] The present invention aims to solve the above problems of the prior art. A high-speed SubLVDS transmitter circuit with adjustable output swing is proposed. The technical solution of the present invention is as follows:

[0006] A high-speed SubLVDS transmitter circuit with adjustable output swing, comprising: a control circuit (1), a single-ended to differential circuit (2), a bias circuit (3), a driver circuit (4), and a common-mode feedback circuit (5), wherein the input end of the control circuit (1) is connected to an external logic signal, the output end of the control circuit (1) is respectively connected to the switch control MOS tubes of the bias circuit (3) and the driver circuit (4), the input end of the single-ended to differential circuit (2) is connected to an external input data signal, and the output end is connected to the input end of the driver circuit (4); the control circuit (1) is used to control the shutdown and mode switching of the entire circuit, the single-ended to differential circuit (2) is used to convert the input single-ended data signal into a differential signal, the bias circuit (3) is used to provide bias current to the driver circuit (4) and the common-mode feedback circuit (5), and the common-mode feedback circuit (5) is used to control the common-mode voltage V O , so that it remains stable.

[0007] Furthermore, the control circuit (1) comprises: a PMOS tube M1, a PMOS tube M3, an NMOS tube M2, and an NMOS tube M4, wherein the source of the PMOS tube M1 and the source of the PMOS tube M3 are connected to an external power supply VDD, the gate of the PMOS tube M1 and the gate of the NMOS tube M2 are connected to an external enable signal EN, the drain of the PMOS tube M1 and the drain of the NMOS tube M2 are connected, the gate of the PMOS tube M3 and the gate of the NMOS tube M4 are connected to an external selection signal SEL, the drain of the PMOS tube M3 and the drain of the NMOS tube M4 are connected, and the sources of the NMOS tubes M2 and M4 are connected to an external ground line GND.

[0008] Furthermore, in the control circuit (1), the external enable signal EN is passed through an inverter composed of the PMOS tube M1 and the NMOS tube M2 to obtain a signal ENP, and the start-up of the entire circuit is further controlled by the signal ENP. Similarly, the external selection signal SEL is passed through an inverter composed of the PMOS tube M3 and the NMOS tube M4 to obtain a signal SELP, and the signal SELP further controls the switching of the differential output voltage swing.

[0009] Furthermore, the single-ended to differential circuit (2) comprises: NMOS tube M6, PMOS tube M5, PMOS tube M7, NMOS tube M8, PMOS tube M9, NMOS tube M10, PMOS tube M11, NMOS tube M12, PMOS tube M13, NMOS tube M14, PMOS tube M15, NMOS tube M16, PMOS tube M17, NMOS tube M18, PMOS tube M19, NMOS tube M20, PMOS tube M21, and NMOS tube M22. The sources of the PMOS tube M7, the PMOS tube M9, the PMOS tube M11, the PMOS tube M13, the PMOS tube M15, the PMOS tube M17, the PMOS tube M19 and the PMOS tube M21 are respectively connected to the external power supply VDD, the sources of the NMOS tube M8, the NMOS tube M10, the NMOS tube M12, the NMOS tube M14, the NMOS tube M16, the NMOS tube M18, the NMOS tube M20 and the NMOS tube M22 are respectively connected to the external ground line GND, and the gate of the PMOS tube M13 is connected to the external ground line GND. The gate of the PMOS tube M13 is connected to the drain of the NMOS tube M14, the gate of the PMOS tube M15, the gate of the NMOS tube M16, the source of the PMOS tube M5 and the drain of the NMOS tube M6 respectively; the drain of the PMOS tube M15 is connected to the drain of the NMOS tube M16, the gate of the PMOS tube M17 and the gate of the NMOS tube M18 respectively; the drain of the PMOS tube M17 is connected to the drain of the NMOS tube M18, the gate of the PMOS tube M19 and the gate of the NMOS tube M20 respectively. The gate of the PMOS tube M19 is connected to the gate of the NMOS tube M20, the drain of the PMOS tube M19 is connected to the drain of the NMOS tube M20, the gate of the PMOS tube M21 and the gate of the NMOS tube M22, the drain of the PMOS tube M21 is connected to the drain of the NMOS tube M22, the gate of the PMOS tube M40 and the gate of the NMOS tube M42, the gate of the PMOS tube M5 is connected to the external signal A, the gate of the NMOS tube M6 is connected to the external signal B, the drain of the PMOS tube M5 ... The source of the transistor M6 is connected to the gate of the PMOS transistor M7 and the gate of the NMOS transistor M8. The drain of the PMOS transistor M7 is respectively connected to the drain of the NMOS transistor M8, the gate of the PMOS transistor M9 and the gate of the NMOS transistor M10. The drain of the PMOS transistor M9 is respectively connected to the drain of the NMOS transistor M10, the gate of the PMOS transistor M11 and the gate of the NMOS transistor M12. The drain of the PMOS transistor M11 is respectively connected to the drain of the NMOS transistor M12, the gate of the PMOS transistor M39 and the gate of the NMOS transistor M41.

[0010] Furthermore, in the single-ended to differential circuit (2), the PMOS tube M5 and the NMOS tube M6 form a transmission gate structure, and the remaining adjacent PMOS tubes and NMOS tubes form an inverter structure, wherein the transmission delay of the transmission gate structure is consistent with the transmission delay of the inverter formed by the PMOS tube M15 and the NMOS tube M16, and the width-to-length ratios of the inverters of the latter stages are multiplied in proportion, so as to enhance the driving capability of the signal so that it can drive the driver circuit (4), and the width-to-length ratios of the PMOS tube M7, the PMOS tube M9, the PMOS tube M11, the PMOS tube M17, the PMOS tube M19, and the PMOS tube M21 should be the same, but the number is different, and the number is multiplied in proportion. Similarly, the width-to-length ratios of the NMOS tube M8, the NMOS tube M10, the NMOS tube M12, the NMOS tube M18, the NMOS tube M20, and the NMOS tube M22 should also be the same, but the number is different, and the number is multiplied in proportion.

[0011] Furthermore, the bias circuit (3) comprises: an external current source Ibas, a PMOS tube M23, an NMOS tube M24, an NMOS tube M26, an NMOS tube M25, an NMOS tube M27, a resistor R1, a PMOS tube M28, a PMOS tube M30, a PMOS tube M29, and a PMOS tube M31. Among them, one end of the external current source Ibas is respectively connected to the source of the PMOS tube M28, the source of the PMOS tube M29 and the external power supply VDD, the other end of the external current source Ibas is connected to the source of the PMOS tube M23, the gate of the PMOS tube M23 is respectively connected to the drain of the PMOS tube M1, the drain of the NMOS tube M2, the gate of the NMOS tube M25 and the gate of the PMOS tube M31, the drain of the PMOS tube M23 is respectively connected to the drain of the NMOS tube M24, the gate of the NMOS tube M24, the gate of the NMOS tube M26, the gate of the NMOS tube M27 and the drain of the NMOS tube M25, the source of the NMOS tube M24 is respectively connected to the source of the NMOS tube M25, the gate of the NMOS tube M26, the gate of the NMOS tube M27 and the drain of the NMOS tube M25. The source of the OS transistor M26, the source of the NMOS transistor M27 and the external ground line GND are connected, the gate of the PMOS transistor M28 is respectively connected to the drain of the PMOS transistor M28, the drain of the NMOS transistor M28 and the gate of the PMOS transistor M44, the gate of the PMOS transistor M29 is respectively connected to the drain of the PMOS transistor M31, the gate of the PMOS transistor M33, the drain of the PMOS transistor M35, the drain of the PMOS transistor M30 and one end of the resistor R1, the drain of the PMOS transistor M29 is connected to the source of the PMOS transistor M30, and the gate of the PMOS transistor M30 is respectively connected to the other end of the resistor R1, the drain of the NMOS transistor M27, the gate of the PMOS transistor M34 and the drain of the PMOS transistor M36.

[0012] Furthermore, in the bias circuit (3), the external current source Ibas can be provided by a bandgap reference, the width-to-length ratios of the NMOS tubes M24, M26 and M27 should be the same, but the numbers are different, the resistor R1 is mainly used to control the voltage of the gate of the PMOS tube M30, the width-to-length ratios of the PMOS tubes M28 and M44 are the same, but the numbers are different; the width-to-length ratios of the PMOS tubes M29, M33 and M37 are the same, but the numbers are different, and they are in a proportional relationship; the width-to-length ratios of the PMOS tubes M30, M34 and M38 are the same, but the numbers are different, and they are in a proportional relationship, and the proportional relationship is the same as that of the PMOS tubes M29, M33 and M37.

[0013] Furthermore, the driver circuit (4) includes: PMOS tube M32, PMOS tube M33, PMOS tube M34, PMOS tube M35, PMOS tube M36, PMOS tube M37, PMOS tube M38, PMOS tube M39, PMOS tube M40, NMOS tube M41, NMOS tube M42, NMOS tube M43, resistor R2, resistor R3, resistor RL. Among them, the source of PMOS tube M32 is connected to the source of PMOS tube M33, the source of PMOS tube M37 and the external power supply VDD, the drain of PMOS tube M33 is connected to the source of PMOS tube M34, the gate of PMOS tube M35 is connected to the gate of PMOS tube M36, the drain of PMOS tube M3 and the drain of NMOS tube M4, the gate of PMOS tube M37 is connected to the source of PMOS tube M35, the gate of PMOS tube M38 is connected to the gate of PMOS tube M39, and the gate of PMOS tube M40 is connected to the gate of PMOS tube M41. The source of the PMOS tube M36 is connected, the drain of the PMOS tube M37 is connected to the source of the PMOS tube M38, the drain of the PMOS tube M34 is respectively connected to the drain of the PMOS tube M38, the source of the PMOS tube M39 and the source of the PMOS tube M40, the drain of the PMOS tube M39 is respectively connected to the drain of the NMOS tube M41, one end of the resistor R2 and one end of the resistor RL, the drain of the PMOS tube M40 is respectively connected to the drain of the NMOS tube M42. One end of the resistor R3 is connected to the other end of the resistor RL, the other end of the resistor R2 is respectively connected to the other end of the resistor R and the gate of the PMOS tube M45, the source of the NMOS tube M41 is respectively connected to the source of the NMOS tube M42 and the drain of the NMOS tube M43, the gate of the NMOS tube M43 is respectively connected to the drain of the NMOS tube M48 and the drain of the PMOS tube M46, and the source of the NMOS tube M43 is connected to the external ground line GND.

[0014] Furthermore, the PMOS tube M33 and the PMOS tube M34, the PMOS tube M37 and the PMOS tube M38 in the driver circuit (4) form two current sources, which mirror the current of the bias circuit (3) to provide a driving current for the driver circuit (4); the PMOS tube M35 and the PMOS tube M36 serve as switch control tubes for swing switching to control the shutdown of one of the current sources; the PMOS tube M39, the PMOS tube M40, the NMOS tube M41 and the NMOS tube M42 serve as four switch MOS tubes, and either the PMOS tube M39 and the PMOS tube N The MOS tube M42 is turned on, or the PMOS tube M40 and the NMOS tube M41 are turned on; the resistors R2 and R3 are used to detect the common mode voltage of the circuit, and in order to prevent the driver circuit (4) from being affected, their resistance values ​​should be much larger than the resistor RL; the resistor RL is a matching resistor, and its value is 100Ω; through the switching of signals, the PMOS tube M39 and the PMOS tube NMOS tube M42, the PMOS tube M40 and the NMOS tube M41 are alternately turned on, thereby changing the direction of the current flowing through the resistor RL in the driver circuit (4), and further changing the positive and negative of the output differential voltage.

[0015] Furthermore, the common-mode feedback circuit (5) comprises: a PMOS tube M44, a PMOS tube M45, a PMOS tube M46, an NMOS tube M47, an NMOS tube M48, a resistor R4, a resistor R5, a resistor R6, and a resistor R7. Wherein, the source of the PMOS tube M44 and one end of the resistor R4 are connected to the external power supply VDD, the gate of the PMOS tube M44 is connected to the gate of the PMOS tube M28, the drain of the PMOS tube M44 is respectively connected to the source of the PMOS tube M45 and the source of the PMOS tube M46, the drain of the PMOS tube M45 is respectively connected to the gate of the NMOS tube M47, the drain of the NMOS tube M47 and the gate of the NMOS tube M48, the drain of the PMOS tube M46 is respectively connected to the drain of the NMOS tube M48 and the gate of the NMOS tube M43, the source of the NMOS tube M47 is respectively connected to the source of the NMOS tube M48, one end of the resistor R7 and the external ground line GND, the other end of the resistor R7 is connected to one end of the resistor R6, the other end of the resistor R6 is respectively connected to one end of the resistor R5 and the gate of the PMOS tube M46, and the other end of the resistor R5 is connected to the other end of the resistor R4;

[0016] In the common-mode feedback circuit (5), resistors R4, R5, R6 and R7 form a resistor voltage-dividing branch. By controlling the ratio of the resistors, the reference voltage VCM is approximately equal to about 1V. The common-mode feedback circuit (5) can be regarded as a five-tube operational amplifier with the PMOS tube M44 as a current source. By OThe common-mode voltage is compared with the reference voltage VCM, and the gate voltage of the NMOS tube M43 is adjusted through the output, so as to control the common-mode voltage to remain stable.

[0017] The advantages and beneficial effects of the present invention are as follows:

[0018] 1. In order to obtain an output signal with a small output differential swing voltage fluctuation range, the bias circuit and driver circuit proposed in the present invention adopt a Cascode current mirror structure, so that the current mirror flowing through the circuit is more accurate and stable, thereby making the output more stable; the proposed structure has the characteristics of adjustable output swing, and can output differential signals that meet the LVDS output voltage size, and can output differential signals that meet the SubLVDS size, and can accurately output at a high speed of 2Gbps.

[0019] 2. The proposed high-speed SubLVDS transmitter circuit with adjustable output swing has the advantages of low cost, small area and good integration. The proposed high-speed SubLVDS transmitter circuit with adjustable output swing can be realized by only MOS tubes and a few resistors, avoiding the use of capacitors to increase the chip area, and has the advantages of cost saving, low power consumption and high integration.

[0020] 3. The proposed high-speed and output swing adjustable SubLVDS transmitter circuit directly controls the shutdown of the driver circuit MOS tube according to the change of the input signal level, and does not have a logical relationship with other signals, and has high reliability. In the entire transmitter circuit, the circuit stabilizes the common mode voltage through the common mode feedback circuit, and the final output differential voltage depends on the difference between OUTN-OUTP, which is very little affected by the process angle and temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of a SubLVDS transmitter circuit diagram with high speed and adjustable output swing proposed in a preferred embodiment of the present invention.

[0022] Figure 2 Output simulation results when the output swing is 150mV at room temperature in the TT process corner.

[0023] Figure 3 Output simulation results when the output swing is 150mV at low temperature of SS process corner.

[0024] Figure 4 Output simulation results when the output swing is 150mV at high temperature of the FF process corner.

[0025] Figure 5 Output simulation results when the output swing is 350mV at room temperature in the TT process corner.

[0026] Figure 6 Output simulation results when the output swing is 350mV at low temperature of SS process corner.

[0027] Figure 7 Output simulation results when the output swing is 350mV at high temperature of the FF process corner. DETAILED DESCRIPTION

[0028] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0029] The technical solution of the present invention to solve the above technical problems is:

[0030] like Figure 1 As shown: A technology of a high-speed SubLVDS transmitter circuit with adjustable output swing, including a control circuit 1, a single-ended to differential circuit 2, a bias circuit 3, a driver circuit 4, and a common-mode feedback circuit 5, wherein the control circuit 1 is used to control the shutdown and mode switching of the entire circuit, the single-ended to differential circuit 2 is used to convert the input single-ended data signal into a differential signal, the bias circuit 3 is used to provide a bias current to the driver circuit 4 and the common-mode feedback circuit 5, and the common-mode feedback circuit 5 is used to control the common-mode voltage V of the driver circuit 4 O , so that it remains in a stable range.

[0031] As a high-speed SubLVDS transmitter solution with adjustable output swing, Figure 1 As shown, the control circuit 1 includes: a PMOS tube M1, a PMOS tube M3, an NMOS tube M2, and an NMOS tube M4. The source of the PMOS tube M1 and the source of the PMOS tube M3 are connected to an external power supply VDD, the gate of the PMOS tube M1 and the gate of the NMOS tube M2 are connected to an external enable signal EN, the drain of the PMOS tube M1 and the drain of the NMOS tube M2 are connected, the gate of the PMOS tube M3 and the gate of the NMOS tube M4 are connected to an external selection signal SEL, the drain of the PMOS tube M3 and the drain of the NMOS tube M4 are connected, and the sources of the NMOS tubes M2 and M4 are connected to an external ground line GND.

[0032] The single-ended to differential circuit 2 includes: NMOS tube M6, PMOS tube M5, PMOS tube M7, NMOS tube M8, PMOS tube M9, NMOS tube M10, PMOS tube M11, NMOS tube M12, PMOS tube M13, NMOS tube M14, PMOS tube M15, NMOS tube M16, PMOS tube M17, NMOS tube M18, PMOS tube M19, NMOS tube M20, PMOS tube M21, and NMOS tube M22. The sources of the PMOS tube M7, the PMOS tube M9, the PMOS tube M11, the PMOS tube M13, the PMOS tube M15, the PMOS tube M17, the PMOS tube M19 and the PMOS tube M21 are respectively connected to the external power supply VDD, the sources of the NMOS tube M8, the NMOS tube M10, the NMOS tube M12, the NMOS tube M14, the NMOS tube M16, the NMOS tube M18, the NMOS tube M20 and the NMOS tube M22 are respectively connected to the external ground line GND, and the gate of the PMOS tube M13 is connected to the external ground line GND. The gate of the PMOS tube M13 is connected to the drain of the NMOS tube M14, the gate of the PMOS tube M15, the gate of the NMOS tube M16, the source of the PMOS tube M5 and the drain of the NMOS tube M6 respectively; the drain of the PMOS tube M15 is connected to the drain of the NMOS tube M16, the gate of the PMOS tube M17 and the gate of the NMOS tube M18 respectively; the drain of the PMOS tube M17 is connected to the drain of the NMOS tube M18, the gate of the PMOS tube M19 and the gate of the NMOS tube M20 respectively. The gate of the PMOS tube M19 is connected to the gate of the NMOS tube M20, the drain of the PMOS tube M19 is connected to the drain of the NMOS tube M20, the gate of the PMOS tube M21 and the gate of the NMOS tube M22, the drain of the PMOS tube M21 is connected to the drain of the NMOS tube M22, the gate of the PMOS tube M40 and the gate of the NMOS tube M42, the gate of the PMOS tube M5 is connected to the external signal A, the gate of the NMOS tube M6 is connected to the external signal B, the drain of the PMOS tube M5 ... The source of the transistor M6 is connected to the gate of the PMOS transistor M7 and the gate of the NMOS transistor M8. The drain of the PMOS transistor M7 is respectively connected to the drain of the NMOS transistor M8, the gate of the PMOS transistor M9 and the gate of the NMOS transistor M10. The drain of the PMOS transistor M9 is respectively connected to the drain of the NMOS transistor M10, the gate of the PMOS transistor M11 and the gate of the NMOS transistor M12. The drain of the PMOS transistor M11 is respectively connected to the drain of the NMOS transistor M12, the gate of the PMOS transistor M39 and the gate of the NMOS transistor M41.

[0033] The bias circuit 3 includes: an external current source Ibas, a PMOS tube M23, an NMOS tube M24, an NMOS tube M26, an NMOS tube M25, an NMOS tube M27, a resistor R1, a PMOS tube M28, a PMOS tube M30, a PMOS tube M29, and a PMOS tube M31. Among them, one end of the external current source Ibas is respectively connected to the source of the PMOS tube M28, the source of the PMOS tube M29 and the external power supply VDD, the other end of the external current source Ibas is connected to the source of the PMOS tube M23, the gate of the PMOS tube M23 is respectively connected to the drain of the PMOS tube M1, the drain of the NMOS tube M2, the gate of the NMOS tube M25 and the gate of the PMOS tube M31, the drain of the PMOS tube M23 is respectively connected to the drain of the NMOS tube M24, the gate of the NMOS tube M24, the gate of the NMOS tube M26, the gate of the NMOS tube M27 and the drain of the NMOS tube M25, the source of the NMOS tube M24 is respectively connected to the source of the NMOS tube M25, the gate of the NMOS tube M26, the gate of the NMOS tube M27 and the drain of the NMOS tube M25. The source of the OS transistor M26, the source of the NMOS transistor M27 and the external ground line GND are connected, the gate of the PMOS transistor M28 is respectively connected to the drain of the PMOS transistor M28, the drain of the NMOS transistor M28 and the gate of the PMOS transistor M44, the gate of the PMOS transistor M29 is respectively connected to the drain of the PMOS transistor M31, the gate of the PMOS transistor M33, the drain of the PMOS transistor M35, the drain of the PMOS transistor M30 and one end of the resistor R1, the drain of the PMOS transistor M29 is connected to the source of the PMOS transistor M30, and the gate of the PMOS transistor M30 is respectively connected to the other end of the resistor R1, the drain of the NMOS transistor M27, the gate of the PMOS transistor M34 and the drain of the PMOS transistor M36.

[0034] The driver circuit 4 includes: PMOS tube M32, PMOS tube M33, PMOS tube M34, PMOS tube M35, PMOS tube M36, PMOS tube M37, PMOS tube M38, PMOS tube M39, PMOS tube M40, NMOS tube M41, NMOS tube M42, NMOS tube M43, resistor R2, resistor R3, and resistor RL. Among them, the source of PMOS tube M32 is connected to the source of PMOS tube M33, the source of PMOS tube M37 and the external power supply VDD, the drain of PMOS tube M33 is connected to the source of PMOS tube M34, the gate of PMOS tube M35 is connected to the gate of PMOS tube M36, the drain of PMOS tube M3 and the drain of NMOS tube M4, the gate of PMOS tube M37 is connected to the source of PMOS tube M35, the gate of PMOS tube M38 is connected to the gate of PMOS tube M39, and the gate of PMOS tube M40 is connected to the gate of PMOS tube M41. The source of the PMOS tube M36 is connected, the drain of the PMOS tube M37 is connected to the source of the PMOS tube M38, the drain of the PMOS tube M34 is respectively connected to the drain of the PMOS tube M38, the source of the PMOS tube M39 and the source of the PMOS tube M40, the drain of the PMOS tube M39 is respectively connected to the drain of the NMOS tube M41, one end of the resistor R2 and one end of the resistor RL, the drain of the PMOS tube M40 is respectively connected to the drain of the NMOS tube M42. One end of the resistor R3 is connected to the other end of the resistor RL, the other end of the resistor R2 is respectively connected to the other end of the resistor R and the gate of the PMOS tube M45, the source of the NMOS tube M41 is respectively connected to the source of the NMOS tube M42 and the drain of the NMOS tube M43, the gate of the NMOS tube M43 is respectively connected to the drain of the NMOS tube M48 and the drain of the PMOS tube M46, and the source of the NMOS tube M43 is connected to the external ground line GND.

[0035] The common-mode feedback circuit 5 includes: a PMOS tube M44, a PMOS tube M45, a PMOS tube M46, an NMOS tube M47, an NMOS tube M48, a resistor R4, a resistor R5, a resistor R6, and a resistor R7. Among them, the source of the PMOS tube M44 and one end of the resistor R4 are connected to the external power supply VDD, the gate of the PMOS tube M44 is connected to the gate of the PMOS tube M28, the drain of the PMOS tube M44 is respectively connected to the source of the PMOS tube M45 and the source of the PMOS tube M46, the drain of the PMOS tube M45 is connected to the gate of the NMOS tube M47, the drain of the NMOS tube M47 and the gate of the NMOS tube M48, the drain of the PMOS tube M46 is respectively connected to the drain of the NMOS tube M48 and the gate of the NMOS tube M43, the source of the NMOS tube M47 is respectively connected to the source of the NMOS tube M48, one end of the resistor R7 and the external ground line GND, the other end of the resistor R7 is connected to one end of the resistor R6, the other end of the resistor R6 is respectively connected to one end of the resistor R5 and the gate of the PMOS tube M46, and the other end of the resistor R5 is connected to the other end of the resistor R4.

[0036] Among them, EN in the control circuit 1 is an enable signal input from the outside. When EN is "1", ENP is "0". At this time, the PMOS tube M23 is turned off, the NMOS tube M25 is turned on, and the PMOS tubes M31 and M32 are turned on, so that the gate voltages of the NMOS tubes M24 and M26 are pulled down, and the gate voltages of the PMOS tubes M29, M33, M30 and M34 are pulled up. No current is generated in the entire circuit, thereby turning off the circuit. Otherwise, the circuit is turned on and works normally. SEL is a mode switching signal. When SEL is "1", SELP is "0". At this time, the PMOS tubes M35 and M36 are turned on. At this time, the circuit outputs a differential swing of the LVDS size. Otherwise, it outputs a SubLVDS differential swing. In the single-ended to differential circuit 2, signals A and B are input signals of the transmission gate. When the circuit works normally, signal A is low, signal B is high, and the transmission gate is turned on. At the same time, the transmission delay of the transmission gate should be as much as possible to ensure that it is the same as the transmission delay of the inverter composed of the PMOS tube M15 and the NMOS tube M16, and finally output a pair of inverted differential signals IN and IP. In the bias circuit 3, Ibas is an external current source, which can be provided by an external bandgap reference. After the current comes in, it is mirrored by the current mirror and then provided to the driver circuit 4 and the common-mode feedback circuit 5.

[0037] In the driver circuit 4, IN and IP are a pair of inverted signals, IN and IP are input terminal signals, OUTN and OUTP are output terminals of the driver circuit, and the driving current flowing through the circuit is Im. When the input signal IN is high level "1" and IP is low level "0", the PMOS tube M40 and the NMOS tube M41 are turned on, and the current direction is M40→OUTN→RL→OUTP→M41. The voltage OUTN-OUTP across the matching resistor RL is positive, and the SubLVDS signal is VOD=OUTN-OUTP, with a magnitude of I m ×RL. Therefore, the SubLVDS signal is positive at this time. When the input signal IN is high level "0" and IP is low level "1", the PMOS tube M39 and the NMOS tube M42 are turned on, and the current direction is M39→OUTP→RL→OUTN→M42. The voltage OUTN-OUTP across the matching resistor RL is negative, and the SubLVDS signal is VOD=OUTN-OUTP, with a magnitude of -I m ×RL. Therefore, the SubLVDS signal is negative at this time.

[0038] When the driver circuit 4 is working, the current source branch formed by the PMOS tube M33 and the PMOS tube M34 will always be open, and the current source branch formed by the PMOS tube M37 and the PMOS tube M38 is controlled by the switch PMOS tube M35 and the PMOS tube M36, thereby changing the current flowing through the driver circuit and further changing the swing of the output differential voltage. The circuit has two swings that can be switched. When SEL inputs logic "0", SELP is logic "1", PMOS tubes M35 and PMOS tubes M36 are turned off, and the current source composed of PMOS tubes M33 and PMOS tubes M34 participates in the work. The driver circuit finally outputs swing one, that is, the output differential voltage signal that meets the SubLVDS protocol, typically with a size of ±150mV; if SEL is logic "1", SELP is logic "0", PMOS tubes M35 and PMOS tubes M36 are turned on, and the current source composed of PMOS tubes M37 and PMOS tubes M38 and the current source composed of PMOS tubes M33 and PMOS tubes M34 provide current for the driver together. The driver circuit finally outputs swing two, which meets the output differential voltage signal of the LVDS protocol, and typically with a size of ±350mV.

[0039] In the common-mode feedback circuit 5, if the common-mode detection voltage result is V O If the voltage VCM of the five-tube op amp decreases and is less than the reference voltage VCM, the output voltage of the five-tube op amp will increase, and the gate voltage of the NMOS tube M43 will increase. The gate-source voltage VGS of the NMOS tube M43 will increase, causing the current to increase. Therefore, the total current flowing through the circuit will increase, V OThat is, the average values ​​of the output voltages OUTN and OUTP increase, forming a complete negative feedback network to achieve the function of adjusting the common-mode voltage; the resistor voltage divider structure composed of resistors R4, R5, R6, and R7 is used to obtain the reference voltage VCM, which can be obtained. By adjusting the proportional relationship between them, the reference voltage VCM can be obtained. In the present invention, VCM is 0.95V.

[0040] Furthermore, in typical applications, the input signal of the circuit is a single-ended digital signal, while the input of the driver requires a dual-ended input. The single-ended input signal is converted into a pair of inverted differential signals through a single-to-dual circuit. In order to increase the output driving capability, several stages of inverters with gradually multiplied width-to-length ratios are added after the output differential signal, and finally two pairs of inverted differential signals IN and IP are obtained.

[0041] Furthermore, in the driver circuit, IN and IP are a pair of inverted signals, IN and IP are input signals, OUTN and OUTP are outputs of the driver circuit, and the driving current flowing through the circuit is Im. When the input signal IN is high level "1" and IP is low level "0", the PMOS tube M40 and the NMOS tube M41 are turned on, and the current direction is M40→OUTN→RL→OUTP→M41. The voltage OUTN-OUTP across the matching resistor RL is positive, and the SubLVDS signal is VOD=OUTN-OUTP, with a magnitude of I m ×RL. Therefore, the SubLVDS signal is positive at this time. When the input signal IN is high level "0" and IP is low level "1", the PMOS tube M39 and the NMOS tube M42 are turned on, and the current direction is M39→OUTP→RL→OUTN→M42. The voltage OUTN-OUTP across the matching resistor RL is negative, and the SubLVDS signal is VOD=OUTN-OUTP, with a magnitude of -I m ×RL. Therefore, the SubLVDS signal is negative at this time.

[0042] Furthermore, when the driver circuit is working, the current source branch formed by the PMOS tube M33 and the PMOS tube M34 will always be open, and the current source branch formed by the PMOS tube M37 and the PMOS tube M38 is controlled by the switch PMOS tube M35 and the PMOS tube M36, thereby changing the current flowing through the driver circuit and further changing the swing of the output differential voltage. The circuit has two swings that can be switched. When EN inputs a logic low level and SEL inputs a logic low level, ENP and SELP are logic high levels, PMOS tubes M31 and M32 are turned off, PMOS tube M23 is turned on, NMOS tube M25 is turned off, and PMOS tubes M35 and M36 are turned off to work. At this time, the current source composed of PMOS tubes M33 and PMOS tubes M34 participates in the work, and the driver circuit finally outputs swing one, and the output is ±150mV at this time; if SEL is a logic high level, SELP is a logic low level, PMOS tubes M35 and PMOS tubes M36 are turned on, and the current source composed of PMOS tubes M37 and PMOS tubes M38 and the current source composed of PMOS tubes M33 and PMOS tubes M34 together provide current for the driver, and the driver circuit finally outputs swing two, and the output is ±350mV at this time.

[0043] Furthermore, in order to read the common-mode level value between the output levels OUTN and OUTP, the common-mode feedback circuit connects two large resistors R2 and R3 in series between the output voltages OUTN and OUTP, and connects them in parallel with the matching load impedance RL. The values ​​of R2 and R3 are much larger than RL, so that almost all the current of the driver flows through RL without affecting the output signal. The common-mode voltage is When designing, R2=R3, so it can be simplified to That is, the common-mode feedback voltage V O is approximately the average of the two output levels; the output end of the five-tube op amp is connected to the gate of the tail current source NMOS tube M43 of the driver circuit to control the common-mode level of the circuit. If the result of the common-mode detection voltage is V O If the voltage VCM of the five-tube op amp increases and exceeds the reference voltage VCM, the output voltage of the five-tube op amp decreases, and the gate voltage of the NMOS tube M43 decreases. The gate-source voltage VGS of the NMOS tube M43 decreases, resulting in a decrease in the current. Therefore, the total current flowing through the circuit will decrease, V O That is, the average value of the output voltages OUTN and OUTP decreases, forming a complete negative feedback network to achieve the function of adjusting the common-mode voltage; the resistor voltage divider structure composed of resistors R4, R5, R6, and R7 is used to obtain the reference voltage VCM, which can be obtained. By adjusting the proportional relationship between them, the reference voltage VCM can be obtained, and this reference voltage can also be generated by an external bandgap reference.

[0044] Simulation Results

[0045] During simulation, the transmission rate of the input signal is 2Gbps, that is, the signal 1bit width is 0.5ns. The SubLVDS protocol requires the output differential voltage range to be between 100mV-200mV, the standard value is 150mV, and the common mode voltage to be between 0.8V-1V, the standard value is 0.9V; the LVDS protocol requires the output differential voltage range to be between 250mV-450mV, the standard value is 350mV. OUTN and OUTP in the figure represent the output signal level, V O It indicates the common mode voltage, and VOD indicates the differential output voltage signal.

[0046] The simulation results of 150mV output at room temperature (typical case) of TT process corner are as follows Figure 2 As shown in the figure, it can be seen that the output differential voltage is about ±151mV and the common mode voltage is about 0.955V, which meets the protocol requirements. The simulation results are consistent with the above analysis. Figure 3 As shown in the figure, it can be seen that the output differential voltage is about ±140mV and the common mode voltage is about 0.955V, which meets the protocol requirements. The simulation results of 150mV output at high temperature of FF process are shown in the figure. Figure 4 As shown in the figure, it can be seen that the output differential voltage is about ±163mV and the common mode voltage is about 0.955V, which meets the protocol requirements. The simulation results of 350mV output at room temperature of TT process corner are shown in the figure. Figure 5 As shown in the figure, it can be seen that the output differential voltage is about ±352mV and the common mode voltage is about 0.955V. The simulation result of 350mV output at low temperature of SS process is as follows: Figure 6 As shown in the figure, it can be seen that the output differential voltage is about ±328mV and the common mode voltage is about 0.955V. The simulation result of 350mV output at high temperature of FF process is as follows: Figure 6 As shown, it can be seen that the output differential voltage is about ±373mV and the common mode voltage is about 0.955V, which meets the protocol requirements. According to the above simulation results, it can be seen that even in extreme cases, the proposed high-speed and output swing adjustable SubLVDS transmitter circuit still meets the protocol requirements.

[0047] It can be seen from the above results that the high-speed and output swing adjustable SubLVDS transmitter circuit of the present invention can output common-mode voltage and output differential voltage signals that meet the requirements of the SubLVDS protocol, and at the same time, can output differential output voltage signals that meet the LVDS requirements under the same common-mode voltage.

[0048] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions.

[0049] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0050] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high-speed SubLVDS transmitter circuit with adjustable output swing, characterized in that: include: A control circuit (1), a single-ended to differential circuit (2), a bias circuit (3), a driver circuit (4), and a common-mode feedback circuit (5), wherein the input end of the control circuit (1) is connected to an external logic signal, the output end of the control circuit (1) is respectively connected to the switch control MOS tubes of the bias circuit (3) and the driver circuit (4), the input end of the single-ended to differential circuit (2) is connected to an external input data signal, and the output end is connected to the input end of the driver circuit (4); the control circuit (1) is used to control the shutdown and mode switching of the entire circuit, the single-ended to differential circuit (2) is used to convert the input single-ended data signal into a differential signal, the bias circuit (3) is used to provide bias current to the driver circuit (4) and the common-mode feedback circuit (5), and the common-mode feedback circuit (5) is used to control the common-mode voltage V of the driver circuit (4). O , so that it remains stable.

2. A high-speed SubLVDS transmitter circuit with adjustable output swing according to claim 1, characterized in that: The control circuit (1) comprises: a PMOS tube M1, a PMOS tube M3, an NMOS tube M2, and an NMOS tube M4, wherein the source of the PMOS tube M1 and the source of the PMOS tube M3 are connected to an external power supply VDD, the gate of the PMOS tube M1 and the gate of the NMOS tube M2 are connected to an external enable signal EN, the drain of the PMOS tube M1 and the drain of the NMOS tube M2 are connected, the gate of the PMOS tube M3 and the gate of the NMOS tube M4 are connected to an external selection signal SEL, the drain of the PMOS tube M3 and the drain of the NMOS tube M4 are connected, and the sources of the NMOS tubes M2 and M4 are connected to an external ground line GND.

3. A high-speed SubLVDS transmitter circuit with adjustable output swing according to claim 2, characterized in that: In the control circuit (1), the external enable signal EN is passed through an inverter composed of a PMOS tube M1 and an NMOS tube M2 to obtain a signal ENP, and the start-up of the entire circuit is further controlled by the signal ENP. Similarly, the external selection signal SEL is passed through an inverter composed of a PMOS tube M3 and an NMOS tube M4 to obtain a signal SELP, and the signal SELP further controls the switching of the differential output voltage swing.

4. The high-speed SubLVDS transmitter circuit with adjustable output swing according to claim 1, characterized in that: The single-ended to differential circuit (2) comprises: an NMOS tube M6, a PMOS tube M5, a PMOS tube M7, an NMOS tube M8, a PMOS tube M9, an NMOS tube M10, a PMOS tube M11, an NMOS tube M12, a PMOS tube M13, an NMOS tube M14, a PMOS tube M15, an NMOS tube M16, a PMOS tube M17, an NMOS tube M18, a PMOS tube M19, an NMOS tube M20, a PMOS tube M21, and an NMOS tube M22. The sources of the PMOS tube M7, the PMOS tube M9, the PMOS tube M11, the PMOS tube M13, the PMOS tube M15, the PMOS tube M17, the PMOS tube M19 and the PMOS tube M21 are respectively connected to the external power supply VDD, the sources of the NMOS tube M8, the NMOS tube M10, the NMOS tube M12, the NMOS tube M14, the NMOS tube M16, the NMOS tube M18, the NMOS tube M20 and the NMOS tube M22 are respectively connected to the external ground line GND, and the gate of the PMOS tube M13 is connected to the external ground line GND. The gate of the PMOS tube M13 is connected to the drain of the NMOS tube M14, the gate of the PMOS tube M15, the gate of the NMOS tube M16, the source of the PMOS tube M5 and the drain of the NMOS tube M6 respectively; the drain of the PMOS tube M15 is connected to the drain of the NMOS tube M16, the gate of the PMOS tube M17 and the gate of the NMOS tube M18 respectively; the drain of the PMOS tube M17 is connected to the drain of the NMOS tube M18, the gate of the PMOS tube M19 and the gate of the NMOS tube M20 respectively. The gate of the PMOS tube M19 is connected to the gate of the NMOS tube M20, the drain of the PMOS tube M19 is connected to the drain of the NMOS tube M20, the gate of the PMOS tube M21 and the gate of the NMOS tube M22, the drain of the PMOS tube M21 is connected to the drain of the NMOS tube M22, the gate of the PMOS tube M40 and the gate of the NMOS tube M42, the gate of the PMOS tube M5 is connected to the external signal A, the gate of the NMOS tube M6 is connected to the external signal B, the drain of the PMOS tube M5 ... The source of the transistor M6 is connected to the gate of the PMOS transistor M7 and the gate of the NMOS transistor M8. The drain of the PMOS transistor M7 is respectively connected to the drain of the NMOS transistor M8, the gate of the PMOS transistor M9 and the gate of the NMOS transistor M10. The drain of the PMOS transistor M9 is respectively connected to the drain of the NMOS transistor M10, the gate of the PMOS transistor M11 and the gate of the NMOS transistor M12. The drain of the PMOS transistor M11 is respectively connected to the drain of the NMOS transistor M12, the gate of the PMOS transistor M39 and the gate of the NMOS transistor M41.

5. The high-speed SubLVDS transmitter circuit with adjustable output swing according to claim 4, characterized in that: In the single-ended to differential circuit (2), the PMOS tube M5 and the NMOS tube M6 form a transmission gate structure, and the remaining adjacent PMOS tubes and NMOS tubes form an inverter structure, wherein the transmission delay of the transmission gate structure is consistent with the transmission delay of the inverter formed by the PMOS tube M15 and the NMOS tube M16, and the width-to-length ratios of the inverters of the latter stages are multiplied in proportion, so as to enhance the driving capability of the signal so that it can drive the driver circuit (4), and the width-to-length ratios of the PMOS tube M7, the PMOS tube M9, the PMOS tube M11, the PMOS tube M17, the PMOS tube M19, and the PMOS tube M21 should be the same, but the number is different, and the number is multiplied in proportion. Similarly, the width-to-length ratios of the NMOS tube M8, the NMOS tube M10, the NMOS tube M12, the NMOS tube M18, the NMOS tube M20, and the NMOS tube M22 should also be the same, but the number is different, and the number is multiplied in proportion.

6. The high-speed SubLVDS transmitter circuit with adjustable output swing according to claim 1, characterized in that: The bias circuit (3) comprises: an external current source Ibas, a PMOS tube M23, an NMOS tube M24, an NMOS tube M26, an NMOS tube M25, an NMOS tube M27, a resistor R1, a PMOS tube M28, a PMOS tube M30, a PMOS tube M29, and a PMOS tube M31. Among them, one end of the external current source Ibas is respectively connected to the source of the PMOS tube M28, the source of the PMOS tube M29 and the external power supply VDD, the other end of the external current source Ibas is connected to the source of the PMOS tube M23, the gate of the PMOS tube M23 is respectively connected to the drain of the PMOS tube M1, the drain of the NMOS tube M2, the gate of the NMOS tube M25 and the gate of the PMOS tube M31, the drain of the PMOS tube M23 is respectively connected to the drain of the NMOS tube M24, the gate of the NMOS tube M24, the gate of the NMOS tube M26, the gate of the NMOS tube M27 and the drain of the NMOS tube M25, the source of the NMOS tube M24 is respectively connected to the source of the NMOS tube M25, the gate of the NMOS tube M26, the gate of the NMOS tube M27 and the drain of the NMOS tube M25. The source of the OS transistor M26, the source of the NMOS transistor M27 and the external ground line GND are connected, the gate of the PMOS transistor M28 is respectively connected to the drain of the PMOS transistor M28, the drain of the NMOS transistor M28 and the gate of the PMOS transistor M44, the gate of the PMOS transistor M29 is respectively connected to the drain of the PMOS transistor M31, the gate of the PMOS transistor M33, the drain of the PMOS transistor M35, the drain of the PMOS transistor M30 and one end of the resistor R1, the drain of the PMOS transistor M29 is connected to the source of the PMOS transistor M30, and the gate of the PMOS transistor M30 is respectively connected to the other end of the resistor R1, the drain of the NMOS transistor M27, the gate of the PMOS transistor M34 and the drain of the PMOS transistor M36.

7. The high-speed SubLVDS transmitter circuit with adjustable output swing according to claim 6, characterized in that: In the bias circuit (3), the external current source Ibas can be provided by a bandgap reference. The width-to-length ratios of the NMOS tubes M24, M26 and M27 should be the same, but the numbers are different. The resistor R1 is mainly used to control the voltage of the gate of the PMOS tube M30. The width-to-length ratios of the PMOS tubes M28 and M44 are the same, but the numbers are different. The width-to-length ratios of the PMOS tubes M29, M33 and M37 are the same, but the numbers are different and in a proportional relationship. The width-to-length ratios of the PMOS tubes M30, M34 and M38 are the same, but the numbers are different and in a proportional relationship. The proportional relationship is the same as that of the PMOS tubes M29, M33 and M37.

8. The high-speed SubLVDS transmitter circuit with adjustable output swing according to claim 1, characterized in that: The driver circuit (4) comprises: a PMOS tube M32, a PMOS tube M33, a PMOS tube M34, a PMOS tube M35, a PMOS tube M36, a PMOS tube M37, a PMOS tube M38, a PMOS tube M39, a PMOS tube M40, an NMOS tube M41, an NMOS tube M42, an NMOS tube M43, a resistor R2, a resistor R3, and a resistor RL. Among them, the source of the PMOS tube M32 is connected to the source of the PMOS tube M33, the source of the PMOS tube M37, and the external power supply VDD, the drain of the PMOS tube M33 is connected to the source of the PMOS tube M34, the gate of the PMOS tube M35 is connected to the gate of the PMOS tube M36, the drain of the PMOS tube M3, and the drain of the NMOS tube M4, the gate of the PMOS tube M37 is connected to the source of the PMOS tube M35, and the gate of the PMOS tube M38 is connected to the gate of the PMOS tube M39. The source of the PMOS tube M36 is connected, the drain of the PMOS tube M37 is connected to the source of the PMOS tube M38, the drain of the PMOS tube M34 is respectively connected to the drain of the PMOS tube M38, the source of the PMOS tube M39 and the source of the PMOS tube M40, the drain of the PMOS tube M39 is respectively connected to the drain of the NMOS tube M41, one end of the resistor R2 and one end of the resistor RL, the drain of the PMOS tube M40 is respectively connected to the drain of the NMOS tube M42. One end of the resistor R3 is connected to the other end of the resistor RL, the other end of the resistor R2 is respectively connected to the other end of the resistor R and the gate of the PMOS tube M45, the source of the NMOS tube M41 is respectively connected to the source of the NMOS tube M42 and the drain of the NMOS tube M43, the gate of the NMOS tube M43 is respectively connected to the drain of the NMOS tube M48 and the drain of the PMOS tube M46, and the source of the NMOS tube M43 is connected to the external ground line GND.

9. The high-speed SubLVDS transmitter circuit with adjustable output swing according to claim 8, characterized in that: The PMOS tube M33 and the PMOS tube M34, the PMOS tube M37 and the PMOS tube M38 in the driver circuit (4) form two current sources, which mirror the current of the bias circuit (3) and provide driving current for the driver circuit (4); the PMOS tube M35 and the PMOS tube M36 serve as switch control tubes for swing switching to control the shutdown of one of the current sources; the PMOS tube M39, the PMOS tube M40, the NMOS tube M41 and the NMOS tube M42 serve as four switch MOS tubes, either the PMOS tube M39 and the PMOS tube NMOS The transistor M42 is turned on, or the PMOS transistor M40 and the NMOS transistor M41 are turned on; the resistors R2 and R3 are used to detect the common mode voltage of the circuit, and in order to prevent the driver circuit (4) from being affected, their resistance values ​​should be much larger than the resistor RL; the resistor RL is a matching resistor, and its value is 100Ω; through the switching of signals, the PMOS transistor M39 and the PMOS transistor NMOS transistor M42, the PMOS transistor M40 and the NMOS transistor M41 are alternately turned on, thereby changing the direction of the current flowing through the resistor RL in the driver circuit (4), and further changing the positive and negative of the output differential voltage.

10. The high-speed SubLVDS transmitter circuit with adjustable output swing according to claim 1, characterized in that: The common-mode feedback circuit (5) comprises: a PMOS tube M44, a PMOS tube M45, a PMOS tube M46, an NMOS tube M47, an NMOS tube M48, a resistor R4, a resistor R5, a resistor R6, and a resistor R7. Wherein, the source of the PMOS tube M44 and one end of the resistor R4 are connected to the external power supply VDD, the gate of the PMOS tube M44 is connected to the gate of the PMOS tube M28, the drain of the PMOS tube M44 is respectively connected to the source of the PMOS tube M45 and the source of the PMOS tube M46, the drain of the PMOS tube M45 is respectively connected to the gate of the NMOS tube M47, the drain of the NMOS tube M47 and the gate of the NMOS tube M48, the drain of the PMOS tube M46 is respectively connected to the drain of the NMOS tube M48 and the gate of the NMOS tube M43, the source of the NMOS tube M47 is respectively connected to the source of the NMOS tube M48, one end of the resistor R7 and the external ground line GND, the other end of the resistor R7 is connected to one end of the resistor R6, the other end of the resistor R6 is respectively connected to one end of the resistor R5 and the gate of the PMOS tube M46, and the other end of the resistor R5 is connected to the other end of the resistor R4; In the common-mode feedback circuit (5), resistors R4, R5, R6 and R7 form a resistor voltage-dividing branch. By controlling the ratio of the resistors, the reference voltage VCM is approximately equal to about 1V. The common-mode feedback circuit (5) can be regarded as a five-tube operational amplifier with the PMOS tube M44 as a current source. By O The common-mode voltage is compared with the reference voltage VCM, and the gate voltage of the NMOS tube M43 is adjusted through the output, so as to control the common-mode voltage to remain stable.

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