An output phase shifting unit for a fractional frequency synthesizer

Abstract

This invention proposes an output phase-shifting unit for a fractional-number frequency synthesizer, belonging to the field of integrated circuit technology. It includes a resettable Delta-Sigma modulator and a counter. The resettable Delta-Sigma modulator generates a control sequence for controlling the fractional-number division, while the counter controls the reset time of the resettable Delta-Sigma modulator and generates a reset signal. The resettable Delta-Sigma modulator and the counter share the same clock signal. At the start of phase adjustment, the invention resets the resettable Delta-Sigma modulator and simultaneously loads the corresponding count value into the counter, which then begins counting. When the count value is full, a signal is generated, and the resettable Delta-Sigma modulator is reset again upon receiving the signal, thereby shifting the output sequence of the Delta-Sigma modulator and achieving phase shifting of the output signal without changing the division ratio.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to an output phase-shifting unit for a fractional frequency synthesizer. Background Technology

[0002] With the booming development of the communications market, the requirements for wireless communication technology are constantly increasing. Personal wireless communication systems, wireless local area networks (WLANs), satellite navigation systems, and satellite television are experiencing rapid growth. Simultaneously, wireless communication technology is also widely used in high-end technology fields such as space technology and electronic warfare. Among these technologies, digital phased array beamforming, high-speed serial-to-parallel conversion, and multiplexed clock systems have also found widespread application. In these technologies, phase synchronization of multiple local oscillator signals is crucial to their performance, thus placing demands on the phase-shifting function of the frequency synthesizer's output signal.

[0003] Traditional fractional frequency synthesizer output phase shifting units are mainly divided into two types:

[0004] One type is analog, which relies on the time delay characteristics of devices or circuits to shift the signal phase. However, this type of output phase shifter has lower accuracy, higher power consumption, and difficulty in covering a 360° phase shift range;

[0005] Another approach is the digital method, which uses a digital-to-time converter to transform the digital control signal into an analog time delay. However, the design of this output phase-shifting unit is relatively complex and requires a trade-off between accuracy and linearity. Summary of the Invention

[0006] In view of this, the present invention proposes an output phase-shifting unit for a fractional-number frequency synthesizer. The present invention effectively achieves high phase-shifting accuracy and good linearity in a fractional-number frequency synthesizer with only a small amount of additional circuitry.

[0007] The technical solution adopted in this invention is as follows:

[0008] An output phase-shifting unit for a fractional frequency synthesizer includes a resettable Delta-Sigma modulator and a counter. The resettable Delta-Sigma modulator is used to generate a control sequence for controlling fractional frequency division, and the counter is used to control the reset time of the resettable Delta-Sigma modulator and generate a reset signal.

[0009] The counter's input terminal receives the count value, the overflow signal output terminal is connected to the reset port of the resettable Delta-Sigma modulator, and the clock signal port is connected to the clock signal.

[0010] The resettable Delta-Sigma modulator has an FRAC input port for inputting the numerator of the fractional division ratio, an MOD input port for inputting the denominator of the fractional division ratio, an output for outputting the control sequence, a clock signal port for connecting to the clock signal, and a reset port for connecting to the counter overflow signal output port and an external reset signal.

[0011] The resettable Delta-Sigma modulator and counter share the same clock signal.

[0012] Furthermore, the resettable Delta-Sigma modulator has a MASH 1-1-1 structure, including a Sigma-Delta modulator and a noise shaping circuit. The Sigma-Delta modulator is composed of three first-order Sigma-Delta modulators connected in series.

[0013] The carry signal of the third-stage first-order Sigma-Delta modulator is input to the first input port of the first three-input accumulator. At the same time, the carry signal is inverted after passing through a delay circuit and input to the second input port of the first three-input accumulator.

[0014] The carry signal of the second-stage first-order Sigma-Delta modulator is connected to the third input port of the first three-input accumulator after passing through a delay circuit.

[0015] The accumulated result output from the first three-input accumulator is connected to the first input of the second three-input accumulator. At the same time, the accumulated result is inverted after passing through a delay circuit and then connected to the second input of the second three-input accumulator.

[0016] The carry signal of the first-stage first-order Sigma-Delta modulator is input to the third input of the second three-input accumulator after passing through two delay circuits.

[0017] The accumulated result output by the second three-input accumulator is the control sequence.

[0018] Furthermore, at the start of fractional division, the numerator and denominator values ​​of the fractional division ratio are input through the FRAC and MOD ports of the resettable Delta-Sigma modulator;

[0019] At the start of phase adjustment, the resettable Delta-Sigma modulator is first reset by an external reset signal. At the same time, the counter is loaded with the corresponding count value through the input terminal and starts counting.

[0020] When the count value is full, the counter generates a signal and outputs it to the resettable Delta-Sigma modulator through the overflow signal output terminal. After receiving the signal, the resettable Delta-Sigma modulator resets itself again, thereby achieving the shift of the control sequence without changing the fractional division ratio.

[0021] Furthermore, the relationship between the shift phase of the control sequence and the counter count value is as follows:

[0022]

[0023] in, The shift phase is represented by the phase difference of the control sequence; k0 is the count value input to the counter; FRAC is the fractional frequency divider numerator of the FRAC port of the resettable Delta-Sigma modulator, and MOD is the fractional frequency divider denominator of the MOD port of the resettable Delta-Sigma modulator.

[0024] The beneficial effects of this invention are as follows:

[0025] 1. This invention performs two resets on the Delta-Sigma modulator, one at the start of the phase shift and the other at the full count, thereby effectively achieving high phase shift accuracy and good linearity of the fractional frequency synthesizer with only a small amount of additional circuitry.

[0026] 2. This invention uses a counter timing reset method to reset the widely used Delta-Sigma modulator, so that the new sequence is shifted relative to the original sequence, and the new sequence is the same as the original sequence, that is, the small value remains unchanged.

[0027] 3. The present invention can calculate the count value according to the relationship between phase and reset time and load it into the counter. At the start of phase adjustment, the Delta-Sigma modulator is reset and counting begins. After the count value is full, the Delta-Sigma modulator is reset again, thereby accurately changing the output phase of the Delta-Sigma modulator.

[0028] 4. This invention can be used in a signal generator, wherein the signal source can be provided by memory, hard disk, operating system and host computer software. The user can set the required signal frequency and phase, and the corresponding data will be input into the frequency synthesizer chip to generate a signal with the required frequency and phase.

[0029] In summary, this invention utilizes a resettable Delta-Sigma modulator to generate a sequence that controls the division ratio, and uses a counter to control the reset time to achieve sequence shifting. This invention achieves high phase-shifting accuracy and good linearity without changing the division ratio, while avoiding the use of complex RF circuits and digital time conversion circuits, effectively saving the cost of the frequency synthesizer chip. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the output phase shifting unit for a fractional frequency synthesizer in an embodiment of the present invention.

[0031] Figure 2 yes Figure 1 A schematic diagram of the resettable Delta-Sigma modulator.

[0032] Figure 3 This is a flowchart of the sequence translation in an embodiment of the present invention.

[0033] Figure 4 This is a flowchart of the count value calculation in an embodiment of the present invention.

[0034] Figures 5(a) and 5(b) are comparison diagrams of sequence shifting results in the embodiments of the present invention. Figure 5(a) is the output result of the third-order Sigma-Delta modulator, and Figure 5(b) is the output result after sequence shifting.

[0035] Figure 6 This is a diagram showing the phase shift result of the output signal in an embodiment of the present invention. Detailed Implementation

[0036] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the described embodiments are merely some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0037] An output phase-shifting unit for a fractional frequency synthesizer includes a resettable Delta-Sigma modulator and a counter. The resettable Delta-Sigma modulator is used to generate a control sequence for controlling fractional frequency division, and the counter is used to control the reset time of the resettable Delta-Sigma modulator and generate a reset signal.

[0038] The counter's input terminal receives the count value, the overflow signal output terminal is connected to the reset port of the resettable Delta-Sigma modulator, and the clock signal port is connected to the clock signal.

[0039] The resettable Delta-Sigma modulator has an FRAC input port for inputting the numerator of the fractional division ratio, an MOD input port for inputting the denominator of the fractional division ratio, an output for outputting the control sequence, a clock signal port for connecting to the clock signal, and a reset port for connecting to the counter overflow signal output port and an external reset signal.

[0040] The resettable Delta-Sigma modulator and counter share the same clock signal.

[0041] The resettable Delta-Sigma modulator has a MASH 1-1-1 structure, which includes a Sigma-Delta modulator and a noise shaping circuit. The Sigma-Delta modulator is composed of three first-order Sigma-Delta modulators connected in series.

[0042] The carry signal of the third-stage first-order Sigma-Delta modulator is input to the first input port of the first three-input accumulator. At the same time, the carry signal is inverted after passing through a delay circuit and input to the second input port of the first three-input accumulator.

[0043] The carry signal of the second-stage first-order Sigma-Delta modulator is connected to the third input port of the first three-input accumulator after passing through a delay circuit.

[0044] The accumulated result output from the first three-input accumulator is connected to the first input of the second three-input accumulator. At the same time, the accumulated result is inverted after passing through a delay circuit and then connected to the second input of the second three-input accumulator.

[0045] The carry signal of the first-stage first-order Sigma-Delta modulator is input to the third input of the second three-input accumulator after passing through two delay circuits.

[0046] The accumulated result output by the second three-input accumulator is the control sequence.

[0047] At the start of fractional division, the numerator and denominator values ​​of the fractional division ratio are input through the FRAC and MOD ports of the resettable Delta-Sigma modulator.

[0048] The relationship between the shift phase of the control sequence and the counter count value is as follows:

[0049]

[0050] in, The shift phase is represented by the phase difference of the control sequence; k0 is the count value input to the counter; FRAC is the fractional frequency divider numerator of the FRAC port of the resettable Delta-Sigma modulator, and MOD is the fractional frequency divider denominator of the MOD port of the resettable Delta-Sigma modulator.

[0051] The count value is calculated based on the above relationship. At the start of phase adjustment, the resettable Delta-Sigma modulator is first reset by an external reset signal. At the same time, the counter is loaded with the calculated count value through the input terminal and starts counting.

[0052] When the count value is full, the counter generates a signal and outputs it to the resettable Delta-Sigma modulator through the overflow signal output terminal. After receiving the signal, the resettable Delta-Sigma modulator resets itself again, thereby achieving the shift of the control sequence without changing the fractional division ratio.

[0053] It is evident that this output phase shifting unit solves the problem of high-precision and high-linearity phase shifting of the output signal with only a small amount of additional circuitry.

[0054] Here is a more specific example:

[0055] Figure 1 This is the schematic diagram of the phase-shifting unit output of a fractional frequency synthesizer. Figure 1 This section primarily describes the connection relationship between counter 101 and Delta-Sigma modulator 102. Counter 101's input terminal k0 receives the count value, and its output terminal is connected to the reset terminal RST of Delta-Sigma modulator 102. Delta-Sigma modulator 102's input terminals MOD and FRAC receive the fractional division ratio, and its output terminal MC outputs the generated sequence. Both modules share a single clock, typically connected to a feedback divider signal.

[0056] Figure 2 This is a schematic diagram of a Delta-Sigma modulator. It employs a MASH 1-1-1 structure, comprising three first-order Sigma-Delta modulators and a noise shaping circuit. The three first-order Sigma-Delta modulators are connected in series, and the carry input is fed into the noise shaping circuit, which outputs the generated control sequence.

[0057] Figure 3 The flowchart for sequence translation is as follows:

[0058] Step 301: At the start of the phase shift, calculate and load the count value;

[0059] Step 302: Reset the Delta-Sigma modulator to output the sequence from the beginning;

[0060] Step 303: The counter starts counting and outputs a signal when the count value is full;

[0061] Step 304: When the Delta-Sigma modulator receives the signal, it immediately resets again. The sequence output remains unchanged, so the fractional frequency division ratio remains unchanged. The new sequence is offset relative to the original sequence, thereby realizing the phase shift function of the fractional frequency synthesizer output.

[0062] Figure 4 The flowchart for calculating the count value is as follows:

[0063] Step 401: Read the phase value that needs to be moved;

[0064] Step 402: Read the current fractional frequency division value;

[0065] Step 403, according to the formula Calculate the required count value, where Let k be the phase value of the shift, k0 be the count value, FRAC be the numerator of the fractional frequency division, and MOD be the denominator of the fractional frequency division.

[0066] Step 404: Load the obtained count value into the counter.

[0067] Figures 5(a) and 5(b) compare the sequence shifting results. Figure 5(a) shows the output of the constant third-order Sigma-Delta modulator, and Figure 5(b) shows the output after sequence shifting. As can be seen from the figures, after the second reset, the output sequence of the Sigma-Delta modulator is equivalent to being shifted, which can realize the function of shifting the output of the fractional frequency synthesizer.

[0068] Figure 6 The output signal phase-shifting result is shown in the diagram. The original phase signal and the phase-shifted signal are compared. The result shows that the two signals are 135° out of phase, demonstrating that this method achieves the phase-shifting function of the fractional frequency synthesizer output.

[0069] In summary, this invention calculates the count value according to the formula, uses a counter to control the reset time of the Delta-Sigma modulator, and resets the Delta-Sigma modulator twice, at the beginning and end of the count, thereby achieving the translation of the output sequence of the Delta-Sigma modulator.

[0070] This invention achieves a 360° phase shift range without changing the fractional division ratio, exhibiting excellent phase shift accuracy and linearity while minimizing impact on loop performance. Unaffected by process, voltage, or temperature, this invention achieves high phase shift accuracy with only a small increase in additional circuitry and power consumption, effectively saving on the cost of the frequency synthesizer chip.

Claims

1. An output phase shifting unit for a fractional frequency synthesizer, characterized by The resettable delta-sigma modulator is used to generate a control sequence for controlling fractional frequency division, and the counter is used to control the reset time of the resettable delta-sigma modulator and generate a reset signal; The input end of the counter inputs a count value, the overflow signal output end is connected to the reset port of the resettable delta-sigma modulator, and the clock signal port is connected to a clock signal; The FRAC input port of the resettable delta-sigma modulator inputs a numerator value of a fractional frequency division ratio, the MOD port inputs a denominator value of the fractional frequency division ratio, the output end outputs a control sequence, the clock signal port is connected to a clock signal, and the reset port is connected to the overflow signal output end of the counter and an external reset signal; The resettable delta-sigma modulator and the counter share the same clock signal; At the start of fractional frequency division, the numerator value and the denominator value of the fractional frequency division ratio are input through the FRAC port and the MOD port of the resettable delta-sigma modulator; At the start of phase adjustment, the resettable delta-sigma modulator is first reset by an external reset signal, and at the same time, the counter loads a corresponding count value through the input end and starts counting; When the count value is full, the counter generates a signal and outputs it to the resettable delta-sigma modulator through the overflow signal output end, and the resettable delta-sigma modulator resets the delta-sigma modulator again after receiving the signal, thereby achieving the translation of the control sequence without changing the fractional frequency division ratio.

2. An output phase shifting unit for a fractional frequency synthesizer as claimed in claim 1, characterized in that, The resettable delta-sigma modulator is of a MASH 1-1-1 structure, and includes a Sigma-Delta modulator and a noise shaping circuit, wherein the Sigma-Delta modulator is composed of three first-order Sigma-Delta modulators connected in series; The carry signal of the third-order Sigma-Delta modulator is input to the first input port of the first three-input accumulator, and the carry signal is input to the second input port of the first three-input accumulator after being inverted by a delay device; The carry signal of the second-order Sigma-Delta modulator is input to the third input port of the first three-input accumulator after being delayed by a delay device; The accumulated result output by the first three-input accumulator is input to the first input port of the second three-input accumulator, and the accumulated result is input to the second input port of the second three-input accumulator after being inverted by a delay device; The carry signal of the first-order Sigma-Delta modulator is input to the third input port of the second three-input accumulator after being delayed by two delay devices; The accumulated result output by the second three-input accumulator is the control sequence.

3. An output phase shifting unit for a fractional frequency synthesizer as claimed in claim 1, characterized in that, The relationship between the moving phase of the control sequence translation and the count value of the counter is as follows: ， wherein, is the mobile phase, embodied by the phase difference of the control sequence; is the count value input to the counter; FRAC is the fractional divider numerator input to the FRAC port of the resettable delta-sigma modulator, MOD is the fractional divider denominator input to the MOD port of the resettable delta-sigma modulator.

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