Capacitor array calibration method, controller, medium and product

Abstract

The embodiment of the invention provides a capacitor array calibration method, a controller, a medium and a product, which are applied to the technical field of analog-to-digital signal conversion and applied to a capacitor array calibration system, the system comprises a basic capacitor array, a plurality of temperature decoding capacitor arrays and an A / D conversion module, the method comprises the following steps: acquiring residual voltages of to-be-calibrated capacitors in a basic capacitor array and temperature decoding capacitor arrays; performing analog-to-digital conversion on each residual voltage through an A / D conversion module to obtain a digital code of each capacitor to be calibrated; through a preset mismatch code calculation formula, mismatch codes of the to-be-calibrated capacitors are obtained through calculation according to the digital codes; and calibrating the basic capacitor array and each temperature decoding capacitor array according to each mismatch code. According to the embodiment of the invention, the basic capacitor array and each temperature decoding capacitor array are calibrated through each mismatch code, so that the phenomenon of electric leakage of the capacitor arrays can be avoided, and the accuracy of the circuit is improved.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital signal conversion, and in particular to a calibration method, controller, medium and product of a capacitor array. Background Art

[0002] In the related art, the mismatch calibration of the traditional switched capacitor array generally relies on the binary decoding method. Although this method is relatively simple in operation, at the moment of decoding switching, all bits will be briefly set to a high level. Taking the four-bit binary code as an example, when the code is switched from 1000 to 0111, due to the circuit timing limitation, the state of 1111 may appear briefly. This state will cause leakage in the capacitor array, which will adversely affect the accuracy of the circuit. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a calibration method, controller, medium and product of a capacitor array, aiming to avoid leakage of the capacitor array, thereby improving the accuracy of the circuit.

[0004] In a first aspect, an embodiment of the present application provides a calibration method for a capacitor array, which is applied to a calibration system for a capacitor array, the system comprising a basic capacitor array, a plurality of temperature decoding capacitor arrays and an A / D conversion module, the method comprising: Acquiring residual voltages of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays; Performing analog-to-digital conversion on each of the residual voltages through the A / D conversion module to obtain a digital code of each of the capacitors to be calibrated; The mismatch code of each capacitor to be calibrated is calculated according to the digital code by using a preset mismatch code calculation formula; The basic capacitor array and the temperature decoding capacitor arrays are calibrated according to the mismatch codes.

[0005] According to some embodiments of the present application, the system further includes a digital module, a switch logic module and a switch module, the switch module includes a plurality of switches, and the plurality of switches correspond one-to-one to the capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays, and the obtaining of the residual voltage of the capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays includes: By means of the digital module, the switching of the output voltage of the switch logic module is controlled according to a preset control logic, and the access voltage of each switch is controlled according to the output voltage; The residual voltages of the capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays are obtained according to the respective access voltages.

[0006] According to some embodiments of the present application, the mismatch code of each capacitor to be calibrated is calculated according to the digital code using a preset mismatch code calculation formula, including one of the following: When the capacitor to be calibrated belongs to a basic capacitor array, the digital code is input into a first preset mismatch code calculation formula to obtain a mismatch code of the capacitor to be calibrated; When the capacitor to be calibrated belongs to a temperature decoding capacitor array, the digital code is input into a second preset mismatch code calculation formula to obtain the mismatch code of the capacitor to be calibrated.

[0007] According to some embodiments of the present application, the system further includes a register, after obtaining the mismatch code of each capacitor to be calibrated according to the digital code by calculating the mismatch code according to the preset mismatch code calculation formula, including: Each of the mismatch codes is stored in the register.

[0008] According to some embodiments of the present application, the first preset mismatch code calculation formula is: ; in, is the mismatch code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in each of the temperature decoding capacitor arrays, and n is the total number of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays.

[0009] According to some embodiments of the present application, the second preset mismatch code calculation formula is: ; in, is a mismatch code of a capacitor to be calibrated in the temperature decoding capacitor array, A digital code of the capacitor to be calibrated in the temperature decoding capacitor array, is the digital code of the capacitor to be calibrated in each of the temperature decoding capacitor arrays, and n is the total number of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays.

[0010] According to some embodiments of the present application, the system further includes a D / A conversion module, and the calibrating the basic capacitor array and each of the temperature decoding capacitor arrays according to each of the mismatch codes includes: Performing digital-to-analog conversion on each of the mismatch codes through the D / A conversion module to obtain an analog signal of each of the capacitors to be calibrated; The basic capacitor array and each of the temperature decoding capacitor arrays are calibrated according to the analog signal.

[0011] In a second aspect, an embodiment of the present application provides a controller, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the calibration method of the capacitor array of the first aspect mentioned above when running the computer program.

[0012] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the calibration method of the capacitor array as described in the first aspect above.

[0013] In a fourth aspect, an embodiment of the present application provides a computer program product, comprising a computer program or computer instructions, wherein the computer program or the computer instructions are stored in a computer-readable storage medium, a processor of a computer device reads the computer program or the computer instructions from the computer-readable storage medium, and the processor executes the computer program or the computer instructions, so that the computer device performs the calibration method of the capacitor array as described in the first aspect above.

[0014] According to the technical solution of the embodiment of the present application, at least the following beneficial effects are achieved: the embodiment of the present application proposes a calibration method, a controller, a medium and a product for a capacitor array, which are applied to the field of analog-to-digital signal conversion technology, and applied to a calibration system for a capacitor array. The system includes a basic capacitor array, multiple temperature decoding capacitor arrays and an A / D conversion module. The method includes: obtaining the residual voltage of the capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array; performing analog-to-digital conversion on each residual voltage through the A / D conversion module to obtain a digital code for each capacitor to be calibrated; calculating the mismatch code of each capacitor to be calibrated according to the digital code through a preset mismatch code calculation formula; calibrating the basic capacitor array and each temperature decoding capacitor array according to each mismatch code. The embodiment of the present application calibrates the basic capacitor array and each temperature decoding capacitor array through each mismatch code, thereby avoiding leakage of the capacitor array and improving the accuracy of the circuit.

[0015] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0017] Figure 1 is a schematic structural diagram of a capacitance array calibration system provided by an embodiment of the present application; Figure 2 is a structural schematic diagram of a capacitance array calibration system provided by another embodiment of the present application; Figure 3 is a flow chart of a capacitance array calibration method provided by one embodiment of the present application; Figure 4 yes Figure 3 The sub-step flow chart of step S310 shown; Figure 5 yes Figure 3 The sub-step flow chart of step S330 shown; Figure 6 yes Figure 3 The sub-step flow chart of step S340 shown; Figure 7 It is a schematic diagram of a controller for a calibration method for a capacitor array provided in one embodiment of the present application. DETAILED DESCRIPTION

[0018] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0019] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0020] In the description of this application, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0021] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0022] In some cases, mismatch calibration of conventional switched capacitor arrays generally relies on binary decoding. Although this method is relatively simple to operate, at the moment of decoding switching, all bits will be briefly set to a high level. Taking four-bit binary coding as an example, when the code switches from 1000 to 0111, due to circuit timing limitations, the state of 1111 may appear briefly. This state will cause leakage in the capacitor array, which will adversely affect the accuracy of the circuit.

[0023] In addition, the traditional binary decoding calibration method also has the problem of the capacitor array being too large. For an N-bit capacitor array, in order to ensure that the differential nonlinear error is within an acceptable range, the selection of unit capacitors must meet specific requirements. In order to reduce the nonlinear error and the complexity of the calibration circuit, traditional methods tend to choose larger unit capacitors. However, this approach directly leads to an increase in the overall area of ​​the capacitor array, which is not conducive to the miniaturization of the circuit and the improvement of its integration.

[0024] Based on the above situation, the embodiments of the present application propose a calibration method, controller, medium and product for a capacitor array, aiming to avoid leakage of the capacitor array, thereby improving the accuracy of the circuit.

[0025] Various embodiments of the capacitance array calibration system of the present application are further described below in conjunction with the accompanying drawings.

[0026] like Figure 1 and Figure 2 As shown, Figure 1 is a schematic structural diagram of a capacitance array calibration system provided by an embodiment of the present application; Figure 2 It is a structural schematic diagram of a capacitance array calibration system provided in another embodiment of the present application.

[0027] In one embodiment, a calibration system for a capacitor array includes a basic capacitor array, a plurality of temperature decoding capacitor arrays, and an A / D conversion module.

[0028] It can be understood that the basic capacitor array, multiple temperature decoding capacitor arrays and the A / D conversion module are connected in sequence; illustratively, the basic capacitor array is bit1, the multiple temperature decoding capacitor arrays are bit2, bit3 and bit4, the basic capacitor array bit1 is connected to the temperature decoding capacitor array bit2, the temperature decoding capacitor array bit2 is connected to the temperature decoding capacitor array bit4 through the temperature decoding capacitor array bit3, and the temperature decoding capacitor array bit4 is connected to the A / D conversion module.

[0029] It is understandable that the number of the above-mentioned temperature decoding capacitor arrays can be 2, 3, or 4, and can be set according to actual needs. The embodiment of the present application does not specifically limit the number of the temperature decoding capacitor arrays.

[0030] It is understandable that the number of capacitors to be calibrated in the above-mentioned temperature decoding capacitor array can be 1, 2, 3, or 4, which can be set according to actual needs. The embodiment of the present application does not specifically limit the number of temperature decoding capacitor arrays.

[0031] In addition, in one embodiment, the calibration system of the capacitor array further includes a digital module, a switch logic module and a switch module.

[0032] It can be understood that the switch module includes a plurality of switches, and the plurality of switches correspond one-to-one to the capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array.

[0033] It can be understood that the digital module is connected to the A / D conversion module.

[0034] In addition, in one embodiment, the calibration system of the capacitor array further includes a register.

[0035] It can be understood that the registers are connected to the digital modules.

[0036] In addition, in one embodiment, the calibration system for the capacitor array further includes a D / A conversion module.

[0037] It can be understood that the D / A conversion module is connected to the temperature decoding capacitor array.

[0038] Based on the hardware structure of the capacitor array calibration system of each of the above embodiments, various embodiments of the capacitor array calibration method of the present application are respectively proposed below.

[0039] like Figure 3 As shown, Figure 3 It is a flow chart of a capacitance array calibration method provided by an embodiment of the present application; the capacitance array calibration method may include but is not limited to step S310, step S320, step S330 and step S340.

[0040] Step S310, obtaining the residual voltage of the capacitor to be calibrated in the basic capacitor array and each temperature decoding capacitor array; Step S320, performing analog-to-digital conversion on each residual voltage through an A / D conversion module to obtain a digital code of each capacitor to be calibrated; Step S330, obtaining the mismatch code of each capacitor to be calibrated according to the digital code by using a preset mismatch code calculation formula; Step S340: calibrate the basic capacitor array and each temperature decoding capacitor array according to each mismatch code.

[0041] In one embodiment, the embodiment of the present application is applied to a calibration system of a capacitor array, firstly, the residual voltage of the capacitor to be calibrated in the basic capacitor array and each temperature decoding capacitor array is obtained; then, each residual voltage is converted into an analog-to-digital value through an A / D conversion module to obtain a digital code of each capacitor to be calibrated; then, the mismatch code of each capacitor to be calibrated is calculated according to the digital code through a preset mismatch code calculation formula; finally, the basic capacitor array and each temperature decoding capacitor array are calibrated according to each mismatch code. Therefore, the embodiment of the present application calibrates the basic capacitor array and each temperature decoding capacitor array through each mismatch code, so as to avoid leakage of the capacitor array, thereby improving the accuracy of the circuit.

[0042] It can be understood that the errors caused by manufacturing mismatch between the basic capacitor array and each temperature decoding capacitor array can be compensated by each mismatch code, thereby completing the calibration of the temperature decoding capacitor array.

[0043] It is understandable that when the temperature decoding capacitor array switches between encoding and encoding, the 16-bit temperature decoding will only have one bit change. Therefore, the use of the temperature decoding capacitor array can avoid the leakage of the capacitor array. At the same time, using the temperature decoding capacitor array, the DNL error of the unit capacitance of an N-bit capacitor array only needs to satisfy the following formula: ,in, is the DNL standard deviation of the unit capacitor array, is the standard deviation of the manufacturing mismatch per unit capacitance.

[0044] It is understandable that using the temperature decoding capacitor array can use a smaller unit capacitor, thereby reducing the capacitor array area while ensuring high accuracy.

[0045] In addition, if Figure 4 As shown, Figure 4 yes Figure 3 The sub-step flow chart of step S310 is shown; regarding the above-mentioned step S310, it may include but is not limited to step S410 and step S420.

[0046] Step S410: Using a digital module, the output voltage of the switch logic module is switched according to a preset control logic, and the access voltage of each switch is controlled according to the output voltage; Step S420: Obtain residual voltages of capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array according to each access voltage.

[0047] In one embodiment, the digital module controls the switching of the output voltage of the switch logic module according to the preset control logic, thereby changing the access voltage of each switch, and then obtaining the residual voltage of the capacitor to be calibrated in the basic capacitor array and each temperature decoding capacitor array.

[0048] It can be understood that the digital module controls the switch logic module to output high level and low level, thereby realizing the voltage switching of each switch between vrefp and vrefn, and then obtaining the residual voltage of the capacitor to be calibrated in the basic capacitor array and each temperature decoding capacitor array.

[0049] Exemplarily, in order to obtain the residual voltage of the capacitor C_1 to be calibrated, the digital module will first output a high level to the switch S_1 to turn on vrefp, and output a low level to the remaining switches to turn on vrefn. After maintaining the preset time, the residual voltage of the capacitor C_1 to be calibrated is obtained; in order to obtain the residual voltage of the capacitor C_2 to be calibrated, the digital module will first output a high level to the switch S_2 to turn on vrefp, and output a low level to the remaining switches to turn on vrefn. After maintaining the preset time, the residual voltage of the capacitor C_2 to be calibrated is obtained; the method for obtaining the residual capacitance of the remaining capacitors can refer to the above-mentioned method of obtaining the residual voltage of the capacitor C_1 to be calibrated and the capacitor C_2 to be calibrated, which will not be repeated here.

[0050] In addition, if Figure 5 As shown, Figure 5 yes Figure 3 The sub-step flow chart of step S330 is shown; regarding the above-mentioned step S330, it may include but is not limited to step S510 and step S520.

[0051] Step S510: When the capacitor to be calibrated belongs to the basic capacitor array, the digital code is input into a first preset mismatch code calculation formula to obtain the mismatch code of the capacitor to be calibrated; Step S520: When the capacitor to be calibrated belongs to the temperature decoding capacitor array, the digital code is input into a second preset mismatch code calculation formula to obtain the mismatch code of the capacitor to be calibrated.

[0052] It can be understood that both the basic capacitor array and the temperature decoding capacitor array have corresponding mismatch code calculation formulas.

[0053] In addition, in one embodiment, after step S330, the method further includes: storing each mismatch code in a register.

[0054] It can be understood that after the mismatch codes of the capacitors to be calibrated are obtained, each mismatch code is stored in a register.

[0055] It can be understood that the calculation formula of the first preset mismatch code is: ,in, is the mismatch code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in each temperature decoding capacitor array, and n is the total number of capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array.

[0056] Exemplarily, the mismatch code of the capacitor C_1 to be calibrated in the basic capacitor array is 1. The digital code of the capacitor C_1 to be calibrated in the basic capacitor array is 1. The digital codes of the capacitors to be calibrated C_2, C_3 to C_8 in each temperature decoding capacitor array are 2. 3 to 8, the total number of capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array is 8, then the mismatch code of the capacitor C_1 to be calibrated is calculated by the formula Can be calculated.

[0057] It can be understood that the second preset mismatch code calculation formula is: ,in, is the mismatch code of the capacitor to be calibrated in the temperature decoding capacitor array, is the digital code of the capacitor to be calibrated in the temperature decoding capacitor array, is the digital code of the capacitor to be calibrated in each temperature decoding capacitor array, and n is the total number of capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array.

[0058] Exemplarily, the digital codes of the capacitors to be calibrated C_2, C_3 to C_8 in each temperature decoding capacitor array are: 2. 3 to 8, the total number of capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array is 8, then the mismatch code of the capacitor C_2 to be calibrated is calculated by the formula It can be calculated that the mismatch code of the capacitor C_3 to be calibrated is calculated by the formula Can be calculated.

[0059] In addition, if Figure 6 As shown, Figure 6 yes Figure 3 The sub-step flow chart of step S340 is shown; regarding the above-mentioned step S340, it may include but is not limited to step S610 and step S620.

[0060] Step S610: Perform digital-to-analog conversion on each mismatch code through a D / A conversion module to obtain an analog signal of each capacitor to be calibrated; Step S620: calibrate the basic capacitor array and each temperature decoding capacitor array according to the analog signal.

[0061] In one embodiment, the D / A conversion module reads the mismatch code in the register and performs digital-to-analog conversion on the mismatch code to obtain the analog signal of each capacitor to be calibrated, thereby superimposing the analog signal on the plate node of the temperature decoding capacitor array. In this way, the mismatch between the basic capacitor array and each temperature decoding capacitor array caused by process manufacturing deviation is compensated, thereby completing the calibration of the capacitor array.

[0062] Based on the calibration methods of multiple capacitor arrays in the above-mentioned various embodiments, overall embodiments of the calibration methods of capacitor arrays of the present application are respectively proposed below.

[0063] (1) Obtaining residual voltage: like Figure 1 As shown, there is a 4-bit capacitor array to be calibrated, where capacitors C_2, C_3...C_8 are unit capacitors after temperature decoding of the 3-bit capacitor array bit2, bit3, bit4 to be calibrated. The digital module completes the switching of switches S1, S2...S9 between voltages vrefp and vrefn through the switch logic module, and the residual voltages of capacitors C_1, C_2, C_3...C_8 due to process manufacturing deviations can be obtained at the Vp node on the upper plate of the capacitor array.

[0064] (2) Treatment of residual voltage: The A / D conversion module performs analog-to-digital conversion on the residual voltages of capacitors C_1, C_2, C_3…C_8 to obtain D_mis1 (digital code of the residual voltage of capacitor C_1 to be calibrated), D_mis2 (digital code of the residual voltage of capacitor C_2 to be calibrated)…D_mis8 (digital code of the residual voltage of capacitor C_8 to be calibrated). The digital module obtains the digital code and converts the capacitors to be calibrated of each temperature decoding capacitor array into Processing, where x = 2, 3...8, the capacitance C_1 to be calibrated of the basic capacitance array is calculated by the formula Processing is performed to obtain the mismatch codes Dcal1, Dcal2...Dcal8 of the capacitors C_1, C_2...C_8 respectively and send them to the register for storage.

[0065] (3) Mismatch code recovery: The D / A module will read the mismatch code in the register, convert the numerical signal into an analog signal, and superimpose it on the upper plate node Vp of the capacitor array to compensate for the mismatch caused by the manufacturing process deviation of the capacitor array, thereby completing the calibration of the capacitor array.

[0066] Based on the calibration methods of the capacitor array in the above-mentioned embodiments, various embodiments of the controller, computer-readable storage medium and computer program product of the present application are respectively proposed below.

[0067] like Figure 7 As shown, Figure 7 700 is a schematic diagram of a controller for a capacitance array calibration method provided by an embodiment of the present application. The controller 700 implemented in the present application includes: a processor 710, a memory 720, and a computer program stored in the memory 720 and executable on the processor 710, wherein: Figure 7 In the figure, a processor 710 and a memory 720 are taken as an example.

[0068] The processor 710 and the memory 720 may be connected via a bus or other means. Figure 7 The example of connecting through bus is taken in the following.

[0069] The memory 720, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory 720 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 720 optionally includes a memory 720 remotely arranged relative to the processor 710, and these remote memories 720 can be connected to the controller 700 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0070] Those skilled in the art will understand that Figure 7 The device structure shown in the figure does not constitute a limitation on the controller 700, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0071] exist Figure 7 In the controller 700 shown, the processor 710 can be used to call the control program stored in the memory 720, so as to implement the calibration method of the capacitor array described above. Specifically, the non-transient software program and instructions required to implement the calibration method of the capacitor array of the above embodiment are stored in the memory 720, and when executed by the processor 710, the calibration method of the capacitor array of the above embodiment is executed.

[0072] It is worth noting that since the controller 700 of the embodiment of the present application can execute the calibration method of the capacitor array of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the controller 700 of the embodiment of the present application can refer to the specific implementation methods and technical effects of the calibration method of the capacitor array of any of the above-mentioned embodiments.

[0073] In addition, an embodiment of the present application further provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to execute the above-mentioned capacitance array calibration method. Figures 3 to 6 The method steps in .

[0074] It is worth noting that since the computer-readable storage medium of the embodiment of the present application can execute the calibration method of the capacitor array of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the computer-readable storage medium of the embodiment of the present application can refer to the specific implementation methods and technical effects of the calibration method of the capacitor array of any of the above-mentioned embodiments.

[0075] In addition, an embodiment of the present application further provides a computer program product, including a computer program or a computer instruction, the computer program or the computer instruction is stored in a computer-readable storage medium, the processor of the computer device reads the computer program or the computer instruction from the computer-readable storage medium, and the processor executes the computer program or the computer instruction, so that the computer device executes the above-described capacitance array calibration method. Exemplarily, the above-described Figures 3 to 6 The method steps in .

[0076] It is worth noting that since the computer program product of the embodiments of the present application can execute the calibration method of the capacitor array of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the computer program product of the embodiments of the present application can refer to the specific implementation methods and technical effects of the calibration method of the capacitor array of any of the above-mentioned embodiments.

[0077] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media generally include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0078] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0079] In several embodiments provided in the present application, it should be understood that the disclosed systems, apparatuses and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of apparatuses or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0080] It should also be understood that the various implementations provided in the embodiments of the present application can be combined arbitrarily to achieve different technical effects.

[0081] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make various equivalent modifications or substitutions under the shared conditions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A method for calibrating a capacitor array, characterized in that: A calibration system applied to a capacitor array, the system comprising a basic capacitor array, a plurality of temperature decoding capacitor arrays and an A / D conversion module, the method comprising: Acquiring residual voltages of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays; Performing analog-to-digital conversion on each of the residual voltages through the A / D conversion module to obtain a digital code of each of the capacitors to be calibrated; The mismatch code of each capacitor to be calibrated is calculated according to the digital code by using a preset mismatch code calculation formula; The basic capacitor array and the temperature decoding capacitor arrays are calibrated according to the mismatch codes.

2. The method for calibrating a capacitor array according to claim 1, characterized in that: The system further includes a digital module, a switch logic module and a switch module, wherein the switch module includes a plurality of switches, and the plurality of switches correspond one-to-one to the capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays, and the obtaining of the residual voltage of the capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays includes: By means of the digital module, the switching of the output voltage of the switch logic module is controlled according to a preset control logic, and the access voltage of each switch is controlled according to the output voltage; The residual voltages of the capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays are obtained according to the respective access voltages.

3. The method for calibrating a capacitor array according to claim 1, wherein: The step of calculating the mismatch code of each capacitor to be calibrated according to the digital code by using a preset mismatch code calculation formula includes one of the following: When the capacitor to be calibrated belongs to a basic capacitor array, the digital code is input into a first preset mismatch code calculation formula to obtain a mismatch code of the capacitor to be calibrated; When the capacitor to be calibrated belongs to a temperature decoding capacitor array, the digital code is input into a second preset mismatch code calculation formula to obtain the mismatch code of the capacitor to be calibrated.

4. The method for calibrating a capacitor array according to claim 3, characterized in that: The system further includes a register, which, after obtaining the mismatch code of each capacitor to be calibrated by calculating the mismatch code according to the digital code using a preset mismatch code calculation formula, includes: Each of the mismatch codes is stored in the register.

5. The method for calibrating a capacitor array according to claim 3, characterized in that: The calculation formula of the first preset mismatch code is: ； in, is the mismatch code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in each of the temperature decoding capacitor arrays, and n is the total number of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays.

6. The method for calibrating a capacitor array according to claim 3, characterized in that: The calculation formula of the second preset mismatch code is: ； in, is a mismatch code of a capacitor to be calibrated in the temperature decoding capacitor array, A digital code of the capacitor to be calibrated in the temperature decoding capacitor array, is the digital code of the capacitor to be calibrated in each of the temperature decoding capacitor arrays, and n is the total number of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays.

7. The method for calibrating a capacitor array according to claim 1, characterized in that: The system further includes a D / A conversion module, and the step of calibrating the basic capacitor array and each temperature decoding capacitor array according to each mismatch code includes: Performing digital-to-analog conversion on each of the mismatch codes through the D / A conversion module to obtain an analog signal of each of the capacitors to be calibrated; The basic capacitor array and each of the temperature decoding capacitor arrays are calibrated according to the analog signal.

8. A controller, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the capacitance array calibration method according to any one of claims 1 to 7 when executing the computer program.

9. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the calibration method of the capacitor array according to any one of claims 1 to 7.

10. A computer program product comprising a computer program or computer instructions, characterized in that The computer program or the computer instructions are stored in a computer-readable storage medium, and a processor of a computer device reads the computer program or the computer instructions from the computer-readable storage medium. The processor executes the computer program or the computer instructions, so that the computer device performs the calibration method for a capacitor array as described in any one of claims 1 to 7.

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