CoB-based multichannel analog signal acquisition system and method

Abstract

The invention belongs to the technical field of analog signal acquisition, and discloses a multi-channel analog signal acquisition system and method based on CoB. An acquisition circuit comprises a bare chip, a plastic package chip, a ceramic package chip and a passive resistor-capacitor which are installed on one side of a package substrate and form an integrated structure through encapsulation, and signals are led out from the other side of the package substrate through BGA solder balls; the bare chips comprise a plurality of ADC bare chips and an FPGA bare chip, and the plurality of ADC bare chips are vertically stacked and are connected with the FPGA bare chip; the plurality of ADC bare chips are used for analog signal measurement; the plastic package chip is used for reducing the voltage of an input VCC power supply and providing the VCC power supply to the ADC bare chip and the FPGA bare chip; the ceramic sealing chip is used for acquiring a working clock of the system; the passive resistor-capacitor consists of a power supply and a resistor-capacitor and is used for storing, releasing or changing electric energy in an acquisition system, and the ADC bare chip and the FPGA bare chip realize multi-layer stacking through a cantilever beam structure, so that the occupied area of the chips is reduced, the cost is reduced, and the flexibility and the expandability are enhanced.

Description

Technical Field

[0001] The invention belongs to the technical field of analog signal acquisition, and relates to a CoB-based multi-channel analog signal acquisition system and method. Background Art

[0002] In electronic sensor systems, especially in applications such as telemetry, health management, and sensor monitoring, it is often necessary to measure hundreds of analog signals simultaneously. Currently, there are three main types of multi-channel analog measurement solutions: switch multiplexing multi-channel ADC bare chips, multiple single-channel ADC bare chips, and multi-channel synchronous sampling ADC bare chips.

[0003] Use switch multiplexing type multi-channel ADC bare chip (Analog Digital Converter, analog-to-digital converter) input to switch, and each channel is sampled in time. This method has low sampling rate, poor accuracy, channel switching requires settling time, and debugging is difficult. Multiple single-channel ADC bare chips can improve accuracy and sampling rate, but the circuit is expensive and large in size, making it difficult to apply to multiple application scenarios. Multi-channel synchronous sampling ADC bare chip.

[0004] A multi-channel synchronous sampling ADC bare chip can add multiple sample-and-hold front ends to a single ADC bare chip. The sample-and-hold can hold signals from different channels, and the ADC bare chip converts them by polling. Only one ADC bare chip is needed to achieve synchronous analog-to-digital conversion of multiple channels, and no additional setup time is required. This reduces the circuit area and cost while ensuring that the sampling rate and sampling accuracy are not affected. However, the number of electrical signals drawn out increases linearly with the number of ADC bare chips, resulting in difficulties in printed circuit board wiring, and ultimately leading to problems such as large circuit design area, high cost, and difficulty in debugging. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention aims to provide a multi-channel analog signal acquisition system and method based on CoB, replace ADC bare chips and FPGA bare chips with larger packaging areas with bare chips, and realize multi-layer stacking of bare chips through a cantilever beam structure, thereby reducing the chip occupation area; realize the minimum FPGA bare chip system in the packaging substrate, connect the digital signals of all ADC bare chips to the FPGA bare chip through the high-density wiring capability of the packaging substrate, realize synchronous sampling of the ADC bare chips through a unified clock, and frame the sampled data through internal logic design, and send data to the outside through serial low IO communication methods such as UART, QSPI, LVDS, etc., thereby reducing the wiring pressure of the receiving side equipment, so as to realize a universal and standardized integrated design unit; realize the unified assembly of bare chips, plastic-encapsulated chips, ceramic-encapsulated chips and passive resistors and capacitors on the packaging substrate, realize integrated integration through potting or plastic-encapsulation means, and lead out signals to the outside through the BGA solder balls on the bottom surface of the packaging substrate.

[0006] In order to achieve the above object, the present invention adopts the following technical solution:

[0007] The present invention provides a CoB-based multi-channel analog signal acquisition system, comprising a bare chip, a plastic-encapsulated chip, a ceramic-encapsulated chip, and a passive resistor and capacitor installed on one side of a packaging substrate, forming an integrated structure through potting, and the other side of the packaging substrate leads out signals through BGA solder balls; the bare chip comprises a plurality of ADC bare chips and FPGA bare chips, the plurality of ADC bare chips are vertically stacked, and connected to the FPGA bare chip through an ADC bare chip interface IP; the plurality of ADC bare chips are used for analog signal measurement; the plastic-encapsulated chip is used for stepping down an input VCC power supply and providing it to the ADC bare chip and the FPGA bare chip; the ceramic-encapsulated chip is used for acquiring the working clock of the system; the passive resistor and capacitor is composed of a power supply and a resistor and capacitor, and is used for storing, releasing or changing the electric energy in the acquisition system.

[0008] Furthermore, each of the ADC bare chips can independently implement 8 to 16 channels of analog signal measurement.

[0009] Furthermore, the FPGA bare chip, the FLASH bare chip and the temperature sensor are an integrated structure, the FPGA bare chip is used to synchronously sample and convert multiple ADC bare chips; the FLASH bare chip is used to store configuration information of the FPGA bare chip; and the temperature sensor is used to perform temperature compensation on the ADC bare chip.

[0010] Furthermore, the plastic package chip is used to reduce the input VCC power supply to 3.3V and 1.1V, and provide them to the FPGA bare chip and the ADC bare chip.

[0011] Furthermore, the ADC bare chip interface IP is installed at the input end of the FPGA bare chip, and each ADC bare chip interface IP receives the measurement voltage of each channel of the ADC bare chip.

[0012] Furthermore, the output end of the FPGA bare chip is connected to the interface IP, and is connected to an external receiving device through the interface IP.

[0013] Furthermore, the interface IP includes UART, QSPI, and LVDS; and the external receiving device obtains the sampled data according to the interface IP.

[0014] Furthermore, a silicon gasket is arranged between two adjacent ADC bare chips, and the multiple ADC bare chips are connected to the packaging substrate through bonding wires.

[0015] Furthermore, the FLASH bare chip is arranged on the upper end of the FPGA bare chip, a silicon gasket is arranged between the FLASH bare chip and the FPGA bare chip, a copper wire is arranged on the upper end of the silicon gasket, and the signal of the FLASH bare chip is extended to the outside of the silicon gasket through the copper wire, and then connected to the packaging substrate through bonding wires.

[0016] A CoB-based multi-channel analog signal acquisition method is based on the above-mentioned CoB-based multi-channel analog signal acquisition system, comprising the following steps: bare chips, plastic-sealed chips, ceramic-sealed chips, and passive resistors and capacitors are mounted on one side of a packaging substrate and potted as a whole; an ADC bare chip is connected to an FPGA bare chip, and the FPGA bare chip performs synchronous sampling on the ADC bare chip; the FPGA bare chip collects data and frames it, and sends the framed data to the outside through a UART, QSPI, or LVDS serial low IO number communication method.

[0017] Compared with the prior art, the present invention has the following beneficial technical effects:

[0018] The present invention discloses a multi-channel analog signal acquisition system based on CoB, wherein ADC bare chips and FPGA bare chips are stacked in multiple layers through a cantilever beam structure, thereby reducing chip occupation area, reducing costs, and enhancing flexibility and scalability.

[0019] The present invention discloses a multi-channel analog signal acquisition system based on CoB. An ADC bare chip and an FPGA bare chip are connected through an ADC bare chip interface IP. A unified clock is used to synchronously sample the ADC bare chip. The sampled data is framed through internal logic. The framed data is sent to the outside through a UART, QSPI, or LVDS serial low IO number communication mode, thereby reducing the wiring pressure of a receiving-side device.

[0020] The present invention discloses a multi-channel analog signal acquisition system based on CoB. A bare chip, a plastic-sealed chip, a ceramic-sealed chip and a passive resistor and capacitor are integrated into an integrated structure through potting or plastic sealing. Signals are externally led out through BGA solder balls on the bottom surface of a packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a structural diagram of a CoB-based multi-channel analog signal acquisition system of the present invention;

[0022] Figure 2 It is a multi-ADC acquisition system based on FPGA in an embodiment of the present invention;

[0023] Figure 3 This is a working logic diagram of the FPGA in the embodiment of the present invention;

[0024] Figure 4 A diagram showing a vertical stacking structure of multiple ADC bare chips in an embodiment of the present invention;

[0025] Figure 5 It is a stacking structure diagram of an FPGA bare chip and a FLASH bare chip in an embodiment of the present invention;

[0026] Figure 6 It is an assembly flow chart of a multi-channel analog signal acquisition system in an embodiment of the present invention;

[0027] Figure 7 This is a packaging substrate layout of a CoB-based multi-channel analog signal acquisition system in an embodiment of the present invention;

[0028] Figure 8 These are the front and back sides of a circuit sample of a 48-channel analog signal acquisition system in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0030] Example 1

[0031] The present invention discloses a CoB-based multi-channel analog signal acquisition system, comprising a bare chip, a plastic-encapsulated chip, a ceramic-encapsulated chip, and a passive resistor and capacitor installed on one side of a packaging substrate, forming an integrated structure through potting, and the other side of the packaging substrate leads out signals through BGA solder balls; the bare chip comprises a plurality of ADC bare chips and FPGA bare chips, the plurality of ADC bare chips are vertically stacked, and connected to the FPGA bare chip through an ADC bare chip interface IP; the plurality of ADC bare chips are used for analog signal measurement; the plastic-encapsulated chip is used for reducing the voltage of an input VCC power supply and providing it to the ADC bare chip and the FPGA bare chip; the ceramic-encapsulated chip is used for the working clock of the acquisition system; the passive resistor and capacitor are composed of a power supply and a resistor and capacitor, and are used for storing, releasing or changing the electric energy in the acquisition system.

[0032] The multi-layer stacking structure makes the data transmission path between the ADC bare chip and the FPGA bare chip shorter, reduces signal delay, thereby improving data throughput, and reduces the length and complexity of the interconnection between chips, thereby reducing power consumption. It can more finely control the power consumption of each layer of chips, achieve overall power consumption reduction, and be applied to more fields.

[0033] Specifically, Figure 1 As shown, the bare chip includes multiple ADC bare chips and FPGA bare chips. Each ADC bare chip can realize 8-16 channels of analog signal measurement, can receive signals from different analog sources simultaneously or sequentially, and convert them into digital signals. Each channel has independent sampling, quantization and encoding functions, thereby ensuring that each analog signal can be accurately converted into a corresponding digital signal.

[0034] ADC bare chip is the unpackaged form of analog-to-digital converter, which usually includes sampling and holding circuit, quantizer and encoder. It mainly converts continuous analog signals into discrete digital signals and is widely used in communication, data acquisition, audio processing, image processing and other fields.

[0035] FPGA bare chip, FLASH bare chip, ceramic chip, passive RC synchronous sampling ADC bare chip, FPGA bare chip is connected to multiple ADC bare chips through ADC bare chip interface IP, such as Figure 4 As shown, multiple ADC bare chips are homogeneous and have the same area. A silicon gasket without any electrical wiring can be used as an intermediate pad to leave room for the height of the bonding wire arch to ensure that the upper and lower layers of bare chips are bonded to the packaging substrate.

[0036] As an intermediate layer, the silicon gasket can ensure that multiple ADC bare chips can be placed stably on the package substrate and electrically connected to the package substrate through bonding wires. The bottom ADC bare chip is fixed to the package substrate by an adhesive, which can be epoxy resin, wafer bonding film (DAF), etc. After curing, the adhesive can provide sufficient mechanical strength and electrical isolation.

[0037] The FPGA bare chip performs synchronous sampling and conversion on multiple ADC bare chips and implements external digital interfaces. The FLASH bare chip is used to store the configuration information of the FPGA, such as Figure 5 As shown, the FLASH bare chip is arranged on the upper end of the FPGA bare chip, a silicon gasket is arranged between the FLASH bare chip and the FPGA bare chip, a copper sheet is arranged on the upper end of the silicon gasket, the FLASH bare chip is connected to the silicon gasket through the copper sheet, and the silicon gasket and the FPGA bare chip are connected to the packaging substrate through bonding wires.

[0038] Specifically, the FPGA bare chip has a high degree of flexibility and programmability, and can synchronously sample and convert multiple bare chips. It is controlled by the logic and timing management inside the FPGA. The FPGA bare chip can generate a synchronous clock signal and distribute it to each ADC bare chip to ensure that they are sampled at the same time. At the same time, the FPGA bare chip can also receive the conversion results from the ADC bare chip and perform further processing or storage.

[0039] The FLASH bare chip is usually placed on the top of the FPGA bare chip because the FLASH bare chip area is smaller than the FPGA bare chip area. The FLASH bare chip is isolated from the FPGA bare chip by a silicon gasket, which acts as a buffer and support, helping to protect the FLASH bare chip and FPGA bare chip from physical damage. The FLASH bare chip signal is extended to the outside through the silicon gasket and then electrically connected to the package substrate.

[0040] In summary, the FLASH bare chip, silicon gasket, and FPGA bare chip are designed from top to bottom, which realizes the synchronous sampling and conversion of multiple ADC bare chips by the FPGA bare chip, and provides an external digital interface and a FLASH memory for storing FPGA configuration information.

[0041] The ceramic package chip, that is, the crystal oscillator is a ceramic package device, which generates a standard clock as the working clock of the multi-channel analog signal acquisition system, which can ensure the high accuracy of the FPGA bare chip. When converting analog signals to digital signals, the ADC bare chip can sample and quantize at fixed and precise time intervals, minimize quantization errors and additional noise caused by clock jitter, so that the data finally collected and processed truly reflects the characteristics of the original analog signal.

[0042] Passive resistors and capacitors consist of a power supply and resistors and capacitors, and are used to store, release or change electrical energy in the acquisition system.

[0043] The plastic chip, also known as the DC / DC step-down converter, reduces the input VCC power supply to 3.3V and 1.1V for use by the digital logic of the FPGA bare chip and the ADC bare chip. Figure 6 shown.

[0044] like Figure 2 He Ru Figure 3 As shown in the figure, the internal logic of the FPGA bare chip can greatly reduce the number of digital signals connected to the outside. The FPGA input end is connected to the ADC interface IP. Each ADC interface IP is connected to an ADC bare chip to receive the measured voltage results of each channel of the ADC, which mainly include the reset signal RESET, the converter busy signal BUSY, the conversion start signal CONVST, the chip select signal CS and the 8-bit data bus DATA[7:0].

[0045] The reset signal RESET is used to initialize or reset the ADC interface IP and the ADC bare chip to return them to a known state. When the RESET signal is activated, the ADC interface IP and the ADC bare chip should be reset to their default state.

[0046] The converter busy signal BUSY indicates whether the ADC bare chip is performing a conversion operation. When the BUSY signal is high, it means that the ADC bare chip is busy and a new conversion cannot be started. Only when the BUSY signal is low can a new conversion be started through the conversion start signal CONVST.

[0047] The conversion start signal CONVST is used to start the conversion operation of the ADC bare chip. When the BUSY signal is low, the conversion of the ADC bare chip is started by activating the conversion start signal CONVST. After the conversion is completed, the BUSY signal will be pulled high again until the next conversion is started.

[0048] The chip select signal CS is used to select or activate a specific ADC interface IP and ADC bare chip. The chip select signal CS is used to select the ADC to be communicated with currently. Only the selected ADC will respond to other control signals and operations on the data bus.

[0049] The 8-bit data bus DATA[7:0] is used to transmit the digital results after ADC conversion. When the ADC bare chip completes the conversion, the conversion result will be placed on the DATA bus.

[0050] At system startup, all ADC interface IPs and ADC bare chips are initialized through the RESET signal, and the parameters of each ADC interface IP, such as sampling rate, resolution, etc., are configured to ensure that they work as expected. When data acquisition is required, first check the BUSY signal to ensure that the ADC bare chip is not busy. Select a specific ADC bare chip by activating the CS signal, and activate the CONVST signal to start the conversion. Wait for the conversion to complete (the BUSY signal goes low), and then read the conversion result from the DATA bus. Monitor the status signals of the ADC interface IP and ADC bare chip to detect any possible errors or abnormal conditions. If an error is detected, appropriate measures can be taken, such as resetting the ADC interface IP and ADC, recording error information, or notifying the system administrator. Adjust the sampling rate and resolution of the ADC bare chip according to application requirements to balance accuracy and speed, and use state machines or pipeline technology to optimize data acquisition and processing processes to improve system performance.

[0051] Integrate the ADC interface IP into a larger FPGA system to interact with other modules (such as processors, memories, communication interfaces, etc.), and ensure signal synchronization and timing matching between the ADC interface IP and other modules to avoid data loss or errors.

[0052] The temperature sensor is a functional module dedicated to temperature measurement. It can obtain the temperature value of the circuit in real time, communicate with the FPGA bare chip through the temperature sensor interface IP, and transmit temperature data. The FPGA bare chip, as the main controller, is responsible for receiving the temperature data sent by the temperature sensor and performing real-time compensation on all sampled voltage signals according to the temperature data to reduce the impact of ambient temperature on the measured voltage. After the voltage sampling and compensation of each channel is completed, the digital framing serializes the sampled data in a certain format and serializes all sampled data.

[0053] The serialized sampling data is sent through the interface IP, including three types: UART, QSPI, and LVDS. The external receiving device can select the appropriate interface according to actual needs to obtain the power sampling data of all channels.

[0054] In summary, multiple ADC bare chips are stacked vertically, and the electrical connection between multiple ADC bare chips can be achieved through the cantilever beam structure to ensure the smooth transmission of signals and data between chips. The FLASH bare chip is set on the upper end of the FPGA bare chip and connected through the silicon gasket to reduce the packaging area and reduce the volume and weight of the multi-channel analog signal acquisition system. The FPGA minimum system is realized in the packaging substrate. Through the high-density wiring capability of the packaging substrate, the digital signals of all ADC bare chips are connected to the FPGA bare chip. The ADC bare chips are synchronously sampled through a unified clock, and the sampled data is framed through the internal logic design. Finally, the data is sent to the outside through serial low IO communication methods such as UART, QSPI, LVDS, etc., thereby reducing the wiring pressure of the receiving side equipment to realize a universal and standardized integrated design unit. Integrated integration is achieved through potting or plastic sealing, and the BGA solder balls on the bottom of the packaging substrate lead out signals to the outside.

[0055] Example 2

[0056] A multi-channel analog signal acquisition method based on CoB comprises the following steps: a bare chip, a plastic-sealed chip, a ceramic-sealed chip, and a passive resistor and capacitor are mounted on one side of a packaging substrate and potted as a whole; an ADC bare chip is connected to an FPGA bare chip, and the ceramic-sealed chip synchronously samples the ADC bare chip; the FPGA bare chip acquires data and frames it, and the framed data is sent to the outside through a UART, QSPI, or LVDS serial low IO number communication method.

[0057] Specifically, the ceramic chip acts as a clock generator, providing an accurate clock signal for the ADC bare chip, which helps reduce sampling errors and improve the accuracy of data acquisition. The ADC bare chip converts the sampled analog signal into a digital signal and transmits it to the FPGA bare chip through the ADC bare chip interface IP. After receiving the data, the FPGA bare chip performs data processing and framing operations according to the preset algorithms and protocols. During the framing process, the FPGA will package the data into data packets with a certain format for subsequent transmission and processing.

[0058] like Figure 7 As shown in the figure, there are 3 groups of 6 ADC bare chips, which are placed in the upper left, upper right, and lower left positions of the layout, which helps to optimize the signal path, reduce interference, and facilitate the parallel acquisition of multi-channel analog signals. The FPGA bare chip and the FLASH bare chip are located in the lower right of the layout. Figure 8As shown in the figure, the front of the sample has been potted to protect the internal chips and circuits from interference and damage from the external environment. The polished surface shows clear identification, including product model, production date, manufacturer information, etc. The back of the sample is the BGA (Ball Grid Array) pads that lead out the circuit. These pads are used to connect to the motherboard or other circuit modules. BGA packaging has the advantages of high density and high reliability, and is suitable for high-speed and high-frequency signal transmission.

[0059] In summary, efficient, stable and reliable multi-channel analog signal acquisition and processing can be achieved. At the same time, the BGA pad provides convenience for the expansion and integration of the multi-channel analog signal acquisition system.

[0060] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

Claims

1. A multi-channel analog signal acquisition system based on CoB, characterized in that: It includes a bare chip, a plastic-encapsulated chip, a ceramic-encapsulated chip, and a passive resistor and capacitor installed on one side of a packaging substrate, which are potted to form an integrated structure, and the other side of the packaging substrate leads out signals through BGA solder balls; The bare chip includes a plurality of ADC bare chips and FPGA bare chips, wherein the plurality of ADC bare chips are vertically stacked and connected to the FPGA bare chip through an ADC bare chip interface IP; the plurality of ADC bare chips are used for analog signal measurement; The plastic package chip is used to step down the input VCC power supply and provide it to the ADC bare chip and the FPGA bare chip; The ceramic chip is used to collect the working clock of the system; The passive resistor and capacitor are composed of a power supply and a resistor and capacitor, and are used to store, release or change the electric energy in the collection system.

2. The CoB-based multi-channel analog signal acquisition system according to claim 1, characterized in that: Each of the ADC bare chips can independently implement 8 to 16 channels of analog signal measurement.

3. The CoB-based multi-channel analog signal acquisition system according to claim 2, characterized in that: The FPGA bare chip, the FLASH bare chip and the temperature sensor are integrated into one structure. The FPGA bare chip is used to synchronously sample and convert multiple ADC bare chips; the FLASH bare chip is used to store configuration information of the FPGA bare chip; and the temperature sensor is used to perform temperature compensation on the ADC bare chip.

4. The CoB-based multi-channel analog signal acquisition system according to claim 1, characterized in that: The plastic package chip is used to reduce the input VCC power supply to 3.3V and 1.1V, and provide them to the FPGA bare chip and the ADC bare chip.

5. The CoB-based multi-channel analog signal acquisition system according to claim 4, characterized in that: The ADC bare chip interface IP is installed at the input end of the FPGA bare chip, and each ADC bare chip interface IP receives the measurement voltage of each channel of the ADC bare chip.

6. The CoB-based multi-channel analog signal acquisition system according to claim 5, characterized in that: The output end of the FPGA bare chip is connected to the interface IP, and is connected to an external receiving device through the interface IP.

7. The CoB-based multi-channel analog signal acquisition system according to claim 6, characterized in that: The interface IP includes UART, QSPI, and LVDS; The external receiving device obtains the sampled data according to the interface IP.

8. The CoB-based multi-channel analog signal acquisition system according to claim 3, characterized in that: A silicon gasket is arranged between two adjacent ADC bare chips, and a plurality of ADC bare chips are connected to the packaging substrate through bonding wires.

9. The CoB-based multi-channel analog signal acquisition system according to claim 3, characterized in that: The FLASH bare chip is arranged on the upper end of the FPGA bare chip, a silicon gasket is arranged between the FLASH bare chip and the FPGA bare chip, the FLASH bare chip is extended to the outside of the silicon gasket through the copper wire on the silicon gasket, and then connected to the packaging substrate through the bonding wire.

10. A CoB-based multi-channel analog signal acquisition method, based on the CoB-based multi-channel analog signal acquisition system according to any one of claims 1 to 9, characterized in that: The following steps are involved: Bare chips, plastic-encapsulated chips, ceramic-encapsulated chips, and passive resistors and capacitors are installed on one side of the packaging substrate and potted as a whole; The ADC bare chip is connected to the FPGA bare chip, and the FPGA bare chip performs synchronous sampling on the ADC bare chip; The FPGA bare chip collects data and frames it, and sends the framed data to the outside through UART, QSPI, and LVDS serial low IO number communication methods.

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