Amplification and comparison multiplexing circuit for noise shaping SAR ADC

Abstract

The invention provides an amplification and comparison multiplexing circuit for a noise shaping SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The amplification and comparison multiplexing circuit comprises a voltage-time converter and a phase discriminator, according to an existing voltage-time converter, the gain of an amplifier only depends on the ratio of capacitance to current through mutual conversion of a voltage domain and a time domain, and the robustness of a circuit is remarkably improved. On the basis, the comparator and the dynamic amplifier are combined to realize time division multiplexing of comparison and amplification functions, so that the power consumption and the hardware overhead are further reduced.

Description

Technical Field

[0001] The invention discloses an amplification and comparison multiplexing circuit for a noise shaping SAR ADC, belonging to the technical field of analog integrated circuits. Background Art

[0002] The role of an analog-to-digital converter is to convert continuous analog signals from the outside world into discrete digital signals so that digital systems can process, analyze, and store them. This conversion process is essential to modern electronic technology because it allows digital devices to process analog information such as sound, images, and sensor data. Among all types of ADCs, the analog circuit scale of the successive approximation analog-to-digital converter (SAR ADC) is much smaller than the digital circuit scale, and its advantages are more evident in advanced processes with low voltage, low power consumption, and high speed. The noise-shaped SAR ADC combines the advantages of the simple structure and low power consumption of the SAR ADC with the noise shaping technology of the Sigma-Delta ADC to achieve high precision with fewer bits. Due to its high efficiency, it is very suitable for application scenarios that require high precision. This combination has made the noise-shaped SAR ADC a research hotspot in academia, and has achieved innovative results in the fields of consumer electronics, wireless communications, and so on.

[0003] Among them, the key to determining the performance of noise shaping SAR ADC lies in the processing of residual voltage. It can be mainly divided into two methods: active and passive. The advantage of passive is that it does not generate additional power consumption, but it cannot achieve high gain. The advantage of active is that the gain is higher, but the overall power consumption will increase. In order to achieve better noise shaping effect, active amplifiers are mostly used in the existing technology. In order to reduce the power consumption of the amplifier, a dynamic amplifier is derived. Its advantage is that there is no static power consumption, but the disadvantage is that it is easily affected by temperature and process. To address this problem, existing solutions such as Figure 1 The circuit includes a voltage-to-time converter, which is used to convert the quantization result into C DAC After the residual voltage on the plate is converted into a time difference, the time difference is converted into a voltage difference through a discharge operation to complete the amplification of the residual voltage. This method makes the gain of the amplifier depend only on the ratio of capacitance to discharge current, which significantly improves the robustness.

[0004] In order to further reduce the power consumption of ADC, the time domain comparator has more advantages than the traditional voltage comparator. It converts the input voltage into a time difference through a voltage-to-time conversion circuit, and then compares the time difference through a trigger. This operation corresponds exactly to the working process of the above-mentioned voltage-to-time converter. Therefore, the present invention combines the comparison function and the amplification function on the basis of the existing scheme, realizes the time-division multiplexing of comparison and amplification, and saves hardware overhead while reducing power consumption. Summary of the invention

[0005] The purpose of the present invention is to address the deficiencies of the existing technology and propose an amplification and comparison multiplexing circuit for noise shaping SAR ADC. Through simple circuit improvement, the voltage difference is converted into a time difference, and the functions of comparison and residual voltage amplification are respectively completed under different clock phases, thereby realizing time-sharing multiplexing of comparison and amplification in the same circuit, effectively reducing power consumption and hardware overhead, and having good robustness, and can be widely used in noise shaping SAR ADC.

[0006] The technical solution to achieve the purpose of the present invention is:

[0007] An amplification and comparison multiplexing circuit for a noise shaping SAR ADC, characterized by comprising:

[0008] Voltage-time conversion circuit is used to compare C after each quantization DACP (C DACN ) plates and amplifies the residual voltage after the conversion cycle is completed.

[0009] The phase detector is used to generate a comparison result after converting the voltage difference into a time difference.

[0010] Among them, the sampling capacitor C s1 The lower plate is grounded; one end of the first switch Φ1 is connected to the sampling capacitor C s1 The upper plate, the input of the inverter INV1, and the other end is connected to the current source I DACP ; One end of the second switch Φ2 is connected to C f4 The upper plate, one end of the third switch Φ3, the PMOS transistor M P1 The other end is connected to the current source I RESP ; C f4 The lower plate of the third switch Φ3 is connected to C f4 The upper plate, one end of the second switch Φ2, the PMOS transistor M P1 The gate end of the fourth switch Φ4 is connected to the input of the inverter INV3, the PMOS transistor M P1 The drain terminal of the PMOS transistor M P2 The drain end of the eighth switch Φ8, one end of the eighth switch Φ8, and the other end of the eighth switch Φ8 are grounded; the input end of the inverter INV1 is connected to the sampling capacitor C s1 The upper plate, one end of the first switch Φ1, the output end is connected to the first input end of the NAND gate NAND1; the second input end of the NAND gate NAND1 is connected to the clock Φ EN The output terminal is connected to the first input terminal of AND gate AND1 and the positive input terminal of phase detector PD; the second input terminal of AND gate AND1 is connected to clock Φ DA , the output terminal is used as the control signal of the second switch Φ2; the PMOS transistor M P1 The gate terminal C f4The upper plate, one end of the second switch Φ2, one end of the third switch Φ3, and the source end are connected to the power supply.

[0011] Sampling capacitor C s2 The lower plate is grounded; one end of the fifth switch Φ5 is connected to the sampling capacitor C s2 The upper plate, the input of the inverter INV2, and the other end is connected to the current source I DACN ; One end of the sixth switch Φ6 is connected to C f5 The upper plate, one end of the seventh switch Φ7, the PMOS transistor M P2 The other end is connected to the current source I RESN ; C f5 The lower plate of the seventh switch Φ7 is connected to C f5 The upper plate, one end of the sixth switch Φ6, the PMOS transistor M P2 The gate end of the eighth switch Φ8 is connected to the input of the inverter INV3, the PMOS transistor M P1 The drain terminal of the PMOS transistor M P2 The drain end of the inverter INV2 is connected to the sampling capacitor C s2 The upper plate, one end of the fifth switch Φ5, the output end is connected to the first input end of the NAND gate NAND2; the second input end of the NAND gate NAND2 is connected to the clock Φ EN The output terminal is connected to the first input terminal of AND gate AND2 and the negative input terminal of phase detector PD; the second input terminal of AND gate AND2 is connected to clock Φ DA , the output terminal is used as the control signal of the sixth switch Φ6; the PMOS transistor M P2 The gate terminal C f5 The upper plate, one end of the sixth switch Φ6, one end of the seventh switch Φ7, and the source end are connected to the power supply.

[0012] The positive input terminal of the phase detector is connected to C s1 The upper plate voltage is converted to the output of the NAND gate after the first stage voltage-time conversion, and the negative input terminal is connected to C s2 The upper plate voltage is converted into the output of the NAND gate after the first stage voltage-time conversion. The phase detector includes a PMOS transistor M P1 、M P2 、M P3 、M P4 , NMOS transistor M N1 、M N2 , inverters INV4, INV5 and three-input NAND gates NAND1, NAND2. Among them, the PMOS transistor M P1 The gate terminal is connected to the negative input terminal Vin of the phase detector, the source terminal is connected to the power supply, and the drain terminal is connected to the PMOS transistor M P2 The source of the PMOS transistor M P2The gate terminal of the NMOS transistor M is connected to the positive input terminal Vip of the phase detector, and the drain terminal is connected to the second input terminal of the three-input NAND gate NAND1, the output terminal of the inverter INV4, and the input terminal of the inverter INV5. N1 The gate terminal of the PMOS transistor M is connected to the positive input terminal Vip of the phase detector, the drain terminal is connected to the GND of the inverter INV4, and the source terminal is grounded. P3 The gate terminal is connected to the positive input terminal Vip of the phase detector, the source terminal is connected to the power supply, and the drain terminal is connected to the PMOS transistor M P4 The source of the PMOS transistor M P4 The gate terminal of the NMOS transistor M is connected to the negative input terminal Vin of the phase detector, and the drain terminal is connected to the second input terminal of the three-input NAND gate NAND2, the output terminal of the inverter INV5, and the input terminal of the inverter INV4. N2 The gate terminal is connected to the negative input terminal Vin of the phase detector, the drain terminal is connected to the GND of the inverter INV5, and the source terminal is grounded. The first input terminal of the three-input NAND gate NAND1 is connected to the reset signal, the third input terminal is connected to the output OUTB of NAND2, and the output terminal OUT is connected to the first input terminal of NAND2. The third input terminal of the three-input NAND gate NAND2 is connected to the reset signal.

[0013] An amplification and comparison multiplexing circuit for noise shaping SAR ADC, the working steps of the circuit are briefly described as follows.

[0014] Comparison phase: During the comparison cycle, the capacitor C DACP (C DACN ) are sampled to C s1 (C s2 ) upper plate. After Φ1(Φ5) is opened, C s1 (C s2 ) through the current source I DACP (I DACN ) are charged to reach the flip threshold of inverter INV1 (INV2) respectively, and the time difference TIN when INV1 (INV2) outputs low level is sent to the phase detector input through the NAND gate to obtain the comparison result.

[0015] Amplification stage: During the amplification cycle, the capacitor C DACP (C DACN ) are sampled to C s1 (C s2 ) upper plate. After Φ1(Φ5) is opened, C s1 (C s2 ) through the current source I DACP (I DACN) are charged to reach the flip threshold of inverter INV1 (INV2). The time difference TIN of INV1 (INV2) outputting low level is sent to the input of the second-stage AND gate AND1 (AND2) through the NAND gate NAND1 (NAND2), thereby generating the time difference of Φ2 (Φ6) opening. In the pre-charging phase, Φ3 (Φ7) is opened to make C f4 (C f5 ) is pre-charged to the power supply voltage, and there is a time difference TIN between the opening of the discharge switch Φ2 (Φ6), so M P1 (M P2 ) also has a time difference TIN. Therefore, after two levels of voltage-time-voltage conversion, C f4 (C f5 )'s upper plate gets the amplified residual voltage V RESP (V RESN ). P1 or M P2 After one of them is turned on, the input of the inverter INV3 is pulled up to the power supply voltage, and the output enable signal becomes a low level, ending the amplification process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of an existing voltage-to-time conversion circuit.

[0017] Figure 2 It is a schematic diagram of the circuit structure of the present invention.

[0018] Figure 3 It is a schematic diagram of the phase detector structure in the circuit of the present invention.

[0019] Figure 4 Schematic diagram of the timing of the circuit of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose and technical advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of application of the present invention.

[0021] like Figure 2 The circuit structure diagram of the present invention is shown as an amplification and comparison multiplexing circuit for noise shaping SAR ADC, including a sampling capacitor C s1 (C s2 ), voltage-to-time conversion circuit, phase detector. In the comparison cycle, the voltage-to-time converter acts as a comparator. In each comparison process, C s1 (C s2 ) through the current source I DACP (I DACN ) for charging operation, since C s1(C s2 ) has a difference in voltage on the upper plate, so the time it takes for the two to reach the flip threshold of the inverter INV1 (INV2) through charging is different, so the subsequent time when the NAND gate NAND1 (NAND2) outputs a high level is different. The time when the NAND gate AND1 (AND2) outputs a high level is used as the input of the phase detector, and the positive and negative ends V DACP 、V DACN The voltage comparison.

[0022] like Figure 3 The diagram shows the structure of the phase detector in the circuit of the present invention. When the inputs are all low, the reset signal is low, the phase detector is reset, and both ends of its output are high. When the reset signal of the phase detector becomes high and the inputs are one high and one low, if Vip is high, the second input of the three-input NAND gate NAND1 is pulled low, OUT=1, OUTB=0. If Vin is high, the second input of the three-input NAND gate NAND2 is pulled low, OUTB=1, OUT=0. Thus, the comparison of the input signals is completed.

[0023] During the amplification cycle, when the noise shaping SAR ADC completes the normal conversion process, the residual voltage at the positive terminal remains at C DACP On the upper plate, the positive input voltage V of the voltage-to-time converter is obtained after passing through the voltage buffer. P After switch Φ1 is turned on, the current source I DACP V P When V P When it is charged to the flip threshold of inverter INV1, it outputs a low level; the residual voltage at the negative end remains at C DACN The negative input voltage V of the voltage-to-time converter is obtained after passing through the voltage buffer. N After switch Φ5 is turned on, the current source I DACN V N When V N When it is charged to the flip threshold of the inverter INV2, it outputs a low level. P -V N ) is converted into a time difference TIN. The gain of this process (V2T) is expressed as:

[0024]

[0025] Then the time difference TIN turns on switch Φ2 through AND gate AND1, and turns on switch Φ6 through AND gate AND2. The time difference between the two switches turning on is still TIN. RESP C f4 The upper plate voltage is discharged, and the current source I RESN Cf5 The upper plate voltage is discharged. f4 Upper plate voltage V RESP is discharged to the PMOS transistor M P1 threshold voltage, or C f5 Upper plate voltage V RESN is discharged to the PMOS transistor M P2 When the threshold voltage reaches , the inverter INV3 output pulls the enable signal to a low level, ending the amplification process. The gain of this process (T2V) is expressed as:

[0026]

[0027] Therefore, the gain of the entire amplification process is expressed as:

[0028]

[0029] The time difference TIN of the V2T and T2V processes is the same and can be canceled. From the above formula, it can be seen that the gain of the voltage-to-time converter is only related to the capacitance and the discharge current. Through the time-division multiplexing method, the circuit of the present invention realizes the amplification and comparison functions under different clock phases, which effectively saves hardware overhead compared with the existing technical solutions.

Claims

1. An amplification and comparison multiplexing circuit for noise shaping SAR ADC, characterized in that: include: Voltage-to-time conversion circuit, phase detector; The voltage-to-time conversion circuit, wherein the sampling capacitor C s1 The lower plate is grounded; one end of the first switch Φ1 is connected to the sampling capacitor C s1 The upper plate, the input of the inverter INV1, and the other end is connected to the current source I DACP ; One end of the second switch Φ2 is connected to C f4 The upper plate, one end of the third switch Φ3, the PMOS transistor M P1 The gate terminal is connected to the current source I RESP ; C f4 The lower plate of the third switch Φ3 is connected to C f4 The upper plate, one end of the second switch Φ2, the PMOS transistor M P1 The gate end of the fourth switch Φ4 is connected to the input of the inverter INV3, the PMOS transistor M P1 The drain terminal of the PMOS transistor M P2 The drain end of the eighth switch Φ8, one end of the eighth switch Φ8, and the other end of the eighth switch Φ8 are grounded; the input end of the inverter INV1 is connected to the sampling capacitor C s1 The upper plate, one end of the first switch Φ1, the output end is connected to the first input end of the NAND gate NAND1; the second input end of the NAND gate NAND1 is connected to the clock Φ EN The output terminal is connected to the first input terminal of AND gate AND1 and the positive input terminal of phase detector PD; the second input terminal of AND gate AND1 is connected to clock Φ DA , the output terminal is used as the control signal of the second switch Φ2; the PMOS transistor M P1 The gate terminal C f4 The upper plate, one end of the second switch Φ2, one end of the third switch Φ3, and the source end are connected to the power supply; Sampling capacitor C s2 The lower plate is grounded; one end of the fifth switch Φ5 is connected to the sampling capacitor C s2 The upper plate, the input of the inverter INV2, and the other end is connected to the current source I DACN ; One end of the sixth switch Φ6 is connected to C f5 The upper plate, one end of the seventh switch Φ7, the PMOS transistor M P2 The gate terminal is connected to the current source I RESN ; C f5 The lower plate of the seventh switch Φ7 is connected to C f5 The upper plate, one end of the sixth switch Φ6, the PMOS transistor M P2 The gate end of the eighth switch Φ8 is connected to the input of the inverter INV3, the PMOS transistor M P1 The drain terminal of the PMOS transistor M P2 The drain end of the inverter INV2 is connected to the sampling capacitor C s2 The upper plate, one end of the fifth switch Φ5, the output end is connected to the first input end of the NAND gate NAND2; the second input end of the NAND gate NAND2 is connected to the clock Φ EN The output terminal is connected to the first input terminal of AND gate AND2 and the negative input terminal of phase detector PD; the second input terminal of AND gate AND2 is connected to the clock Φ DA , the output terminal is used as the control signal of the sixth switch Φ6; the PMOS transistor M P2 The gate terminal C f5 The upper plate, one end of the sixth switch Φ6, one end of the seventh switch Φ7, and the source end are connected to the power supply.

2. The circuit according to claim 1, characterized in that The phase detector circuit, wherein the positive input terminal of the phase detector is connected to C s1 The upper plate voltage is converted to the output of the NAND gate after the first stage voltage-time conversion, and the negative input terminal is connected to C s2 The upper plate voltage is converted into the output of the NAND gate after the first-stage voltage-time conversion; the phase detector includes a PMOS transistor M P1 、M P2 、M P3 、M P4 , NMOS transistor M N1 、M N2 , inverters INV4, INV5 and three-input NAND gates NAND1, NAND2; wherein, PMOS transistor M P1 The gate terminal is connected to the negative input terminal Vin of the phase detector, the source terminal is connected to the power supply, and the drain terminal is connected to the PMOS transistor M P2 The source of the PMOS transistor M P2 The gate terminal is connected to the positive input terminal Vip of the phase detector, and the drain terminal is connected to the second input terminal of the three-input NAND gate NAND1, the output terminal of the inverter INV4, and the input terminal of the inverter INV5; the NMOS transistor M N1 The gate terminal of the PMOS transistor M is connected to the positive input terminal Vip of the phase detector, the drain terminal is connected to the GND of the inverter INV4, and the source terminal is grounded; P3 The gate terminal is connected to the positive input terminal Vip of the phase detector, the source terminal is connected to the power supply, and the drain terminal is connected to the PMOS transistor M P4 The source of the PMOS transistor M P4 The gate terminal is connected to the negative input terminal Vin of the phase detector, and the drain terminal is connected to the second input terminal of the three-input NAND gate NAND2, the output terminal of the inverter INV5, and the input terminal of the inverter INV4; NMOS transistor M N2 The gate terminal is connected to the negative input terminal Vin of the phase detector, the drain terminal is connected to the GND of the inverter INV5, and the source terminal is grounded; the first input terminal of the three-input NAND gate NAND1 is connected to the reset signal, the third input terminal is connected to the output OUTB of NAND2, and the output terminal OUT is connected to the first input terminal of NAND2; the third input terminal of the three-input NAND gate NAND2 is connected to the reset signal.

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