Sigma-Delta analog-to-digital converter and quantization circuit thereof

Abstract

The invention discloses a Sigma-Delta analog-to-digital converter and a quantization circuit thereof, and the analog-to-digital converter comprises an adder which is used for providing a differential positive input signal and a differential negative input signal; the quantizer comprises a plurality of quantization units, each quantization unit comprises a first capacitor, a first capacitor bank, a second capacitor bank, a fourth capacitor and a comparator, the first capacitor and the first capacitor bank provide positive input voltage for the comparator, and the second capacitor bank and the fourth capacitor provide negative input voltage for the comparator, so that the comparator outputs quantization voltage, the first capacitor group comprises a plurality of second capacitors, the second capacitor group comprises a plurality of third capacitors, the capacitance values of the first capacitor and the fourth capacitor are equal, the capacitance values of the second capacitors and the third capacitors are equal, and the capacitance value of the first capacitor is 1.5 times of the capacitance value of the second capacitor; the threshold voltage of the quantization unit in a jitter mode is 1.5 times that in a normal mode, and the number of capacitors can be reduced, so that the hardware cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital converters, and in particular to a Sigma-Delta analog-to-digital converter and a quantization circuit thereof. Background Art

[0002] In recent years, the information field has placed increasingly higher requirements on the performance of ADC (Analog-to-digital converter). People have begun to pay attention to how to reduce static errors and, when the static errors are fixed, use dither technology to reduce the overall error of ADC quantization and improve the ADC's SNR (Signal-to-Noise Ratio).

[0003] One method of reducing the overall error of ADC quantization by using dithering technology in the prior art Sigma-Delta ADC is to increase the quantization level of the Sigma-Delta modulator quantizer by 0.5 times. For an n-bit quantizer, if the dithering technology is not used (dither off), the quantization level is -(2 n -1)ref,-(2 n -3)ref,…-ref,ref,…(2 n -3)ref,(2 n -1)ref, then the quantization level when using dithering technology (dither on) needs to become -(2 n -1.5)ref,-(2 n -3.5)ref,…-0.5ref,1.5ref,…(2 n -0.5)ref.

[0004] The quantizer of the prior art usually generates the quantization level through capacitors. n -1 quantization unit, each quantization unit requires 2 n In the prior art, to increase the quantizer by 0.5 ref, it is necessary to double the capacitance of each quantization unit and add two unit capacitors C, which requires a total of 2 (2 n +1)C, for an n-bit quantizer, 2 n+1 (2 n +1)C, the hardware cost is relatively high.

[0005] Therefore, a new Sigma-Delta analog-to-digital converter and its quantization circuit need to be proposed. Summary of the invention

[0006] In view of the above problems, an object of the present invention is to provide a Sigma-Delta analog-to-digital converter and a quantization circuit thereof, so as to reduce the hardware cost of the Sigma-Delta analog-to-digital converter implementing the dithering technology.

[0007] According to one aspect of the present invention, a quantization circuit of a Sigma-Delta analog-to-digital converter is provided, comprising an adder for providing a differential positive input signal and a negative input signal; a quantizer, comprising a plurality of quantization units, each of the quantization units comprising: a first capacitor, a first capacitor group, a second capacitor group, a fourth capacitor and a comparator, the first capacitor and the first capacitor group providing a positive input voltage for the comparator, the second capacitor group and the fourth capacitor providing a negative input voltage for the comparator, so that the comparator outputs a quantization voltage, wherein the first capacitor group comprises a plurality of second capacitors, the second capacitor group comprises a plurality of third capacitors, the capacitance values ​​of the first capacitor and the fourth capacitor are equal, the capacitance values ​​of the second capacitor and the third capacitor are equal, and the capacitance value of the first capacitor is 1.5 times the capacitance value of the second capacitor.

[0008] Optionally, the quantization circuit further comprises a jitter signal generating circuit, which is used to generate a jitter signal in a jitter mode of the quantization circuit and provide the jitter signal to the quantization unit.

[0009] Optionally, when the quantization circuit adopts the dithering mode, the first end of the first capacitor is selected to be connected to the common mode voltage or the ground, and the second end of the first capacitor is connected to the positive input terminal of the comparator; the first end of the second capacitor is selected to be connected to the common mode voltage or the positive input signal, and the second end of the second capacitor is connected to the positive input terminal of the comparator; the first end of the third capacitor is selected to be connected to the common mode voltage or the negative input signal, and the second end of the third capacitor is connected to the negative input terminal of the comparator; the first end of the fourth capacitor is selected to be connected to the negative reference signal or the ground, and the second end of the fourth capacitor is connected to the negative input terminal of the comparator.

[0010] Optionally, when the quantization circuit adopts the jitter mode, the first ends of the first to fourth capacitors select the signal to be connected through a switch, and the switch is controlled by the jitter signal and / or a clock signal. In the first phase of the clock signal, the first end of the first capacitor is connected to the common mode voltage, the first end of the second capacitor is connected to the common mode voltage, the first end of the third capacitor is connected to the common mode voltage, and the first end of the fourth capacitor is connected to the negative reference signal; in the second phase of the clock signal, the first end of the first capacitor is grounded, the first end of the second capacitor is connected to the positive input signal, the first end of the third capacitor is connected to the negative input signal, and the first end of the fourth capacitor is grounded.

[0011] Optionally, the number of second capacitors in the first capacitor group is 2 n-1 The number of third capacitors in the second capacitor group is 2 n-1 Wherein, n represents the number of bits of the quantizer.

[0012] Optionally, the number of second capacitors in the first capacitor group is 2 n-1 -1, the number of the third capacitors in the second capacitor group is 2 n-1 -1, where n represents the number of bits of the quantizer.

[0013] Optionally, the quantization circuit switches between the dithering mode and the normal mode by changing a connection mode of the first capacitor, the fourth capacitor and the first end of one of the second capacitors of the quantization unit.

[0014] Optionally, when the quantization circuit adopts the normal mode, the first ends of the first capacitor and the fourth capacitor are constantly grounded, and the first end of one of the second capacitors in the second capacitor group is selectively connected to a positive reference signal or a positive input signal, wherein the first ends of the first to fourth capacitors select the signal to be connected through a switch, and the switch is controlled by the clock signal, and in the first phase of the clock signal, the first end of one of the second capacitors is connected to a positive reference voltage, and in the second phase of the clock signal, the first end of one of the second capacitors is connected to a positive input signal.

[0015] Optionally, an average value of the positive reference signal and the negative reference signal is equal to an average value of the positive input signal and the negative input signal, and the common mode voltage is an average value of the positive reference signal and the negative reference signal.

[0016] According to another aspect of the present invention, there is provided a Sigma-Delta analog-to-digital converter, comprising a Sigma-Delta modulator, wherein the Sigma-Delta modulator comprises a cascaded multi-order modulation circuit; and the quantization circuit as described above.

[0017] The present invention provides a Sigma-Delta analog-to-digital converter and a quantization circuit thereof. The Sigma-Delta analog-to-digital converter includes a cascaded multi-order modulation circuit and a quantization circuit. The quantization circuit includes an adder and a quantizer. The quantizer has multiple quantization units, each of which includes a first capacitor, a first capacitor group, a second capacitor group and a fourth capacitor. The first capacitor group includes multiple second capacitors, the second capacitor group includes multiple third capacitors, the first capacitor and the fourth capacitor have the same capacitance value, the second capacitor and the third capacitor have the same capacitance value, and the first capacitor has a capacitance value that is 1.5 times that of the second capacitor, so that the threshold voltage of the quantization unit in the jitter mode can be 1.5 times that of the threshold voltage of the quantization unit in the normal mode, and the number of capacitors can be reduced, thereby reducing hardware costs.

[0018] In addition, when the quantization unit provided in the present application switches between the dithering mode and the normal mode, it is only necessary to change the first terminal voltages of the first capacitor, the fourth capacitor and one of the second capacitors. Therefore, the circuit structure is relatively simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram showing the structure of a quantization unit that does not use dithering technology in the prior art is shown;

[0021] Figure 2 A schematic diagram of the structure of a quantization unit using dithering technology in the prior art is shown;

[0022] Figure 3 A schematic structural diagram of a Sigma-Delta modulator according to an embodiment of the present invention is shown;

[0023] Figure 4a-4b A schematic diagram of the structure of a quantization unit according to a first embodiment of the present invention is shown;

[0024] Figure 5 A schematic structural diagram of a quantization unit according to a second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0026] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0027] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0028] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0029] Figure 1 FIG. 1 shows a schematic diagram of the structure of a quantization unit in the prior art that does not use dithering technology. Figure 1 , the quantization unit 100 includes capacitors C1, 2 n-1 -1 capacitor C2, 2 n-1 A capacitor C3 and a comparator 10 , wherein the capacitance values ​​of the capacitors C1 , C2 and C3 are equal, and are all unit capacitances C.

[0030] The first end of capacitor C1 is selectively connected to the positive reference signal refp or the positive input signal inp according to a clock signal, the second end of capacitor C1 is connected to the positive input terminal of comparator 10, the first end of capacitor C2 is selectively connected to the common mode voltage cm or the positive input signal inp according to the clock signal, the second end of capacitor C2 is connected to the positive input terminal of comparator 10, the first end of capacitor C3 is selectively connected to the common mode voltage cm or the negative input signal inm according to the clock signal, and the second end of capacitor C3 is connected to the negative input terminal of comparator 10.

[0031] In the first phase (phase1) of the clock signal, the first end of the capacitor C1 is connected to the positive reference signal refp, the first end of the capacitor C2 and the first end of the capacitor C3 are connected to the common mode voltage cm, and in the second phase (phase2) of the clock signal, the first end of the capacitor C1 is connected to the positive input signal inp, the first end of the capacitor C2 is connected to the positive input signal inp, and the first end of the capacitor C3 is connected to the negative input signal inm. Wherein, refp+refm=inp+inm=2*cm, refm represents the negative reference signal, and the positive input signal inp and the negative input signal inm are differential output signals of the adder connected to the quantizer in the Sigma-Delta modulator.

[0032] According to the charge distribution principle, when the clock signal changes from the first phase to the second phase, the change in the voltage difference between the positive and negative input voltages of the comparator 10 is:

[0033] △(op-om)=[2 n (inp-inm)-(refp-refm)] / 2 n =(2 n in-ref) / 2 n

[0034] Among them, op represents the positive input voltage of the comparator 10, om represents the negative input voltage of the comparator 10, inp represents the positive input signal, inm represents the negative input signal, refp represents the positive reference signal, refm represents the negative reference signal, in represents inp-inm, and ref represents refp-refm.

[0035] Figure 2 FIG. 1 shows a schematic diagram of the structure of a quantization unit using a dithering technique in the prior art. Figure 2 , the quantization unit 200 adds capacitors C4 and C5 with a capacitance value of unit capacitance C on the basis of the quantization unit 100, and sets the number of capacitors C2 to 2 n -2, set the number of capacitors C3 to 2 n, the capacitance values ​​of capacitors C1-C3 are all set to 2C. The connection method of capacitors C1-C3 is the same as that of quantization unit 100, which will not be repeated here.

[0036] The first end of capacitor C4 is connected to the positive reference signal refp or the ground gnd according to the clock signal and the jitter signal, the second end of capacitor C4 is connected to the positive input end of comparator 10, the first end of capacitor C5 is connected to the common mode voltage cm or the ground gnd according to the clock signal, and the second end of capacitor C5 is connected to the negative input end of comparator 10.

[0037] In the first phase of the clock signal, the first end of capacitor C4 is connected to the positive reference signal refp, and the first end of capacitor C5 is connected to the common mode voltage cm. In the second phase of the clock signal, the first end of capacitor C4 and the first end of capacitor C5 are connected to the ground gnd.

[0038] According to the charge distribution principle, when the clock signal changes from the first phase to the second phase, the voltage difference between the positive and negative input voltages of the comparator 10 changes by:

[0039] △(op-om)=[2 n (inp-inm)-1.5(refp-refm)] / (2 n +1)=(2 n in-1.5ref) / (2 n +1)

[0040] Among them, op represents the positive input voltage of the comparator 10, om represents the negative input voltage of the comparator 10, inp represents the positive input signal, inm represents the negative input signal, refp represents the positive reference signal, refm represents the negative reference signal, in represents inp-inm, and ref represents refp-refm.

[0041] In summary, although the quantization unit 200 increases the threshold voltage of the quantization level ref by 0.5 times the threshold voltage of the quantization unit 100 to 1.5ref, the unit capacitance required is (2 n+1 +2)C, which is more than twice the unit capacitance required by the quantization unit 100 when the dithering technology is not used, so the hardware cost is relatively high. The main reason why the quantization unit 200 needs to use so many capacitors is that it is impossible to directly obtain a 0.5C capacitor. Based on this, the present invention provides a new quantization unit to solve the above problem.

[0042] Figure 3 A schematic structural diagram of a Sigma-Delta modulator according to an embodiment of the present invention is shown.

[0043] The Sigma-Delta modulator is an important component of the Sigma-Delta ADC. Figure 3 The Sigma-Delta modulator provided in the embodiment of the present invention includes a cascaded first-order modulation circuit 3000, a second-order modulation circuit 2000 and a quantization circuit 1000. The first-order modulation circuit 3000 includes gain amplifiers b1-b3, an adder Σ1 and an integrator 3100, the second-order modulation circuit 2000 includes an adder Σ2 and an integrator 2100 connected in sequence, and the quantization circuit 1000 includes an adder Σ3 and a quantizer 1100 connected in sequence, wherein the adder Σ3 is used to provide a differential positive input signal inp and a negative input signal inm to the quantizer 1100. The quantizer 1100 has a plurality of quantization units, and the number of quantization units is related to the number of bits of the quantizer. An n-bit quantizer generally has 2 n A quantitative unit.

[0044] In addition, the Sigma-Delta modulator further includes a dithering signal generator (not shown in the figure). In the dithering mode of the quantization circuit 1000, the dithering signal generator generates a dithering signal and provides it to the quantization unit.

[0045] Figure 4a-4b The quantization circuit provided by the embodiment of the present invention has a dithering mode and a normal mode. Figure 4a FIG. 4 shows a schematic diagram of the quantization unit 300 when applied to the dithering mode. Figure 4b FIG. 4 is a schematic diagram showing the quantization unit 300 being applied in the normal mode.

[0046] See also Figure 4a The quantization unit 300 includes a capacitor C11, a first capacitor group, a second capacitor group, a capacitor C14 and a comparator 20, wherein the first capacitor group includes 2 n-1 The second capacitor group includes 2 n-1 The capacitance values ​​of capacitors C11 and C14 are equal, and the capacitance values ​​of capacitors C12 and C13 are equal, wherein the capacitance value of capacitor C11 is 1.5 times the unit capacitance C, and the capacitance value of capacitor C12 is the unit capacitance C. The comparator 20 generates an output signal DOP according to its positive input voltage op and negative input voltage om.

[0047] The first end of capacitor C11 is selectively connected to common mode voltage cm or ground gnd, the second end of capacitor C11 is connected to the positive input end of comparator 20, the first end of capacitor C12 is selectively connected to common mode voltage cm or positive input signal inp, the second end of capacitor C12 is connected to the positive input end of comparator 20, the first end of capacitor C13 is selectively connected to common mode voltage cm or negative input signal inm, the second end of capacitor C13 is connected to the negative input end of comparator 20, the first end of capacitor C14 is selectively connected to negative reference signal refm or ground, and the second end of capacitor C14 is connected to the negative input end of comparator 20. Wherein, positive input signal inp and negative input signal inm are differential output signals provided by adder Σ3, refp+refm=inp+inm=2*cm. For example, in the jitter mode, the first ends of capacitors C11-C14 select the signal to be connected through a switch, and the switch is controlled by the clock signal and / or the jitter signal.

[0048] In the first phase of the clock signal, the first end of capacitor C11 is connected to the common mode voltage cm, the first end of capacitor C12 is connected to the common mode voltage cm, the first end of capacitor C13 is connected to the common mode voltage cm, and the first end of capacitor C14 is connected to the negative reference signal refm. In the second phase of the clock signal, the first end of capacitor C11 is connected to the ground gnd, the first end of capacitor C12 is connected to the positive input signal inp, the first end of capacitor C13 is connected to the negative input signal inm, and the first end of capacitor C14 is connected to the ground gnd.

[0049] In the first phase of the clock signal, the comparator 20 resets its positive input voltage op and negative input voltage om, so that the positive input voltage op and negative input voltage om of the comparator 20 are equal. When the clock signal changes from the first phase to the second phase, the change in the capacitor charge is mainly reflected in the difference between the positive and negative input voltages of the comparator 20, specifically:

[0050] In the first phase of the clock signal, the charge amount at the positive input terminal of the comparator 20 is:

[0051] Q1p=(2 n-1 +1.5)C×(op1-cm)

[0052] In the first phase of the clock signal, the charge amount at the negative input terminal of the comparator 20 is:

[0053] Q1m=2 n-1 C×(om1-cm)+1.5C×(om1-refm)

[0054] In the second phase of the clock signal, the charge amount at the positive input terminal of the comparator 20 is:

[0055] Q2p=2 n-1C×(op2-inp)+1.5C×(op2-0)

[0056] In the second phase of the clock signal, the charge amount at the negative input terminal of the comparator 20 is:

[0057] Q2m=2 n-1 C×(om2-inm)+1.5C×(om2-0)

[0058] According to the charge distribution principle, Q1p = Q2p, Q1m = Q2m, thus we get:

[0059] (op2-om2)-(op1-om1)=[2 n (inp-inm)-1.5(refp-refm)] / (2 n +3)=(2 n

[0060] in-1.5ref) / (2 n +3)

[0061] Among them, op1 represents the positive input voltage of the first phase comparator 20 of the clock signal, om1 represents the negative input voltage of the first phase comparator 20 of the clock signal, op2 represents the positive input voltage of the second phase comparator 20 of the clock signal, om2 represents the negative input voltage of the second phase comparator 20 of the clock signal, inp represents the positive input signal, inm represents the negative input signal, refp represents the positive reference signal, refm represents the negative reference signal, in represents inp-inm, and ref represents refp-refm.

[0062] When the quantization unit 300 switches from the dithering mode to the normal mode, see Figure 4b , at this time, the second capacitor group can be regarded as (2 n-1 -1) capacitors C121 and one capacitor C122. It is only necessary to switch the first terminal voltages of capacitors C11, capacitor C122 and capacitor C14, so that the first terminals of capacitors C11 and C14 are constantly connected to ground gnd, and the first terminal of capacitor C122 is connected to the positive reference signal refp or the positive input signal inp according to the clock signal to complete the switching of the quantization unit 300 from the jitter mode to the normal mode. Specifically, in the first phase of the clock signal, the first terminal of capacitor C122 is connected to the positive reference signal refp, and in the second phase of the clock signal, the first terminal of capacitor C122 is connected to the positive input signal inp. For example, in the normal mode, the first terminals of capacitors C11-C14 select the signal to be connected through the switch, and the switch is controlled by the clock signal.

[0063] According to the capacitance charge conservation principle, in the normal mode of the quantization unit 300, when the clock signal changes from the first phase to the second phase, the voltage difference between the positive and negative input voltages of the comparator 20 changes by:

[0064] (op2-om2)-(op1-om1)=[2 n (inp-inm)-1.5(refp-refm)] / (2 n +3)=(2 n

[0065] in-ref) / (2 n +3)

[0066] Among them, op1 represents the positive input voltage of the first phase comparator 20 of the clock signal, om1 represents the negative input voltage of the first phase comparator 20 of the clock signal, op2 represents the positive input voltage of the second phase comparator 20 of the clock signal, om2 represents the negative input voltage of the second phase comparator 20 of the clock signal, inp represents the positive input signal, inm represents the negative input signal, refp represents the positive reference signal, refm represents the negative reference signal, in represents inp-inm, and ref represents refp-refm.

[0067] In summary, the quantization unit 300 provided in the embodiment of the present invention can realize that its threshold voltage is ref in normal mode and its threshold voltage is 1.5ref in dithering mode. And only two 1.5C capacitors need to be added on the basis of the quantization unit 100, which saves 2 compared with the quantization unit 200 in the prior art. n-1 The unit capacitor reduces the circuit cost. In addition, when switching between the jitter mode and the normal mode, it is only necessary to change the connection of the first ends of the three capacitors, so the circuit complexity is also low.

[0068] Figure 5 A schematic structural diagram of a quantization unit according to a second embodiment of the present invention is shown.

[0069] See Figure 4 and Figure 5 The structure of the quantization unit 300 provided in the first embodiment of the present invention is substantially the same as that of the quantization unit 400 provided in the second embodiment, except that the first capacitor group of the quantization unit 400 only includes 2 n-1 -1 capacitor C12, the second capacitor group only includes 2 n-1 −1 capacitor C13, therefore, the quantization unit 400 is reduced by one capacitor C12 and one capacitor C13 relative to the quantization unit 300.

[0070] In the jitter mode, according to the charge conservation principle, when the clock signal changes from the first phase to the second phase, the voltage difference between the positive and negative input voltages of the comparator 20 changes by:

[0071] (op2-om2)-(op1-om1)=[(2 n +1)(inp-inm)-1.5(refp-refm)] / (2 n +1)

[0072] =[(2 n +1)in-1.5ref] / (2 n +1)

[0073] Among them, op1 represents the positive input voltage of the first phase comparator 20 of the clock signal, om1 represents the negative input voltage of the first phase comparator 20 of the clock signal, op2 represents the positive input voltage of the second phase comparator 20 of the clock signal, om2 represents the negative input voltage of the second phase comparator 20 of the clock signal, inp represents the positive input signal, inm represents the negative input signal, refp represents the positive reference signal, refm represents the negative reference signal, in represents inp-inm, and ref represents refp-refm.

[0074] Although the quantization unit 400 reduces two capacitors compared to the quantization unit 300, in a specific implementation process, the number of switches required is greater than that of the quantization unit 300. Therefore, when the area of ​​a single switch is large, the solution of the quantization unit 300 is better than that of the quantization unit 400.

[0075] In addition, the quantization unit 400 can also be applied to the normal mode. The specific principle is the same as that when the quantization unit 300 is applied to the normal mode, and will not be repeated here.

[0076] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A quantization circuit of a Sigma-Delta analog-to-digital converter, comprising: an adder for providing a differential positive input signal and a negative input signal; A quantizer, comprising a plurality of quantization units, each of which comprises: a first capacitor, a first capacitor group, a second capacitor group, a fourth capacitor and a comparator, wherein the first capacitor and the first capacitor group provide a positive input voltage for the comparator, and the second capacitor group and the fourth capacitor provide a negative input voltage for the comparator, so that the comparator outputs a quantized voltage, Among them, the first capacitor group includes multiple second capacitors, the second capacitor group includes multiple third capacitors, the capacitance values ​​of the first capacitor and the fourth capacitor are equal, the capacitance values ​​of the second capacitor and the third capacitor are equal, and the capacitance value of the first capacitor is 1.5 times the capacitance value of the second capacitor.

2. The quantization circuit according to claim 1, further comprising: The jitter signal generating circuit is used to generate a jitter signal in the jitter mode of the quantization circuit and provide the jitter signal to the quantization unit.

3. The quantization circuit according to claim 2, wherein: When the quantization circuit adopts the dithering mode, A first end of the first capacitor is selectively connected to a common mode voltage or ground, and a second end of the first capacitor is connected to a positive input end of the comparator; A first end of the second capacitor is selectively connected to a common mode voltage or a positive input signal, and a second end of the second capacitor is connected to a positive input end of the comparator; The first end of the third capacitor is selectively connected to the common mode voltage or the negative input signal, and the second end of the third capacitor is connected to the negative input end of the comparator; A first end of the fourth capacitor is selectively connected to a negative reference signal or to ground, and a second end of the fourth capacitor is connected to a negative input end of the comparator.

4. The quantization circuit according to claim 3, wherein: When the quantization circuit adopts the dithering mode, the first ends of the first to fourth capacitors select the signals to be connected through switches, and the switches are controlled by the dithering signal and / or a clock signal. In a first phase of the clock signal, a first end of the first capacitor is connected to the common mode voltage, a first end of the second capacitor is connected to the common mode voltage, a first end of the third capacitor is connected to the common mode voltage, and a first end of the fourth capacitor is connected to the negative reference signal; In the second phase of the clock signal, the first end of the first capacitor is grounded, the first end of the second capacitor is connected to the positive input signal, the first end of the third capacitor is connected to the negative input signal, and the first end of the fourth capacitor is grounded.

5. The quantization circuit according to claim 4, wherein: The number of second capacitors in the first capacitor group is 2 n-1 The number of third capacitors in the second capacitor group is 2 n-1 Wherein, n represents the number of bits of the quantizer.

6. The quantization circuit according to claim 4, wherein: The number of second capacitors in the first capacitor group is 2 n-1 -1, the number of the third capacitors in the second capacitor group is 2 n-1 -1, where n represents the number of bits of the quantizer.

7. The quantization circuit according to claim 4, wherein: The quantization circuit switches between the dithering mode and the normal mode by changing the connection mode of the first capacitor, the fourth capacitor and the first end of one of the second capacitors of the quantization unit.

8. The quantization circuit according to claim 7, wherein: When the quantization circuit adopts the normal mode, the first terminals of the first capacitor and the fourth capacitor are permanently grounded, and the first terminal of one of the second capacitors in the second capacitor group is selectively connected to a positive reference signal or a positive input signal. Among them, the first ends of the first to fourth capacitors select the signal to be connected through a switch, and the switch is controlled by the clock signal. In the first phase of the clock signal, the first end of one of the second capacitors is connected to the positive reference voltage, and in the second phase of the clock signal, the first end of one of the second capacitors is connected to the positive input signal.

9. The quantization circuit according to claim 4, wherein: An average value of the positive reference signal and the negative reference signal is equal to an average value of the positive input signal and the negative input signal, and the common mode voltage is an average value of the positive reference signal and the negative reference signal.

10. A Sigma-Delta analog-to-digital converter, comprising a Sigma-Delta modulator, wherein the Sigma-Delta modulator comprises: Cascaded multi-order modulation circuit; as well as A quantization circuit as claimed in any one of claims 1 to 9.

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