Variable-bit-width parallel-serial conversion circuit

Abstract

The invention relates to a variable bit width parallel-serial conversion circuit, which comprises a circuit body, the circuit body comprises two paths of paths for transmitting clock signals and one path for transmitting control signals, and the paths for transmitting the clock signals comprise a low-speed parallel data clock CLKRD and a high-speed serial data clock CLKLINK. A path for transmitting a control signal provides a low speed pulse control signal CLKRDLOAD. The maximum bit width number can be set to be N, a parallel-serial conversion circuit included in the circuit body is composed of 2N D triggers DFFs and N data selectors MUX, N D triggers are arranged in the third row, and the N D triggers DFFs in the first row and the N D triggers DFFs in the third row are formed respectively. Therefore, under the condition that the maximum bit width N is determined by hardware, a parallel-serial conversion circuit composed of 2N D triggers DFFs and N data selectors MUX is utilized to be matched with M-time frequency division of a high-speed serial data clock, and parallel / serial conversion of any variable bit width is achieved in a TX circuit.

Description

Technical Field

[0001] The invention relates to a conversion circuit, in particular to a variable bit width parallel-to-serial conversion circuit. Background Art

[0002] As for the existing serial interface technology, it is widely used in the field of data transmission. With the further increase in data transmission rate requirements, traditional low-speed serial interface technology is gradually unable to meet the demand. At the same time, in order to increase the total bandwidth of data, the first conventional way is to increase the transmission bit width of data, that is, the parallel interface method. However, with the development of parallel interfaces, people have found that the shortage of chip IO number, crosstalk between parallel port data, and difficulties in data synchronization will limit the improvement of parallel interface data transmission rate.

[0003] At present, the emergence of high-speed serial (HSS) interface technology can apply serial technology and parallel technology to data transmission at the same time. While solving the limitations of parallel interfaces, it can further improve the data transmission rate. Therefore, high-speed serial interface technology gradually replaces parallel interface technology and becomes the mainstream technology in today's high-speed data transmission field.

[0004] During the implementation, the low-speed parallel signal is converted into a high-speed differential signal and sent through the serial link through the SerDes technology in the high-speed serial link. At the same time, it can receive the high-speed differential signal of the serial input and correctly convert it into a low-speed parallel signal, that is, complete the data parallel-serial and serial-parallel conversion. Specifically, in the SerDes technology, it is necessary to complete the transmission and reception of high-speed data at the same time. The circuit that completes data transmission is called TX, and the circuit that completes data reception is called RX. In the TX circuit, converting low-speed parallel data into high-speed serial data is a very important step.

[0005] The traditional parallel-to-serial conversion circuit structure is as follows Figure 1 The whole circuit is realized by cascading several 2-bit parallel to 1-bit serial circuits. The bit width of the parallel-to-serial conversion is fixed at 2. N Therefore, since the hardware conditions are fixed and cannot be changed arbitrarily, it is impossible to realize the function of arbitrarily changing the bit width.

[0006] In view of the above-mentioned defects, the designers have actively carried out research and innovation in order to create a variable bit width parallel-to-serial conversion circuit to make it more valuable for industrial use. Summary of the invention

[0007] In order to solve the above technical problems, an object of the present invention is to provide a variable bit width parallel-to-serial conversion circuit.

[0008] The variable bit width parallel-to-serial conversion circuit of the present invention comprises a circuit body, wherein: the circuit body comprises two paths for transmitting clock signals and one path for transmitting control signals.

[0009] The path for transmitting the clock signal includes a low-speed parallel data clock CLK_RD and a high-speed serial data clock CLK_LINK.

[0010] The path for transmitting the control signal provides a low-speed pulse control signal CLK_RD_LOAD,

[0011] Assuming the maximum bit width is N, the parallel-to-serial conversion circuit included in the circuit body is composed of 2N D flip-flops DFF and N data selectors MUX.

[0012] The 2N D flip-flops DFF in the parallel-to-serial conversion circuit are divided into N in the first row and N in the third row, forming the N D flip-flops DFF in the first row and the N D flip-flops DFF in the third row respectively;

[0013] N data selectors MUX exist in the second row, constituting the N data selectors MUX of the second row.

[0014] Furthermore, in the variable bit width parallel-to-serial conversion circuit, the input ports D of the N D flip-flops DFF in the first row are connected to the parallel input data D in The N bits are connected,

[0015] The clock ports CK of the N D flip-flops DFF in the first row are connected to the low-speed parallel data clock CLK_RD, and the output ports Q are connected to the same input end of the N data selectors MUX in the second row.

[0016] Furthermore, in the above-mentioned variable bit width parallel-to-serial conversion circuit, the input port D of the N D flip-flops DFF in the third row is connected to the output end of the N data selectors MUX in the second row, the clock port CK of the N D flip-flops DFF in the third row is connected to the high-speed serial data clock CLK_LINK, the output port Q of the first N-1 D flip-flops DFF is connected to the other input end of the last N-1 data selectors MUX in the second row, and the output port Q of the last D flip-flop DFF is connected to the D flip-flop BUF for output.

[0017] Furthermore, in the above variable bit width parallel-to-serial conversion circuit, the two input ports of the N data selectors MUX in the second row are connected to the output ports Q of the D flip-flops DFF corresponding to the first row and the third row, respectively.

[0018] The output ports of the N data selectors MUX in the second row are respectively connected to the input ports D of the corresponding D flip-flops DFF in the third row, and the control signals of the N data selectors MUX are connected to the low-speed pulse control signal CLK_RD_LOAD. In the circuit body, the input end of the first data selector MUX does not receive serial data and is connected to the ground.

[0019] By means of the above scheme, the present invention has at least the following advantages:

[0020] 1. Under the condition that the maximum bit width N is determined by hardware, a parallel-to-serial conversion circuit consisting of 2N D flip-flops DFF and N data selectors MUX is used, combined with the M-fold frequency division of the high-speed serial data clock, to realize parallel / serial conversion of arbitrary variable bit width in the TX circuit.

[0021] 2. During the implementation, there is no need to use an additional parallel-to-serial conversion circuit with a maximum bit width of M, which can provide convenience for the use of SerDes chips with variable transmission rates.

[0022] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural diagram of a traditional parallel-to-serial conversion circuit.

[0024] Figure 2 This is the structural diagram of the parallel-to-serial conversion circuit with arbitrarily variable bit width proposed in this paper.

[0025] Figure 3 This is the working timing diagram of the parallel-to-serial conversion circuit with arbitrarily variable bit width proposed in this paper.

[0026] Figure 4 It is a schematic diagram of the structure of a data transmission chip that supports the HDMI2.0 protocol. DETAILED DESCRIPTION

[0027] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0028] like Figures 2 to 4The variable bit width parallel-to-serial conversion circuit includes a circuit body, which is characterized in that the circuit body includes two paths for transmitting clock signals and a path for transmitting control signals. Specifically, the paths for transmitting clock signals include a low-speed parallel data clock CLK_RD and a high-speed serial data clock CLK_LINK. At the same time, the path for transmitting the control signal provides a low-speed pulse control signal CLK_RD_LOAD. In order to meet the conversion of any bit width, the maximum bit width is set to N, and the parallel-to-serial conversion circuit included in the circuit body is composed of 2N D flip-flops DFF and N data selectors MUX. During the implementation, the 2N D flip-flops DFF in the parallel-to-serial conversion circuit are divided into N in the first row and N in the third row. In this way, the N D flip-flops DFF in the first row and the N D flip-flops DFF in the third row are respectively constituted. In addition, N data selectors MUX are used in the second row to constitute N data selectors MUX in the second row. For ease of understanding, the first row, second row, and third row described in the present invention are combined Figure 2 Arrangement order from top to bottom.

[0029] In combination with a preferred embodiment of the present invention, the input ports D of the N D flip-flops DFF in the first row are parallel to the input data D in At the same time, the clock ports CK of the N D flip-flops DFF in the first row are connected to the low-speed parallel data clock CLK_RD, and the output ports Q are connected to the same input end of the N data selectors MUX in the second row.

[0030] Further, the input port D of the N D flip-flops DFF in the third row is connected to the output end of the N data selectors MUX in the second row. At the same time, the clock port CK of the N D flip-flops DFF in the third row is connected to the high-speed serial data clock CLK_LINK. In addition, the output port Q of the first N-1 D flip-flops DFF is connected to the other input end of the N-1 data selectors MUX in the second row. Furthermore, the output port Q of the last D flip-flop DFF is connected to the D flip-flop BUF for output.

[0031] In combination with the actual implementation, the two input ports of the N data selectors MUX in the second row are respectively connected to the output ports Q of the D flip-flops DFF corresponding to the first and third rows. At the same time, the output ports of the N data selectors MUX in the second row are respectively connected to the input ports D of the D flip-flops DFF corresponding to the third row. In addition, the control signals of the N data selectors MUX are connected to the low-speed pulse control signal CLK_RD_LOAD. During the final circuit layout, the input end of the first data selector MUX in the circuit body does not receive serial data and is connected to the ground.

[0032] The working principle of the present invention is as follows:

[0033] During the circuit layout, the low-speed parallel data clock signal CLK_RD synchronously samples the input parallel data DATA_IN through the upper N D flip-flops DFF to the data output port Q, ie, the same input end of the N data selectors MUX.

[0034] At the same time, the low-speed pulse control signal CLK_RD_LOAD controls the data selector MUX to synchronously transmit the sampled low-speed parallel data to the data input port D of the N D flip-flops DFF below at the beginning of each parallel-to-serial conversion. Afterwards, the low-speed pulse control signal CLK_RD_LOAD controls the data selector MUX to select another input. The high-speed serial data clock signal CLK_LINK controls the data selector MUX to select another input with the participation of the low-speed pulse control signal CLK_RD_LOAD. Subsequently, the N D flip-flops DFF below are triggered to convert the parallel data into serial data DATA_OUT.

[0035] like Figure 3 In order to better implement the present invention, the timing diagram of the entire parallel-to-serial conversion process (taking N=10 as an example) is first assembled for description.

[0036] The low-speed pulse control signal CLK_RD_LOAD is a pulse signal having a period the same as that of the low-speed parallel data clock CLK_RD and a pulse width the same as that of the high-speed serial data clock CLK_LINK.

[0037] During this period, the frequency of the low-speed parallel data clock CLK_RD is the transmission rate of the parallel data. Therefore, to achieve N-bit parallel-to-serial conversion, the pulse width and the frequency of the high-speed serial data clock CLK_LINK must be N times the frequency of the low-speed parallel data clock CLK_RD.

[0038] The low-speed pulse control signal CLK_RD_LOAD can be regarded as the sign of the start of each parallel-to-serial conversion process. During the implementation, after the high pulse of the low-speed pulse control signal CLK_RD_LOAD ends, the pulse width and the high-speed serial data clock CLK_LINK are based on the transmission rate of the serial data, and the parallel input data sampled by the low-speed parallel data clock CLK_RD are output to DATA_OUT one by one. After that, a parallel-to-serial conversion is completed before the next high pulse of the low-speed pulse control signal CLK_RD_LOAD arrives.

[0039] At the same time, in this parallel-to-serial conversion process, the rising edge of the low-speed parallel data clock CLK_RD has sampled the parallel input data for the next parallel-to-serial conversion to the output port Q of the first row of N D flip-flops DFF. Therefore, when the next high pulse of the low-speed pulse control signal CLK_RD_LOAD arrives, the new parallel input data will be transmitted to the input port D of the third row of N D flip-flops DFF through the second row of N data selectors MUX, and the next parallel-to-serial conversion will start after the high pulse ends.

[0040] It can be seen that the circuit provided by the present invention is different from the traditional parallel-to-serial conversion circuit. Under the condition that the maximum bit width N is determined by hardware, the actual parallel-to-serial conversion bit width M (M≤N) to be completed can be arbitrarily changed according to the needs, without the need to use an additional parallel-to-serial conversion circuit with a maximum bit width of M. The implementation method is as follows:

[0041] If you want to convert M bits of parallel data into serial data, you only need to input parallel data to the M D flip-flops DFF in the first row closest to the output end. The input ends of the remaining NM D flip-flops DFF in the first row are connected to a fixed level. At this time, after completing the M-bit parallel-to-serial conversion, the redundant NM data will be naturally truncated. And after the next parallel-to-serial conversion process starts, it will be updated to the next set of useful parallel data.

[0042] Of course, in order to realize M-bit parallel / serial conversion under the hardware condition of maximum bit width N, the high-speed serial data clock needs to be divided by M times. The realization of this function is not the object protected by the present invention and can be processed by existing technology or other methods, which will not be elaborated here.

[0043] Combination Figure 4 From the perspective of the present invention, the variable bit width parallel-to-serial conversion circuit provided by the present invention is applied to a data transmission chip (TX) supporting the HDMI2.0 protocol. The main circuit of the data transmission chip is composed of input registers, protocol layers, N-bit parallel-to-serial conversion circuits, differential signal transmitters, PLL and other modules. In this embodiment, N of the N-bit parallel-to-serial conversion circuit is preset to 10, that is, the same circuit module can realize the conversion of any parallel data less than or equal to 10 bits to serial data.

[0044] Its workflow in practical application is as follows:

[0045] First, the input register buffers and stores the input data.

[0046] Subsequently, the protocol layer encodes the input low-speed parallel data in different formats according to the HDMI2.0 interface protocol to ensure that the data does not stop jumping for a long time. This can prevent possible erroneous sampling in the clock recovery circuit (CDR) in the data receiving chip (RX).

[0047] After that, the N-bit parallel-to-serial conversion circuit converts the low-speed parallel data encoded by the protocol layer into a high-speed low-voltage signal, that is, high-speed serial data. Thus, the most critical parallel-to-serial conversion function in TX is realized. After that, the differential signal transmitter drives the high-speed differential signal and sends it to the input IO of the RX chip as the output of the TX chip. During the implementation, the PLL provides the circuit with a low-speed parallel data clock and a high-speed serial data clock.

[0048] Next, according to the working principle of the parallel-to-serial conversion circuit with arbitrarily variable bit width of the present invention, the structural diagram of the 10-bit parallel-to-serial conversion circuit in this application is as follows: Figure 2 N is 10. The connection method is that the input port D of the 10 D flip-flops DFF in the first row is respectively connected to the 10 bits of the parallel input data DATA_IN, and the clock port CK is connected to the CLK_RD clock signal. At the same time, the output port Q is connected to the same input end of the 10 data selectors MUX in the second row. The input port D of the 10 D flip-flops DFF in the third row is connected to the output end of the 10 data selectors MUX in the second row. The clock port CK is connected to the CLK_LINK clock signal. In this way, the output port Q of the first 9 D flip-flops DFF is connected to the other input end of the last 9 data selectors MUX in the second row, and the output port Q of the last D flip-flop DFF is connected to the output BUF. The two input ports of the 10 data selectors MUX in the second row are respectively connected to the output ports Q of the D flip-flops DFF in the first and third rows according to the aforementioned connection method. In addition, the output port is respectively connected to the input port D of the D flip-flops DFF in the third row according to the aforementioned connection method. Furthermore, the control signal of the 10 data selectors MUX is connected to the pulse signal CLK_RD_LOAD. The input end on one side of the first data selector MUX does not receive serial data and is connected to ground.

[0049] During implementation, the high-speed serial data clock CLK_LINK, the low-speed parallel data clock CLK_RD, and the low-speed pulse control signal CLK_RD_LOAD are all generated by the PLL.

[0050] Specifically, the low-speed parallel data clock signal CLK_RD transmits the 10-bit input parallel data DATA_IN encoded by the protocol layer through the 10 D flip-flops DFF above, and then synchronously samples it to the data output port Q, that is, the same input end of the 10 data selectors MUX.

[0051] At the beginning of each parallel-to-serial conversion, the low-speed pulse control signal CLK_RD_LOAD controls the data selector MUX to synchronously transmit the sampled low-speed parallel data to the data input ports D of the lower 10 D flip-flops DFF.

[0052] After that, the low-speed pulse control signal CLK_RD_LOAD controls the data selector MUX to select another input. The high-speed serial data clock signal CLK_LINK triggers the 10 D flip-flops DFF below to convert the parallel data into serial data DATA_OUT, which is transmitted to the differential signal transmitter as the output of the parallel-to-serial conversion circuit.

[0053] Through simulation verification, it can be seen that the data transmission chip constructed using the structural circuit of the present application can support the 6GSPS data transmission rate required by the HDMI2.0 protocol, and can meet the requirements of bit error rate and eye width under different PVT conditions.

[0054] It can be seen from the above textual description and the accompanying drawings that the present invention has the following advantages:

[0055] 1. Under the condition that the maximum bit width N is determined by hardware, a parallel-to-serial conversion circuit consisting of 2N D flip-flops DFF and N data selectors MUX is used, combined with the M-fold frequency division of the high-speed serial data clock, to realize parallel / serial conversion of arbitrary variable bit width in the TX circuit.

[0056] 2. During the implementation, there is no need to use an additional parallel-to-serial conversion circuit with a maximum bit width of M, which can provide convenience for the use of SerDes chips with variable transmission rates.

[0057] In addition, the indicated orientations or positional relationships described in the present invention are all based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or structure referred to must have a specific orientation or be operated with a specific orientation structure. Therefore, they cannot be understood as limitations on the present invention.

[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A variable bit width parallel-to-serial conversion circuit, comprising a circuit body, characterized in that: The circuit body includes two paths for transmitting clock signals and one path for transmitting control signals. The path for transmitting the clock signal includes a low-speed parallel data clock CLK_RD and a high-speed serial data clock CLK_LINK. The path for transmitting the control signal provides a low-speed pulse control signal CLK_RD_LOAD, Assuming the maximum bit width is N, the parallel-to-serial conversion circuit included in the circuit body is composed of 2N D flip-flops DFF and N data selectors MUX. The 2N D flip-flops DFF in the parallel-to-serial conversion circuit are divided into N in the first row and N in the third row, forming the N D flip-flops DFF in the first row and the N D flip-flops DFF in the third row respectively; N data selectors MUX exist in the second row, constituting the N data selectors MUX of the second row.

2. The variable bit width parallel-to-serial conversion circuit according to claim 1, characterized in that: The input ports D of the N D flip-flops DFF in the first row are parallel to the input data D in The N bits are connected, The clock ports CK of the N D flip-flops DFF in the first row are connected to the low-speed parallel data clock CLK_RD, and the output ports Q are connected to the same input end of the N data selectors MUX in the second row.

3. The variable bit width parallel-to-serial conversion circuit according to claim 1, characterized in that: The input ports D of the N D flip-flops DFF in the third row are connected to the output ends of the N data selectors MUX in the second row, the clock ports CK of the N D flip-flops DFF in the third row are connected to the high-speed serial data clock CLK_LINK, the output ports Q of the first N-1 D flip-flops DFF are connected to the other input ends of the last N-1 data selectors MUX in the second row, and the output port Q of the last D flip-flop DFF is connected to the D flip-flop BUF for output.

4. The variable bit width parallel-to-serial conversion circuit according to claim 1, characterized in that: The two input ports of the N data selectors MUX in the second row are respectively connected to the output ports Q of the D flip-flops DFF corresponding to the first row and the third row. The output ports of the N data selectors MUX in the second row are respectively connected to the input ports D of the corresponding D flip-flops DFF in the third row, and the control signals of the N data selectors MUX are connected to the low-speed pulse control signal CLK_RD_LOAD. In the circuit body, the input end of the first data selector MUX does not receive serial data and is connected to the ground.

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