Aurora protocol-based line rate security adaptive negotiation method

Abstract

The invention discloses a line rate safety adaptive negotiation method based on an Aurora protocol, which comprises the following steps of: when the line rate of a satellite load is switched or a link between ground detection equipment and the load is interrupted due to unstable hardware connection, firstly stopping transmitting and receiving data, and switching the Aurora line rate to the highest grade by dynamically reconfiguring a port; and then resetting the channel, if the high-speed transceiver successfully synchronizes and establishes a link successfully, starting to transmit and receive data, and if the high-speed transceiver fails to synchronize within a certain time, reducing a gear Aurora line rate to wait for the high-speed transceiver to synchronize again. According to the line rate safety adaptive negotiation method based on the Aurora protocol, safety adaptive adjustment of the line rate based on the Aurora protocol is achieved, links are reconnected under the condition that FPGA does not need to be reconfigured, the test process of ground detection equipment is simplified, the test efficiency is improved, meanwhile, data sending is stopped when link linkage is unstable, and the test efficiency is improved. And the reliability of the ground detection equipment on the satellite load flow test is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a line rate security adaptive negotiation method based on the Aurora protocol. Background Art

[0002] With the continuous progress and innovation of aerospace technology, the popularity and application of satellite Internet are becoming more and more extensive. Satellite communication systems can now provide communication services worldwide, especially in remote areas that are difficult to reach with ground communication facilities. However, due to the difficulty and high cost of repairing satellite payloads on orbit, the introduction of ground detection systems has become crucial. Ground detection systems can reveal potential defects in satellite payloads. Through ground detection systems, the risk of satellite payload failure can be significantly reduced, and the cost of on-orbit maintenance can be greatly reduced.

[0003] In recent years, satellite ground detection equipment has widely adopted the GTX interface based on the Aurora protocol because it needs to process and transmit a large amount of high-speed and high-reliability data. The Aurora protocol is a high-performance serial communication protocol designed specifically for FPGAs, supporting data transmission rates up to 12.5Gbps, effectively meeting the data throughput requirements of satellite ground detection equipment. The high reliability of the GTX interface is crucial to ensuring the long-term stable operation of on-orbit satellite payloads.

[0004] Due to the different application scenarios and structures of on-orbit satellite payloads, the line rates required by the Aurora protocol of different ground detection equipment are very different, which leads to the need to develop a variety of ground detection equipment to adapt to different line rates, thereby increasing the development cost, extending the development cycle, and making software maintenance and updates complicated. Yang Kaixiang et al., in "Design and Implementation of Multi-channel Fiber High-speed Serial Transmission System", 2017:61-64, made different designs for different Aurora line rates, fixed the two Aurora line rate services to two different ports, and each port supported one Aurora line rate. When the rate adjustment is required, the corresponding interface can be switched on the hardware to achieve line rate compatibility. However, this method requires changing the physical connection of the ground detection equipment, and achieving Aurora line rate compatibility through hardware, which makes the testing process cumbersome.

[0005] Aloisio used a dynamic configuration port to achieve Aurora line rate compatibility in "A Frequency Agile, Self-Adaptive Serial Link on XilinxFPGAs", 2015:955-962; Yuan Yisen also used a dynamic configuration port to achieve Aurora line rate compatibility in "Software-based Radar Data Preprocessing and Interface FPGA Design". Both of them achieve Aurora line rate compatibility through software rather than hardware, and require manual operation of the host computer interface. When the line rate of the Aurora interface of the test party is switched, the ground detection equipment takes a long time to adapt to the switched line rate, which is not friendly to automated testing. In addition, there is a hidden danger in the way of implementing Aurora line rate switching with a dynamic configuration port: when the Aurora line rate is switched using a dynamic configuration port, even if the channel connection is unstable, data is still being sent. At this time, data transmission will cause data errors or losses, making the ground detection system's flow test of the satellite payload unreliable. Summary of the invention

[0006] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is that the existing Aurora line rate switching method based on the dynamic configuration port still requires multiple manual operations on the upper computer interface. When the line rate of the Aurora interface of the test party is switched, the time for the ground detection equipment to adapt to the switched line rate is long, which is not friendly to the automated test, and in the process of switching the line rate channel connection instability, the data is still being sent, and the transmitted data will be erroneous or lost at this time, causing the ground detection system to test the satellite payload unreliable. The present invention provides a line rate safety adaptive negotiation method based on the Aurora protocol, which can realize the safe adaptive adjustment of the line rate based on the Aurora protocol. Whenever the load of different Aurora line rates is switched or the link between the local ground detection device and the load is interrupted due to unstable hardware connection, data transmission will be stopped, and the clock of the Aurora interface will be automatically controlled through the dynamic reconfiguration port to change the line rate of Aurora, so as to reconnect the link without reconfiguring the FPGA, simplifying the test process of the ground detection equipment, improving the test efficiency, and stopping data transmission when the link link is unstable, so as to improve the reliability of the ground detection equipment for satellite payload flow testing.

[0007] To achieve the above-mentioned purpose, the present invention provides a line rate security adaptive negotiation method based on the Aurora protocol. Whenever the line rate of the satellite payload is switched or the link between the local surface detection device and the payload is interrupted due to unstable hardware connection, the data transmission and reception is first stopped, and the Aurora line rate is switched to the highest level by dynamically reconfiguring the port. Then, the channel is reset. If the high-speed transceiver is synchronized successfully and the link is successfully established, data transmission and reception begins. If the high-speed transceiver fails to synchronize within a certain period of time, the Aurora line rate is reduced by one level to wait for the high-speed transceiver to be synchronized again.

[0008] Furthermore, a line rate control architecture for realizing the process of switching the line rate to the highest level and reducing the line rate by one level includes a line rate control module, a quadruple frequency phase-locked loop and a high-speed transceiver;

[0009] Among them, the line rate control module is used to control the pre-divider, feedback divider and high-speed transceiver clock divider of the quadruple phase-locked loop by dynamically reconfiguring the port address to achieve the control of the output clock frequency, thereby matching the line rate of the Aurora interface and completing the line rate change.

[0010] Further, the line rate of the port switching is switched by dynamically reconfiguring the port, which specifically includes the following steps:

[0011] Calculate the division coefficients of the pre-divider, feedback divider and high-speed transceiver divider in the quadruple frequency phase-locked loop required for the corresponding line rate;

[0012] Write the frequency division coefficient into the corresponding value in the corresponding register address;

[0013] After completing the modification of the corresponding value in the register address, the sending physical medium adaptation layer is reset;

[0014] After waiting for the transmission rate adaptation to be completed, the transmission physical coding sublayer is reset.

[0015] Furthermore, the clocks supplied to the physical coding sublayer and the physical medium adaptation layer are controlled by controlling the frequency division coefficients of the pre-divider, the feedback divider and the high-speed transceiver divider in the quadruple frequency phase-locked loop.

[0016] Furthermore, the quadruple frequency phase-locked loop in the Quad is used to provide clocks for high-speed transceivers.

[0017] Furthermore, the quadrupled PLL output provides signals for the transmit and receive clock dividers of each high-speed transceiver within the same Quad, and the high-speed transceiver clock dividers control the generation of serial and parallel clocks used by the physical coding sublayer and the physical medium sublayer.

[0018] Furthermore, the quadruple frequency phase-locked loop output provides independent signals for the transmit and receive clock dividers of each high-speed transceiver in the same Quad.

[0019] Furthermore, by dynamically reconfiguring the port switching line rate, the line rate can be changed without re-burning the program.

[0020] Furthermore, the Aurora line rate is determined by the pre-divider, feedback divider of the quadruple phase-locked loop and the clock divider of the high-speed transceiver.

[0021] Furthermore, after dynamically reconfiguring the port, it is necessary to wait for the signal adaptation to be completed and the signal to be pulled low before changing the required transmission or reception line rate.

[0022] Technical Effects

[0023] The present invention provides a line rate safety adaptive negotiation method based on the Aurora protocol, which can realize the line rate adaptive adjustment based on the Aurora protocol. Whenever a load with a different Aurora line rate is switched or a link between a local ground detection device and the load is interrupted due to unstable hardware connection, data transmission is first stopped, and then the clock of the Aurora interface is automatically controlled by dynamically reconfiguring the port to change the line rate of Aurora, thereby reconnecting the link without reconfiguring the FPGA, simplifying the test process of the ground detection device, improving the test efficiency and the versatility of the ground detection device, and stopping data transmission when the link is unstable, thereby improving the reliability of the ground detection device in testing the satellite load flow.

[0024] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a flow chart of a line rate security adaptive negotiation method based on the Aurora protocol according to a preferred embodiment of the present invention;

[0026] Figure 2 It is a line rate control architecture diagram of a line rate security adaptive negotiation method based on the Aurora protocol according to a preferred embodiment of the present invention;

[0027] Figure 3 It is a timing diagram of a rate dynamic reconfiguration of a line rate security adaptive negotiation method based on the Aurora protocol according to a preferred embodiment of the present invention;

[0028] Figure 4It is a simulation result diagram of line rate security adaptive negotiation of a line rate security adaptive negotiation method based on the Aurora protocol according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0030] In the following description, specific details such as specific internal procedures and techniques are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0031] To facilitate understanding of the present invention, the following briefly describes the relevant concepts of the present invention:

[0032] QPLL: The full name of QPLL is Quad Phase-Locked Loop, which is a quadruple frequency phase-locked loop, mainly used for high-speed data transmission and communication.

[0033] FPGA: Field Programmable Gate Array. It is a product further developed on the basis of programmable devices such as PAL, GAL, CPLD, etc. It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0034] like Figure 1 As shown, the embodiment of the present invention provides a line rate safety adaptive negotiation method based on the Aurora protocol. Whenever the line rate of the satellite payload is switched or the link between the local surface detection device and the payload is interrupted due to unstable hardware connection, the data transmission and reception is first stopped, and the Aurora line rate is switched to the highest level by dynamically reconfiguring the port. Then, the channel is reset. If the high-speed transceiver is synchronized successfully and the link is established successfully, data transmission and reception begins. If the high-speed transceiver fails to synchronize within a certain period of time, the Aurora line rate is reduced by one level to wait for the high-speed transceiver to synchronize again. The steps are:

[0035] Step 1: Whenever the line rate of the satellite payload is switched or the link between the local surface detection equipment and the payload is interrupted due to unstable hardware connection, the Aurora line rate is first switched to the highest level by dynamically reconfiguring the port control of the quadruple frequency phase-locked loop's pre-divider, feedback divider, and high-speed transceiver clock divider.

[0036] Step 2: After the Aurora line rate is switched to the highest level, stop sending and receiving data immediately.

[0037] Step 3: After data transmission and reception stops, reset the channel.

[0038] Step 4: After the channel is automatically reset, wait for the high-speed transceiver to synchronize.

[0039] Step 5: If the high-speed transceiver is successfully synchronized, it indicates that the link is successfully established and the process ends; if the high-speed transceiver fails to synchronize within a certain period of time, steps 5-7 are repeated until the high-speed transceiver is successfully synchronized;

[0040] Step 6: If the line rate at this time is the lowest, return to step 1; if the line rate at this time is not the lowest, dynamically reconfigure the port to control the pre-divider, feedback divider and high-speed transceiver clock divider of the quadruple phase-locked loop, and switch the Aurora line rate down one gear.

[0041] Step 7: After the Aurora line rate drops by one level, the channel automatically resets and waits for the high-speed transceiver to synchronize, then returns to step 5 to complete the remaining process.

[0042] The line rate control architecture for realizing the process of switching the line rate to the highest level and reducing the line rate by one level includes a line rate control module, a quadruple frequency phase-locked loop and a high-speed transceiver;

[0043] Among them, the line rate control module is used to control the pre-divider, feedback divider and high-speed transceiver clock divider of the quadruple phase-locked loop by dynamically reconfiguring the port address to achieve the control of the output clock frequency, thereby matching the line rate of the Aurora interface and completing the line rate change.

[0044] Switching line rates by dynamically reconfiguring ports includes the following steps:

[0045] Step 1: Calculate the frequency division coefficients of the pre-divider, feedback divider and high-speed transceiver divider in the quadruple frequency phase-locked loop required for the corresponding line rate.

[0046] Step 2: Write the frequency division coefficient calculated in step 1 into the corresponding value in the corresponding register address.

[0047] Step 3: After completing the modification of the corresponding value in the register address, the sending physical medium adaptation layer is reset.

[0048] Step 4: After waiting for the transmission rate adaptation to be completed, the transmission physical coding sublayer is reset.

[0049] Specifically, a quadruple frequency phase-locked loop in the Quad is used instead of a clock phase-locked loop to provide a clock for the high-speed transceiver;

[0050] The quadrupled PLL output provides signals to the transmit and receive clock dividers of each high-speed transceiver within the same Quad, which control the generation of serial and parallel clocks used by the physical coding sublayer and physical medium sublayer.

[0051] The input clock is divided by a frequency division coefficient before entering the phase detector. The coefficient is controlled by the line rate control module and is selected from 1, 2, 3, and 4.

[0052] The coefficient of the feedback divider determines the multiplication ratio of the voltage-controlled oscillator. The coefficient is controlled by the line rate control module and is selected from 16, 20, 32, 40, 64, 66, 80, and 100.

[0053] From the above, we can get the clock frequency output by the quadruple phase-locked loop, where f Clk_Ref The user clock Qpll_Fb_div is the division coefficient of the feedback divider, QPll_Clk_div is the division coefficient of the pre-divider, and the line rate control module also controls the clock divider in the high-speed transceiver. The control coefficient range is selected from 1, 2, 4, 8, and 16.

[0054] From the above, we can get the clock frequency output by the high-speed transceiver. Where Gt_Div is the division factor of the high-speed transceiver divider.

[0055] Substituting the calculation method of the high-speed transceiver output clock frequency into the clock frequency output by the quadruple phase-locked loop,

[0056] Among them, Qpll_Fb_div is 16 or 20 or 32 or 40 or 64 or 66 or 80 or 100; QPll_Clk_div is 1 or 2 or 3 or 4; Gt_Div is 1 or 2 or 4 or 8 or 16.

[0057] From the above, the values ​​of QPll_Clk_div×Gt_Div are 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, and 64.

[0058] So in the end,

[0059]

[0060] The frequencies of the reference clock and the voltage controlled oscillator feedback clock are compared to determine if frequency lock has been achieved.

[0061] The quadrupling phase-locked loop output provides independent signals for the transmit and receive clock dividers of each high-speed transceiver within the same Quad.

[0062] Both the rising and falling edges of the quadrupled PLL output are used to generate the required line rate.

[0063] The voltage controlled oscillator selected by the quadruple frequency phase-locked loop is a high-frequency voltage controlled oscillator instead of a low-frequency voltage controlled oscillator.

[0064] After configuring the quadrupling phase-locked loop feedback divider coefficient, the quadrupling phase-locked loop pre-divider coefficient, and the clock divider coefficient in the high-speed transceiver through dynamic partial reconfiguration, a dynamic partial reconfiguration write is initiated to the corresponding port address position in the dynamic partial reconfiguration port address table of the GT's channel primitive after a delay of 100 clock cycles.

[0065] Wait for the send rate adaptation completion signal to be pulled low, change the required line rate, and after a delay of 50 clock cycles, determine whether the send physical medium adaptation layer reset completion signal is pulled low. If not, repeat the previous operation.

[0066] If it is determined that the send physical medium adaptation layer reset completion signal has been pulled low, the primitive dynamic reconfiguration port is restored to its original setting before being pulled high, and the send physical coding sublayer is reset after a delay of 1000 clock cycles.

[0067] The serial I / O data of the Aurora channel received by the high-speed transceiver is subjected to channel logic processing after clock recovery, frame synchronization, and serial-to-parallel conversion.

[0068] The clocks given to the physical coding sublayer and the physical medium adaptation layer are controlled by controlling the frequency division coefficients of the pre-divider, feedback divider and high-speed transceiver divider in the quadruple frequency phase-locked loop.

[0069] The quadrupling phase-locked loop in the Quad is used to provide clocks for high-speed transceivers.

[0070] Furthermore, the quadrupled phase-locked loop output provides signals for the transmit and receive clock dividers of each high-speed transceiver in the same Quad, and the high-speed transceiver clock dividers control the generation of serial and parallel clocks used by the physical coding sublayer and the physical medium sublayer. The signals provided by the quadrupled phase-locked loop output for the transmit and receive clock dividers of each high-speed transceiver in the same Quad are independent.

[0071] The line rate can be changed by dynamically reconfiguring the port switching line rate without reprogramming. The Aurora line rate is determined by the pre-divider, feedback divider of the quad-frequency phase-locked loop and the clock divider of the high-speed transceiver.

[0072] After dynamically reconfiguring the port, you need to wait for the signal adaptation completion signal to be pulled low before changing the required transmit or receive line rate.

[0073] The present invention provides a line rate security adaptive negotiation method based on the Aurora protocol. Taking the conversion of a 625M line rate satellite payload to a 1.25G line rate satellite payload as an example, the line rate security adaptive negotiation process includes the following steps:

[0074] The ground detection equipment and the satellite payload are communicating at a line rate of 625M. When the line rate of the satellite payload changes, data transmission is stopped first, and the Aurora line rate is dynamically reconfigured to 10G through dynamic reconfiguration of the port. Then the channel is reset and the high-speed transceiver is waited for synchronization. The failure of high-speed transceiver synchronization leads to link establishment failure. The Aurora line rate is dynamically reconfigured to 5G. The ground detection equipment performs the same operation at a line rate of 5G, and then the port is dynamically reconfigured to 2.5G. After the synchronization fails, the port is dynamically reconfigured to 1.25G. After the channel is reset, the high-speed transceiver is waited for synchronization. After the synchronization is successfully completed, the data is sent. The flowchart of the line rate secure adaptive negotiation method based on the Aurora protocol is shown in the figure. Figure 1 The simulation results of line rate security adaptive negotiation for this example are shown in the figure below. Figure 4 The specific steps of switching line rates by dynamically reconfiguring ports are as follows.

[0075] The line rate control architecture of the line rate security adaptive negotiation method based on the Aurora protocol is shown in the figure below: Figure 2 As shown, first determine the output clock frequency f of the clock chip Clk_Ref Since 156.25M is a common factor of 625M, 1.25G, 2.5G, 5G and 10G line rates, the input clock frequency f is selected Clk_Ref The input clock passes through the QPLL phase detector, charge pump loop filter and high-frequency voltage-controlled oscillator, and then passes through the feedback divider and returns to the phase detector to compare the input clock and the feedback clock of the voltage-controlled oscillator to determine whether the frequency lock has been achieved. The QPLL provides the clock for the high-speed transceiver. The QPLL output provides signals for the TX and RX clock dividers of each high-speed transceiver in the same Quad, controls the generation of serial and parallel clocks used by the physical coding sublayer and the physical medium sublayer, and controls the generation of serial and parallel clocks used by the physical coding sublayer and the physical medium sublayer according to the clock frequency output by the QPLL. and the high-speed transceiver output clock frequency Substituting the calculation method of the high-speed transceiver output clock frequency into the QPLL output clock frequency, we get: Therefore, the coefficient of the feedback divider is selected as 64, the coefficient of the pre-divider is selected as 1, and the coefficient of the clock divider in the high-speed transceiver is selected as 16. At this time, the line rate corresponding to the Aurora interface is 625M.

[0076] When data is transmitted at a 625M line rate, the data is passed to the user transmission interface, and the standard clock compensation module is embedded in the core to control the periodic transmission of the clock compensation character. After that, the data is transmitted to the channel logic module to drive the corresponding high-speed transceiver, process the encoding and decoding of the control characters, and perform error detection CRC. The data is then handed over to the GTX for serial encoding, and then the encoded serial data is sent to the Aurora core at the other end for reception, decoding, and serial-to-parallel conversion.

[0077] A simplified timing diagram of the rate dynamic reconfiguration based on the line rate security adaptive negotiation method of the Aurora protocol is shown in Figure 3 As shown in the figure, after having the feedback divider, pre-divider and clock divider coefficients corresponding to the line rate, it is necessary to configure the line rate by modifying the value of the register through the dynamic partial reconfiguration address, rather than re-burning the program to configure the line rate. After the line rate control module modifies the coefficient of the QPLL feedback divider, after a delay of 100 clock cycles, the dynamic partial reconfiguration write is initiated for the corresponding register space mapping relationship in the address table of the dynamic partial reconfiguration address port of the channel primitive of the GT. Wait for the transmission rate adaptation completion signal to be pulled low, change the required line rate, and after a delay of 50 clock cycles, determine whether the transmission physical media adaptation layer reset completion signal is pulled low. If it is not pulled low, repeat the operation in the previous paragraph. If it is determined that the transmission physical media adaptation layer reset completion signal has been pulled low, restore the original setting of the primitive dynamic partial reconfiguration address before pulling high, and reset the transmission physical coding sublayer after a delay of 1000 clock cycles. At this time, the process of switching from 625M line rate to 1.25G line rate has been completed.

[0078] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A line rate security adaptive negotiation method based on the Aurora protocol, characterized in that: Whenever the line rate of the satellite payload is switched or the link between the local surface detection equipment and the payload is interrupted due to unstable hardware connection, the data transmission and reception is stopped first, and the Aurora line rate is switched to the highest level by dynamically reconfiguring the port. Then the channel is reset. If the high-speed transceiver is synchronized successfully and the link is established successfully, data transmission and reception begins. If the high-speed transceiver fails to synchronize within a certain period of time, the Aurora line rate is reduced by one level and the high-speed transceiver synchronization is waited for again.

2. A line rate security adaptive negotiation method based on the Aurora protocol as claimed in claim 1, characterized in that: A line rate control architecture for realizing the process of switching the line rate to the highest level and reducing the line rate by one level includes a line rate control module, a quadruple frequency phase-locked loop and a high-speed transceiver; The line rate control module is used to control the pre-divider, feedback divider and high-speed transceiver clock divider of the quadruple frequency phase-locked loop by dynamically reconfiguring the port address to achieve the control of the output clock frequency, thereby matching the line rate of the Aurora interface and completing the line rate change.

3. A line rate security adaptive negotiation method based on the Aurora protocol as claimed in claim 2, characterized in that: Switching line rates by dynamically reconfiguring ports includes the following steps: Calculate the division coefficients of the pre-divider, feedback divider, and high-speed transceiver divider in the quadruple frequency phase-locked loop required for the corresponding line rate. Write the calculated frequency division coefficient into the corresponding value in the corresponding register address; After completing the modification of the corresponding value in the register address, the sending physical medium adaptation layer is reset; After waiting for the transmission rate adaptation to be completed, the transmission physical coding sublayer is reset.

4. A line rate security adaptive negotiation method based on the Aurora protocol as claimed in claim 3, characterized in that: The clocks given to the physical coding sublayer and the physical medium adaptation layer are controlled by controlling the frequency division coefficients of the pre-divider, feedback divider and high-speed transceiver divider in the quadruple frequency phase-locked loop.

5. A line rate security adaptive negotiation method based on the Aurora protocol as claimed in claim 2, characterized in that: The quadrupling phase-locked loop in the Quad is used to provide clocks for high-speed transceivers.

6. A line rate security adaptive negotiation method based on the Aurora protocol as claimed in claim 5, characterized in that: The quadrupled PLL output provides signals for the transmit and receive clock dividers of each high-speed transceiver within the same Quad. The high-speed transceiver clock dividers control the generation of serial and parallel clocks used by the physical coding sublayer and the physical medium sublayer.

7. A line rate security adaptive negotiation method based on the Aurora protocol as claimed in claim 6, characterized in that: The quadruple frequency phase-locked loop output provides independent signals for the transmit and receive clock dividers of each high-speed transceiver in the same Quad.

8. A line rate security adaptive negotiation method based on the Aurora protocol as claimed in claim 2, characterized in that: By dynamically reconfiguring the port switching line rate, line rate changes can be achieved without re-programming.

9. A line rate security adaptive negotiation method based on the Aurora protocol as claimed in claim 1, characterized in that: The Aurora line rate is determined by the pre-divider of the quadruple frequency phase-locked loop, the feedback divider and the clock divider of the high-speed transceiver.

10. A line rate security adaptive negotiation method based on the Aurora protocol as claimed in claim 1, characterized in that: After dynamically reconfiguring the port, you need to wait for the signal adaptation completion signal to be pulled low before changing the required transmit or receive line rate.

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