Synchronous circuit

Abstract

The invention provides a synchronization circuit, and relates to the technical field of communication, the synchronization circuit comprises N integration unit circuits, and the target integration unit circuit is used for comparing whether a target symbol value in a received current synchronization sequence is consistent with a preset symbol value of a corresponding bit in a preset weight sequence specified by a protocol; charging or discharging the positive output end of the target integration unit circuit and the negative output end of the target integration unit circuit according to a preset symbol value; and the N integration unit circuits are used for integrating the bias current and comparing the voltage difference between the target positive output end and the target negative output end after the integration is finished so as to determine whether the synchronization succeeds or not. By implementing the technical scheme provided by the invention, the effect of reducing the power consumption of the synchronous circuit is achieved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a synchronization circuit. Background Art

[0002] In the communication system, synchronization is a very important step. In some low-power applications, the receiver needs to decide whether to sleep or receive subsequent signals through synchronization. The principle of synchronization is as follows: when the system receives, it is necessary to ensure that the time to start demodulation is consistent with the time when the transmitter transmits the modulation sequence. Therefore, the transmitter will transmit a synchronization sequence in advance. The sequence consists of a series of symbols (or symbol values). In order to ensure that the synchronization sequence can be correctly received even in the worst transmission environment, the synchronization sequence is generally transmitted using the simplest low level and high level. Each symbol is either high or low. The protocol generally specifies whether each symbol of the synchronization sequence is high or low, and specifies the length of the sequence. Before the demodulation starts, the receiver is always monitoring and sends each received symbol to the synchronization circuit. The synchronization circuit is responsible for comparing whether the received symbol sequence is consistent with the synchronization sequence specified by the protocol. If each symbol is consistent within the sequence length, it means that the synchronization is successful, and the receiver starts the subsequent demodulation circuit and starts demodulation. It can be seen that the synchronization process is actually equivalent to the dot multiplication and accumulation of each bit encoded with 0 and 1. The length of the synchronization sequence is N. Only when the result of the dot multiplication and accumulation is N, it means that the synchronization is successful.

[0003] Since such communication protocols often have very high requirements on power consumption, and most of the time, except for the synchronization circuit, the other parts of the receiver are in sleep mode. Therefore, the synchronization circuit itself generally has very high requirements on power consumption. The synchronization circuit in the related technology often uses digital circuits to implement point multiplication and accumulation operations, and designs the storage unit circuit separately from the point multiplication and accumulation. However, the use of digital circuits to implement point multiplication and addition operations often consumes a lot of power and cannot meet the requirements of low power consumption. Summary of the invention

[0004] In order to solve the above problems, the present application provides a synchronization circuit.

[0005] In a first aspect, the present application provides a synchronization circuit, comprising: N integral unit circuits, wherein each integral unit circuit in the N integral unit circuits is connected in parallel with each other, wherein the positive output terminals of each integral unit circuit are connected together as a target positive output terminal, and the negative output terminals of each integral unit circuit are connected together as a target negative output terminal, and N is a positive integer greater than 1; the target positive output terminal is connected to a common mode voltage through a first switch, the target negative output terminal is connected to the common mode voltage through a second switch, the target positive output terminal is electrically connected to a ground terminal through a first capacitor, and the target negative output terminal is electrically connected to a ground terminal through a second capacitor, wherein the capacitance value of the first capacitor and the capacitance value of the second capacitor are equal; the target integral unit circuit The target integral unit circuit is any one of the N integral unit circuits, the target integral unit circuit includes a target storage unit, a target PMOS tube, a first PMOS tube, a second PMOS tube, a target NMOS tube, a first NMOS tube and a second NMOS tube, the target storage unit is an SRAM including 6 transistors, wherein the positive output end of the target storage unit is electrically connected to the gate of the first PMOS tube and the gate of the first NMOS tube, the drain of the first PMOS tube is electrically connected to the drain of the first NMOS tube and serves as the negative output end of the target integral unit circuit, the negative output end of the target storage unit is electrically connected to the gate of the second PMOS tube and the gate of the second NMOS tube, the second PMOS tube is electrically connected to the gate of the second NMOS tube, and the The drain of the S tube is electrically connected to the drain of the second NMOS tube and serves as the positive output terminal of the target integration unit circuit, the source of the first PMOS tube and the source of the second PMOS tube are both electrically connected to the drain of the target PMOS tube, the source of the target PMOS tube is electrically connected to the power supply terminal, the source of the first NMOS tube and the source of the second NMOS tube are both electrically connected to the drain of the target NMOS tube, and the source of the target NMOS tube is electrically connected to the ground terminal; the gate of the target PMOS tube is electrically connected to the P current mirror bias through the third switch, and the gate of the target NMOS tube is electrically connected to the N current mirror bias through the fourth switch, wherein the P current mirror bias and the N current mirror bias are both bias currents provided by the target current mirror; the target The integration unit circuit is used to compare whether the target symbol value in the received current synchronization sequence is consistent with the preset symbol value of the corresponding bit in the preset weight sequence specified by the protocol, wherein the third switch and the fourth switch are controlled to be closed or opened according to the preset weight sequence; the target PMOS tube and the target NMOS tube are turned on or off according to the preset symbol value, thereby realizing the charging or discharging of the positive output end and the negative output end of the target integration unit circuit; N integration unit circuits are used to integrate the bias current in the process of comparing the current synchronization sequence with the preset weight sequence, and after the integration is completed, compare the voltage difference between the target positive output end and the target negative output end to determine whether the synchronization is successful.

[0006] By adopting the above technical solution, N integral unit circuits are connected in parallel, and each integral unit circuit includes a target storage unit and multiple MOS tubes. These structures enable the circuit to efficiently complete the synchronization operation under low power consumption conditions. The target PMOS tube and the target NMOS tube are turned on or off according to the preset symbol value, so as to realize the charging or discharging of the positive output terminal and the negative output terminal of the target integral unit circuit. This design avoids the high power consumption problem caused by the complex point multiplication and accumulation operations in the traditional digital circuit, and achieves the effect of reducing the power consumption of the synchronization circuit. In addition, by comparing the voltage difference between the target positive output terminal and the target negative output terminal to determine whether the synchronization is successful, the accuracy and reliability of the synchronization judgment are further improved. The synchronization circuit of the present technical solution is implemented by an analog circuit, which not only significantly reduces the power consumption, but also ensures the stability and accuracy of the synchronization process.

[0007] Optionally, the target integration unit circuit also includes: a fifth switch and a sixth switch, the gate of the target PMOS tube is electrically connected to the power supply terminal through the fifth switch, and the gate of the target NMOS tube is electrically connected to the ground terminal through the sixth switch, and the target integration unit circuit is divided into a writing stage and a post-reading integration stage, wherein in the writing stage, the fifth switch and the sixth switch are in a closed state; in the post-reading integration stage, the fifth switch and the sixth switch are in an open state.

[0008] By adopting the above technical solution, when the target integral unit circuit is in the writing stage, the fifth switch and the sixth switch are in the closed state, so that the gate of the target PMOS tube is connected to the power supply terminal, and the gate of the target NMOS tube is connected to the ground terminal, that is, the target PMOS tube and the target NMOS tube are not turned on. At this time, the peripheral circuit of the target storage unit does not affect the update of the storage value of the target storage unit, and the positive output terminal of the target integral unit circuit and the negative output terminal of the target integral unit circuit are both connected to the common mode voltage for reset. When in the post-reading integration stage, the fifth switch and the sixth switch are in the open state, and the target integral unit circuit controls the on and off of the target PMOS tube and the target NMOS tube according to the preset symbol value, so as to realize the charging or discharging of the positive output terminal of the target integral unit circuit and the negative output terminal of the target integral unit circuit.

[0009] Optionally, the above-mentioned synchronization circuit also includes a target comparator, wherein the first positive input terminal of the target comparator is electrically connected to the target positive output terminal, the first negative input terminal of the target comparator is electrically connected to the target negative output terminal, the second positive input terminal of the target comparator is used to access the positive reference voltage, and the second negative input terminal of the target comparator is used to access the negative reference voltage; the target comparator is used to compare the first voltage difference and the second voltage difference and output the comparison result, wherein the first voltage difference is used to represent the voltage difference between the voltage of the target positive output terminal and the voltage of the target negative output terminal, and the second voltage difference is used to represent the voltage difference between the positive reference voltage and the negative reference voltage.

[0010] By adopting the above technical solution, the target comparator can accurately compare the difference between the voltage of the target positive output terminal and the target negative output terminal and the reference voltage, so as to accurately determine whether the synchronization is successful. Specifically, by comparing the first voltage difference and the second voltage difference, the target comparator can output a corresponding synchronization success signal when the receiver receives the correct synchronization sequence, thereby improving the reliability and accuracy of synchronization detection and reducing the misjudgment rate. At the same time, this design enables the synchronization circuit to maintain high performance under low power consumption conditions, meeting the needs of low power consumption applications.

[0011] Optionally, set the positive reference voltage and negative reference voltage according to the following formula: V REFP =VCM + N×I×T / (2C), V REFN =VCM - N×I×T / (2C), where V REFP is the positive reference voltage, V REFN is a negative reference voltage, VCM is a common mode voltage, I is a bias current, T is the duration of the post-reading integration phase, C is the capacitance value of the first capacitor, the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor, and the bias current of the target PMOS tube is equal to the bias current of the target NMOS tube.

[0012] By adopting the above technical solution, the calculation formulas for the positive reference voltage and the negative reference voltage take into account the influence of the common mode voltage VCM, the bias current I, the duration T of the post-reading integration phase, and the capacitance value C of the first capacitor; this setting method ensures that a stable reference voltage can be maintained under different working conditions (such as temperature changes, power supply fluctuations, etc.), thereby improving the reliability and accuracy of the synchronization circuit; the various parameters in the formula can effectively reflect the changes in various physical quantities during the synchronization process, making the synchronization detection more accurate and reducing the possibility of misjudgment; especially in low-power applications, this precise voltage reference setting method helps to further optimize power consumption performance, because the correct voltage setting can reduce unnecessary energy consumption and improve the efficiency of the overall system.

[0013] Optionally, when the comparison result indicates that the first voltage difference is greater than the second voltage difference, it is determined that the synchronization is successful; when the comparison result indicates that the first voltage difference is less than or equal to the second voltage difference, it is determined that the synchronization is unsuccessful.

[0014] By adopting the above technical solution, the target comparator compares the voltage difference between the target positive output terminal and the target negative output terminal, and determines the synchronization result according to the preset conditions. When the first voltage difference is greater than the second voltage difference, it indicates that the symbol value in the synchronization sequence completely matches the preset weight sequence specified by the protocol, and the synchronization is successful; conversely, if the first voltage difference is less than or equal to the second voltage difference, it indicates that at least one symbol value does not match, and the synchronization fails. This design improves the reliability and accuracy of synchronization detection while maintaining low power consumption characteristics.

[0015] Optionally, the target comparator includes: a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, wherein the gate of the third NMOS tube serves as the second negative input terminal of the target comparator, the gate of the fourth NMOS tube serves as the first positive input terminal of the target comparator, the gate of the fifth NMOS tube serves as the second positive input terminal of the target comparator, and the gate of the sixth NMOS tube serves as the first negative input terminal of the target comparator; the drain of the third NMOS tube and the drain of the fourth NMOS tube are both electrically connected to the source of the seventh NMOS tube, and the drain of the seventh NMOS tube is electrically connected to the drain of the third PMOS tube; the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are both electrically connected to the source of the eighth NMOS tube The source of the target comparator is electrically connected to the source of the target comparator, the drain of the eighth NMOS tube is electrically connected to the drain of the fourth PMOS tube; the drain of the fifth PMOS tube is electrically connected to the gate of the seventh NMOS tube and the gate of the fourth PMOS tube, and the drain of the sixth PMOS tube is electrically connected to the gate of the eighth NMOS tube and the gate of the third PMOS tube; the source of the third PMOS tube, the source of the fourth PMOS tube, the source of the fifth PMOS tube and the source of the sixth PMOS tube are all electrically connected to the power supply terminal, the source of the third NMOS tube, the source of the fourth NMOS tube, the source of the fifth NMOS tube and the source of the sixth NMOS tube are all electrically connected to the drain of the ninth NMOS tube, and the source of the ninth NMOS tube is electrically connected to the ground terminal; the gate of the fifth PMOS tube, the gate of the sixth PMOS tube and the gate of the ninth NMOS tube are all electrically connected to the enable terminal; the drain of the sixth PMOS tube serves as the output terminal of the target comparator.

[0016] By adopting the above technical solution, the target comparator can efficiently complete the accurate comparison of the voltage difference between the target positive output terminal and the target negative output terminal. Specifically, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are respectively used as input stages to receive the signals of the target positive output terminal and the target negative output terminal and the positive and negative reference voltage signals. The seventh NMOS tube and the eighth NMOS tube are used as load tubes to form a current mirror structure with the corresponding PMOS tubes to ensure the consistency of the current. The fifth PMOS tube and the sixth PMOS tube are used as feedback control tubes to adjust the voltage of each node so that the entire comparator has a higher gain and fast response characteristics. The ninth NMOS tube is used as an enable switch, which can turn off the circuit when comparison is not required to reduce power consumption. Finally, the drain of the sixth PMOS tube is used as an output terminal to output the comparison result, realizing high-speed synchronous detection under low power consumption.

[0017] Optionally, the target storage unit includes: a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a seventh PMOS tube and an eighth PMOS tube, wherein the drain of the tenth NMOS tube is electrically connected to the drain of the seventh PMOS tube, the gate of the tenth NMOS tube is electrically connected to the gate of the seventh PMOS tube, the drain of the eleventh NMOS tube is electrically connected to the drain of the eighth PMOS tube, the gate of the eleventh NMOS tube is electrically connected to the gate of the eighth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube are both electrically connected to the power supply terminal, and the source of the tenth NMOS tube and the source of the eleventh NMOS tube are both electrically connected to the power supply terminal. The drain of the tenth NMOS tube is also electrically connected to the gate of the eleventh NMOS tube, the drain of the eleventh NMOS tube is also electrically connected to the gate of the tenth NMOS tube, the drain of the tenth NMOS tube is also electrically connected to the drain of the twelfth NMOS tube, the drain of the eleventh NMOS tube is also electrically connected to the drain of the thirteenth NMOS tube, the gate of the twelfth NMOS tube and the gate of the thirteenth NMOS tube are both electrically connected to the target word line, the source of the twelfth NMOS tube serves as the positive output terminal of the target storage unit, the source of the thirteenth NMOS tube serves as the negative output terminal of the target storage unit, and the target word line is used to select the target storage unit for read and write operations.

[0018] By adopting the above technical solution, the target storage unit adopts a six-transistor SRAM structure, which can stably and reliably store one bit of data. Specifically: the tenth NMOS tube, the eleventh NMOS tube, the seventh PMOS tube and the eighth PMOS tube constitute a cross-coupled inverter, and the twelfth NMOS tube and the thirteenth NMOS tube are used as access transistors, which are respectively connected to the target word line, realizing the selective read and write operation of the storage unit, and improving the flexibility and controllability of the circuit. This design not only reduces power consumption, but also improves the overall performance and reliability of the synchronous circuit.

[0019] Optionally, when the preset symbol value is 1, the target PMOS tube is turned off and the target NMOS tube is turned on; when the preset symbol value is 0, the target PMOS tube is turned on and the target NMOS tube is turned off.

[0020] By adopting the above technical solution, when the preset symbol value is 1, the target PMOS tube is turned off and the target NMOS tube is turned on. At this time, the negative output end of the target storage unit is electrically connected to the ground end through the target NMOS tube, so that the negative output end of the target integral unit circuit is discharged; when the preset symbol value is 0, the target PMOS tube is turned on and the target NMOS tube is turned off. At this time, the positive output end of the target storage unit is electrically connected to the power supply end through the target PMOS tube, so that the positive output end of the target integral unit circuit is charged. This design can accurately control the charging and discharging process of the target integral unit circuit, ensuring that the symbol value in the current synchronization sequence is accurately compared and integrated within each symbol cycle, thereby improving the accuracy of synchronization detection. At the same time, by using analog circuits instead of digital circuits to realize point multiplication and accumulation operations, power consumption is greatly reduced to meet the needs of low-power applications. The design of this target integral unit circuit provides higher flexibility, and can flexibly control the charging or discharging behavior of the circuit according to different preset symbol values. Accurate charging and discharging control helps to improve the accuracy of the synchronization circuit and reduce synchronization errors.

[0021] Optionally, the above synchronization circuit also includes: a weight rotation update circuit, which is used to update only one SRAM value in each symbol period of receiving the current synchronization sequence and shift the weight sequence by one bit.

[0022] By adopting the above technical solution, the weight rotation update circuit can update only one SRAM value in each symbol period and shift the weight sequence by one bit. This enables the synchronization circuit to dynamically adjust the preset weight sequence to ensure accurate comparison every time a new synchronization symbol is received, thereby improving the flexibility and accuracy of synchronization detection. At the same time, this method further reduces power consumption and meets the requirements of low-power design.

[0023] Optionally, the weight rotation update circuit includes: multiple registers for storing each symbol value in the weight sequence; and a shift controller for controlling data transfer between the multiple registers to implement a shift operation within each symbol period.

[0024] By adopting the above technical solution, multiple registers are used to store the symbol values ​​in the weight sequence, ensuring that the data of each symbol period is fully prepared and avoiding data loss or error; the displacement controller realizes the displacement operation in each symbol period, so that the weight sequence can be updated at the appropriate time point, ensuring the accuracy and timeliness of the synchronization process; this design method avoids frequent full-volume update operations and significantly reduces the energy consumption of the circuit, especially in low-power application scenarios. This technical solution can achieve the update of only one SRAM value in each symbol period and shift the weight sequence by one bit, which not only simplifies the hardware design and reduces the circuit complexity, but also effectively reduces power consumption and improves the overall efficiency and reliability of the system.

[0025] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages: 1. The synchronization circuit of this technical solution is implemented by an analog circuit, which not only significantly reduces power consumption but also ensures the stability and accuracy of the synchronization process; 2. The setting of reference voltage can effectively reflect the changes of various physical quantities during the synchronization process, making synchronization detection more accurate and reducing the possibility of misjudgment; especially in low-power applications, this precise voltage reference setting method helps to further optimize power consumption performance, because the correct voltage setting can reduce unnecessary energy consumption and improve the efficiency of the overall system; 3. The design of this target integration unit circuit provides higher flexibility and can flexibly control the charging or discharging behavior of the circuit according to different preset symbol values. Precise charging and discharging control helps to improve the accuracy of the synchronization circuit and reduce synchronization errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the overall structure of a synchronization circuit provided in an embodiment of the present application; Figure 2 is a schematic diagram of an integration unit circuit provided in an embodiment of the present application; Figure 3 is a schematic diagram of a target comparator provided in an embodiment of the present application; Figure 4 is an internal circuit structure diagram of a target comparator provided in an embodiment of the present application; Figure 5 is a circuit structure diagram of a six-transistor SRAM provided in an embodiment of the present application; Figure 6 This is an example diagram of an N-tube current bias and a P-tube current bias provided in an embodiment of the present application; Figure 7 This is a schematic diagram of a weight rotation update circuit provided in an embodiment of the present application.

[0027] Description of reference numerals: S1-first switch, S2-second switch, S3-third switch, S4-fourth switch, S5-fifth switch, S6-sixth switch, N0-target NMOS tube, N1-first NMOS tube, N2-second NMOS tube, N3-third NMOS tube, N4-fourth NMOS tube, N5-fifth NMOS tube, N6-sixth NMOS tube, N7-seventh NMOS tube, N8-eighth NMOS tube, N9-ninth NMOS tube, N10-tenth NMOS tube, N11- The eleventh NMOS tube, N12-the twelfth NMOS tube, N13-the thirteenth NMOS tube, N14-the fourteenth NMOS tube, N15-the fifteenth NMOS tube, P0-the target PMOS tube, P1-the first PMOS tube, P2-the second PMOS tube, P3-the third PMOS tube, P4-the fourth PMOS tube, P5-the fifth PMOS tube, P6-the sixth PMOS tube, P7-the seventh PMOS tube, P8-the eighth PMOS tube, C1-the first capacitor, C2-the second capacitor. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0029] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0030] In the description of the embodiments of the present application, the term "plurality" means two or more. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0031] The following is combined with Figure 1-Figure 7 The embodiments of the present application are described.

[0032] The present application provides a synchronization circuit, such as Figure 1 As shown, Figure 1 : is a schematic diagram of the overall structure of a synchronization circuit provided by an embodiment of the present application, the synchronization circuit comprising: N integration unit circuits, each of the N integration unit circuits is connected in parallel with each other, wherein the positive output terminals of each integration unit circuit are connected together as a target positive output terminal, and the negative output terminals of each integration unit circuit are connected together as a target negative output terminal, and N is a positive integer greater than 2; the target positive output terminal is connected to a common mode voltage through a first switch S1, the target negative output terminal is connected to a common mode voltage through a second switch S2, the target positive output terminal is electrically connected to a ground terminal through a first capacitor C1, and the target negative output terminal is electrically connected to a ground terminal through a second capacitor C2, wherein the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 are equal; the target integration unit circuit is any integration unit circuit among the N integration unit circuits, such as Figure 2As shown, the target integration unit circuit includes a target storage unit, a target PMOS tube P0, a first PMOS tube P1, a second PMOS tube P2, a target NMOS tube N0, a first NMOS tube N1 and a second NMOS tube N2. The target storage unit is an SRAM including 6 transistors, wherein the positive output terminal of the target storage unit is electrically connected to the gate of the first PMOS tube P1 and the gate of the first NMOS tube N1, and the drain of the first PMOS tube P1 is electrically connected to the drain of the first NMOS tube N1 and serves as the target integration unit circuit. The negative output end of the target storage unit is electrically connected to the gate of the second PMOS tube P2 and the gate of the second NMOS tube N2. The drain of the second PMOS tube P2 is electrically connected to the drain of the second NMOS tube N2 and serves as the positive output end of the target integration unit circuit. The source of the first PMOS tube P1 and the source of the second PMOS tube P2 are electrically connected to the drain of the target PMOS tube P0. The source of the target PMOS tube P0 is electrically connected to the power supply terminal. The source of the first NMOS tube N1 and the source of the second NMOS tube N2 are electrically connected to the target The drain of the NMOS tube N0 is electrically connected, and the source of the target NMOS tube N0 is electrically connected to the ground terminal; the gate of the target PMOS tube P0 is electrically connected to the P current mirror bias through the third switch S3, and the gate of the target NMOS tube N0 is electrically connected to the N current mirror bias through the fourth switch S4, wherein the P current mirror bias and the N current mirror bias are bias currents provided by the target current mirror; the target integration unit circuit is used to compare whether the target symbol value in the received current synchronization sequence is consistent with the preset symbol value of the corresponding bit in the preset weight sequence specified in the protocol, wherein the third switch S3 and the fourth switch S4 are controlled to be closed or opened according to the preset weight sequence; the target PMOS tube P0 and the target NMOS tube N0 are turned on or off according to the preset symbol value, thereby realizing the charging or discharging of the positive output end of the target integration unit circuit and the negative output end of the target integration unit circuit; the N integration unit circuits are used to integrate the bias current in the process of comparing the current synchronization sequence with the preset weight sequence, and after the integration is completed, compare the voltage difference between the target positive output end and the target negative output end to determine whether the synchronization is successful.

[0033] In the above embodiment, N integral unit circuits are connected in parallel, and each integral unit circuit includes a target storage unit and a plurality of MOS tubes. These structures enable the circuit to efficiently complete the synchronization operation under low power consumption conditions. The target PMOS tube P0 and the target NMOS tube N0 are turned on or off according to the preset symbol value, so as to realize the charging or discharging of the positive output terminal and the negative output terminal of the target integral unit circuit. This design avoids the high power consumption problem caused by the complex point multiplication and accumulation operations in the traditional digital circuit. In addition, by comparing the voltage difference between the target positive output terminal and the target negative output terminal to determine whether the synchronization is successful, the accuracy and reliability of the synchronization judgment are further improved. The synchronization circuit of this embodiment is implemented by an analog circuit, which not only significantly reduces the power consumption, but also ensures the stability and accuracy of the synchronization process.

[0034] The synchronization circuit of this embodiment is composed of N integration unit circuits, which are connected in parallel. Each integration unit circuit has a positive output terminal and a negative output terminal, which are respectively connected to a target positive output terminal and a target negative output terminal; the target positive output terminal and the target negative output terminal are respectively connected to the ground terminal through equal value capacitors to maintain voltage balance. Each integration unit circuit includes a target storage unit (or can be called an SRAM storage unit) for storing bit data. Figure 2 Where Q1 represents the positive output terminal of the target storage unit, Q1N represents the negative output terminal of the target storage unit, and the positive and negative output terminals of the target storage unit are respectively connected to the gate of the PMOS tube (such as Figure 2 The gates of P1 and P2 in the figure) and the gates of NMOS tubes (such as Figure 2 The gates of N1 and N2 in the circuit are connected to each other, and bias current is provided to the target PMOS tube P0 and the target NMOS tube N0 through the P current mirror bias and the N current mirror bias. The P current mirror bias and the N current mirror bias are both bias currents provided by the target current mirrors. The target PMOS tube P0 and the target NMOS tube N0 are controlled to be turned on or off according to the preset symbol value, so as to realize charging or discharging of the positive output terminal and the negative output terminal of the integration unit circuit. The N integration unit circuits integrate the bias current. After the integration, the voltage difference between the target positive output terminal and the target negative output terminal is compared, so as to judge whether the symbol value in the current synchronization sequence is consistent with the preset symbol value in the preset weight sequence, and then determine whether the synchronization is successful.

[0035] The current synchronization sequence includes N symbol values. The synchronization circuit of this embodiment is composed of N integral unit circuits connected in parallel, and each integral unit is responsible for processing a symbol value in the synchronization sequence. In each integral unit, the target PMOS tube P0 or the target NMOS tube N0 is selectively turned on according to whether the received symbol value (high level or low level) is consistent with the preset symbol value of the corresponding bit in the preset weight sequence to charge or discharge the positive output terminal or the negative output terminal. When all symbol values ​​are processed, the entire circuit will compare the voltage difference between the target positive output terminal and the target negative output terminal. If the voltage difference reaches a certain threshold, it means that all symbols are matched successfully, that is, synchronization is achieved. The synchronization process in the related art usually relies on digital circuits to perform complex calculations, such as point multiplication and accumulation. These operations are not ideal for power-sensitive application scenarios because they consume more energy. The synchronization circuit in this embodiment uses an analog integration method instead of a digital logic operation, thereby greatly reducing power consumption, and is particularly suitable for wireless communication devices with strict power consumption restrictions; at the same time, since no complex digital processing steps are required, the synchronization judgment can be completed faster, which helps to improve the response speed of the overall communication system.

[0036] In an optional embodiment, if Figure 2 As shown, the target integration unit circuit also includes: a fifth switch S5 and a sixth switch S6, the gate of the target PMOS tube P0 is electrically connected to the power supply terminal through the fifth switch S5, and the gate of the target NMOS tube N0 is electrically connected to the ground terminal through the sixth switch, and the target integration unit circuit is divided into a writing stage and a post-reading integration stage, wherein, in the writing stage, the fifth switch and the sixth switch are in a closed state; in the post-reading integration stage, the fifth switch and the sixth switch are in an open state.

[0037] In the above embodiment, when the target integration unit circuit is in the writing stage, the fifth switch and the sixth switch are in the closed state, so that the gate of the target PMOS tube P0 is connected to the power supply terminal, and the gate of the target NMOS tube N0 is connected to the ground terminal, that is, the target PMOS tube P0 and the target NMOS tube N0 are both not turned on, which is equivalent to zeroing. At this time, the peripheral circuit of the target storage unit does not affect the update of the storage value of the target storage unit, and the positive output terminal of the target integration unit circuit and the negative output terminal of the target integration unit circuit are both connected to the common mode voltage for reset. When in the post-reading integration stage, the fifth switch S5 and the sixth switch S6 are in the open state, and the target integration unit circuit controls the on and off of the target PMOS tube P0 and the target NMOS tube N0 according to the preset symbol value, so as to realize the charging or discharging of the positive output terminal of the target integration unit circuit and the negative output terminal of the target integration unit circuit.

[0038] The integration unit circuit is divided into two stages, a writing stage and a post-reading integration stage. The writing stage and the post-reading integration stage of the target integration unit circuit are controlled by introducing the fifth switch and the sixth switch. Specifically, in the writing stage, the fifth switch and the sixth switch are closed, allowing data to be written to the target storage unit (or called SRAM storage unit) in the target integration unit circuit. In the post-reading integration stage, the fifth switch and the sixth switch are disconnected, and data integration processing begins. At this time, the states of the third switch and the fourth switch are controlled according to the preset symbol value in the preset weight sequence, thereby determining whether the target PMOS tube P0 and the target NMOS tube N0 are turned on or off, thereby realizing charging or discharging of the corresponding output terminals.

[0039] In an optional embodiment, the synchronization circuit further includes a target comparator, such as Figure 3 As shown, the first positive input terminal of the target comparator is electrically connected to the target positive output terminal, the first negative input terminal of the target comparator is electrically connected to the target negative output terminal, the second positive input terminal of the target comparator is used to access the positive reference voltage, and the second negative input terminal of the target comparator is used to access the negative reference voltage; the target comparator is used to compare the first voltage difference and the second voltage difference and output a comparison result, wherein the first voltage difference is used to represent the voltage difference between the voltage of the target positive output terminal and the voltage of the target negative output terminal, and the second voltage difference is used to represent the voltage difference between the positive reference voltage and the negative reference voltage.

[0040] The target comparator of this embodiment is a four-input comparator, wherein the first positive input terminal of the target comparator is electrically connected to the target positive output terminal (i.e., the positive output terminal of the N integral unit circuits), and the first negative input terminal of the target comparator is electrically connected to the target negative output terminal, that is, the first positive input terminal and the first negative input terminal of the target comparator are respectively connected to the ground terminal through the first capacitor and the second capacitor, and the target comparator can accurately compare the difference between the voltage of the target positive output terminal and the target negative output terminal and the reference voltage (including the positive reference voltage and the negative reference voltage), so as to accurately determine whether the synchronization is successful. Specifically, the target comparator can output a corresponding synchronization success signal when the receiver receives the correct synchronization sequence by comparing the first voltage difference and the second voltage difference, thereby improving the reliability and accuracy of synchronization detection and reducing the misjudgment rate. At the same time, this design enables the synchronization circuit to maintain high performance under low power consumption conditions, meeting the needs of low power consumption applications.

[0041] After each integration unit completes the matching process of the received symbol value with the preset symbol value, the target positive output terminal and the target negative output terminal of the entire synchronization circuit will accumulate corresponding charges to form two output voltages. A target comparator is added to the synchronization circuit to compare the voltage difference between the target positive output terminal and the target negative output terminal. The first positive input terminal of the target comparator is connected to the target positive output terminal, the first negative input terminal is connected to the target negative output terminal, the second positive input terminal is connected to the positive reference voltage, and the second negative input terminal is connected to the negative reference voltage. The target comparator compares the first voltage difference and the second voltage difference. According to the comparison result, the target comparator outputs a signal whether the synchronization is successful. By accurately comparing the voltage difference, the target comparator can more accurately determine whether the synchronization is successful, thereby improving the reliability of synchronization.

[0042] In an optional embodiment, the positive reference voltage and the negative reference voltage are set according to the following formula: V REFP =VCM +N×I×T / (2C), V REFN =VCM - N×I×T / (2C), where V REFP is the positive reference voltage, V REFN is a negative reference voltage, VCM is a common mode voltage, I is a bias current, T is the duration of the post-reading integration phase, C is the capacitance value of the first capacitor C1, the capacitance value of the first capacitor C1 is equal to the capacitance value of the second capacitor C2, and the bias current of the target PMOS tube P0 is equal to the bias current of the target NMOS tube N0.

[0043] In the above embodiment, the calculation formulas for the positive reference voltage and the negative reference voltage take into account the influence of the common mode voltage VCM, the bias current I, the duration T of the post-reading integration phase, and the capacitance value of the first capacitor C; this setting method ensures that a stable reference voltage can be maintained under different working conditions (such as temperature changes, power supply fluctuations, etc.), thereby improving the reliability and accuracy of the synchronization circuit; the various parameters in the formula can effectively reflect the changes in various physical quantities during the synchronization process, making the synchronization detection more accurate and reducing the possibility of misjudgment; especially in low-power applications, this precise voltage reference setting method helps to further optimize power consumption performance, because the correct voltage setting can reduce unnecessary energy consumption and improve the efficiency of the overall system.

[0044] In this embodiment, the synchronization circuit sets the positive reference voltage (V REFP ) and a negative reference voltage (V REFN), in order to achieve accurate voltage comparison, thereby improving the accuracy of synchronization judgment. By accurately calculating and setting the reference voltage, it is possible to more accurately judge whether the synchronization is successful, thereby improving the reliability of synchronization. The formula can dynamically adjust the reference voltage according to different working conditions (such as current value, duration and capacitance value), so that the synchronization circuit can adapt to different working environments; accurate voltage comparison can reduce unnecessary power consumption, especially in low-power communication systems, this design helps to further reduce power consumption. The dynamically adjusted reference voltage can better match the characteristics of the received signal, improve the accuracy and reliability of synchronization detection, especially in low signal-to-noise ratio environments; by associating the reference voltage with the key parameters of the integration process, the system can offset the impact of external interference to a certain extent and maintain stable synchronization performance.

[0045] In an optional embodiment, when the comparison result indicates that the first voltage difference is greater than the second voltage difference, it is determined that the synchronization is successful; when the comparison result indicates that the first voltage difference is less than or equal to the second voltage difference, it is determined that the synchronization is unsuccessful.

[0046] In the above embodiment, the target comparator compares the voltage difference between the target positive output terminal and the target negative output terminal, and determines the synchronization result according to the preset conditions. When the first voltage difference is greater than the second voltage difference, it indicates that the symbol value in the synchronization sequence completely matches the preset weight sequence specified by the protocol, and the synchronization is successful; conversely, if the first voltage difference is less than or equal to the second voltage difference, it indicates that at least one symbol value does not match, and the synchronization fails. This design improves the reliability and accuracy of synchronization detection while maintaining low power consumption characteristics.

[0047] The target comparator in this embodiment is used to compare two voltage differences, namely the first voltage difference and the second voltage difference. If the comparison result shows that the first voltage difference is greater than the second voltage difference, the synchronization is determined to be successful; if the first voltage difference is less than or equal to the second voltage difference, the synchronization is determined to be unsuccessful. By judging the synchronization state through a clear voltage difference comparison result, the accuracy of synchronization judgment is improved, especially in complex environments; by comparing the two voltage differences, noise interference can be effectively filtered out and the anti-interference ability of the synchronization circuit can be enhanced. By introducing a clear voltage difference comparison condition, it is ensured that the synchronization is successful only when the received synchronization sequence fully complies with the preset mode, reducing the risk of misjudgment; this embodiment provides a simple synchronization success judgment logic, simplifies the design and implementation of the synchronization circuit, and by directly comparing the size of the voltage difference, the logic of synchronization judgment can be simplified, reducing the complexity and design cost of the circuit.

[0048] In an optional embodiment, if Figure 4As shown, the target comparator includes: a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a ninth NMOS tube N9, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5 and a sixth PMOS tube P6, wherein the gate of the third NMOS tube N3 serves as the second negative input terminal of the target comparator, the gate of the fourth NMOS tube N4 serves as the first positive input terminal of the target comparator, the gate of the fifth NMOS tube N5 serves as the second positive input terminal of the target comparator, and the gate of the sixth NMOS tube N6 serves as the first negative input terminal of the target comparator; the drain of the third NMOS tube N3 and the drain of the fourth NMOS tube N4 are both electrically connected to the source of the seventh NMOS tube N7, and the drain of the seventh NMOS tube N7 is electrically connected to the drain of the third PMOS tube P0; the drain of the fifth NMOS tube N5 and the drain of the sixth NMOS tube N6 are both electrically connected to the source of the eighth NMOS tube N8. The source of the eighth NMOS tube N8 is electrically connected to the drain of the fourth PMOS tube P4; the drain of the fifth PMOS tube P5 is electrically connected to the gate of the seventh NMOS tube N7 and the gate of the fourth PMOS tube P4, the drain of the sixth PMOS tube P6 is electrically connected to the gate of the eighth NMOS tube N8 and the gate of the third PMOS tube P3; the source of the third PMOS tube P3, the source of the fourth PMOS tube P4, the source of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6 are electrically connected to the gate of the eighth NMOS tube N8 and the gate of the third PMOS tube P3; the source of the third PMOS tube P3, the source of the fourth PMOS tube P4, the source of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6 The sources are all electrically connected to the power supply terminal, the source of the third NMOS tube N3, the source of the fourth NMOS tube N4, the source of the fifth NMOS tube N5 and the source of the sixth NMOS tube N6 are all electrically connected to the drain of the ninth NMOS tube N9, and the source of the ninth NMOS tube N9 is electrically connected to the ground terminal; the gate of the fifth PMOS tube P5, the gate of the sixth PMOS tube P6 and the gate of the ninth NMOS tube N9 are all electrically connected to the enable terminal; the drain of the sixth PMOS tube P6 serves as the output terminal of the target comparator.

[0049] In the above embodiment, if Figure 4As shown, EN is the enable terminal, VIP is the first positive input terminal, which is used to access the voltage of the aforementioned target positive output terminal, and VIN is the first negative input terminal, which is used to access the voltage of the aforementioned target negative output terminal. The target comparator can efficiently complete the accurate comparison of the voltage difference between the target positive output terminal and the target negative output terminal. Specifically, the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5 and the sixth NMOS tube N6 are respectively used as input stages to receive signals from the target positive output terminal and the target negative output terminal as well as positive and negative reference voltage signals. The seventh NMOS tube N7 and the eighth NMOS tube N8 are used as load tubes to form a current mirror structure with the corresponding PMOS tubes to ensure the consistency of the current. The fifth PMOS tube P5 and the sixth PMOS tube P6 are used as feedback control tubes to adjust the voltage of each node so that the entire comparator has a higher gain and fast response characteristics. The ninth NMOS tube N9 is used as an enable switch, which can turn off the circuit when comparison is not required to reduce power consumption. Finally, the drain of the sixth PMOS tube P6 is used as the output terminal, as shown in Figure 4 The VOP in the output compares the result, achieving high-speed synchronous detection with low power consumption.

[0050] The target comparator is composed of a plurality of NMOS transistors (the third NMOS transistor N3 to the ninth NMOS transistor N9) and PMOS transistors (the third PMOS transistor P3 to the sixth PMOS transistor P6), the gates of these transistors are respectively connected to the input terminal and the reference voltage terminal of the target comparator, the gate of the third NMOS transistor N3 is used as the second negative input terminal, the gate of the fourth NMOS transistor N4 is used as the first positive input terminal, the gate of the fifth NMOS transistor N5 is used as the second positive input terminal, the gate of the sixth NMOS transistor N6 is used as the first negative input terminal, the drains of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to the source of the seventh NMOS transistor N7, and the drains of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are connected to the source of the eighth NMOS transistor N8. These NMOS transistors form a differential pair with the corresponding PMOS transistors (such as the third PMOS transistor P3 and the fourth PMOS transistor P4) for comparing voltage differences, the drain of the sixth PMOS transistor P6 is used as the output terminal of the target comparator, and the synchronization state is output according to the comparison result of the differential pair. The differential pair design can respond quickly to voltage changes, improving the response speed of the synchronous circuit. The differential pair design helps to reduce noise interference and enhance the circuit's anti-interference ability in complex electromagnetic environments.

[0051] In an optional embodiment, if Figure 5As shown, the target storage unit includes: a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a thirteenth NMOS tube N13, a seventh PMOS tube P7 and an eighth PMOS tube P8, wherein the drain of the tenth NMOS tube N10 is electrically connected to the drain of the seventh PMOS tube P7, the gate of the tenth NMOS tube N10 is electrically connected to the gate of the seventh PMOS tube P7, the drain of the eleventh NMOS tube N11 is electrically connected to the drain of the eighth PMOS tube P8, the gate of the eleventh NMOS tube N11 is electrically connected to the gate of the eighth PMOS tube P8, the source of the seventh PMOS tube P7 and the source of the eighth PMOS tube P8 are both electrically connected to the power supply terminal, the source of the tenth NMOS tube N10 is electrically connected to the eleventh NMOS tube N11, and the gate of the eleventh NMOS tube N11 is electrically connected to the gate of the eighth PMOS tube P8. The sources of the transistors N11 are all electrically connected to the ground terminal; the drain of the tenth NMOS transistor N10 is also electrically connected to the gate of the eleventh NMOS transistor N11, the drain of the eleventh NMOS transistor N11 is also electrically connected to the gate of the tenth NMOS transistor N10, the drain of the tenth NMOS transistor N10 is also electrically connected to the drain of the twelfth NMOS transistor N12, the drain of the eleventh NMOS transistor N11 is also electrically connected to the drain of the thirteenth NMOS transistor N13, the gate of the twelfth NMOS transistor N12 and the gate of the thirteenth NMOS transistor N13 are both electrically connected to the target word line, the source of the twelfth NMOS tube serves as the positive output terminal of the target storage unit, the source of the thirteenth NMOS tube serves as the negative output terminal of the target storage unit, and the target word line is used to select the target storage unit for read and write operations.

[0052] In the above embodiment, if Figure 5 As shown, VDD is the power supply terminal, WL is the target word line, which is used to select the target storage unit. The target storage unit adopts a six-transistor SRAM structure, which can stably and reliably store one bit of data. Specifically: the tenth NMOS tube N10, the eleventh NMOS tube N11, the seventh PMOS tube P7 and the eighth PMOS tube P8 constitute a cross-coupled inverter, and the twelfth NMOS tube N12 and the thirteenth NMOS tube N13 are used as access transistors, which are respectively connected to the target word line, realizing the selective read and write operation of the storage unit, and improving the flexibility and controllability of the circuit. This design not only reduces power consumption, but also improves the overall performance and reliability of the synchronous circuit.

[0053] The target memory cell is a key circuit component for storing data and allowing read and write operations through specific control signals (such as target word lines). In this implementation, the target memory cell adopts a cross-reverse NMOS and PMOS structure to form a cross-coupled inverter, that is, the seventh PMOS tube P7 and the tenth NMOS tube N10 form an inverter, and the eighth PMOS tube P8 and the eleventh NMOS tube N11 form another inverter. The two inverters are connected to each other to form a bistable circuit, which can store one bit of data (0 or 1); in order to realize the data reading and writing operations of the memory cell, the twelfth NMOS tube N12 and the thirteenth NMOS tube N13 are introduced as access transistors, and their gates are connected to the target word line (Word Line). When the word line is activated, the external circuit is allowed to access the data in the memory cell; the source of the twelfth NMOS tube N12 is used as a positive output terminal for reading the stored high-level data, and the source of the thirteenth NMOS tube N13 is used as a negative output terminal for reading the stored low-level data. The word line is activated only when a read or write operation is required, and is disconnected the rest of the time, reducing static power consumption. This circuit helps improve the stability of the memory cell and reduce changes in the storage state caused by factors such as component non-ideality, noise, and temperature drift.

[0054] In an optional embodiment, when the preset symbol value is 1, the target PMOS tube P0 is turned off and the target NMOS tube N0 is turned on; when the preset symbol value is 0, the target PMOS tube P0 is turned on and the target NMOS tube N0 is turned off.

[0055] In the above embodiment, when the preset symbol value is 1, the target PMOS tube P0 is turned off and the target NMOS tube N0 is turned on. At this time, the negative output end of the target storage unit is electrically connected to the ground end through the target NMOS tube N0, so that the negative output end of the target integral unit circuit is discharged; when the preset symbol value is 0, the target PMOS tube P0 is turned on and the target NMOS tube N0 is turned off. At this time, the positive output end of the target storage unit is electrically connected to the power supply end through the target PMOS tube P0, so that the positive output end of the target integral unit circuit is charged. This design can accurately control the charging and discharging process of the target integral unit circuit, ensuring that the symbol value in the current synchronization sequence is accurately compared and integrated within each symbol cycle, thereby improving the accuracy of synchronization detection. At the same time, by using analog circuits instead of digital circuits to realize point multiplication and accumulation operations, power consumption is greatly reduced, meeting the needs of low-power applications. The design of this target integral unit circuit provides higher flexibility, and can flexibly control the charging or discharging behavior of the circuit according to different preset symbol values. Accurate charging and discharging control helps to improve the accuracy of the synchronization circuit and reduce synchronization errors.

[0056] In this embodiment, the conduction states of the target PMOS tube P0 and the target NMOS tube N0 will change accordingly according to different preset symbol values. For example, when the preset symbol value is 1, the target PMOS tube P0 is cut off (non-conductive), and the target NMOS tube N0 is turned on (allowing current to flow). When the preset symbol value is 0, the target PMOS tube P0 is turned on, and the target NMOS tube N0 is cut off. This control mechanism enables the positive output end of the target integral unit circuit to be discharged through the target NMOS tube N0 when the preset symbol value is 1; and when the preset symbol value is 0, the positive output end can be charged through the target PMOS tube P0. By accurately controlling the conduction states of the target PMOS tube P0 and the target NMOS tube N0 according to the preset symbol value, unnecessary power consumption can be reduced, especially in low-power communication systems; by utilizing the complementary characteristics of PMOS and NMOS, the change of the preset symbol value can be quickly responded to, and the response speed of the synchronization circuit can be improved.

[0057] In an optional embodiment, the synchronization circuit further includes: a weight rotation update circuit, which is used to update only one SRAM value in each symbol period of receiving the current synchronization sequence and shift the weight sequence by one bit.

[0058] In the above embodiment, the weight rotation update circuit can update only one SRAM value in each symbol period and shift the weight sequence by one position. This enables the synchronization circuit to dynamically adjust the preset weight sequence to ensure accurate comparison every time a new synchronization symbol is received, thereby improving the flexibility and accuracy of synchronization detection. At the same time, this method further reduces power consumption and meets the requirements of low-power design.

[0059] If updating multiple SRAM values ​​at the same time may require more computing resources and power consumption, this embodiment may help reduce resource consumption and power consumption by reducing the number of SRAMs updated each time. The weight rotation update circuit ensures that when each synchronization sequence symbol is received, only the single SRAM unit corresponding to the symbol is updated, which means that only one preset symbol value will be changed each time; with the arrival of each symbol cycle, the weight sequence will move one position to one side so that the next symbol can be correctly matched with the updated weight sequence; by updating a single SRAM unit cycle by cycle and shifting the weight sequence, the data integrity and accuracy in the synchronization process are ensured, and the possibility of misjudgment is reduced; by shifting the weight sequence, the influence of external noise can be offset to a certain extent, and the accuracy of synchronization judgment can be maintained. This embodiment simplifies the update process of the weight sequence by updating only one SRAM value, improves the update efficiency, reduces the number of SRAMs updated each time, and helps to reduce the consumption of computing resources and power consumption; through the displacement operation of the weight sequence, the adaptability of the weight sequence to changes in the received signal is enhanced; this embodiment provides a flexible weight update mechanism, and the update strategy and weight sequence can be adjusted as needed to adapt to different application scenarios and requirements.

[0060] In an optional embodiment, the weight rotation update circuit includes: a plurality of registers for storing each symbol value in the weight sequence; a shift controller for controlling data transfer between the plurality of registers to implement a shift operation within each symbol period.

[0061] In the above embodiment, multiple registers are used to store the symbol values ​​in the weight sequence, ensuring that the data of each symbol period is fully prepared and avoiding data loss or error; the displacement controller implements the displacement operation in each symbol period, so that the weight sequence can be updated at the appropriate time point, ensuring the accuracy and timeliness of the synchronization process; this design method avoids frequent full-volume update operations and significantly reduces the energy consumption of the circuit, especially in low-power application scenarios. This embodiment can achieve the update of only one SRAM value in each symbol period and shift the weight sequence by one bit, which not only simplifies the hardware design and reduces the circuit complexity, but also effectively reduces power consumption and improves the overall efficiency and reliability of the system.

[0062] The weight rotation update circuit of this embodiment includes multiple registers, which are used to store the values ​​of each symbol in the weight sequence. These registers can maintain and update the weight values ​​and provide the necessary weight data for the synchronization circuit; the displacement controller is responsible for controlling the data transfer between the multiple registers to realize the displacement operation within each symbol period, which means that at the beginning of each new symbol period, the weight sequence will be shifted to the left or right by one bit according to the instruction of the displacement controller to update the weight value in the SRAM. The weight rotation update circuit can ensure that only one SRAM value is updated in each symbol period, which can improve the efficiency of weight update and reduce unnecessary calculations and data processing; the weight update mechanism implemented by the displacement controller can reduce the power consumption of the circuit and simplify the circuit design, because it is not necessary to update all weight values ​​at the same time, thereby reducing the load of the circuit; accurate weight update and displacement operation help to improve the accuracy of the synchronization circuit in processing the synchronization sequence, thereby improving the performance of the entire communication system.

[0063] It should be noted that the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application will be described in detail below in conjunction with specific embodiments.

[0064] An embodiment of the present application provides a synchronization circuit implemented by an analog method.

[0065] First, the basic unit of this synchronous circuit is modified from a 6-transistor SRAM. Figure 5 A 6-transistor SRAM (corresponding to the target storage cell mentioned above) is shown, which can be seen to consist of two pairs of cross-coupled inverters (such as Figure 5 P7, P8, N10 and N11) form LATCH, and then two NMOS tubes (such as Figure 5 N12 and N13 in the middle form a write circuit. SRAM is divided into three working states, storage state, read state and write state. In the storage state, WL (corresponding to the aforementioned target word line) is low, and the connection between LATCH and INP and INN is disconnected. As long as the power is on, the SRAM recording result can be saved all the time. In the read state, INP and INN are pre-charged to half of the power supply, and then WL is high. INP and INN redistribute charge according to the storage result of SRAM. The voltage of the node connected to the high-level output of SRAM remains unchanged, while the voltage of the node connected to the low-level output of SRAM is reduced due to charge redistribution. The voltage difference is amplified by the sensitive amplifier, thereby achieving the purpose of reading the SRAM result. In the write state, INP and INN are driven by the previous stage circuit, high level and low level respectively, and WL is high. Since the previous stage drive is stronger, the state of SRAM can be changed to achieve the purpose of modifying the SRAM recording result.

[0066] The SRAM can be improved to obtain an integration unit circuit (corresponding to the aforementioned target integration unit circuit). By connecting these integration units in parallel, the synchronization function can be realized. Figure 2 , whose core is a 6T SRAM (i.e. Figure 2 The target storage unit in the SRAM is stored in the SRAM. The integration circuit is divided into two stages: the writing stage and the post-reading integration stage. In the writing stage, the principle is the same as that described before. The system selects the correct SRAM for update through WL. The difference is that at this time, the P-tube current mirror and N-tube current mirror of each unit are connected to the zeroing terminal and are not turned on. Therefore, the circuits around the SRAM do not affect the update of the SRAM storage value. At this time, the positive and negative outputs of the integration unit circuit are connected to the common mode voltage VCM for reset.

[0067] The key to the system lies in the post-reading integration stage. In this stage, the switches from the target PMOS tube P0 and the target NMOS tube N0 to the bias (including the aforementioned third switch S3 and fourth switch S4) are controlled by the weight output. The weight value is equal to the value of the symbol corresponding to one bit in the synchronization sequence specified by the protocol. If the symbol value is 1, the target NMOS tube N0 is turned on. At this time, there are two situations: the SRAM value is 1, then according to Figure 2 , SRAM output Q1 is 1, the discharge path from the negative output to the target NMOS tube N0 is turned on, and the negative output terminal discharges down through a rated current; SRAM is 0, then according to Figure 2 , the target NMOS tube N0 is turned on, but the SRAM output Q1N is 1, the discharge path of the positive output to the target NMOS tube N0 is turned on, and the positive output end is discharged down through a rated current.

[0068] If the symbol value is 0, the target NMOS tube N0 is turned on. There are two cases: the SRAM value is 1, then according to Figure 2 , SRAM output Q1N is 0, the charging path from the positive output to the target PMOS tube P0 is turned on, and the positive output terminal is charged up by a rated current; SRAM is 0, then according to Figure 2 , the target PMOS tube P0 is turned on, but the SRAM output Q1 is 0, the charging path from the negative output to the target PMOS tube P0 is turned on, and the negative output terminal is charged and increased by a rated current. Figure 2 The target NMOS tube N0 and the target PMOS tube P0 in the embodiment are provided with bias current by current mirrors, such as Figure 2 The N current mirror bias and P current mirror bias in the specific current mirror circuit are as follows: Figure 6 shown.

[0069] To sum up, if the weight value and the value recorded in SRAM are the same, the positive terminal voltage minus the negative terminal voltage increases during the integration stage; if the weight value and the value recorded in SRAM are different, the positive terminal voltage minus the negative terminal voltage decreases during the integration stage.

[0070] Figure 1 For the synchronization circuit implemented in parallel, assuming that the length of the synchronization sequence is N, the synchronization circuit is composed of N integral unit circuits, and each unit is responsible for comparing the corresponding bit weight with the received symbol. Assuming that the N-tube current mirror and the P-tube current mirror current of each unit are consistent, assuming that the positive and negative outputs are each connected to the same capacitor C (corresponding to Figure 1 The first capacitor C1 and the second capacitor C2). At the end of the integration phase, the voltage difference between the positive and negative terminals is (AB)×I×T / C. A is the number of cells with the same weight as the received symbol, and B is the number of cells with different weights than the received symbol. It is assumed here that the capacitor is large enough so that charging and discharging will not cause saturation of the circuit. I is the current of the P-tube current mirror and the N-tube current mirror, and T is the duration of the integration phase. It should be noted that in order to ensure the correctness of the result, the current of the P-tube current mirror and the N-tube current mirror must be the same, so you can use Figure 6 The current replication circuit in ensures that the two current mirror currents are the same, such as Figure 6 The current mirror circuit is composed of the fourteenth NMOS tube N14, the fifteenth NMOS tube N15 and the reference power supply. Figure 6 The P current mirror bias and N current mirror bias in Figure 2 correspond.

[0071] In order to finally determine whether the output of the parallel synchronous circuit meets the synchronization conditions, it is necessary Figure 3 The four-input comparator in the circuit is used for comparison. The comparator has two positive inputs and two negative inputs as inputs. Assume that the two positive input voltages are VP1 (corresponding to the voltage of the aforementioned target positive output terminal) and VP2 (corresponding to the aforementioned positive reference voltage), and the two negative input voltages are VN1 (corresponding to the voltage of the aforementioned target negative output terminal) and VN2 (corresponding to the aforementioned negative reference voltage). VP1=V OUTP , VP2=V REFP , VN1=V OUTN , VN2=V REFN , then the comparator is at (V OUTP -V OUTN )-(V REFP -V REFN )>0, the output is high. That is, when the voltage difference between the positive and negative terminals is greater than the difference between the positive reference and the negative reference, it is judged as 1. The positive reference voltage can be set to VCM+N×I*T / 2C, and the negative reference voltage can be set to VCM-N×I*T / 2C. When V OUTP-V OUTN Greater than or equal to V REFP -V REFN When , it means that the integral output is greater than or equal to N×I*T / C. According to the previous analysis, each symbol in the synchronization sequence is equal to the value specified by the protocol, and the synchronization is successful. Of course, there are non-ideal factors such as mismatch, noise, and interference in the actual circuit, and V REFP -V REFN It is set to be slightly smaller than N×I*T / C to cover the effects of noise, mismatch, and interference. Of course, the difference between the two cannot be too large, otherwise it will cause system missynchronization, and the system will wake up for demodulation at an inappropriate time, wasting power consumption.

[0072] Figure 4 This is a method for implementing a 4-input comparator. Two inputs are added to the classic dual-input comparator to achieve (V OUTP -V OUTN )-(V REF PV REFN ) function.

[0073] It should be noted that the operation of SRAM is a relatively power-consuming process. The corresponding WL needs to be selected as high, and the corresponding drive circuit needs to be connected to the positive and negative output terminals of the SRAM. If the results stored in N SRAMs need to be updated every time synchronization is performed, it will consume a lot of power. In order to reduce the power consumption of updating SRAM, only one SRAM can be updated at a time, and the weights can be rotated and shifted. Figure 7 The weight rotation update circuit diagram, also known as the weight shift operation circuit, is a circuit consisting of N D flip-flops (such as Figure 7 The shift register is composed of DFF1~DFFN in the SRAM, and only one bit is shifted in each symbol cycle. For example, in the first cycle, the SRAM stores 1 to N symbol results, and the weight sequence also stores the synchronization sequence specified by the 1 to N bit protocol. In the second cycle, the Nth storage unit in the SRAM is replaced by the latest received symbol, and the weight sequence is shifted by one bit. The original first weight is transferred to the second, the second to the third, and so on. The Nth is transferred to the original first position.

[0074] In subsequent operations, the weight is shifted by one bit in each cycle, and the SRAM updates the Nth bit, the N-1th bit, the N-2th bit in sequence until it is updated to the first bit. Then the next cycle is started. This ensures that only one SRAM value is updated each time, reducing power consumption.

[0075] A low-power synchronization circuit implemented by analogy is proposed in the embodiment of the present application. By relying on this circuit, the power consumption of logical operations caused by point multiplication and addition operations in the digital synchronization circuit is avoided. The synchronization operation is realized only by integration, which simplifies the circuit implementation and reduces power consumption.

[0076] It should be noted that: when the device provided in the above embodiment realizes its function, only the division of the above functional modules is used as an example. In actual application, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0077] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0078] The above is only an exemplary embodiment of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification, those skilled in the art will easily think of other embodiments of the present disclosure.

[0079] This application is intended to cover any modifications, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field not recorded in the present disclosure.

Claims

1. A synchronous circuit, characterized in that: include: N integration unit circuits, wherein each of the N integration unit circuits is connected in parallel with each other, wherein the positive output terminals of each of the integration unit circuits are connected together as a target positive output terminal, and the negative output terminals of each of the integration unit circuits are connected together as a target negative output terminal, and N is a positive integer greater than 1; The target positive output terminal is connected to a common mode voltage through a first switch, the target negative output terminal is connected to the common mode voltage through a second switch, the target positive output terminal is electrically connected to a ground terminal through a first capacitor, and the target negative output terminal is electrically connected to the ground terminal through a second capacitor, wherein the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor; The target integration unit circuit is any one of the N integration unit circuits, and the target integration unit circuit includes a target storage unit, a target PMOS transistor, a first PMOS transistor, a second PMOS transistor, a target NMOS transistor, a first NMOS transistor, and a second NMOS transistor. The target storage unit is an SRAM including six transistors, wherein: The positive output terminal of the target storage unit is electrically connected to the gate of the first PMOS tube and the gate of the first NMOS tube, the drain of the first PMOS tube is electrically connected to the drain of the first NMOS tube and serves as the negative output terminal of the target integration unit circuit, the negative output terminal of the target storage unit is electrically connected to the gate of the second PMOS tube and the gate of the second NMOS tube, the drain of the second PMOS tube is electrically connected to the drain of the second NMOS tube and serves as the positive output terminal of the target integration unit circuit, the source of the first PMOS tube and the source of the second PMOS tube are electrically connected to the drain of the target PMOS tube, the source of the target PMOS tube is electrically connected to the power supply terminal, the source of the first NMOS tube and the source of the second NMOS tube are electrically connected to the drain of the target NMOS tube, and the source of the target NMOS tube is electrically connected to the ground terminal; The gate of the target PMOS tube is electrically connected to the P current mirror bias through a third switch, and the gate of the target NMOS tube is electrically connected to the N current mirror bias through a fourth switch, wherein the P current mirror bias and the N current mirror bias are both bias currents provided by the target current mirror; The target integration unit circuit is used to compare whether the target symbol value in the received current synchronization sequence is consistent with the preset symbol value of the corresponding bit in the preset weight sequence specified in the protocol, wherein the third switch and the fourth switch are controlled to be closed or opened according to the preset weight sequence; The target PMOS transistor and the target NMOS transistor are turned on or off according to the preset sign value, so as to realize charging or discharging of the positive output end of the target integration unit circuit and the negative output end of the target integration unit circuit; The N integration unit circuits are used to integrate the bias current during the comparison between the current synchronization sequence and the preset weight sequence, and after the integration, compare the voltage difference between the target positive output terminal and the target negative output terminal to determine whether the synchronization is successful.

2. The synchronization circuit according to claim 1, characterized in that: The target integration unit circuit further includes: a fifth switch and a sixth switch, the gate of the target PMOS tube is electrically connected to the power supply terminal through the fifth switch, and the gate of the target NMOS tube is electrically connected to the ground terminal through the sixth switch, and the target integration unit circuit is divided into a writing stage and a post-reading integration stage, wherein: In the writing phase, the fifth switch and the sixth switch are in a closed state; in the post-reading integration phase, the fifth switch and the sixth switch are in an open state.

3. The synchronization circuit according to claim 1, characterized in that: The synchronization circuit further includes a target comparator, wherein a first positive input terminal of the target comparator is electrically connected to the target positive output terminal, a first negative input terminal of the target comparator is electrically connected to the target negative output terminal, a second positive input terminal of the target comparator is used to access a positive reference voltage, and a second negative input terminal of the target comparator is used to access a negative reference voltage; The target comparator is used to compare a first voltage difference and a second voltage difference and output a comparison result, wherein the first voltage difference is used to represent the voltage difference between the voltage of the target positive output terminal and the voltage of the target negative output terminal, and the second voltage difference is used to represent the voltage difference between the positive reference voltage and the negative reference voltage.

4. The synchronization circuit according to claim 3, characterized in that: The positive reference voltage and the negative reference voltage are set according to the following formula: In REFP =VCM + N×I×T / (2C), V REFN =VCM - N×I×T / (2C), Among them, V REFP is the positive reference voltage, V REFN is the negative reference voltage, VCM is the common mode voltage, I is the bias current, T is the duration of the post-reading integration phase, C is the capacitance value of the first capacitor, and the bias current of the target PMOS tube is equal to the bias current of the target NMOS tube.

5. The synchronization circuit according to claim 3, characterized in that: When the comparison result indicates that the first voltage difference is greater than the second voltage difference, it is determined that the synchronization is successful; when the comparison result indicates that the first voltage difference is less than or equal to the second voltage difference, it is determined that the synchronization is unsuccessful.

6. The synchronization circuit according to claim 3, characterized in that: The target comparator includes: a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, wherein: The gate of the third NMOS tube serves as the second negative input terminal of the target comparator, the gate of the fourth NMOS tube serves as the first positive input terminal of the target comparator, the gate of the fifth NMOS tube serves as the second positive input terminal of the target comparator, and the gate of the sixth NMOS tube serves as the first negative input terminal of the target comparator; The drain of the third NMOS tube and the drain of the fourth NMOS tube are both electrically connected to the source of the seventh NMOS tube, and the drain of the seventh NMOS tube is electrically connected to the drain of the third PMOS tube; the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are both electrically connected to the source of the eighth NMOS tube, and the drain of the eighth NMOS tube is electrically connected to the drain of the fourth PMOS tube; the drain of the fifth PMOS tube is both electrically connected to the gate of the seventh NMOS tube and the gate of the fourth PMOS tube, and the drain of the sixth PMOS tube is both electrically connected to the gate of the eighth NMOS tube and the gate of the third PMOS tube; The source of the third PMOS tube, the source of the fourth PMOS tube, the source of the fifth PMOS tube and the source of the sixth PMOS tube are all electrically connected to the power supply end, the source of the third NMOS tube, the source of the fourth NMOS tube, the source of the fifth NMOS tube and the source of the sixth NMOS tube are all electrically connected to the drain of the ninth NMOS tube, and the source of the ninth NMOS tube is electrically connected to the ground end; the gate of the fifth PMOS tube, the gate of the sixth PMOS tube and the gate of the ninth NMOS tube are all electrically connected to the enable end; the drain of the sixth PMOS tube serves as the output end of the target comparator.

7. The synchronization circuit according to claim 1, characterized in that: The target storage unit includes: a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a seventh PMOS tube and an eighth PMOS tube, wherein: The drain of the tenth NMOS tube is electrically connected to the drain of the seventh PMOS tube, the gate of the tenth NMOS tube is electrically connected to the gate of the seventh PMOS tube, the drain of the eleventh NMOS tube is electrically connected to the drain of the eighth PMOS tube, the gate of the eleventh NMOS tube is electrically connected to the gate of the eighth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube are both electrically connected to the power supply terminal, and the source of the tenth NMOS tube and the source of the eleventh NMOS tube are both electrically connected to the ground terminal; The drain of the tenth NMOS tube is also electrically connected to the gate of the eleventh NMOS tube, the drain of the eleventh NMOS tube is also electrically connected to the gate of the tenth NMOS tube, the drain of the tenth NMOS tube is also electrically connected to the drain of the twelfth NMOS tube, the drain of the eleventh NMOS tube is also electrically connected to the drain of the thirteenth NMOS tube, the gate of the twelfth NMOS tube and the gate of the thirteenth NMOS tube are both electrically connected to the target word line, the source of the twelfth NMOS tube serves as the positive output end of the target storage unit, the source of the thirteenth NMOS tube serves as the negative output end of the target storage unit, and the target word line is used to select the read and write operations on the target storage unit.

8. The synchronization circuit according to claim 1, characterized in that: When the preset symbol value is 1, the target PMOS tube is turned off and the target NMOS tube is turned on; when the preset symbol value is 0, the target PMOS tube is turned on and the target NMOS tube is turned off.

9. The synchronization circuit according to claim 1, characterized in that: The synchronization circuit also includes: a weight rotation update circuit, which is used to update only one SRAM value in each symbol period of receiving the current synchronization sequence and shift the weight sequence by one bit.

10. The synchronization circuit according to claim 9, characterized in that: The weight rotation update circuit comprises: A plurality of registers, for storing each symbol value in the weight sequence; The shift controller is used to control the data transfer between the multiple registers to realize the shift operation in each symbol period.

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