Chip verification system and method

Abstract

The invention provides a chip verification system and method, and relates to the technical field of high-performance computing, in particular to a chip verification system which comprises a test case module, an AXI bus function model, an AXI bus monitor, an APB bus function model, an APB bus monitor, a CPU and a to-be-tested design module. Wherein format conversion of transmission data is realized based on an AXI bus function model and an APB bus function model of a VMM verification framework, high management control efficiency of a to-be-tested design module is realized, read-write response or read-write request information sent by the to-be-tested design module is processed in real time, an RDMA network card chip can be fully verified, and the reliability of the RDMA network card chip is improved. A verification platform is provided for application of the RDMA network card chip in multiple scenes in the high-performance computing field, the development period of the RDMA network card chip is shortened, and the verification efficiency of the RDMA network card chip is improved.

Description

Technical Field

[0001] The present application relates to the field of high performance computing technology, and in particular to a chip verification system and method. Background Art

[0002] In the era of rapid development of information technology, the demand for high-performance networks in the fields of high-performance computing (HPC), big data processing and distributed storage is gradually emerging. When processing large amounts of data, the traditional TCP / IP protocol stack requires multi-layer processing, which has high CPU (Central Processing Unit) and memory overhead. In addition, due to its own multiple memory copy characteristics, it cannot meet the needs of high-speed networks. Therefore, RDMA (Remote Direct Memory Access) technology has been introduced in data center networks. RDMA technology enables remote computers to communicate over the network by bypassing the kernel and using zero copy. The high bandwidth and low latency of RDMA can better meet the needs of future data center network bandwidth. The network interface controller that implements the RDMA protocol is called an RDMA network card chip. In order to reduce the development risk, it is very important to conduct hardware and software co-verification based on FPGA prototypes before the RDMA network card chip is taped out.

[0003] In the prior art, there are two methods for verifying chips: the verification platform of Synopsys's high-performance ASIC (HighPperformance ASIC System) series and EDA (Electronic Design Automationr) simulation. For RDMA network card chips, large amounts of random data verification are very important. However, traditional EDA simulation takes a long time to verify large amounts of data, and is highly complex, so EDA simulation cannot meet the verification requirements of RDMA network card chips. Moreover, the above-mentioned technical methods for verifying chips, the solutions focus on simulating circuit behavior, do not have the flexibility of simulation architecture, and when processing large amounts of data and multiple test scenarios, the implementation complexity is high, making it difficult to verify complex chip designs, and cannot meet the high efficiency requirements of simulation verification of RDMA network card chips.

[0004] Therefore, how to improve the verification efficiency of RDMA network card chips is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] To solve the above technical problems, the present application provides a chip verification system that can improve the verification efficiency of RDMA network card chips. The present application also provides a chip verification method that has the same technical effect.

[0006] The first objective of the present application is to provide a chip verification system.

[0007] The above-mentioned application objective 1 of the present application is achieved through the following technical solutions: A chip verification system is applied to an RDMA network card chip. The system is implemented based on a VMM verification framework. The system includes: a test case module, an AXI bus function model, an AXI bus monitor, an APB bus function model, an APB bus monitor, a CPU and a design module to be tested; the test case module is connected to the CPU, and the CPU is also respectively connected to the AXI bus function model, the AXI bus monitor, the APB bus function model and the APB bus monitor; the design module to be tested is respectively connected to the AXI bus function model and the AXI bus monitor through the AXI bus; the design module to be tested is also respectively connected to the APB bus function model and the APB bus monitor through the APB bus, wherein: The test case module is used to obtain configuration data of the verification task and send the configuration data to the CPU; The CPU is used to encapsulate the configuration data into transaction-level data, and send the transaction-level data to the AXI bus function model and the APB bus function model respectively; The AXI bus functional model is used to convert the transaction-level data into a first interface timing signal according to the AXI protocol, and send the first interface timing signal to the design module to be tested to drive the design module to be tested to output a first interface response signal according to the first interface timing signal; The APB bus function model is used to convert the transaction-level data into a second interface timing signal according to the APB protocol, and send the second interface timing signal to the design module to be tested to drive the design module to be tested to output a second interface response signal according to the second interface timing signal; The AXI bus monitor is used to convert the first interface response signal into a first message transaction according to the AXI protocol, and output the first message transaction; The APB bus monitor is used to convert the second interface response signal into a second message transaction according to the APB protocol, and output the second message transaction.

[0008] Preferably, in the chip verification system, the CPU is further used to detect whether the configuration data is valid and obtain a detection result; Correspondingly, when executing the step of encapsulating the configuration data into transaction-level data, the CPU is specifically configured to: when the detection result indicates that the configuration data is valid, encapsulate the configuration data into transaction-level data.

[0009] Preferably, in the chip verification system, the CPU is also used to monitor the number of send queue elements sent by the AXI bus functional model and the number of work queue elements received by the AXI bus monitor, and when the number of send queue elements is equal to the number of work queue elements, the simulation process is controlled to end.

[0010] Preferably, the chip verification system further comprises a generator, wherein: The generator is connected to the APB bus function model and the AXI bus function model respectively; The generator is used to generate randomized transaction data that meets preset constraints according to the configuration data through a randomization method, and send the randomized transaction data to the APB bus functional model and the AXI bus functional model.

[0011] Preferably, in the chip verification system, the APB bus function model is also used to obtain configuration data of the XGMAC core, and start the design module to be tested according to the configuration data of the XGMAC core.

[0012] The second objective of the present application is to provide a chip verification method.

[0013] The second application objective of the present application is achieved through the following technical solutions: A chip verification method is applied to an RDMA network card chip. The method is implemented based on the above chip verification system, wherein the system is implemented based on a VMM verification framework. The system includes: a test case module, an AXI bus function model, an AXI bus monitor, an APB bus function model, an APB bus monitor, a CPU and a design module to be tested; the test case module is connected to the CPU, and the CPU is also respectively connected to the AXI bus function model, the AXI bus monitor, the APB bus function model and the APB bus monitor; the design module to be tested is respectively connected to the AXI bus function model and the AXI bus monitor through the AXI bus; the design module to be tested is also respectively connected to the APB bus function model and the APB bus monitor through the APB bus. The method includes: Using the test case module, obtaining configuration data of the verification task, and sending the configuration data to the CPU; Using the CPU, encapsulating the configuration data into transaction-level data, and sending the transaction-level data to the AXI bus function model and the APB bus function model respectively; Using the AXI bus functional model, according to the AXI protocol, converting the transaction-level data into a first interface timing signal, and sending the first interface timing signal to the design module to be tested, so as to drive the design module to be tested, and outputting a first interface response signal according to the first interface timing signal; Using the APB bus function model, according to the APB protocol, converting the transaction-level data into a second interface timing signal, and sending the second interface timing signal to the design module to be tested to drive the design module to be tested, and outputting a second interface response signal according to the second interface timing signal; Using the AXI bus monitor, according to the AXI protocol, converting the first interface response signal into a first message transaction, and outputting the first message transaction; The APB bus monitor is used to convert the second interface response signal into a second message transaction according to the APB protocol, and the second message transaction is output.

[0014] Preferably, the chip verification method further includes: Using the CPU, detecting whether the configuration data is valid, and obtaining a detection result; Correspondingly, the utilizing the CPU to encapsulate the configuration data into transaction-level data specifically includes: when the detection result is that the configuration data is valid, utilizing the CPU to encapsulate the configuration data into transaction-level data.

[0015] Preferably, the chip verification method further includes: The CPU is used to monitor the number of send queue elements sent by the AXI bus functional model and the number of work queue elements received by the AXI bus monitor, and when the number of send queue elements is equal to the number of work queue elements, the simulation process is controlled to end.

[0016] Preferably, the chip verification method further includes: The APB bus function model is used to obtain the configuration data of the XGMAC core, and the design module to be tested is started according to the configuration data of the XGMAC core.

[0017] Preferably, the chip verification method further includes: The APB bus monitor is used to determine whether the read and write operations of the design module to be tested are successful according to the second interface response signal.

[0018] The above technical solution particularly relates to a chip verification system, which is applied to RDMA network card chips, including: a test case module, an AXI bus function model, an AXI bus monitor, an APB bus function model, an APB bus monitor, a CPU and a design module to be tested; wherein, the AXI bus function model and the APB bus function model based on the VMM verification framework realize the format conversion of the transmitted data, realize the high management and control efficiency of the design module to be tested, and through real-time processing of the read-write response or read-write request information sent by the design module to be tested, the RDMA network card chip can be more fully verified, providing a verification platform for the application of RDMA network card chips in multiple scenarios in the field of high-performance computing, and shortening the development cycle of RDMA network card chips. Compared with the traditional EDA simulation method, the above technical solution has low complexity and fast verification speed, and can improve the verification efficiency of RDMA network card chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 This is a schematic diagram of the structure of the VMM verification framework in the embodiment of the present application; Figure 2 This is a schematic diagram of the structure of a chip verification system in an embodiment of the present application; Figure 3 The figure is a flowchart of a chip verification method in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] In the embodiments provided in the present application, it should be understood that the disclosed methods and systems can be implemented in other ways. The system embodiments described below are merely schematic. For example, the division of units and modules is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or modules can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0023] In addition, all functional units in the embodiments of the present application may be integrated into one processor, or each unit may be a separate device, or two or more units may be integrated into one device; each functional unit in the embodiments of the present application may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0024] A person skilled in the art can understand that all or part of the steps of the following method embodiments can be completed by program instructions and related hardware. The aforementioned program instructions can be stored in a computer-readable storage medium. When the program instructions are executed, the steps of the following method embodiments are executed; and the aforementioned storage medium includes: a mobile storage device, a read-only memory (ROM), a magnetic disk or an optical disk, and other media that can store program codes.

[0025] It should be understood that the use of "system", "device", "unit" and / or "module" in this application is only a method for distinguishing different components, elements, parts, parts or assemblies at different levels. However, if other words can achieve the same purpose, the word can be replaced by other expressions.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" and "several" mean two or more, unless otherwise clearly and specifically defined.

[0027] If a flow chart is used in the present application, the flow chart is used to illustrate the operations performed by the system according to the embodiment of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, each step can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or a certain step or several steps of operations can be removed from these processes.

[0028] It should also be noted that, in this article, terms such as "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such articles or devices. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0029] The embodiments of the present application are written in a progressive manner.

[0030] The embodiment of the present application provides a chip verification system, which is applied to an RDMA network card chip and is used to verify the functional correctness of the RDMA network card chip design so as to timely discover defects in the RDMA network card chip design.

[0031] The above chip verification system is implemented based on the VMM (Verification Methodology Manual) verification framework; VMM verification framework is a verification methodology based on SystemVerilog language launched by Synopsys, which aims to improve the efficiency and quality of design verification. It has the advantages of fast verification speed and more comprehensive verification. Its universal and flexible structure enables it to be reused in multiple different projects, and accurate simulation is obtained by simulating the actual working environment of the chip.

[0032] like Figure 1 As shown in the figure, the core components of the VMM verification framework include TC (Test Case), TH (Test Harness), ENV (Environment), SUBENV (Sub-Environment), BFM (Bus Function Model), MONITOR, GENERATOR, RM (Reference Model), SCOREBOARD and DUT (Design Under Test).

[0033] Among them, DUT is the target object of verification, which is a module or the entire system in the hardware design. In the VMM verification methodology, DUT is usually a complex integrated circuit or system, which needs to undergo rigorous verification to ensure that its functions and performance meet the design requirements. DUT is deployed between BFM and MONITOR. It refers to the hardware design system that needs to be verified. DUT integrates multiple functional modules, such as the message encapsulation and parsing module based on the RoCEv2 protocol, the sending queue cache module, the receiving queue cache module, the completion queue cache module, the congestion control module and the flow control module.

[0034] TC is the basic unit in the verification process. It defines the specific test behavior of the DUT. Each test case usually focuses on verifying a specific aspect or a set of characteristics of the DUT. The test case implements stimuli based on operations such as RDMA Write, RDMA Read, and RDMA Send, and checks whether the behavior of the DUT meets expectations. It is used to verify the specified test scenario. In the VMM verification framework, a test case usually contains a series of transactions or operations that are sent to the DUT to verify whether its functions meet expectations.

[0035] TH contains all the logic required to execute the test, including instantiating the DUT, instantiating and connecting the interface system bus, etc. It is the bridge between the test case and the verification environment.

[0036] ENV represents the entire verification platform, and the environment layer defines the set of resources required to execute the test, such as bus functional models, monitors, etc. The environment provides the necessary context information for the test, allowing users to adjust verification parameters as needed.

[0037] SUBENV is a subset of the verification environment ENV, which is used to represent a more fine-grained functional area and to encapsulate and manage the verification logic of a specific function or module. SUBENV can decompose a complex environment into several sub-environments, making the verification environment more modular and easier to manage and maintain.

[0038] BFM simulates the bus behavior in the DUT. It is responsible for converting transaction-level stimulus to signal-level stimulus and passing it to the DUT. In addition, it is responsible for converting the response of the design under test from signal level back to transaction level for further analysis and inspection by the verification environment.

[0039] MONITOR is responsible for monitoring the output results of the DUT interface and converting the signal-level data output by the DUT into transaction-level data of the VMM verification environment, so as to further analyze the behavior of the DUT or serve as basic data for coverage collection.

[0040] GENERATOR is responsible for generating randomized transactions, which are the basis for verifying the DUT. It generates various possible input stimuli according to predefined constraints to cover various operation modes of the DUT. By generating diverse input stimuli, it ensures that the verification process can fully cover the design space of the DUT and discover potential design problems.

[0041] RM is used to generate expected output results. It calculates the expected response according to the design specifications of the DUT based on the input stimulus. RM can be implemented in SystemVerilog or other programming languages, usually based on transaction level modeling (TLM). The output of RM is used as a benchmark to verify the functional correctness of the DUT and is compared with the actual output of the DUT.

[0042] SCOREBOARD is used to compare the actual output of the DUT with the expected output of the RM. It records the execution of all transactions, counts the number of successful and failed transactions, and reports the verification results. SCOREBOARD verifies that the DUT functions correctly by comparing the actual results with the expected results. It is also responsible for recording the execution of transactions and providing detailed information about the verification process.

[0043] like Figure 2 As shown, the chip verification system comprises: a test case module 1, a CPU 2, an AXI bus function model 3, an AXI bus monitor 4, an APB bus function model 5, an APB bus monitor 6 and a design module to be tested 7; the test case module 1 is connected to the CPU 2, and the CPU 2 is also connected to the AXI bus function model 3, the AXI bus monitor 4, the APB bus function model 5 and the APB bus monitor 6 respectively; the design module to be tested 7 is respectively connected to the AXI bus function model 3 and the AXI bus monitor 4 via the AXI bus; the design module to be tested 7 is also respectively connected to the APB bus function model 5 and the APB bus monitor 6 via the APB bus; Specifically, the above-mentioned chip verification system uses the test case module 1 as the TC test case component in the VMM verification framework, which is connected to the ENV verification environment component through the TH test framework component. The subset SUBENV sub-verification environment of the ENV verification environment component is composed of an AXI bus function model 3, an AXI bus monitor 4, an APB bus function model 5, an APB bus monitor 6 and a CPU 2, and the design module to be tested 7 is the target object of verification.

[0044] Test case module 1, used to obtain configuration data of the verification task and send the configuration data to CPU2; Specifically, the configuration data can be pre-set data based on a specific verification task, and the obtained configuration data can be passed to CPU2 through the ENV verification environment component and the SUBENV sub-verification environment. For the verification of the RDMA network card chip, the configuration data that the test case module 1 needs to obtain includes but is not limited to: CQC (Completion Queue Context), SMAC (Source MAC Address), SGID (Subnet Group Identifier), QPC (Queue Pair Context), MRC (Memory Region Context), SQE (Send Queue Element) and RQE (Receive Queue Element), and its detailed information is shown in the following table: Table 1 Detailed information of configuration data

[0045] CPU2 is used to encapsulate the configuration data into transaction-level data, and send the transaction-level data to the AXI bus function model 3 and the APB bus function model 5 respectively; Specifically, CPU2 encapsulates the configuration data into transaction-level data according to the data format specified by the software and hardware, and then passes it to the AXI bus function model 3 and the APB bus function model 5.

[0046] In some embodiments, CPU2 is also used to detect whether the configuration data is valid and obtain a detection result; accordingly, when CPU2 executes the encapsulation of the configuration data into transaction-level data, it is specifically used to: when the detection result is that the configuration data is valid, encapsulate the configuration data into transaction-level data.

[0047] Specifically, CPU2 detects whether the configuration data, mask and operation type provided by the test case module 1 are valid, and obtains the corresponding test result. For example, the theoretical configuration data length is 32 bytes. If the configuration data length is less than 32 bytes, it is invalid configuration data. The numerical value of the operation type is 0~7. If the operation type provided by the test case module 1 is not within the range of 0~7, it is an invalid operation type. If the test result is that the configuration data is valid, the configuration data is encapsulated as transaction-level data, and the present application is not limited to this.

[0048] The AXI bus function model 3 is used to convert the transaction-level data into a first interface timing signal according to the AXI protocol, and send the first interface timing signal to the design module to be tested 7 to drive the design module to be tested 7 to output a first interface response signal according to the first interface timing signal; The APB bus function model 5 is used to convert the transaction-level data into a second interface timing signal according to the APB protocol, and send the second interface timing signal to the design module to be tested 7 to drive the design module to be tested 7 to output a second interface response signal according to the second interface timing signal; Specifically, AXI (Advanced eXtensible Interface) is a high-performance, high-bandwidth, low-latency on-chip communication protocol, and is part of the AMBA (Advanced Microcontroller Bus Architecture) bus architecture proposed by ARM. AXI bus functional model 3 (also referred to as AXI-BFM) implements the conversion of message transactions and AXI interface signals according to the AXI protocol. Specifically, the transaction-level data is converted into a first interface timing signal for driving the design module to be tested 7. APB (Advanced Peripheral Bus), as an advanced peripheral bus, is also one of the most basic bus protocols of the AMBA bus architecture. According to the official definition of ARM, APB is a low-cost interface protocol that can achieve low power consumption and streamlined interface design, reducing the complexity of interface design. APB bus functional model 5 (also referred to as APB-BFM) implements the conversion of message transactions and APB interface signals according to the APB protocol. Specifically, the transaction-level data is converted into a second interface timing signal for driving the design module to be tested 7. The design module to be tested 7 receives the first interface timing signal sent by the AXI bus function model 3 and the second interface timing signal sent by the APB bus function model 5 as the injected stimulus, and outputs response information respectively, that is, outputs the first interface response signal and the second interface response signal respectively. It should be noted that the number of the design modules to be tested 7 can be one or more, which can be flexibly set based on actual needs. Figure 2 Taking the illustrated embodiment as an example, the number of the design modules 7 to be tested is 2, and the present application does not impose any specific limitation on this.

[0049] An AXI bus monitor 4, configured to convert the first interface response signal into a first message transaction according to the AXI protocol, and output the first message transaction; The APB bus monitor 6 is used to convert the second interface response signal into a second message transaction according to the APB protocol, and output the second message transaction.

[0050] Specifically, the AXI bus monitor 4 (also referred to as AXI-MONITOR for short) converts the collected timing signal into a data packet according to the AXI protocol, specifically, converts the first interface response signal into a first message transaction and outputs it; the APB bus monitor 6 (also referred to as APB-MONITOR for short) converts the collected timing signal into a data packet according to the APB protocol, specifically, converts the second interface response signal into a second message transaction and outputs it. The output first message transaction and second message transaction can be stored in a preset storage file, and the present application does not impose any specific restrictions on this.

[0051] In some embodiments, the APB bus monitor 6 is internally provided with an array for storing data (e.g., rom_space[(5120+213)*4096-1], (5120+213)*4096 represents a space for storing 820KB) to simulate the memory area space of RDMA, and the design module to be tested 7 can initiate a read request or a write request to the specified memory area.

[0052] In some embodiments, CPU2 is also used to monitor the number of send queue elements sent by AXI bus function model 3 and the number of work queue elements received by AXI bus monitor 4, and when the number of send queue elements is equal to the number of work queue elements, control the simulation process to end.

[0053] Specifically, CPU2 monitors the number of SQEs sent by the AXI bus function model 3 and the number of CQEs received by the AXI bus monitor 4. If the two are consistent, it indicates that all messages have been sent, and the operations of the design module to be tested 7 and the verification framework have been completed, thereby terminating the simulation process. Otherwise, an error prompt may be given.

[0054] Traditional EDA simulation takes a long time to verify large amounts of data, and is highly complex, so EDA simulation cannot meet the verification requirements of RDMA network card chips. In addition, the traditional technical methods for verifying chips focus on simulating circuit behavior, and do not have the flexibility of simulation architecture. When processing large amounts of data and multiple test scenarios, the implementation complexity is high, making it difficult to verify complex chip designs, and cannot meet the high efficiency requirements of simulation verification of RDMA network card chips.

[0055] The above embodiment particularly relates to a chip verification system, which is applied to RDMA network card chips, including: a test case module 1, an AXI bus function model 3, an AXI bus monitor 4, an APB bus function model 5, an APB bus monitor 6, a CPU 2 and a design module to be tested 7; wherein, the AXI bus function model 3 and the APB bus function model 5 based on the VMM verification framework realize the format conversion of the transmission data, realize the high management and control efficiency of the design module to be tested 7, and through real-time processing of the read-write response or read-write request information sent by the design module to be tested 7, the RDMA network card chip can be more fully verified, providing a verification platform for the application of RDMA network card chips in multiple scenarios in the field of high-performance computing, and shortening the development cycle of RDMA network card chips. Compared with the traditional EDA simulation method, the above embodiment has low complexity and fast verification speed, and can improve the verification efficiency of RDMA network card chips.

[0056] In addition, the above embodiment is a coupling design for the RDMA chip architecture, and a dedicated protocol extension can be performed for RDMA. Among them, the AXI bus function model 3 and the APB bus function model 5 can support dynamic configuration of RDMA transmission parameters (such as memory size, QP attributes, local ACK timeout, retransmission limit and other parameters), while Synopsys's AXI-VIP library and APB-VIP library currently only provide general AXI and APB protocol support. The AXI bus monitor 4 can be used for RDMA semantic level monitoring, such as identifying RoCEv2 message data and comparing message data (messages actively driven by the VMM framework to the DUT and messages output by the DUT to the DUT).

[0057] In addition, the AXI bus functional model 3 can also support RDMA-specific scenario injection (such as PSN jump, message retransmission simulation, memory protection error) to achieve dynamic error injection, while SVTVIP currently only supports standard AXI errors. The AXI bus monitor 4 can also be used to integrate custom coverage models (such as statistical RDMA operation type distribution) to achieve coverage enhancement.

[0058] In other embodiments of the present application, the above-mentioned chip verification system also includes a generator, wherein: the generator is connected to the APB bus function model 5 and the AXI bus function model 3 respectively; the generator is used to generate randomized transaction data that meets preset constraints according to the configuration data through a randomization method, and send the randomized transaction data to the APB bus function model 5 and the AXI bus function model 3.

[0059] Specifically, the generator is the GENERATOR component in the VMM verification framework. The generator can be used to modify the random and constraint processing of the configuration data obtained by the test case module 1 to obtain randomized transaction data, which is further transformed by the AXI bus function model 3 and the APB bus function model 5 to drive the design module to be tested 7 to respond, and the AXI bus monitor 4 and the APB bus monitor 6 transform the response signal output by the design module to be tested 7 and output the message transaction, so as to ensure that the functional points of each sub-module of the design module to be tested 7 are covered as much as possible, thereby improving the comprehensiveness of the RDMA network card chip verification.

[0060] In other embodiments of the present application, the APB bus function model 5 is also used to obtain the configuration data of the XGMAC core, and start the design module to be tested 7 according to the configuration data of the XGMAC core.

[0061] Specifically, the XGMAC (10 Gigabit Media Access Control) core is a MAC layer hardware module for 10G Ethernet (10Gigabit Ethernet), which is used to manage and control the sending and receiving of Ethernet data; the APB bus function module can receive the configuration data of the XGMAC core from the APB-CFG component of the test case module 1. In the VMM verification framework, the APB-CFG component is an important module for configuring APB bus related parameters and behaviors. The test case module 1 can configure the APB-CFG component to implement the configuration of the XGMAC core; the APB bus function module can convert the configuration data of the XGMAC core and pass it to the design module 7 to be tested, so as to drive the design module 7 to be tested, open the RX channel (receiving channel), the TX channel (transmitting channel), configure the CRC (Cyclic Redundancy Check) working mode, etc. to start the XGMAC core.

[0062] like Figure 3As shown, in another embodiment of the present application, a chip verification method is also provided, which is applied to an RDMA network card chip. The method is implemented based on the above-mentioned chip verification system, wherein the chip verification system is implemented based on a VMM verification framework, and the chip verification system includes: a test case module 1, an AXI bus function model 3, an AXI bus monitor 4, an APB bus function model 5, an APB bus monitor 6, a CPU2, and a design module to be tested 7; the test case module 1 is connected to the CPU2, and the CPU2 is also respectively connected to the AXI bus function model 3, the AXI bus monitor 4, the APB bus function model 5, and the APB bus monitor 6; the design module to be tested 7 is respectively connected to the AXI bus function model 3 and the AXI bus monitor 4 through the AXI bus; the design module to be tested 7 is also respectively connected to the APB bus function model 5 and the APB bus monitor 6 through the APB bus, and the above-mentioned chip verification method includes: S101. Using the test case module 1, obtain the configuration data of the verification task and send the configuration data to CPU2; S102. Using CPU2, encapsulate the configuration data into transaction-level data, and send the transaction-level data to AXI bus function model 3 and APB bus function model 5 respectively; S103. Using the AXI bus function model 3, according to the AXI protocol, the transaction-level data is converted into a first interface timing signal, and the first interface timing signal is sent to the design module to be tested 7 to drive the design module to be tested 7, and output a first interface response signal according to the first interface timing signal; S104. Using the APB bus function model 5, according to the APB protocol, the transaction-level data is converted into a second interface timing signal, and the second interface timing signal is sent to the design module to be tested 7 to drive the design module to be tested 7, according to the second interface timing signal, output a second interface response signal; S105. Using the AXI bus monitor 4, for converting the first interface response signal into a first message transaction according to the AXI protocol, and outputting the first message transaction; S106. Using the APB bus monitor 6 to convert the second interface response signal into a second message transaction according to the APB protocol, and output the second message transaction.

[0063] The above embodiment realizes the format conversion of transmission data based on the AXI bus function model 3 and the APB bus function model 5 of the VMM verification framework, realizes high management and control efficiency of the design module 7 to be tested, and can perform a relatively full verification of the RDMA network card chip by real-time processing of the read-write response or read-write request information sent by the design module 7 to be tested, providing a verification platform for the application of RDMA network card chips in multiple scenarios in the field of high-performance computing, and shortening the development cycle of RDMA network card chips. Compared with the traditional EDA simulation method, the above embodiment has low complexity and fast verification speed, and can improve the verification efficiency of RDMA network card chips.

[0064] In other embodiments of the present application, the above-mentioned chip verification method also includes: using CPU2 to detect whether the configuration data is valid to obtain a detection result; accordingly, using CPU2 to encapsulate the configuration data into transaction-level data. One implementation method of the step specifically includes: when the detection result is that the configuration data is valid, using CPU2 to encapsulate the configuration data into transaction-level data.

[0065] In other embodiments of the present application, another chip verification method is provided, which specifically includes: S201. Using the test case module 1, obtain the configuration data of the verification task, and send the configuration data of the verification task to the CPU2 and APB bus function model 5; In S201, specifically, the configuration data of the verification task, after being transmitted by the verification environment, reaches CPU2 and APB bus function model 5; taking the RDMA Write operation as an example, the configuration data specifically includes: the type opcode of the sending operation is RC_WRITE, the memory address remote_addr of the remote operation is 44'h6ac000, the memory size remote_length of the remote operation is 1024 bytes, the virtual start address sge_addr of the local buffer is 44'h6a8000, the length sge_length of the local buffer is 1024 bytes, etc. The requesting end writes the 1024-byte memory data starting from the address 44'h6a8000 of the local buffer to the target location of the remote memory address 44'h6ac000.

[0066] S202. Using the APB bus function model 5, obtain the configuration data of the XGMAC core from the configuration data of the verification task, and start the design module to be tested 7 according to the configuration data of the XGMAC core; In S202, specifically, the APB bus function module obtains the configuration data of the XGMAC core from the configuration data of the verification task, converts the configuration data of the XGMAC core and passes it to the design module to be tested 7, so as to drive the design module to be tested 7, open the RX channel, TX channel, configure the CRC working mode, etc. to start the XGMAC core operation.

[0067] S203. Using CPU2, the configuration data of the verification task is encapsulated as transaction-level data, and the transaction-level data is sent to the AXI bus function model 3 and the APB bus function model 5; In S203 , CPU2 is used to encapsulate the configuration data of the verification task, such as CQC, SMAC, SGID, QPC, MRC, etc., into transaction-level data and transmit it to the AXI bus function model 3 and the APB bus function model 5 .

[0068] S204. Using the AXI bus function model 3, according to the AXI protocol, the transaction-level data is converted into a first interface timing signal, and the first interface timing signal is sent to the design module to be tested 7 to drive the design module to be tested 7 to output a first interface response signal according to the first interface timing signal, and using the AXI bus function model 3, according to the sending queue element, the local memory area space is initialized to a random value, and output to a preset storage file; In S204, specifically, the AXI bus function model 3 receives the transaction-level data sent by the CPU 2, and converts it into a first interface timing signal according to the AXI protocol to configure the design module to be tested 7 to start the operation of the design module to be tested 7, and initializes the local memory area space to a random value according to the SQE, and outputs it to a preset storage file.

[0069] S205. Using the APB bus function model 5, according to the APB protocol, the transaction-level data is converted into a second interface timing signal, and the second interface timing signal is sent to the design module to be tested 7 to drive the design module to be tested 7, according to the second interface timing signal, output a second interface response signal; In S205 , specifically, the APB bus function model 5 receives the transaction-level data sent by the CPU 2 , and converts it into a second interface timing signal according to the APB protocol, so as to configure the design module to be tested 7 to start the work of the design module to be tested 7 .

[0070] S206. Using the AXI bus monitor 4, for converting the first interface response signal into a first message transaction according to the AXI protocol, and outputting the first message transaction; In S206, specifically, the AXI bus monitor 4 is used to monitor and receive the first interface response signal output by the design module to be tested 7, and convert it into a first message transaction, and output it to a preset storage file for storage for data update and display; wherein, if the AXI bus monitor 4 can receive the CQE information sent by the design module to be tested 7, then the RDMA operation is successful, otherwise it fails.

[0071] S207. Using the APB bus monitor 6, according to the second interface response signal, it is determined whether the read and write operation of the design module 7 to be tested is successful, and according to the APB protocol, the second interface response signal is converted into a second message transaction, and the second message transaction is output; In S207, specifically, the APB bus monitor 6 is used to receive the second interface response signal of the design module to be tested 7 to check whether the read and write operations of the design module to be tested 7 configured by the APB bus function model 5 are successful. Specifically, the design module to be tested 7 informs the APB bus monitor 6 whether the write operation is successful through the write response channel of the APB protocol. The BRESP signal of the write response channel indicates the transmission status: OKAY (normal access success / exclusive access failure), EXOKAY (exclusive access success), SLVERR (reached the slave host, but the slave host had an error), DECERR (decoding error, the transmission address is not available from the slave host); the AXI bus monitor 4 is used to monitor and receive the second interface response signal output by the design module to be tested 7, and convert it into a second message transaction, which is output to a preset storage file for storage.

[0072] S208. Using CPU2, monitor the number of sending queue elements sent by AXI bus function model 3 and the number of working queue elements received by AXI bus monitor 4, and when the number of sending queue elements is equal to the number of working queue elements, control the simulation process to end.

[0073] Based on the above embodiments, the above chip verification method uses the AXI bus function model 3 to "translate" the configuration data output by the test case module 1 into the data format of the AXI bus transmission, so as to realize the configuration of the relevant information required for the RDMA transmission in the design module 7 to be tested, and verify the generation of random numbers and constraint mechanisms to ensure the injection of random messages into the design module 7 to be tested, so as to realize the verification of each sub-design module of the design module 7 to be tested.

[0074] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip verification system, characterized in that: Applied to RDMA network card chip, the system is implemented based on VMM verification framework, and the system includes: test case module, AXI bus function model, AXI bus monitor, APB bus function model, APB bus monitor, CPU and design module to be tested; the test case module is connected to the CPU, and the CPU is also respectively connected to the AXI bus function model, the AXI bus monitor, the APB bus function model and the APB bus monitor; the design module to be tested is respectively connected to the AXI bus function model and the AXI bus monitor through the AXI bus; the design module to be tested is also respectively connected to the APB bus function model and the APB bus monitor through the APB bus, wherein: The test case module is used to obtain configuration data of the verification task and send the configuration data to the CPU; The CPU is used to encapsulate the configuration data into transaction-level data, and send the transaction-level data to the AXI bus function model and the APB bus function model respectively; The AXI bus functional model is used to convert the transaction-level data into a first interface timing signal according to the AXI protocol, and send the first interface timing signal to the design module to be tested to drive the design module to be tested to output a first interface response signal according to the first interface timing signal; The APB bus function model is used to convert the transaction-level data into a second interface timing signal according to the APB protocol, and send the second interface timing signal to the design module to be tested to drive the design module to be tested to output a second interface response signal according to the second interface timing signal; The AXI bus monitor is used to convert the first interface response signal into a first message transaction according to the AXI protocol, and output the first message transaction; The APB bus monitor is used to convert the second interface response signal into a second message transaction according to the APB protocol, and output the second message transaction.

2. The system as claimed in claim 1, characterized in that The CPU is further used to detect whether the configuration data is valid and obtain a detection result; Correspondingly, when executing the step of encapsulating the configuration data into transaction-level data, the CPU is specifically configured to: when the detection result indicates that the configuration data is valid, encapsulate the configuration data into transaction-level data.

3. The system as claimed in claim 1, characterized in that The CPU is also used to monitor the number of send queue elements sent by the AXI bus functional model and the number of work queue elements received by the AXI bus monitor, and when the number of send queue elements is equal to the number of work queue elements, control the simulation process to end.

4. The system as claimed in claim 1, characterized in that Also included is a generator, wherein: The generator is connected to the APB bus function model and the AXI bus function model respectively; The generator is used to generate randomized transaction data that meets preset constraints according to the configuration data through a randomization method, and send the randomized transaction data to the APB bus functional model and the AXI bus functional model.

5. The system as claimed in claim 1, characterized in that The APB bus function model is also used to obtain the configuration data of the XGMAC core, and start the design module to be tested according to the configuration data of the XGMAC core.

6. A chip verification method, characterized in that: Applied to an RDMA network card chip, the method is implemented based on the chip verification system according to any one of claims 1 to 5, wherein the system is implemented based on a VMM verification framework, and the system comprises: a test case module, an AXI bus function model, an AXI bus monitor, an APB bus function model, an APB bus monitor, a CPU and a design module to be tested; the test case module is connected to the CPU, and the CPU is also respectively connected to the AXI bus function model, the AXI bus monitor, the APB bus function model and the APB bus monitor; the design module to be tested is respectively connected to the AXI bus function model and the AXI bus monitor through the AXI bus; the design module to be tested is also respectively connected to the APB bus function model and the APB bus monitor through the APB bus, and the method comprises: Using the test case module, obtaining configuration data of the verification task, and sending the configuration data to the CPU; Using the CPU, encapsulating the configuration data into transaction-level data, and sending the transaction-level data to the AXI bus function model and the APB bus function model respectively; Using the AXI bus functional model, according to the AXI protocol, converting the transaction-level data into a first interface timing signal, and sending the first interface timing signal to the design module to be tested, so as to drive the design module to be tested, and outputting a first interface response signal according to the first interface timing signal; Using the APB bus function model, according to the APB protocol, converting the transaction-level data into a second interface timing signal, and sending the second interface timing signal to the design module to be tested to drive the design module to be tested, and outputting a second interface response signal according to the second interface timing signal; Using the AXI bus monitor, according to the AXI protocol, converting the first interface response signal into a first message transaction, and outputting the first message transaction; The APB bus monitor is used to convert the second interface response signal into a second message transaction according to the APB protocol, and the second message transaction is output.

7. The method as claimed in claim 6, characterized in that Also includes: Using the CPU, detecting whether the configuration data is valid, and obtaining a detection result; Correspondingly, the utilizing the CPU to encapsulate the configuration data into transaction-level data specifically includes: when the detection result is that the configuration data is valid, utilizing the CPU to encapsulate the configuration data into transaction-level data.

8. The method as claimed in claim 6, characterized in that Also includes: The CPU is used to monitor the number of send queue elements sent by the AXI bus functional model and the number of work queue elements received by the AXI bus monitor, and when the number of send queue elements is equal to the number of work queue elements, the simulation process is controlled to end.

9. The method as claimed in claim 6, characterized in that Also includes: The APB bus function model is used to obtain the configuration data of the XGMAC core, and the design module to be tested is started according to the configuration data of the XGMAC core.

10. The method according to claim 6, characterized in that Also includes: The APB bus monitor is used to determine whether the read and write operations of the design module to be tested are successful according to the second interface response signal.

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