Chip PCB arc-shaped signal line and wiring method and device thereof, and computer readable storage medium

Abstract

The invention discloses a chip PCB arc signal line, a wiring method and device thereof and a computer readable storage medium, and the method comprises the steps: calculating the maximum number and wiring width of signal lines in adjacent via hole gaps in a ball grid array (BGA) region; determining the intersection point of the signal line in the gap between the two adjacent via holes and the straight line where the centers of the two via holes are located; manufacturing uniform arc-shaped signal line routing line segments at equal intervals with the adjacent via holes; and copying, translating and connecting the uniform arc-shaped signal line routing line segments to form a complete arc-shaped signal line routing. By designing the arc-shaped fan-out signal lines between the gaps of the two adjacent via holes of the BGA, the wiring space utilization rate is high, the number of stacked PCBs can be reduced, and the manufacturing cost of the PCBs is saved; compared with a method for designing the required fan-out signal lines by using a method for routing signal lines in any shape, the method has the advantages that the signal lines are uniform in routing, regular in shape and capable of being copied and utilized, meanwhile, fan-out routing in various directions of the BGA packaging area can be designed, the design efficiency is high, and the time cost is low.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a chip PCB arc signal line and a wiring method, device and computer-readable storage medium thereof. Background Art

[0002] In recent years, the development of the field of intelligent driving in automobiles has placed higher and higher requirements on chip computing power, which requires higher and higher chip integration, and at the same time, the chip packaging must be made smaller and smaller. At present, the core chip packaging of the intelligent driving control ECU basically adopts the ball grid array (BGA) packaging.

[0003] Since the number of inner routing layers required by PCB (Printed Circuit Board) is related to the number of pads in each row of the pad array of BGA, and the larger the BGA size, the more pads there are in each row, the more inner routing layers are needed to take the signal lines of all pads of such BGA out of their area. The routing of BGA pads generally runs a short distance from the pads in one direction (usually at an angle of 0 degrees / 180 degrees, or 45 degrees) to the center point of the four adjacent pads, and then leads the signal routing to the inner layer or another surface layer through vias. This process is called fan-out. Except for small BGA packages (the number of pads in each row of the pad array is within an even number), for large BGA packages, after the pads are fanned out, a PCB with only one signal line between any two adjacent vias in its area requires twice as many inner routing layers as a PCB with two or more signal lines between the two vias, and the PCB design time, labor cost and PCB manufacturing cost are more than twice as high.

[0004] At present, in the field of electronic product design, large BGA packages are generally designed in a standard way, that is, the spacing between adjacent pads is just enough to meet the fan-out drilling, and the gap between any two adjacent vias in the BGA area can pass two signal lines, while BGA package designs with three or more lines are rare. Signal lines of any angle and shape are run between the gaps between two adjacent vias of the BGA. The shape and angle of the signal routing between two adjacent vias are random, and each one is different, and cannot be copied and used. Each signal line can only be designed separately, which makes the design more difficult, and the design time cycle will be very long, and the efficiency is very low. Summary of the invention

[0005] The technical problem to be solved by the embodiments of the present invention is to provide a chip PCB arc signal line and its wiring method, device and computer-readable storage medium to improve wiring efficiency and reduce time cost and PCB manufacturing cost.

[0006] In order to solve the above technical problems, the present invention provides a chip PCB arc signal line wiring method, comprising the following steps:

[0007] Calculate the maximum number of signal lines and their trace width in the gap between adjacent vias in the ball grid array (BGA) area;

[0008] Determine the intersection of the signal line and the straight line where the centers of the two vias are located in the gap between two adjacent vias;

[0009] Create uniform arc-shaped signal line routing segments with equal spacing from adjacent vias;

[0010] A complete arc-shaped signal line is formed by copying, translating and connecting the uniform arc-shaped signal line segments.

[0011] Preferably, the calculating of the maximum number of signal lines and their routing widths in the gaps between adjacent vias in a ball grid array (BGA) region specifically includes:

[0012] According to the process level of PCB manufacturing, determine the minimum signal line width w, the minimum gap b between signal lines, and the minimum gap a between signal lines and vias allowed in the BGA area;

[0013] Measure the gap value c between adjacent vias;

[0014] According to n=(c-2a+b) / (w+b), the number n of signal lines that can be routed in the gaps between adjacent vias is calculated.

[0015] Preferably, determining the intersection of the signal line and the straight line where the centers of the two vias are located in the gap between the two adjacent vias specifically includes:

[0016] Anchor the centers of two adjacent vias and measure the radius from the via centers to the edge of the via plate;

[0017] At least two first line segments having a length equal to the sum of the radius and the minimum clearance value from the signal line to the via hole are connected from the center of each via hole, and the first line segments are ensured to form an equilateral triangle or an isosceles triangle after being extended;

[0018] The end point of the first line segment is used as the intersection point of the straight line where the centers of the two via holes are located and the signal line.

[0019] Preferably, the first line segments extending from the same via hole form an angle of 60 degrees.

[0020] Preferably, the step of making uniform arc-shaped signal line routing segments with equal spacing between adjacent vias specifically includes:

[0021] Connecting a second line segment from each end point of the first line segment to form a 90-degree angle with the first line segment;

[0022] Connect a third line segment at the end point of the second line segment, which forms a 90-degree angle with the second line segment;

[0023] The intersection point of the second line segment and the third line segment at the same via hole is used as an anchor point of the arc routing line segment;

[0024] Draw arc-shaped routing segments between the anchor points, and connect adjacent arc-shaped routing segments; gradually remove the remaining segments to obtain uniform arc-shaped signal line routing segments with equal spacing from adjacent vias.

[0025] Preferably, before calculating the maximum number of signal lines and their routing widths in adjacent via gaps in a ball grid array (BGA) region, the method further includes: uniformly fanning out all pads of the BGA package to lead the signal lines to an inner routing layer of the PCB.

[0026] The present invention also provides a chip PCB arc signal line, which is located in adjacent via gaps within a ball grid array (BGA) area and is formed by copying, translating and connecting multiple uniform arc signal line routing segments, and the endpoints of each uniform arc signal line routing segment are the intersections of the signal line in the gaps between two adjacent vias and the straight lines where the centers of the two vias are located.

[0027] Preferably, the endpoints of each uniform arc-shaped signal line routing segment and the center of the corresponding via hole form an equilateral triangle or an isosceles triangle.

[0028] The present invention also provides a chip PCB arc signal line wiring device, comprising:

[0029] one or more processors;

[0030] Memory;

[0031] One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the chip PCB arc signal line wiring method.

[0032] The present invention also provides a computer-readable storage medium, which includes a stored computer program; wherein, when the computer program is running, it controls the device where the computer-readable storage medium is located to execute the chip PCB arc signal line wiring method.

[0033] The implementation of the present invention has the following beneficial effects: the present invention designs an arc-shaped fan-out signal line between the gaps of two adjacent vias of the BGA, which has a high utilization rate of wiring space compared to only routing one signal line at a 45-degree angle, can reduce the number of PCB stacking layers, and save PCB manufacturing costs; compared to designing the required fan-out signal line by routing a signal line of any shape, the signal line routing is uniform, the shape rules can be copied and utilized, and at the same time, the fan-out routing in various directions of the BGA packaging area can be designed; the design efficiency is high and the time cost is low; the present invention can achieve the design of an ideal arc-shaped routing unit without any DEMO design reference and when the design software has no design function for this type of BGA, and the design software does not need to be upgraded to a version with this BGA packaging fan-out function, and the operation is easy to use, quick and convenient, and cost-saving. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 The present invention is a flowchart of a method for wiring arc signal lines on a chip PCB according to an embodiment of the present invention.

[0036] Figure 2 It is a schematic diagram of the PCB packaging of the chip BGA in an embodiment of the present invention.

[0037] Figure 3 It is a schematic diagram of calculating the maximum number of signal lines and their routing widths by taking any four adjacent vias in a BGA package area as an example in an embodiment of the present invention.

[0038] Figure 4 It is a schematic diagram of determining the intersection of a signal line in a gap between two adjacent via holes and a straight line where the centers of the two via holes are located in an embodiment of the present invention.

[0039] Figure 5 It is a schematic diagram of making uniform arc-shaped signal line routing segments with equal spacing between the vias in the gaps between four adjacent vias in an embodiment of the present invention.

[0040] Figure 6a : is a schematic diagram of arc signal line routing line segments required for making two segments in an embodiment of the present invention, Figure 6b It is a schematic diagram of arc-shaped signal line routing segments between four adjacent vias required for manufacturing in an embodiment of the present invention.

[0041] Figure 7Schematic diagram of arc signal line routing in each direction of each routing layer in the BGA area obtained in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following descriptions of the embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present invention may be implemented.

[0043] Please refer to Figure 1 As shown, the first embodiment of the present invention provides a chip PCB arc signal line wiring method, comprising the following steps:

[0044] Calculate the maximum number of signal lines and their trace width in the gap between adjacent vias in the ball grid array (BGA) area;

[0045] Determine the intersection of the signal line and the straight line where the centers of the two vias are located in the gap between two adjacent vias;

[0046] Create uniform arc-shaped signal line routing segments with equal spacing from adjacent vias;

[0047] A complete arc-shaped signal line is formed by copying, translating and connecting the uniform arc-shaped signal line segments.

[0048] Through the above steps, we can know that

[0049] Specifically, before calculating the maximum number of signal lines and their routing width in the gaps between adjacent vias in the ball grid array (BGA) area, all pads of the BGA package are fanned out uniformly to lead the signal lines to the inner routing layer of the PCB. Specifically, a short line segment is run from the center of the pad outward (at a 45-degree angle, horizontally or vertically) to the center of the gap formed by the other three adjacent pads, and then connected to the through hole, so that the signal line enters the inner routing layer of the PCB. Figure 2 The PCB package of the chip BGA shown has a horizontal axis spacing of 40 mils and a vertical axis spacing of 34.7 mils between two adjacent pads. In the specific signal line routing design, the signal line of the pad is fanned out from the center point of the four adjacent pads at a 90-degree angle, connected to the via, and then the signal routing is switched to other routing layers through the via. Correspondingly, after each pad is connected to the via, the horizontal axis spacing between two adjacent vias is also 40 mils, and the vertical axis spacing is 34.7 mils.

[0050] After completing the fan-out, the number of signal lines and the routing width that need to be routed in each adjacent via gap are calculated and determined based on the size of the adjacent via gap and the electrical performance requirements. In this embodiment, based on the process level of PCB manufacturing, the minimum signal line width allowed in the BGA area (set as w), the minimum gap between signal lines (set as b), and the minimum gap between signal lines and vias (set as a) are determined; then the gap value between adjacent vias is measured (set as c). Then, based on n = (c-2a + b) / (w + b), the number of signal lines n that can be routed in the adjacent via gaps is calculated.

[0051] As an example, Figure 3 For any four adjacent vias in the BGA package area shown, the minimum clearance between signal lines and vias is a = 4mil, the minimum clearance between signal lines is b = 4mil, the clearance between adjacent vias is c = 20mil, and the minimum signal line width w = 4mil allowed in the BGA area. According to n = (c-2a + b) / (w + b), n = 2 is calculated, that is, the gap between two adjacent vias can only pass two signal lines.

[0052] In this embodiment, determining the intersection of the signal line and the straight line where the centers of the two vias are located in the gap between two adjacent vias specifically includes:

[0053] Anchor the centers of two adjacent vias and measure the radius from the via centers to the edge of the via plate;

[0054] At least two line segments having a length equal to the sum of the radius and the minimum clearance value from the signal line to the via hole are connected from the center of each via hole, and it is ensured that the line segments form an equilateral triangle or an isosceles triangle after extension;

[0055] The end point of the line segment is used as the intersection point of the straight line where the centers of the two via holes are located and the signal line.

[0056] Specifically, please refer to Figure 4 As shown, four adjacent vias in any parallelogram position are selected as a reference, and the center to center of any two vias is one side of the triangle.

[0057] Measure the radius r from the center of the via to the edge of the via plate, and connect at least two line segments L1, L2, L3, L4, L5, L6, L7, L8, L9, L10 with a length of r+a (as mentioned above, a is the minimum gap from the signal line to the via) from the center of each via, and L2 forms a 60-degree angle with L1 and L3, L4 forms a 60-degree angle with L5, L7 forms a 60-degree angle with L6 and L8, and L9 forms a 60-degree angle with L10. This ensures that after each line segment is extended, it can form an equilateral triangle or an isosceles triangle as a whole. Figure 4It can be seen that L1, L2, L4, L5, L6, and L7 together form an equilateral triangle, and L2, L3, L7, L8, L9, and L10 also together form an equilateral triangle. Then the end points of L1, L2, L4, L7, L8, and L10 (it can be understood that the starting points of L1, L2, L4, L7, L8, and L10 are the centers of their respective vias) are the intersections of the straight line where the centers of two adjacent vias are located and the signal line in the gap between the two adjacent vias.

[0058] In this embodiment, making uniform arc-shaped signal line routing segments with equal spacing from adjacent vias specifically includes:

[0059] like Figure 5 As shown, take the example of making a uniform arc signal line segment with equal spacing between the vias in the gaps between four adjacent vias:

[0060] At the end point of each line segment L1, L2, L4, L7, L8, L10, connect another line segment l1, l2, l4, l7, l8, l10 (l is the lowercase letter of L) that forms a 90-degree angle with it, and then continue to connect another line segment t1, t2, t4, t7, t8, t10 at the end point of this line segment, and finally every 3 line segments (L1, l1, t1), (L2, l2, t2), (L4, l4, t4), (L7, l7, t7), (L8, l8, t8), (L10, l10, t10) form a J-shaped structure or an axially symmetrical structure of the J-shaped structure. In this way, the intersection point of L1 and l1, the intersection point of L2 and l2, the intersection point of L4 and l4, and the intersection point of L7 and l7 are determined as the anchor points at both ends of the two required arc segments.

[0061] Use the "arc", "off", "4mil" arbitrary arc routing functions of the Allegro software to connect the intersection of L1 and L1 with the intersection of L2 and L2, the intersection of L4 and L4 with the intersection of L7 and L7, the intersection of L2 and L2 with the intersection of L10 and L10, and the intersection of L7 and L7 with the intersection of L8 and L8. Then delete L1, L2, L4, and L7.

[0062] Similarly, use the "arc", "off", "4mil" arbitrary arc function mode of the Allegro software to route a 4mil wide signal line, connect L1 with L2, L4 with L7 respectively, and then remove L2, T2, L4, T4 to get the following Figure 6aThe arc signal line routing line segments required for the two segments are shown. In the same way, after removing L8 and L10, use any arc mode of "arc", "off", "4mil" to route the 4mil wide signal line, respectively connect the original l2 and l10, l7 and l8, and finally remove L3, L5, L6, L9, l1, t1, l2, t2, l4, t4, l7, t7, l10, t10, and get Figure 6b The required arc signal line routing line segments between the four adjacent vias are shown in . By copying, translating and connecting the above two arc signal line routing line segments, a continuous and complete arc signal line routing line segment is obtained until the fan-out BGA area.

[0063] In the same way, Figure 7 As shown, arc signal line routing in various directions can be obtained in each routing layer in the BGA area.

[0064] Corresponding to the chip PCB arc signal line wiring method described in the aforementioned embodiment 1 of the present invention, embodiment 2 of the present invention further provides a chip PCB arc signal line, wherein the chip PCB arc signal line is located in adjacent via gaps within the ball grid array (BGA) area, and is formed by copying, translating and connecting multiple sections of uniform arc signal line routing segments, wherein the endpoint of each uniform arc signal line routing segment is the intersection of the signal line in the gap between two adjacent vias and the straight line where the centers of the two vias are located.

[0065] Preferably, the endpoints of each uniform arc-shaped signal line routing segment and the center of the corresponding via hole form an equilateral triangle or an isosceles triangle.

[0066] For other structural features, please refer to the introduction of the first embodiment of the present invention, which will not be repeated here.

[0067] Corresponding to the chip PCB arc signal line wiring method described in the first embodiment of the present invention, the third embodiment of the present invention further provides an airbag processing device for scrapped vehicles, including:

[0068] one or more processors;

[0069] Memory;

[0070] One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the chip PCB arc signal line wiring method described in embodiment 1 of the present invention.

[0071] Corresponding to the chip PCB arc signal line wiring method described in the aforementioned embodiment 1 of the present invention, embodiment 4 of the present invention provides a computer-readable storage medium, and the computer-readable storage medium includes a stored computer program; wherein, when the computer program is running, it controls the device where the computer-readable storage medium is located to execute the chip PCB arc signal line wiring method as described in embodiment 1 of the present invention.

[0072] Preferably, the computer program can be divided into one or more modules / units (such as computer program 1, computer program 2, ...), and the one or more modules / units are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units can be a series of computer program instruction segments that can complete specific functions, and the instruction segments are used to describe the execution process of the computer program in the device.

[0073] The processor may be a central processing unit (CPU), or other general-purpose processors, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or the processor may be any conventional processor. The processor is the control center of the device, and various parts of the device are connected using various interfaces and lines.

[0074] The memory mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function, etc., and the data storage area can store related data, etc. In addition, the memory can be a high-speed random access memory, or a non-volatile memory, such as a plug-in hard disk, a smart memory card (SmartMedia Card, SMC), a secure digital (Secure Digital, SD) card, and a flash card (Flash Card), etc., or the memory can also be other volatile solid-state storage devices.

[0075] It should be noted that the above-mentioned device may include but is not limited to a processor and a memory, which can be understood by those skilled in the art.

[0076] For the working principle and process of the above embodiment, please refer to the description of the above embodiment of the present invention, which will not be repeated here.

[0077] It can be seen from the above description that compared with the prior art, the beneficial effects of the present invention are as follows: the present invention designs an arc-shaped fan-out signal line between the gaps between two adjacent vias of the BGA, which has a high wiring space utilization rate compared to only running one signal line at a 45-degree angle, can reduce the number of PCB stacking layers, and save PCB manufacturing costs; compared to designing the required fan-out signal lines by routing signal lines of arbitrary shapes, the signal lines are evenly routed, the shape rules can be copied and utilized, and at the same time, fan-out routing in various directions of the BGA packaging area can be designed; the design efficiency is high and the time cost is low; the present invention can achieve the design of an ideal arc routing unit without any DEMO design reference and when the design software has no design function for this type of BGA, and the design software does not need to be upgraded to a version with this BGA package fan-out function, and the operation is easy to use, quick and convenient, and cost-saving.

[0078] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A chip PCB arc signal line wiring method, characterized in that: The following steps are involved: Calculate the maximum number of signal lines and their trace width in the gap between adjacent vias in the ball grid array (BGA) area; Determine the intersection of the signal line and the straight line where the centers of the two vias are located in the gap between two adjacent vias; Create uniform arc-shaped signal line routing segments with equal spacing from adjacent vias; A complete arc-shaped signal line is formed by copying, translating and connecting the uniform arc-shaped signal line segments.

2. The method according to claim 1, characterized in that The calculating of the maximum number of signal lines and their routing widths in the gaps between adjacent vias in the ball grid array (BGA) region specifically includes: According to the process level of PCB manufacturing, determine the minimum signal line width w, the minimum gap b between signal lines, and the minimum gap a between signal lines and vias allowed in the BGA area; Measure the gap value c between adjacent vias; According to n=(c-2a+b) / (w+b), the number n of signal lines that can be routed in the gaps between adjacent vias is calculated.

3. The method according to claim 1, characterized in that The step of determining the intersection of the signal line and the straight line where the centers of the two vias are located in the gap between the two adjacent vias specifically includes: Anchor the centers of two adjacent vias and measure the radius from the via centers to the edge of the via plate; At least two first line segments having a length equal to the sum of the radius and the minimum clearance value from the signal line to the via hole are connected from the center of each via hole, and the first line segments are ensured to form an equilateral triangle or an isosceles triangle after being extended; The end point of the first line segment is used as the intersection point of the straight line where the centers of the two via holes are located and the signal line.

4. The method according to claim 3, characterized in that The first line segments extending from the same via hole form an angle of 60 degrees.

5. The method according to claim 3, characterized in that: The method of making uniform arc-shaped signal line routing segments with equal spacing between adjacent vias specifically includes: Connecting a second line segment from each end point of the first line segment to form a 90-degree angle with the first line segment; Connect a third line segment at the end point of the second line segment, which forms a 90-degree angle with the second line segment; The intersection point of the second line segment and the third line segment at the same via hole is used as an anchor point of the arc routing line segment; Draw arc-shaped routing segments between the anchor points, and connect adjacent arc-shaped routing segments; gradually remove the remaining segments to obtain uniform arc-shaped signal line routing segments with equal spacing from adjacent vias.

6. The method according to claim 1, characterized in that Before calculating the maximum number of signal lines and their routing widths in the gaps between adjacent vias in the ball grid array (BGA) area, it also includes: uniformly fanning out all pads of the BGA package to lead the signal lines to the inner routing layer of the PCB.

7. A chip PCB arc signal line, characterized in that: The chip PCB arc signal line is located in the adjacent via gaps within the ball grid array (BGA) area, and is formed by copying, translating and connecting multiple uniform arc signal line routing segments. The endpoint of each uniform arc signal line routing segment is the intersection of the signal line in the two adjacent via gaps and the straight line where the centers of the two vias are located.

8. The chip PCB arc signal line according to claim 7, characterized in that: The endpoints of each uniform arc-shaped signal line routing segment and the center of the corresponding via hole form an equilateral triangle or an isosceles triangle.

9. A chip PCB arc signal line wiring device, characterized in that: include: one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the chip PCB arc signal line wiring method as described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program; wherein, when the computer program is run, it controls the device where the computer-readable storage medium is located to execute the chip PCB arc signal line wiring method as described in any one of claims 1 to 6.

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