Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and relates to the technical field of semiconductors. The forming method comprises the steps that a stacked film layer is formed on a substrate, the stacked film layer comprises a plurality of first semiconductor layers and a protection layer, the first semiconductor layers extend in the first direction and are distributed at intervals in the second direction, a gap is formed between every two adjacent first semiconductor layers in the second direction, and the second direction intersects with the first direction; the stacked film layer is provided with a groove, and the groove penetrates through the first semiconductor layers in the second direction; protective layers are respectively formed on the end surfaces of the first semiconductor layers exposed in the grooves; etching the first semiconductor layer to reduce the thickness of the first semiconductor layer; the etching rate of the protection layer is smaller than that of the first semiconductor layer. According to the forming method disclosed by the invention, the storage density can be improved under the condition that the number of the first semiconductor layers is not increased.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] Memory is widely used in mobile devices such as mobile phones and tablets due to its advantages of small size, high integration and fast transmission speed. Memory includes multiple chip units integrated on a wafer. However, during the manufacturing process, affected by the manufacturing process, the number of chip units integrated on a single wafer is small, and the storage density is low.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The present disclosure provides a semiconductor structure and a method for forming the same, which can improve storage density without increasing the number of first semiconductor layers.

[0005] According to one aspect of the present disclosure, there is provided a method for forming a semiconductor structure, comprising: A stacked film layer is formed on a substrate, the stacked film layer comprising a plurality of first semiconductor layers and a protective layer, the plurality of first semiconductor layers extend along a first direction and are spaced apart along a second direction, and there is a gap between two adjacent first semiconductor layers along the second direction, and the second direction intersects with the first direction; the stacked film layer has a groove, the groove penetrates each of the first semiconductor layers along the second direction; and the protective layer is respectively formed on the end surface of each of the first semiconductor layers exposed in the groove; The first semiconductor layer is etched to reduce the thickness of the first semiconductor layer; and the etching rate of the protection layer is lower than the etching rate of the first semiconductor layer.

[0006] In an exemplary embodiment of the present disclosure, the forming of a stacked film layer on a substrate includes: forming a plurality of first semiconductor layers and second semiconductor layers alternately distributed along the second direction on the substrate; Etching the first semiconductor layer and the second semiconductor layer to form a groove penetrating each of the first semiconductor layers and each of the second semiconductor layers along the second direction; forming the protective layer on the end surface of each of the first semiconductor layers exposed in the groove; Each of the second semiconductor layers is removed to form the gap between adjacent first semiconductor layers.

[0007] In an exemplary embodiment of the present disclosure, the forming of the protective layer on the end surface of each of the first semiconductor layers exposed in the grooves includes: Etching back the end of the second semiconductor layer close to the trench to form a recess; forming a covering layer in the recess; forming the protective layer on an end surface of the first semiconductor layer close to the groove; The covering layer is removed.

[0008] In an exemplary embodiment of the present disclosure, the forming of the protective layer on the end surface of each of the first semiconductor layers exposed in the grooves includes: Synchronously oxidizing the end of the first semiconductor layer exposed in the trench and the end of the second semiconductor layer exposed in the trench to form the protection layer in the first semiconductor layer near the end of the trench and to form a capping layer at the end of the second semiconductor layer; The covering layer is removed.

[0009] In an exemplary embodiment of the present disclosure, the material of the first semiconductor layer is silicon, the material of the capping layer is silicon nitride, and the forming of the protective layer on the end surface of the first semiconductor layer close to the groove includes: forming a metal layer on a surface of a structure formed by the cover layer and the first semiconductor layer; thermally treating the metal layer to form a metal silicide layer on a surface of the first semiconductor layer; The unreacted metal layer is removed, and the metal silicide layer is used as the protective layer.

[0010] In an exemplary embodiment of the present disclosure, the forming of a protective layer on an end surface of the first semiconductor layer close to the trench includes: Ion doping is performed on an end portion of the first semiconductor layer close to the trench, and the first semiconductor layer containing doped ions is used as the protection layer.

[0011] In an exemplary embodiment of the present disclosure, the forming of a stacked film layer on a substrate includes: forming a plurality of first semiconductor layers and second semiconductor layers alternately distributed along the second direction on the substrate; Etching the first semiconductor layer and the second semiconductor layer to form a groove penetrating each of the first semiconductor layers and each of the second semiconductor layers along the second direction; removing the second semiconductor layer to form the gap; forming a covering layer in the gap, wherein the covering layer covers the upper surface and the lower surface of the first semiconductor layer distributed along the second direction; forming the protective layer in the first semiconductor layer near the end surface of the trench; The cover layer is removed to expose the gap.

[0012] In an exemplary embodiment of the present disclosure, forming a covering layer in the gap, wherein the covering layer covers the upper surface and the lower surface of the first semiconductor layer distributed along the second direction, includes: forming a covering material layer conformally covering the surface of each of the first semiconductor layers; forming a filling layer between the first semiconductor layers having the covering material layer, wherein the filling layer fills the gap between adjacent first semiconductor layers; removing the covering material layer on the end surface of the first semiconductor layer close to the groove to expose the end surface of the first semiconductor layer close to the groove; The filling layer is removed, and the remaining covering material layer is used as the covering layer.

[0013] In an exemplary embodiment of the present disclosure, forming a covering layer in the gap, wherein the covering layer covers the upper surface and the lower surface of the first semiconductor layer distributed along the second direction, includes: forming a covering material layer on the surface of each of the first semiconductor layers, wherein the covering material layer fills the gap; The covering material layer on the end surface of the first semiconductor layer close to the trench is removed to expose the end surface of the first semiconductor layer close to the trench, and the remaining covering material layer is used as the covering layer.

[0014] In an exemplary embodiment of the present disclosure, the forming method further includes: After reducing the thickness of the first semiconductor layer, the protection layer is removed.

[0015] According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure is formed by any one of the above-mentioned methods for forming a semiconductor structure.

[0016] The semiconductor structure and its formation method disclosed in the present invention, by forming a plurality of first semiconductor layers distributed along the second direction on the substrate, can integrate more first semiconductor layers within a unit area, and provide a basis for manufacturing more chip units. By etching the first semiconductor layer to reduce the thickness of the first semiconductor layer, a larger process space can be reserved for the subsequent preparation of word lines between two adjacent first semiconductor layers distributed along the second direction, which helps to reduce the process difficulty of subsequent word line production. In addition, in the process of etching and thinning the first semiconductor layer, since protective layers are respectively formed on the end faces of each first semiconductor layer exposed in the groove, and the etching rate of the protective layer is lower than the etching rate of the first semiconductor layer, in the process of etching and thinning the first semiconductor layer, the end of the first semiconductor layer close to the groove can be protected by the protective layer, which can reduce the damage to the first semiconductor layer in the first direction during the etching process, so that the spacing between the first semiconductor layers on both sides of the groove is relatively small, and more first semiconductor layers can be arranged on the substrate along the first direction, which helps to prepare more chip units on the substrate. That is, the storage density can be improved without increasing the number of layers of the first semiconductor layer.

[0017] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0019] Figure 1 Flow chart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0020] Figure 2 Schematic diagram of the first semiconductor layer, the second semiconductor layer and the trench in the embodiment of the present disclosure.

[0021] Figure 3 Schematic diagram of a protective layer in an embodiment of the present disclosure.

[0022] Figure 4 Schematic diagram of the concave portion in the embodiment of the present disclosure.

[0023] Figure 5 FIG. 4 is a schematic diagram of a covering material layer in an embodiment of the present disclosure.

[0024] Figure 6 FIG. 4 is a schematic diagram of a covering layer in an embodiment of the present disclosure.

[0025] Figure 7 Schematic diagram of a protective layer and a covering layer in an embodiment of the present disclosure.

[0026] Figure 8 Schematic diagram of the metal layer in the embodiment of the present disclosure.

[0027] Fig. 9 Schematic diagram of a metal silicide layer in an embodiment of the present disclosure.

[0028] Fig.10 Schematic diagram of a protective layer and a covering layer in an embodiment of the present disclosure.

[0029] Fig.11 Schematic diagram of a gap in an embodiment of the present disclosure.

[0030] Fig.12 Schematic diagram of a gap in an embodiment of the present disclosure.

[0031] Fig.13 FIG. 4 is a schematic diagram of a covering layer in an embodiment of the present disclosure.

[0032] Fig.14 FIG. 4 is a schematic diagram of a covering layer in an embodiment of the present disclosure.

[0033] Fig.15 Schematic diagram of a covering material layer and a filling layer in an embodiment of the present disclosure.

[0034] Fig.16 This is a schematic diagram after a portion of the filling layer is removed in an embodiment of the present disclosure.

[0035] Fig.17 It is a schematic diagram of the structure after completing step S730 in the embodiment of the present disclosure.

[0036] Fig.18 It is a schematic diagram of the structure after completing step S810 in the embodiment of the present disclosure.

[0037] Fig.19 It is a schematic diagram of the structure after completing step S650 in the embodiment of the present disclosure.

[0038] Fig. 20 It is a schematic diagram of the structure after completing step S120 in one embodiment of the present disclosure.

[0039] Fig.21 It is a schematic diagram of the structure after completing step S130 in one embodiment of the present disclosure.

[0040] In the figure: 1, substrate; 2, stacked film layer; 21, first semiconductor layer; 22, protective layer; 23, second semiconductor layer; 24, protective material layer; 201, groove; 202, gap; 203, recess; 3, covering layer; 31, covering material layer; 4, metal layer; 41, metal silicide layer; 5, filling layer; x, first direction; y, second direction. DETAILED DESCRIPTION

[0041] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0042] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0043] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first" and "second" are used merely as labels and are not intended to limit the quantity of their objects.

[0044] In the manufacturing process of 3D dynamic random access memory (DRAM), in order to improve the storage density, a plurality of semiconductor groups spaced apart laterally are usually formed on a substrate, each semiconductor group including a plurality of first semiconductor layers spaced apart longitudinally; at the same time, in order to facilitate the preparation of word lines between two adjacent first semiconductor layers spaced apart longitudinally, the first semiconductor layer needs to be thinned. However, in the process of thinning the first semiconductor layer, the lateral loss of the first semiconductor layer is large, so that the spacing between adjacent semiconductor groups spaced apart laterally is large, resulting in a small number of chip units formed thereon in the transverse direction and a low storage density.

[0045] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, the forming method includes step S110 and step S120, wherein: Step S110, forming a stacked film layer on a substrate, the stacked film layer comprising a plurality of first semiconductor layers and a protective layer, the plurality of first semiconductor layers extending along a first direction and spaced apart along a second direction, and a gap between two adjacent first semiconductor layers along the second direction, the second direction intersecting with the first direction; the stacked film layer having a groove, the groove penetrating each of the first semiconductor layers along the second direction; the protective layer being respectively formed on the end surface of each of the first semiconductor layers exposed in the groove; Step S120, etching the first semiconductor layer to reduce the thickness of the first semiconductor layer; the etching rate of the protection layer is lower than the etching rate of the first semiconductor layer.

[0046] The method for forming a semiconductor structure disclosed in the present invention forms a plurality of first semiconductor layers distributed along the second direction on a substrate, so that more first semiconductor layers can be integrated within a unit area, providing a basis for manufacturing more chip units. By etching the first semiconductor layer to reduce the thickness of the first semiconductor layer, a larger process space can be reserved for the subsequent preparation of word lines between two adjacent first semiconductor layers distributed along the second direction, which helps to reduce the process difficulty of subsequent word line production. In addition, in the process of etching and thinning the first semiconductor layer, since protective layers are respectively formed on the end faces of each first semiconductor layer exposed in the groove, and the etching rate of the protective layer is lower than the etching rate of the first semiconductor layer, in the process of etching and thinning the first semiconductor layer, the end of the first semiconductor layer close to the groove can be protected by the protective layer, which can reduce the damage to the first semiconductor layer in the first direction during the etching process, so that the spacing between the first semiconductor layers on both sides of the groove is relatively small, and more first semiconductor layers can be arranged on the substrate along the first direction, which helps to prepare more chip units on the substrate. That is, the storage density can be improved without increasing the number of layers of the first semiconductor layer.

[0047] The steps and specific details of the method for forming a semiconductor structure disclosed in the present invention are described in detail below: like Figure 1As shown, in step S110, a stacked film layer is formed on the substrate, the stacked film layer includes a plurality of first semiconductor layers and a protective layer, the plurality of first semiconductor layers extend along a first direction and are spaced apart along a second direction, and there is a gap between two adjacent first semiconductor layers along the second direction, and the second direction intersects with the first direction; the stacked film layer has a groove, and the groove penetrates each first semiconductor layer along the second direction; and a protective layer is respectively formed on the end surface of each first semiconductor layer exposed in the groove.

[0048] like Figure 2 As shown, the substrate 1 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is made to the shape and material of the substrate 1 herein.

[0049] In an exemplary embodiment of the present disclosure, forming a stacked film layer on the substrate 1 (ie, step S110) may include steps S210 to S240, wherein: In step S210 , a plurality of first semiconductor layers 21 and second semiconductor layers 23 are formed on the substrate 1 and are alternately distributed along the second direction y.

[0050] Please continue to see Figure 2 As shown, each first semiconductor layer 21 and each second semiconductor layer 23 can extend along a first direction x, and the first direction x can be any direction parallel to the substrate 1. Each first semiconductor layer 21 and each second semiconductor layer 23 can be stacked and distributed along a second direction y. For example, each first semiconductor layer 21 and each second semiconductor layer 23 can be alternately distributed on the substrate 1 along the second direction y. In one embodiment, in the stacked film layers, the film layer farthest from the substrate 1 is the first semiconductor layer 21.

[0051] In some embodiments of the present disclosure, the material of the first semiconductor layer 21 may be silicon, and the material of the second semiconductor layer 23 may be silicon germanium. The thickness of the first semiconductor layer 21 may be greater than the thickness of the second semiconductor layer 23. For example, the ratio of the thickness of the first semiconductor layer 21 to the thickness of the second semiconductor layer 23 may be 5:1 to 2:1. For example, the thickness of the first semiconductor layer 21 may be 50nm, and the thickness of the second semiconductor layer 23 may be 10nm; or, the thickness of the first semiconductor layer 21 may be 45nm, and the thickness of the second semiconductor layer 23 may be 15nm; or, the thickness of the first semiconductor layer 21 may be 40nm, and the thickness of the second semiconductor layer 23 may be 20nm.

[0052] For example, the number of the first semiconductor layers 21 may be 2 to 20, for example, 2, 6, 10, 14, 18 or 20. Of course, the number of the first semiconductor layers 21 may also be other numbers, which are not listed here one by one.

[0053] In some embodiments of the present disclosure, the second direction y may intersect with the first direction x, for example, the second direction y and the first direction x may be perpendicular to each other. It should be noted that perpendicularity may be absolutely perpendicular or approximately perpendicular, and deviations are inevitable during the manufacturing process. In the present disclosure, the angle deviation may be caused by manufacturing process limitations, so that the angle between the first direction x and the second direction y has a certain deviation. As long as the angle deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y can be considered perpendicular. For example, the preset range may be 10°, that is, the first direction x and the second direction y can be considered perpendicular when the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°.

[0054] A plurality of first semiconductor layers 21 and a plurality of second semiconductor layers 23 alternately distributed along the second direction y can be formed on the substrate 1 by atomic layer deposition, chemical vapor deposition, physical vapor deposition or epitaxial growth. Of course, each first semiconductor layer 21 and each second semiconductor layer 23 can also be formed by other methods. The formation method of the first semiconductor layer 21 and the second semiconductor layer 23 is not particularly limited herein.

[0055] In step S220 , the first semiconductor layer 21 and the second semiconductor layer 23 are etched to form a trench 201 penetrating each first semiconductor layer 21 and each second semiconductor layer 23 along the second direction y.

[0056] The first semiconductor layers 21 and the second semiconductor layers 23 on the substrate 1 may be etched by dry etching to form the grooves 201 (eg Figure 2 As shown); that is, the sidewall of the trench 201 may be formed by each first semiconductor layer 21 and each second semiconductor layer 23.

[0057] In some embodiments of the present disclosure, please continue to refer to Figure 2 As shown, before dry etching, a protective material layer 24 may be formed on the surface of the first semiconductor layer 21 located at the top (i.e., the first semiconductor layer 21 farthest from the substrate 1) away from the substrate 1. The protective material layer 24 may cover the surface of the first semiconductor layer 21 located at the top, and the material of the protective material layer 24 is different from the materials of the first semiconductor layer 21 and the second semiconductor layer 23. In the dry etching process, the etching rate of the protective material layer 24 is much lower than the etching rate of the first semiconductor layer 21 and the second semiconductor layer 23, which can ensure that in the process of etching to form the groove 201, the protective material layer 24 always covers the surface of the first semiconductor layer 21 farthest from the substrate 1, thereby protecting the first semiconductor layer 21 farthest from the substrate 1 from damage. For example, the material of the protective material layer 24 may be silicon oxide.

[0058] In some embodiments of the present disclosure, there may be multiple grooves 201 , and the multiple grooves 201 may be spaced apart along the first direction x, so that the structure formed by each first semiconductor layer 21 and each second semiconductor layer 23 may be divided into multiple spaced apart semiconductor groups by the multiple grooves 201 .

[0059] Step S230 , forming a protection layer on the end surface of the first semiconductor layer 21 close to the trench 201 .

[0060] The material of the protective layer is different from that of the first semiconductor layer 21; and in the subsequent etching process of the first semiconductor layer 21, the etching rate of the protective layer is lower than the etching rate of the first semiconductor layer 21. For example, when the material of the first semiconductor layer 21 is silicon, the material of the protective layer may be silicon oxide, metal silicide, silicon with doped ions, etc. The thickness of the protective layer may be 2nm~5nm, for example, it may be 2nm, 3nm, 4nm or 5nm. Of course, the thickness of the protective layer may also be other values, which are not particularly limited here, as long as it can be ensured that the protective layer will not be consumed in the subsequent thinning process of the first semiconductor layer 21.

[0061] like Figure 3 As shown, protective layers 22 may be formed on the surfaces of the end faces of each first semiconductor layer 21 exposed in the sidewalls of the trench 201. For example, the protective layer 22 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or in-situ water vapor oxidation. Of course, the protective layer 22 may also be formed by other methods, and the method for forming the protective layer 22 is not particularly limited herein.

[0062] In an exemplary embodiment of the present disclosure, forming the protection layer 22 on the end surface of each first semiconductor layer 21 exposed in the trench 201 (ie, step S230) may include steps S310 to S340, wherein: In step S310 , the end of the second semiconductor layer 23 close to the trench 201 is etched back to form a recess 203 .

[0063] like Figure 4 As shown, the end of the second semiconductor layer 23 close to the groove 201 can be isotropically etched to remove part of the second semiconductor layer 23, and the space enclosed by the remaining second semiconductor layer 23 and the two first semiconductor layers 21 located on both sides of the second semiconductor layer 23 in the second direction y can be used as the recess 203. It should be noted that when there are multiple second semiconductor layers 23, the multiple second semiconductor layers 23 can be etched back at the same time to form multiple recesses 203 arranged along the second direction y.

[0064] Step S320 , forming a cover layer 3 in the recess 203 .

[0065] The material of the cover layer 3 is different from the material of the protective layer 22 to be formed subsequently. For example, the material of the protective layer 22 may be silicon oxide, and the material of the cover layer 3 may be silicon nitride, silicon oxynitride, silicon boronitride or aluminum oxide. The cover material layer 31 may be formed on the surface of the structure formed by each first semiconductor layer 21 and each second semiconductor layer 23 remaining after etching back by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Figure 5 As shown, the covering material layer 31 can fill up each recess 203. It should be noted that when a protective material layer 24 is formed on the surface of the first semiconductor layer 21 located at the top, for the convenience of process, a covering material layer 31 can be formed on the surface of the protective material layer 24 at the same time, that is, the covering material layer 31 can cover the surface of the protective material layer 24, cover the sidewall and bottom of the groove 201 and fill up the recess 203.

[0066] like Figure 6 As shown, the covering material layer 31 in the area outside the recess 203 can be removed (that is, the side wall of the first semiconductor layer 21 near the groove 201 is exposed), and the remaining covering material layer 31 in the recess 203 is used as the covering layer 3. It should be noted that, in the first direction x, the end surface of the covering layer 3 near the groove 201 is substantially flush with the end surface of the first semiconductor layer 21 near the groove 201.

[0067] Step S330 , forming a protection layer 22 on the end surface of the first semiconductor layer 21 close to the trench 201 .

[0068] like Figure 7 As shown, the protective layer 22 can be formed on the end surface of the first semiconductor layer 21 near the groove 201 by an in-situ water vapor oxidation process. For example, when the material of the first semiconductor layer 21 is silicon, silicon oxide can be formed on the silicon surface by an in-situ water vapor oxidation process, and the silicon oxide can be used as the protective layer 22.

[0069] In an exemplary embodiment of the present disclosure, the material of the first semiconductor layer 21 is silicon, and the material of the cap layer 3 is silicon nitride. Forming the protective layer 22 on the end surface of the first semiconductor layer 21 close to the groove 201 (ie, step S330) may include steps S410 to S430, wherein: Step S410 , forming a metal layer on the surface of the structure formed by the cover layer 3 and the first semiconductor layer 21 .

[0070] In some embodiments of the present disclosure, the material of the metal layer may be titanium, cobalt, nickel or platinum. Figure 8As shown, the metal layer 4 can be formed on the surface of the structure formed by the cover layer 3 and the first semiconductor layer 21 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. It should be noted that when a protective material layer 24 is formed on the surface of the topmost first semiconductor layer 21, for the convenience of the process, the metal layer 4 can be formed on the surface of the protective material layer 24 at the same time, that is, the metal layer 4 can cover the surface and sidewall of the protective material layer 24, cover the end surface of each first semiconductor layer 21 close to the groove 201 and the surface of each cover layer 3.

[0071] Step S420 , heat-treating the metal layer 4 to form a metal silicide layer 41 on the surface of the first semiconductor layer 21 .

[0072] like Fig. 9 As shown, the metal layer 4 may be thermally annealed to diffuse the metal ions in the metal layer 4 into the first semiconductor layer 21, thereby forming a metal silicide layer 41 at the end of the first semiconductor layer 21. For example, when the material of the metal layer 4 is titanium, the material of the metal silicide layer 41 may be titanium silicide; when the material of the metal layer 4 is cobalt, the material of the metal silicide layer 41 may be cobalt silicide; when the material of the metal layer 4 is nickel, the material of the metal silicide layer 41 may be nickel silicide; when the material of the metal layer 4 is platinum, the material of the metal silicide layer 41 may be platinum silicide.

[0073] Step S430 , removing the unreacted metal layer 4 , and using the metal silicide layer 41 as the protective layer 22 .

[0074] After the metal silicide layer 41 is formed, a selective etching process may be used to remove the unreacted metal layer 4. For example, a dry etching process may be used to remove the unreacted metal layer 4, and the etching gas of the dry etching may be reasonably set according to the specific material of the metal layer 4 and the specific material of the metal silicide layer 41, as long as the metal layer 4 can be removed without damaging (or slightly damaging, but not affecting its protective performance for the first semiconductor layer 21) the metal silicide layer 41.

[0075] In an exemplary embodiment of the present disclosure, forming a protective layer 22 on the end surface of the first semiconductor layer 21 near the groove 201 (i.e., step S330) may include: performing ion doping on the end of the first semiconductor layer 21 near the groove 201. For example, ion doping may be performed on the end of the first semiconductor layer 21 near the groove 201 by ion implantation; for example, the doped ions may be accelerated and implanted into the end of the first semiconductor layer 21 near the groove 201 under the action of a high-energy electric field. Alternatively, the structure composed of the first semiconductor layer 21, the second semiconductor layer 23, and the cover layer 3 may be placed in a gas containing doped ions, and the doped ions may be diffused into the first semiconductor layer 21 by high-temperature heating, and the first semiconductor layer 21 containing doped ions may be used as the protective layer 22. In some embodiments of the present disclosure, the material of the doped ions may be boron, phosphorus, or arsenic.

[0076] Step S340, removing the covering layer 3.

[0077] After forming the protection layer 22 , the cover layer 3 in each recess 203 may be removed by isotropic etching, thereby exposing the end of each remaining second semiconductor layer 23 close to the groove 201 , so as to facilitate the subsequent removal of each second semiconductor layer 23 .

[0078] In an exemplary embodiment of the present disclosure, forming the protection layer 22 on the end surface of each first semiconductor layer 21 exposed in the trench 201 (ie, step S230) may include steps S510 and S520, wherein: In step S510, the end of the first semiconductor layer 21 exposed in the groove 201 and the end of the second semiconductor layer 23 exposed in the groove 201 are simultaneously oxidized to form a protective layer 22 in the first semiconductor layer 21 near the end of the groove 201 and a covering layer 3 at the end of the second semiconductor layer 23.

[0079] In some embodiments of the present disclosure, Fig.10As shown, the material of the protective layer 22 covering the end of the first semiconductor layer 21 is different from the material of the capping layer 3 covering the end of the second semiconductor layer 23. For example, when the material of the first semiconductor layer 21 is silicon and the material of the second semiconductor layer 23 is silicon germanium, the ends of the first semiconductor layer 21 and the second semiconductor layer 23 close to the groove 201 can be simultaneously oxidized under low temperature conditions, thereby forming silicon oxide on the surface of the first semiconductor layer 21 and a mixture of silicon oxide and germanium oxide on the surface of the second semiconductor layer 23; for the convenience of distinction, the silicon oxide located on the first semiconductor layer 21 can be defined as the protective layer 22, and the mixture of silicon oxide and germanium oxide located on the second semiconductor layer 23 can be defined as the capping layer 3. In some embodiments of the present disclosure, the low temperature condition can be a temperature condition below 600°C, for example, it can be 600°C, 580°C, 560°C, 540°C, 520°C or 500°C, of ​​course, it can also be other temperature conditions, which are not listed here one by one.

[0080] Step S520, removing the covering layer 3.

[0081] The cover layer 3 on the second semiconductor layer 23 can be removed by isotropic etching, thereby exposing the end of the second semiconductor layer 23 near the groove 201. In this process, since the cover layer 3 and the protective layer 22 are made of different materials, when the same etching solution is used to remove the cover layer 3, the etching rate of the cover layer 3 is greater than the etching rate of the protective layer 22. In the process of removing the cover layer 3, the protective layer 22 is less damaged, and the protective layer 22 is still retained on the surface of the first semiconductor layer 21 after the cover layer 3 is removed.

[0082] In step S240 , each second semiconductor layer 23 is removed to form a gap 202 between adjacent first semiconductor layers 21 .

[0083] like Fig.11 As shown, after forming the protective layer 22, each second semiconductor layer 23 can be removed, thereby forming a gap 202 between two adjacent first semiconductor layers 21 distributed along the second direction y. That is, in the second direction y, the width of the gap 202 is equal to the thickness of the second semiconductor layer 23. For example, when the thickness of the second semiconductor layer 23 is 10nm, the width of the gap 202 in the second direction y is 10nm; when the thickness of the second semiconductor layer 23 is 15nm, the width of the gap 202 in the second direction y is 15nm; when the thickness of the second semiconductor layer 23 is 20nm, the width of the gap 202 in the second direction y is 20nm.

[0084] In some embodiments of the present disclosure, each second semiconductor layer 23 can be removed by wet etching, and the etching solution for wet etching can be selected according to the specific materials of the first semiconductor layer 21, the second semiconductor layer 23 and the protective layer 22; that is, as long as the etching solution can remove the second semiconductor layer 23 and does not damage (or slightly damages but does not affect its performance) the first semiconductor layer 21 and the protective layer 22, the specific solution for wet etching is not particularly limited.

[0085] In an exemplary embodiment of the present disclosure, forming a stacked film layer 2 on a substrate 1 (ie, step S110) may include steps S610 to S660, wherein: Step S610 , forming a plurality of first semiconductor layers 21 and second semiconductor layers 23 alternately distributed along a second direction y on the substrate 1 .

[0086] The specific materials, distribution, quantity, thickness, etc. of the first semiconductor layer 21 and the second semiconductor layer 23 are similar to those of the first semiconductor layer 21 and the second semiconductor layer 23 in step S210, and therefore, they are not described here. Figure 2 As shown, a plurality of first semiconductor layers 21 and a plurality of second semiconductor layers 23 alternately distributed in sequence along the second direction y can be formed on the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition or epitaxial growth process. Of course, each first semiconductor layer 21 and each second semiconductor layer 23 can also be formed by other methods, and the formation method of the first semiconductor layer 21 and the second semiconductor layer 23 is not particularly limited herein.

[0087] In step S620 , the first semiconductor layer 21 and the second semiconductor layer 23 are etched to form a trench 201 penetrating each first semiconductor layer 21 and each second semiconductor layer 23 along the second direction y.

[0088] Please continue to see Figure 2 As shown, each first semiconductor layer 21 and each second semiconductor layer 23 on the substrate 1 may be etched by dry etching to form a trench 201 ; that is, the sidewall of the trench 201 is formed by each first semiconductor layer 21 and each second semiconductor layer 23 .

[0089] In some embodiments of the present disclosure, please continue to refer to Figure 2As shown, before dry etching, a protective material layer 24 may be formed on the surface of the first semiconductor layer 21 located at the top (i.e., the first semiconductor layer 21 farthest from the substrate 1) away from the substrate 1. The protective material layer 24 may cover the surface of the first semiconductor layer 21 located at the top, and the material of the protective material layer 24 is different from the materials of the first semiconductor layer 21 and the second semiconductor layer 23. In the dry etching process, the etching rate of the protective material layer 24 is much lower than the etching rate of the first semiconductor layer 21 and the second semiconductor layer 23, which can ensure that in the process of etching to form the groove 201, the protective material layer 24 always covers the surface of the first semiconductor layer 21 farthest from the substrate 1, thereby protecting the first semiconductor layer 21 farthest from the substrate 1 from damage. For example, the material of the protective material layer 24 may be silicon oxide.

[0090] In some embodiments of the present disclosure, there may be multiple grooves 201 , and the multiple grooves 201 may be spaced apart along the first direction x, so that the structure formed by each first semiconductor layer 21 and each second semiconductor layer 23 may be divided into multiple spaced apart semiconductor groups by the multiple grooves 201 .

[0091] In step S630 , the second semiconductor layer 23 is removed to form the gap 202 .

[0092] like Fig.12 As shown, after the groove 201 is formed, each second semiconductor layer 23 can be removed, thereby forming a gap 202 located between two adjacent first semiconductor layers 21 in the second direction y. For example, each second semiconductor layer 23 can be removed by wet etching, and the etching solution for wet etching can be selected according to the specific materials of the first semiconductor layer 21 and the second semiconductor layer 23; that is, as long as the etching solution can remove the second semiconductor layer 23 and does not damage (or slightly damages but does not affect its performance) the first semiconductor layer 21, the specific solution for wet etching is not particularly limited here.

[0093] Step S640 , forming a covering layer 3 in the gap 202 , wherein the covering layer 3 covers the upper surface and the lower surface of the first semiconductor layer 21 along the second direction y.

[0094] like Fig.13 and Fig.14 As shown, a covering layer 3 can be formed in each gap 202, and the covering layer 3 can completely cover the upper surface and the lower surface of the first semiconductor layer 21 distributed along the second direction y; at the same time, the covering layer 3 does not cover the end surface of the first semiconductor layer 21 close to the groove 201; that is, the end surface of the first semiconductor layer 21 close to the groove 201 is exposed, so as to facilitate the subsequent formation of a protective layer 22 in the end surface of the first semiconductor layer 21 close to the groove 201. In some embodiments of the present disclosure, please continue to refer to Fig.13As shown, the cover layer 3 can conformally cover the upper surface and the lower surface of the first semiconductor layer 21. In other embodiments of the present disclosure, please continue to refer to Fig.14 The cover layer 3 shown can fill the gap 202 between two adjacent first semiconductor layers 21 along the second direction y. The material of the cover layer 3 is different from the material of the first semiconductor layer 21 and the material of the protective layer 22 to be formed subsequently, so as to reduce the damage to the first semiconductor layer 21 and the protective layer 22 during the subsequent removal of the cover layer 3.

[0095] In an exemplary embodiment of the present disclosure, forming a cover layer 3 in the gap 202, and covering the upper surface and the lower surface of the first semiconductor layer 21 along the second direction y with the cover layer 3 (ie, step S640) may include steps S710 to S740, wherein: Step S710 , forming a covering material layer 31 conformally covering the surface of each first semiconductor layer 21 .

[0096] like Fig.15 As shown, the material of the covering material layer 31 is different from that of the first semiconductor layer 21. For example, the material of the covering material layer 31 may be silicon nitride, silicon oxynitride, silicon boronitride or aluminum oxide. The covering material layer 31 that conformally covers the upper surface of the first semiconductor layer 21, the lower surface of the first semiconductor layer 21 and the end surface of the first semiconductor layer 21 near the groove 201 may be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. It should be noted that when the protective material layer 24 is formed on the first semiconductor layer 21 at the top, the covering material layer 31 will not be formed on the upper surface of the first semiconductor layer 21 at the top, and the covering material layer 31 is formed on the top and sidewalls of the protective material layer 24.

[0097] In some embodiments of the present disclosure, the thickness of the covering material layer 31 is less than half the width of the gap 202 between two adjacent first semiconductor layers 21 in the second direction y, that is, the covering material layer 31 does not fill the gap 202 between two adjacent first semiconductor layers 21 in the second direction y.

[0098] Step S720 , forming a filling layer 5 between the first semiconductor layers 21 having the covering material layer 31 , wherein the filling layer 5 fills the gap 202 between adjacent first semiconductor layers 21 .

[0099] The material of the filling layer 5 is different from that of the covering material layer 31. For example, the material of the filling layer 5 is silicon oxide. The filling layer 5 can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. For the convenience of the process, the filling layer 5 can simultaneously cover the covering material layer 31 located on the end surface of the first semiconductor layer 21 close to the groove 201 and the covering material layer 31 located on the top of the stacked film layer 2. Fig.16 As shown, the filling layer 5 on the top of the stacked film layer 2 and the filling layer 5 on the sidewall of the trench 201 can be removed, thereby exposing the covering material layer 31 on the end surface of the first semiconductor layer 21 close to the trench 201.

[0100] Step S730 , removing the covering material layer 31 on the end surface of the first semiconductor layer 21 close to the trench 201 to expose the end surface of the first semiconductor layer 21 close to the trench 201 .

[0101] like Fig.17 As shown, the covering material layer 31 on the end surface of the first semiconductor layer 21 near the groove 201 can be removed by a dry etching process, thereby exposing the end surface of the first semiconductor layer 21 near the groove 201, so as to facilitate the subsequent formation of the protective layer 22 on the end surface. The etching gas for dry etching can be reasonably set according to the specific materials of the first semiconductor layer 21 and the covering material layer 31, as long as the covering material layer 31 can be removed without damaging the first semiconductor layer 21 (or slightly damaging it but not affecting the performance of the first semiconductor layer 21), and no special limitation is made here on the etching gas for removing the covering material layer 31.

[0102] Step S740 , removing the filling layer 5 , and using the remaining covering material layer 31 as the covering layer 3 .

[0103] Please continue to see Fig.13 As shown, the filling layer 5 can be removed by wet etching, and the etching solution of the wet etching can be reasonably set according to the specific materials of the filling layer 5, the first semiconductor layer 21 and the covering material layer 31. As long as the filling layer 5 can be removed without damaging the first semiconductor layer 21 and the covering material layer 31 (or slightly damaging, but not affecting the electrical properties of the first semiconductor layer 21, and not affecting the protective properties of the covering material layer 31), the etching solution for removing the filling layer 5 is not particularly limited. It should be noted that when the materials of the protective material layer 24 and the filling layer 5 are the same, when removing the filling layer 5, the thickness of the protective material layer 24 can be simultaneously thinned.

[0104] In some other embodiments of the present disclosure, forming a cover layer 3 in the gap 202, and covering the upper surface and the lower surface of the first semiconductor layer 21 along the second direction y with the cover layer 3 (ie, step S640) may include steps S810 and S820, wherein: In step S810 , a covering material layer 31 is formed on the surface of each first semiconductor layer 21 , and the covering material layer 31 fills the gap 202 .

[0105] like Fig.18As shown, the material of the covering material layer 31 is different from the material of the first semiconductor layer 21. For example, the material of the covering material layer 31 may be silicon nitride, silicon oxynitride, silicon boronitride or aluminum oxide. The covering material layer 31 may be formed on the surface of the stacked film layer 2 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this process, the covering material layer 31 may fill the gap 202 between the adjacent first semiconductor layers 21 in the second direction y. It should be noted that in the process of forming the covering material layer 31, for the convenience of the process, the covering material layer 31 may be formed simultaneously on the end surface of the first semiconductor layer 21 near the groove 201 and on the top of the stacked film layer 2 (for example, on the protective material layer 24).

[0106] Step S820 , removing the covering material layer 31 on the end surface of the first semiconductor layer 21 close to the groove 201 to expose the end surface of the first semiconductor layer 21 close to the groove 201 , and using the remaining covering material layer 31 as the covering layer 3 .

[0107] Please continue to see Fig.14 As shown, the covering material layer 31 located on the top of the stacked film layer 2 (for example, on the protective material layer 24 ) and on the end surface of the first semiconductor layer 21 close to the groove 201 can be removed by a dry etching process, and the remaining covering material layer 31 is used as the covering layer 3 .

[0108] Step S650 , forming a protection layer 22 on an end surface of the first semiconductor layer 21 close to the trench 201 .

[0109] like Fig.19 As shown, a protective layer 22 can be formed on the end surface of the first semiconductor layer 21 near the groove 201 by an in-situ water vapor oxidation process. For example, when the material of the first semiconductor layer 21 is silicon, the material of the protective layer 22 is silicon oxide. It should be noted that during the in-situ water vapor oxidation process, since the upper surface and the lower surface of the first semiconductor layer 21 are covered by other film layers (for example, the cover layer 3 or the protective material layer 24), the protective layer 22 will not be formed on the upper surface and the lower surface of the first semiconductor layer 21.

[0110] Step S660 , removing the cover layer 3 to expose the gap 202 .

[0111] Please continue to see Fig.11 As shown, after forming the protection layer 22, the cover layer 3 can be removed by an isotropic etching process, thereby exposing the upper surface and the lower surface of the first semiconductor layer 21 distributed along the second direction y. It should be noted that when the surface of the first semiconductor layer 21 at the top is also covered with the protection material layer 24, the lower surface of the first semiconductor layer 21 at the top is exposed, while the upper surface is not exposed.

[0112] like Figure 1 As shown, in step S120 , the first semiconductor layer 21 is etched to reduce the thickness of the first semiconductor layer 21 ; the etching rate of the protection layer 22 is lower than the etching rate of the first semiconductor layer 21 .

[0113] like Fig. 20 As shown, the first semiconductor layer 21 can be etched by a wet etching process, thereby reducing the thickness of the first semiconductor layer 21, thereby leaving a larger process space for the subsequent preparation of word lines between two adjacent first semiconductor layers 21 distributed along the second direction y, which helps to reduce the process difficulty of subsequent word line production. In addition, in the process of etching and thinning the first semiconductor layer 21, since a protective layer 22 is formed on the end surface of each first semiconductor layer 21 exposed in the groove 201, and the etching rate of the protective layer 22 is lower than the etching rate of the first semiconductor layer 21, in the process of etching and thinning the first semiconductor layer 21, the end of the first semiconductor layer 21 close to the groove 201 can be protected by the protective layer 22, which can reduce the damage to the first semiconductor layer 21 in the first direction x during the etching process, so that the spacing between the semiconductor groups on both sides of the groove 201 is relatively small, and more semiconductor groups can be arranged on the substrate 1 along the first direction x, which helps to prepare more chip units on the substrate 1. That is, the storage density can be improved without increasing the number of layers of the first semiconductor layer 21.

[0114] In an exemplary embodiment of the present disclosure, the method for forming a semiconductor structure of the present disclosure may further include: Step S130 , after reducing the thickness of the first semiconductor layer 21 , removing the protective layer 22 .

[0115] like Fig.21 As shown, the protective layer 22 can be removed by a dry etching process. It should be noted that when the material of the protective layer 22 is titanium silicide or doped silicon, the protective layer 22 can also be retained and used as a functional layer of the chip unit to be formed subsequently. When the material of the protective layer 22 and the material of the protective material layer 24 are both silicon oxide, in the process of removing the protective layer 22, the protective material layer 24 can be thinned, or the protective material layer 24 can be removed simultaneously.

[0116] It should be noted that, although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0117] The present disclosure also provides a semiconductor structure, which can be formed by the method for forming a semiconductor structure of any of the above embodiments. In some embodiments of the present disclosure, in the semiconductor structure formed by the method for forming a semiconductor structure in the present disclosure, after thinning the first semiconductor layer 21, the thickness of the first semiconductor layer 21 lost on both sides of the groove 201 in the first direction x is about 2.5nm, which is about 1.3% of the length of the first semiconductor layer 21 in the first direction x before thinning the first semiconductor layer 21 (180nm). Compared with the prior art (the loss after thinning the first semiconductor layer 21 is about 9.5%), the loss in the formation method of the present application is reduced by 86%.

[0118] The specific details and manufacturing processes of each part of the above-mentioned semiconductor structure have been described in detail in the corresponding semiconductor structure forming method, and therefore, they will not be repeated here.

[0119] For example, the semiconductor structure may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Of course, it may also be other storage devices, which are not listed here one by one.

[0120] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: A stacked film layer is formed on a substrate, the stacked film layer comprising a plurality of first semiconductor layers and a protective layer, the plurality of first semiconductor layers extend along a first direction and are spaced apart along a second direction, and there is a gap between two adjacent first semiconductor layers along the second direction, and the second direction intersects with the first direction; the stacked film layer has a groove, the groove penetrates each of the first semiconductor layers along the second direction; and the protective layer is respectively formed on the end surface of each of the first semiconductor layers exposed in the groove; The first semiconductor layer is etched to reduce the thickness of the first semiconductor layer; and the etching rate of the protection layer is lower than the etching rate of the first semiconductor layer.

2. The forming method according to claim 1, characterized in that: The forming of a stacked film layer on a substrate comprises: forming a plurality of first semiconductor layers and second semiconductor layers alternately distributed along the second direction on the substrate; Etching the first semiconductor layer and the second semiconductor layer to form a groove penetrating each of the first semiconductor layers and each of the second semiconductor layers along the second direction; forming the protective layer on the end surface of each of the first semiconductor layers exposed in the groove; Each of the second semiconductor layers is removed to form the gap between adjacent first semiconductor layers.

3. The forming method according to claim 2, characterized in that: The forming of the protective layer on the end surface of each of the first semiconductor layers exposed in the grooves comprises: Etching back the end of the second semiconductor layer close to the trench to form a recess; forming a covering layer in the recess; forming the protective layer on an end surface of the first semiconductor layer close to the groove; The covering layer is removed.

4. The forming method according to claim 2, characterized in that: The forming of the protective layer on the end surface of each of the first semiconductor layers exposed in the grooves comprises: Synchronously oxidizing the end of the first semiconductor layer exposed in the trench and the end of the second semiconductor layer exposed in the trench to form the protection layer in the first semiconductor layer near the end of the trench and to form a capping layer at the end of the second semiconductor layer; The covering layer is removed.

5. The forming method according to claim 3, characterized in that: The material of the first semiconductor layer is silicon, the material of the cover layer is silicon nitride, and the protective layer is formed on the end surface of the first semiconductor layer close to the groove, comprising: forming a metal layer on a surface of a structure formed by the cover layer and the first semiconductor layer; thermally treating the metal layer to form a metal silicide layer on a surface of the first semiconductor layer; The unreacted metal layer is removed, and the metal silicide layer is used as the protective layer.

6. The forming method according to claim 3, characterized in that: The step of forming a protective layer on an end surface of the first semiconductor layer close to the trench comprises: Ion doping is performed on an end portion of the first semiconductor layer close to the trench, and the first semiconductor layer containing doped ions is used as the protection layer.

7. The forming method according to claim 1, characterized in that: The forming of a stacked film layer on a substrate comprises: forming a plurality of first semiconductor layers and second semiconductor layers alternately distributed along the second direction on the substrate; Etching the first semiconductor layer and the second semiconductor layer to form a groove penetrating each of the first semiconductor layers and each of the second semiconductor layers along the second direction; removing the second semiconductor layer to form the gap; forming a covering layer in the gap, wherein the covering layer covers the upper surface and the lower surface of the first semiconductor layer distributed along the second direction; forming the protective layer in the first semiconductor layer near the end surface of the trench; The cover layer is removed to expose the gap.

8. The forming method according to claim 7, characterized in that: The forming of a covering layer in the gap, wherein the covering layer covers the upper surface and the lower surface of the first semiconductor layer distributed along the second direction, comprises: forming a covering material layer conformally covering the surface of each of the first semiconductor layers; forming a filling layer between the first semiconductor layers having the covering material layer, wherein the filling layer fills the gap between adjacent first semiconductor layers; removing the covering material layer on the end surface of the first semiconductor layer close to the groove to expose the end surface of the first semiconductor layer close to the groove; The filling layer is removed, and the remaining covering material layer is used as the covering layer.

9. The forming method according to claim 7, characterized in that: The forming of a covering layer in the gap, wherein the covering layer covers the upper surface and the lower surface of the first semiconductor layer distributed along the second direction, comprises: forming a covering material layer on the surface of each of the first semiconductor layers, wherein the covering material layer fills the gap; The covering material layer on the end surface of the first semiconductor layer close to the trench is removed to expose the end surface of the first semiconductor layer close to the trench, and the remaining covering material layer is used as the covering layer.

10. The forming method according to any one of claims 1 to 4 and 7 to 9, characterized in that: The forming method further comprises: After reducing the thickness of the first semiconductor layer, the protection layer is removed.

11. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 10.

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