Semiconductor memory device

Abstract

The embodiment of the invention provides a semiconductor memory device with good connection between a selection gate line and a contact. A semiconductor memory device according to one embodiment of the present invention is provided with: a plurality of first conductor layers stacked in a first direction; a first semiconductor layer extending in the first direction in the plurality of first conductor layers; a first charge accumulation layer provided between the plurality of first conductor layers and the first semiconductor layer; a plurality of second conductor layers laminated in the first direction above the plurality of first conductor layers; and a third conductor layer which extends in the first direction from the upper surface of the lowermost layer among the plurality of second conductor layers in one or more layers other than the lowermost layer among the plurality of second conductor layers, and which is in contact with the upper surface of each of the plurality of second conductors.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with an application date of July 25, 2019, application number 201910687436.5, and invention name “Semiconductor Memory Device”.

[0003] [Related applications]

[0004] This application claims priority based on Japanese Patent Application No. 2019-53449 (filing date: March 20, 2019). This application incorporates the entire contents of the basic application by reference. Technical Field

[0005] Embodiments relate to a semiconductor memory device. Background Art

[0006] As a semiconductor memory device capable of storing data in a non-volatile manner, a NAND (Not AND) flash memory is known. In semiconductor memory devices such as the NAND flash memory, a three-dimensional memory structure is increasingly being adopted in order to achieve high integration and large capacity. A structure for leading out contacts connected to a build-up wiring layer in the three-dimensional memory structure is known. Summary of the invention

[0007] Embodiments provide a semiconductor memory device having good connection between a selection gate line and a contact.

[0008] A semiconductor storage device in one embodiment comprises: a plurality of first conductor layers stacked in a first direction; a first semiconductor layer extending along the first direction within the plurality of first conductor layers; a first charge accumulation layer arranged between the plurality of first conductor layers and the first semiconductor layer; a plurality of second conductor layers stacked along the first direction above the plurality of first conductor layers; and a third conductor layer extending along the first direction from the upper surface of the lowest layer among the plurality of second conductor layers within one or more layers other than the lowest layer among the plurality of second conductor layers, and being in contact with the upper surfaces of each of the plurality of second conductors.

[0009] Preferably, a first cross section of the third conductor layer along the lower surface of an upper one of two adjacent second conductor layers in the first direction is similar to a second cross section of the third conductor layer on the lower surface of the lower one of the two adjacent second conductor layers.

[0010] Preferably, the difference between the diameter of the first cross section and the diameter of the second cross section corresponds to the difference in length of the two adjacent second conductive layers along a second direction intersecting the first direction.

[0011] Preferably, when viewed from the first direction, the outer edge of the first cross section is located at a substantially equal width from the outer edge of the second cross section.

[0012] Ideally, the semiconductor storage device also has a first insulating layer and includes a first part and a second part, wherein the first part divides the multiple second conductive layers into a first region and a second region arranged along a third direction intersecting the first direction and the second direction, and the second part extends along the third direction to divide the first region into a third region and a fourth region arranged along the second direction.

[0013] Preferably, the third conductive layer is provided in the third region or the fourth region of the plurality of second conductive layers.

[0014] A semiconductor storage device in another embodiment comprises: a plurality of first conductive layers stacked in a first direction; a first semiconductor layer extending along the first direction within the plurality of first conductive layers; a first charge accumulation layer arranged between the plurality of first conductive layers and the first semiconductor layer; a plurality of second conductive layers stacked along the first direction above the uppermost layer among the plurality of first conductive layers; and a first insulating layer comprising a first portion and a second portion, the first portion extending along a second direction intersecting the first direction to divide the plurality of second conductive layers into a first region and a second region arranged along a third direction intersecting the first direction and the second direction, and the second portion extending along the third direction to divide the first region into a third region and a fourth region arranged along the second direction.

[0015] Preferably, the semiconductor memory device further includes a third conductive layer extending in the first direction in the third region or the fourth region of the plurality of second conductive layers and electrically connecting the plurality of second conductive layers to each other.

[0016] Preferably, the third conductive layer extends from the upper surface of the lowest layer among the plurality of second conductive layers along the first direction in one or more layers other than the lowest layer among the plurality of second conductive layers.

[0017] Preferably, the third conductor layer is in contact with the upper surface of each of the plurality of second conductors.

[0018] Ideally, the upper end of the third conductor layer is located higher than the upper surface of the uppermost layer among the multiple second conductor layers, and the semiconductor storage device also has a fourth conductor layer, which extends from the upper end of the third conductor layer along the first direction and has a diameter smaller than that of the third conductor layer.

[0019] Preferably, the first portion and the second portion of the first insulating layer are provided in a T-shape when viewed from the first direction.

[0020] Ideally, the third conductor layer extends along the first direction within the plurality of second conductor layers, the lower end of the third conductor layer is located on the same layer as the lower end of the first insulating layer, and the upper end of the third conductor layer is located on the same layer as the upper end of the first insulating layer.

[0021] A semiconductor storage device in another embodiment comprises: a plurality of first conductor layers stacked in a first direction; a first semiconductor layer extending along the first direction within the plurality of first conductor layers; a first charge accumulation layer arranged between the plurality of first conductor layers and the first semiconductor layer; a plurality of second conductor layers stacked along the first direction above the uppermost layer among the plurality of first conductor layers; a third conductor layer extending along the first direction within the plurality of second conductor layers and connected to each of the plurality of second conductor layers; and a first insulator layer dividing the plurality of second conductor layers into a first region and a second region along a surface including the first direction and a second direction intersecting the first direction; and the lower end of the third conductor layer is located on the same layer as the lower end of the first insulator layer, and the upper end of the third conductor layer is located on the same layer as the upper end of the first insulator layer.

[0022] Preferably, the first semiconductor layer further extends in the first direction within the plurality of second conductive layers, and the first charge storage layer is further provided between the plurality of second conductive layers and the first semiconductor layer.

[0023] Preferably, the semiconductor storage device further comprises:

[0024] a second semiconductor layer extending in the first direction within the plurality of second conductive layers; and a second insulating layer provided between the plurality of second conductive layers and the second semiconductor layer.

[0025] Preferably, the second insulating layer includes a second charge storage layer.

[0026] According to the embodiment, it is possible to provide a semiconductor memory device in which the connection between the selection gate line and the contact is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a block diagram showing the overall configuration of a memory system including the semiconductor memory device according to the first embodiment.

[0028] Figure 2 This is a circuit diagram showing a portion of a memory cell array of the semiconductor memory device according to the first embodiment.

[0029] Figure 3 This is a plan view of the memory cell array of the semiconductor memory device according to the first embodiment as viewed from above.

[0030] Figure 4 It is along Figure 3 A cross-sectional view of a cell region of a memory cell array along line IV-IV.

[0031] Figure 5 It is along Figure 4 A cross-sectional view of the lower portion of the memory column of the VV line.

[0032] Figure 6 It is along Figure 4 A cross-sectional view of the upper portion of the memory column along line VI-VI.

[0033] Figure 7 It is along Figure 3 A cross-sectional view of the wiring area of ​​the memory cell array taken along line VII-VII.

[0034] Figure 8 Yes Figure 3 A top view of region VIII of the selection gate line is enlarged and viewed from above.

[0035] Figure 9 to Figure 24 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the first embodiment.

[0036] Fig.25 This is a plan view of a memory cell array of a comparative example for explaining the effects of the semiconductor memory device according to the first embodiment, as viewed from above.

[0037] Fig.26 It is along Fig.25 A cross-sectional view of the wiring area of ​​the memory cell array taken along line XXVI-XXVI.

[0038] Fig. 27 This is a plan view of a memory cell array of a semiconductor memory device according to a first variation of the first embodiment, as viewed from above.

[0039] Fig.28 It is along Fig. 27A cross-sectional view of the wiring area of ​​the memory cell array along line XXVIII-XXVIII.

[0040] Fig.29 This is a plan view of a memory cell array of a semiconductor memory device according to a second variation of the first embodiment, as viewed from above.

[0041] Fig.30 It is along Fig.29 A cross-sectional view of the wiring area of ​​the memory cell array along line XXX-XXX.

[0042] Fig.31 It is a cross-sectional view of a wiring region of a memory cell array of a semiconductor memory device according to a second embodiment.

[0043] Figure 32 to Figure 43 It is a cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the second embodiment. DETAILED DESCRIPTION

[0044] The following describes the embodiments with reference to the accompanying drawings. Each embodiment illustrates an apparatus or method for realizing the technical idea of ​​the invention. The accompanying drawings are schematic or conceptual drawings, and the dimensions and ratios of the drawings are not necessarily the same as the actual ones. The technical idea of ​​the present invention is not specified by the shape, structure, configuration, etc. of the constituent elements.

[0045] In addition, in the following description, the same symbols are used for components having substantially the same function and structure. The numbers after the characters constituting the reference symbols are referenced by the reference symbols containing the same characters and are used to distinguish the components having the same structure from each other. In the case where it is not necessary to distinguish the components represented by the reference symbols containing the same characters from each other, these components are respectively referenced by the reference symbols containing only the characters.

[0046] In the following description, the "diameter" of a layer means the average value of the diameter of the outer side of the layer in a cross section parallel to the stacking surface of the layer. The "center" of a cross section of a layer means the centroid of the cross section.

[0047] 1. First Implementation Method

[0048] A semiconductor memory device according to the first embodiment will be described.

[0049] 1.1 Composition

[0050] First, the configuration of the semiconductor memory device according to the first embodiment will be described.

[0051] 1.1.1 Semiconductor storage devices

[0052] Figure 1This is a block diagram for explaining the configuration of a semiconductor memory device according to Embodiment 1. Semiconductor memory device 1 is a NAND flash memory capable of storing data nonvolatilely, and is controlled by an external memory controller 2. Communication between semiconductor memory device 1 and memory controller 2 supports, for example, the NAND interface standard.

[0053] like Figure 1 As shown, the semiconductor memory device 1 includes, for example, a memory cell array 10 , a command register 11 , an address register 12 , a sequencer 13 , a driver module 14 , a row decoder module 15 , and a sense amplifier module 16 .

[0054] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer greater than 1). The block BLK is a collection of a plurality of memory cells capable of storing data in a non-volatile manner, and is used, for example, as a unit for deleting data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one word line. The detailed structure of the memory cell array 10 is described below.

[0055] The command register 11 stores the command CMD received by the semiconductor storage device 1 from the memory controller 2. The command CMD includes, for example, a command for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, or the like.

[0056] The address register 12 stores the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used to select the block BLK, the word line, and the bit line, respectively.

[0057] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16 based on the command CMD stored in the command register 11, and performs read operation, write operation, erase operation, and the like.

[0058] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. The driver module 14 applies the generated voltages to signal lines corresponding to selected word lines based on, for example, the page address PA stored in the address register 12 .

[0059] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA stored in the address register 12. The row decoder module 15 transmits, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0060] The sense amplifier module 16 applies a desired voltage to each bit line in a write operation according to the write data DAT received from the memory controller 2. In addition, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line in a read operation, and transmits the determination result to the memory controller 2 as the read data DAT.

[0061] The semiconductor storage device 1 and the memory controller 2 described above can also be combined to form a semiconductor device. TM A memory card such as a Secure Digital (Secure Digital) card or an SSD (solid state drive).

[0062] 1.1.2 Circuit structure of memory cell array

[0063] Figure 2 This is a circuit diagram for explaining the configuration of a memory cell array of the semiconductor memory device according to the first embodiment. Figure 2 The block BLK among the plurality of blocks BLK included in the memory cell array 10 is shown.

[0064] like Figure 2 As shown, the block BLK includes, for example, 4 string components SU0-SU3. Each string component SU includes a plurality of NAND strings NS associated with bit lines BL0-BLm (m is an integer greater than 1). Each NAND string NS includes, for example, memory cell transistors MT0-MT7, and selection transistors ST1 and ST2. The memory cell transistor MT includes a control gate and a charge accumulation layer, and stores data non-volatilely. The selection transistors ST1 and ST2 are respectively used to select the string component SU during various operations.

[0065] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL, and the source of the selection transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The drain of the selection transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the selection transistor ST2 is connected to the source line SL.

[0066] In the same block BLK, control gates of memory cell transistors MT0-MT7 are commonly connected to word lines WL0-WL7. Gates of select transistors ST1 in string units SU0-SU3 are commonly connected to select gate lines SGD0-SGD3. Gates of select transistors ST2 are commonly connected to select gate line SGS.

[0067] In the circuit configuration of the memory cell array 10 described above, the bit line BL is shared by the NAND strings NS assigned the same column address in each string unit SU. The source line SL is shared by, for example, a plurality of blocks BLK.

[0068] A collection of a plurality of memory cell transistors MT connected to a common word line WL in a string unit SU is, for example, referred to as a unit unit CU. For example, the storage capacity of a unit unit CU including memory cell transistors MT each storing 1 bit of data is defined as "1 page of data". The unit unit CU may have a storage capacity of more than 2 pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0069] In addition, the circuit structure of the memory cell array 10 of the semiconductor memory device 1 of the first embodiment is not limited to the structure described above. For example, the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number. The number of string components SU included in each block BLK can be designed to be any number.

[0070] 1.1.3 Structure of Memory Cell Array

[0071] Hereinafter, an example of the structure of the memory cell array of the semiconductor memory device according to the first embodiment will be described.

[0072] In addition, in the drawings referred to below, the X-axis corresponds to the extension direction of the word line WL, the Y-axis corresponds to the extension direction of the bit line BL, and the Z-axis corresponds to the vertical direction relative to the surface of the semiconductor substrate forming the semiconductor memory device 1. In the top view, shadows are appropriately added for easy viewing of the figure. The shadows added in the top view are not necessarily related to the raw materials or characteristics of the components to which the shadows are added. In the cross-sectional view, components such as the insulator layer (interlayer insulating film), wiring, and contacts are appropriately omitted for easy viewing of the figure.

[0073] 1.1.3.1 Floor plan

[0074] Figure 3 FIG. 1 is a top view for explaining the planar layout of the memory cell array of the semiconductor memory device according to the first embodiment. Figure 3 , as an example, a unit area CA including structures corresponding to string units SU0 to SU3 in a certain block BLK and a part of a wiring area HA where contacts CC are led out from the build-up wiring layer of each string unit SU are shown.

[0075] like Figure 3As shown, the memory cell array 10 includes, for example, a slit SHE, a plurality of slits SLT, a memory column MP, contacts CP and CC, a bit line BL, and a stacked wiring layer. The slit SHE includes a plurality of slits SHE_X and a slit SHE_Y. The plurality of stacked wiring layers include, for example, three layers of selection gate lines SGD (including SGD0 to SGD3 and SGDX located in the same layer respectively), seven layers of word lines WL0 to WL7, and one layer of selection gate line SGS. A plurality of memory columns MP, contacts CP, and bit lines BL are provided in a cell area CA, and a plurality of contacts CC are provided in a wiring area HA.

[0076] A plurality of built-up wiring layers are built up along the Z axis in the order of the selection gate line SGS, the word lines WL0 to WL7 , and the selection gate line SGD from the semiconductor substrate side.

[0077] The plurality of slits SLT are respectively arranged along a specified direction (in Figure 3 The X-axis in the figure extends along the direction intersecting the specified direction (in Figure 3 The plurality of slits SHE_X also extend along the X axis and are arranged along the Y direction between adjacent slits SLT. The slit SHE_Y extends along the Y axis, with both ends reaching adjacent slits SLT. The width of the slit SLT is, for example, greater than the width of the slit SHE. The slit SLT, as well as SHE_X and SHE_Y, include an insulator. The slit SLT, for example, Figure 4 The stacked wiring layers corresponding to the word lines WL, the selection gate lines SGD, and the selection gate lines SGS described below are separated. That is, the slits SLT insulate and separate the string components SU0 to SU3 from other string components (not shown) adjacent to these string components SU0 to SU3. In addition, the slits SHE_X and SHE_Y mutually separate the stacked wiring layers corresponding to the selection gate lines SGD0 to SGD3 corresponding to the string components SU0 to SU3, and the selection gate lines SGDX that do not correspond to any string component SU, and insulate and separate them.

[0078] Thus, the regions separated by the slits SLT and SHE_X and SHE_Y constitute the string units SU0 to SU3. Figure 3 The layout shown is formed by repeatedly configuring the same layout along the Y axis.

[0079] exist Figure 3In the cell area CA, a plurality of memory pillars MP are arranged in a staggered shape of, for example, 16 columns in the area between adjacent slits SLT. That is, in each string component SU0 to SU3, a plurality of memory pillars MP are arranged in a staggered shape of 4 columns. The plurality of memory pillars MP respectively have a portion (lower pillar LP) formed in the memory hole and a portion (upper pillar UP) formed in the SGD hole. The upper pillar UP is arranged at an upper layer than the lower pillar LP, for example, with a smaller diameter than the lower pillar LP.

[0080] That is, when the plane of the memory cell array is viewed from above, the corresponding groups of upper columns UP and lower columns LP have overlapping parts. In this view, the central axis of the corresponding upper column UP may overlap with the central axis of the lower column LP, or may not overlap. In addition, the central axis is defined as the axis passing through the center of any XY cross section of the upper column UP and the lower column LP along the Z axis. For example, any XY cross section is the surface where the upper column UP and the lower column LP meet. Figure 3 In a top view, the lower column LP is arranged in a manner not to overlap with the slit SHE_X. In addition, with respect to the memory column MP arranged near the slit SHE_X or the slit SLT, the central axis of the upper column UP is arranged to be offset relative to the central axis of the lower column LP in a direction away from the nearby slit SHE_X or SLT. In this way, in the semiconductor storage device 1 of the first embodiment, the slit SHE_X or SLT can be designed to avoid contact with the memory column MP.

[0081] The plurality of bit lines BL extend along the Y axis and are arranged along the X axis. In a plan view, each bit line BL is arranged so as to overlap at least one upper pillar UP in each string assembly SU, and two bit lines BL overlap each upper pillar UP. A contact CP is provided between one bit line BL among the plurality of bit lines BL overlapping the upper pillar UP and the upper pillar UP. The string assembly SU is electrically connected to the corresponding bit line BL via the contact CP formed on the upper pillar UP.

[0082] exist Figure 3 In the wiring area HA, the portion of the three layers of selection gate lines SGD corresponding to the selection gate line SGDX forms a step shape in the direction away from the cell area CA along the X-axis. That is, in a plan view, the three layers of stacked wiring layers constituting the selection gate line SGDX are longer along the X-axis as the wiring layers at the lower layers are, and have an area that does not overlap with the wiring layers at the upper layers.

[0083] The group of word lines WL5 to WL7, the group of word lines WL2 to WL4, and the group of selection gate lines SGS and word lines WL0 to WL1 form a step shape along the X-axis. That is, in a plan view, the group of word lines WL5 to WL7 is longer along the X-axis than the selection gate line SGD, and has a region A that does not overlap with the selection gate line SGD. The group of word lines WL2 to WL4 is longer along the X-axis than the group of word lines WL5 to WL7, and has a region B that does not overlap with the region A of the group of word lines WL5 to WL7. The group of selection gate lines SGS and word lines WL0 to WL1 is longer along the X-axis than the group of word lines WL2 to WL4, and has a region C that does not overlap with the region B of the group of word lines WL2 to WL4.

[0084] In addition, the group of word lines WL5 to WL7, the group of word lines WL2 to WL4, and the group of selection gate lines SGS and word lines WL0 to WL1 further form a step shape along the Y axis at the end of the step shape along the X axis. That is, in region A, word line WL6 has a region T_WL6 that does not overlap with region T_WL7 of word line WL7, word line WL5 has a region T_WL5 that does not overlap with regions T_WL6 and T_WL7, and regions T_WL5 to T_WL7 are arranged along the Y axis. In region B, word line WL3 has a region T_WL3 that does not overlap with region T_WL4 of word line WL4, word line WL2 has a region T_WL2 that does not overlap with regions T_WL3 and T_WL4, and regions T_WL2 to T_WL4 are arranged along the Y axis. In region C, word line WL0 has region T_WL0 that does not overlap region T_WL1 of word line WL1, and selection gate line SGS has region T_SGS that does not overlap regions T_WL0 and T_WL1. Regions T_SGS, T_WL0, and T_WL1 are arranged along the Y axis.

[0085] Contacts CC_SGD0 to CC_SGD3, CC_WL0 to CC_WL7, and CC_SGS are respectively provided on selection gate lines SGD0 to SGD3, regions T_WL0 to T_WL7 of word lines WL0 to WL7, and region T_SGS of selection gate line SGS. Contacts CC_SGD0 to CC_SGD3 are in contact with the upper surfaces of the three stacked wiring layers of selection gate lines SGD0 to SGD3, respectively. The diameter of contact CC_SGD on the upper surface of the uppermost layer of selection gate line SGD is larger than the diameters of contacts CC_WL and CC_SGS. Regarding the diameter of contact CC_SGD, Figure 8 Described in detail.

[0086] In addition, the planar layout of the memory cell array 10 described above is only an example and is not limited to this. For example, the number of slits SHE arranged between adjacent slits SLT or the number of string components SU can be designed arbitrarily. In addition, the number and arrangement of memory columns MP, or the bit lines BL connected to the memory columns MP, etc. can also be designed arbitrarily. In addition, the number of steps of the step shape along the Y axis in the arrangement of the regions T_SGS and T_WL0~W_TL7 can also be designed arbitrarily, and the step difference can also be not set along the Y axis.

[0087] 1.1.3.2 Unit area

[0088] Figure 4 It means that along the IV-IV line Figure 3 An example of a cross-sectional structure obtained by cutting the memory cell array 10 of the semiconductor memory device according to the first embodiment. Figure 4 As shown, a conductive layer 21 is provided above the semiconductor substrate 20 via an insulator layer (not shown). A circuit such as the sense amplifier module 16 can be provided on the insulator layer. The conductive layer 21 is formed, for example, in a plate shape extending along the XY plane, and serves as a source line SL. The conductive layer 21 includes, for example, silicon (Si).

[0089] A conductive layer 22 is provided above the conductive layer 21 via an insulating layer (not shown). The conductive layer 22 serves as a selection gate line SGS.

[0090] A plurality of insulating layers (not shown) and conductive layers 23 are alternately stacked on the conductive layer 22. The conductive layers 23 are used as word lines WL0 to WL7 in order from the semiconductor substrate 20. The conductive layers 22 and 23 are formed in a plate shape extending along the XY plane, for example, and contain tungsten (W).

[0091] On top of the conductor layer 23 stacked on the top layer, multiple layers of insulator layers (not shown) and conductor layers 24 are alternately stacked. The Z-direction spacing between the top conductor layer 23 and the bottom conductor layer 24 is greater than the Z-direction spacing between adjacent conductor layers 23 or between conductor layers 24. In other words, the thickness of the insulator layer (INS, not shown) between the top conductor layer 23 and the bottom conductor layer 24 is thicker than the thickness of the insulator layer between adjacent conductor layers 23 or between conductor layers 24. The stacked multiple conductor layers 24 are used as selection gate lines SGDa, SGDb, and SGDc in order from the semiconductor substrate 20 side, and the selection transistor ST1 is provided in the portion of the upper pillar UP corresponding to the selection gate lines SGDa to SGDc. The conductor layer 24 is formed, for example, in a plate shape extending along the XY plane, and contains, for example, tungsten (W).

[0092] A conductor layer 25 is provided above the uppermost conductor layer 24 via an insulating layer (not shown). For example, the conductor layer 25 extends along the Y axis and a plurality of conductor layers are arranged in a line along the X axis, each serving as a bit line BL. The conductor layer 25 includes, for example, copper (Cu).

[0093] The memory pillar MP is provided to extend along the Z axis. Specifically, the lower pillar LP of the memory pillar MP penetrates the conductive layers 22 and 23 and has its bottom in contact with the conductive layer 21. The upper pillar UP of the memory pillar MP penetrates the conductive layer 24 and is in contact with the lower pillar LP.

[0094] In addition, the lower pillar LP in the memory pillar MP includes, for example, a core component 30, a semiconductor layer 31, a stacked film 32, and a semiconductor portion 33, and the upper pillar UP includes, for example, a core component 40, a semiconductor layer 41, a semiconductor layer 42, a stacked film 43, and a semiconductor portion 44. The upper pillar UP is formed in such a way that a part of the semiconductor layer 41 is embedded in the upper end of the lower pillar LP, thereby being electrically connected well to the lower pillar LP.

[0095] The core component 30 of the lower column LP extends along the Z axis, and its upper end is located, for example, above the uppermost conductive layer 23, and the lower end of the core component 30 of the upper column UP is located, for example, within the conductive layer 21. The core component 30 includes, for example, silicon oxide (SiO 2 ) and other insulators.

[0096] The semiconductor layer 31 covers the bottom and side surfaces of the core member 30 and includes, for example, a cylindrical portion. The lower end of the semiconductor layer 31 is in contact with the conductor layer 21 , and the upper end thereof is located above the uppermost conductor layer 23 .

[0097] The laminated film 32 covers the side and bottom surfaces of the semiconductor layer 31, except for the portion where the conductor layer 21 contacts the semiconductor layer 31, and includes, for example, a cylindrical portion. Figure 5 The description is described in detail.

[0098] The semiconductor portion 33 covers the upper surface of the core member 30 and contacts the inner wall portion of the semiconductor layer 31 above the core member 30 and the lower end of the semiconductor layer 41 formed just above the semiconductor portion 33. The semiconductor portion 33 is, for example, cylindrical.

[0099] The core member 40 is provided to extend along the Z axis. The lower end of the core member 40 is located between the uppermost conductor layer 23 and the lowermost conductor layer 24. The upper end of the core member 40 is located above the layer where the uppermost conductor layer 24 is provided.

[0100] The semiconductor layer 41 covers the side and bottom surfaces of the core member 40 and includes, for example, a cylindrical portion. The lower end of the semiconductor layer 41 contacts the semiconductor portion 33 and electrically connects it to the lower pillar LP. The upper end of the semiconductor layer 41 is located above the uppermost conductor layer 24 .

[0101] The semiconductor layer 42 includes a cylindrical portion that covers at least the side surface of a portion of the semiconductor layer 41 that intersects with the conductor layer 24 .

[0102] The stacked film 43 is a gate insulating film of the selection transistor, covers the side surface of the semiconductor layer 42, and includes a cylindrical portion. Figure 7 The description is described in detail.

[0103] The semiconductor portion 44 covers the upper surface of the core component 40 and contacts the inner wall of the portion of the semiconductor layer 41 disposed above the core component 40. The semiconductor portion 44 is provided in a cylindrical shape, for example, and reaches the upper end of the upper pillar UP.

[0104] A columnar contact CP is provided on the upper surface of the semiconductor layer 41, the semiconductor layer 42, and the semiconductor portion 44 in the memory pillar MP. Figure 4 In the cross-sectional view of FIG. 1 , contacts CP corresponding to two of the four memory pillars MP are shown. The remaining two memory pillars MP, for which contacts CP are not shown, are located in the Figure 4 The contact point CP is provided on the cross section on the depth side or the front side of the PCB. The upper surface of each contact point CP is in contact with a corresponding one of the conductive layers 25 (bit lines BL) and is electrically connected.

[0105] The slit SLT is formed, for example, to extend in a plate shape along the XZ plane and divide the conductor layers 22 to 24 in the Y direction. The upper end of the slit SLT is located between the conductor layer 24 and the conductor layer 25. The lower end of the slit SLT is located, for example, in the layer where the conductor layer 21 is provided. The slit SLT includes, for example, an insulator such as silicon oxide.

[0106] The slit SHE_X is formed, for example, to extend in a plate shape along the XZ plane, and divides the conductor layer 24 in the Y direction. The upper end of the slit SHE_X is located between the conductor layer 24 and the conductor layer 25. The lower end of the slit SHE_X is located, for example, between the layer where the uppermost conductor layer 23 is provided and the layer where the conductor layer 24 is provided. The slit SHE_X includes, for example, an insulator such as silicon oxide.

[0107] The upper ends of the slits SLT, the upper ends of the slits SHE_X, and the upper ends of the memory pillars MP may be aligned or may not be aligned.

[0108] Figure 5 Along the VV line Figure 4The XY cross-sectional view obtained by cutting the memory pillar MP shows an example of the cross-sectional structure of the conductive layer 23 including the lower pillar LP and its peripheral edge.

[0109] like Figure 5 As shown in the figure, the core component 30 is arranged at the approximate center of the lower column LP. Furthermore, a semiconductor layer 31 and a laminated film 32 are arranged concentrically around the core component 30. That is, the semiconductor layer 31 and the laminated film 32 are formed along the Z direction in a manner of surrounding the entire side of the core component 30. The laminated film 32 is a film formed by laminating a tunnel insulating film 35, an insulating film 36, and a blocking insulating film 37 in sequence.

[0110] The tunnel insulating film 35 and the barrier insulating film 37 each include, for example, silicon oxide, and the insulating film 36 includes, for example, silicon nitride (SiN).

[0111] Figure 6 Along the VI-VI line Figure 4 The XY cross-sectional view obtained by cutting the memory pillar MP shows an example of the cross-sectional structure of the upper pillar UP.

[0112] like Figure 6 As shown in the figure, the core component 40 is arranged at the approximate center of the upper column UP. Furthermore, a semiconductor layer 41, a semiconductor layer 42, and a stacked film 43 are arranged concentrically around the core component 40. That is, the semiconductor layer 41, the semiconductor layer 42, and the stacked film 43 are formed along the Z direction in a manner of surrounding the entire side of the core component 40. The stacked film 43 is a film formed by stacking a tunnel insulating film 45, an insulating film 46, and a blocking insulating film 47 in sequence.

[0113] The tunnel insulating film 45 and the barrier insulating film 47 each include, for example, silicon oxide, and the insulating film 46 includes, for example, silicon nitride (SiN).

[0114] In the structure of the memory pillar MP described above, the portion where the memory pillar MP intersects the conductor layer 22 functions as the selection transistor ST2. The portion where the memory pillar MP intersects the conductor layer 23 functions as the memory cell transistor MT. The portion where the memory pillar MP intersects the conductor layer 24 functions as the selection transistor ST1.

[0115] That is, the semiconductor layer 31 is used as a channel of each of the memory cell transistor MT and the selection transistor ST2. The insulating film 36 is used as a charge accumulation layer of the memory cell transistor MT and the selection transistor ST2. The semiconductor layer 41 is used as a channel of the selection transistor ST1 and an electrical connection portion between the upper column UP and the lower column LP. The insulating film 46 is used as a charge accumulation layer of the selection transistor ST1. Thus, the memory columns MP each function as, for example, one NAND string NS.

[0116] In addition, the structure of the memory cell array 10 described above is only an example, and the memory cell array 10 may also have other structures. For example, the number of the conductive layer 23 is designed based on the number of word lines WL. The selection gate line SGD is not limited to 3 layers, and can be designed to have any number of layers. The selection gate line SGS may also be allocated with a plurality of conductive layers 22 set as multiple layers. In the case where the selection gate line SGS is set as multiple layers, a conductor different from the conductive layer 22 may also be used. The memory column MP and the conductive layer 25 may be electrically connected via two or more contacts, or may be electrically connected via other wiring. The slit SLT may also contain a variety of insulators.

[0117] 1.1.3.3 Wiring Area

[0118] Figure 7 It means that along the VII-VII line Figure 3 An example of a cross-sectional structure obtained by cutting the memory cell array 10 of the semiconductor memory device according to the first embodiment. Figure 7 As shown, the conductive layers 21 to 24 extend along the X-axis and reach the wiring area HA.

[0119] On the upper surface of the conductive layer 23 used as the word lines WL1, WL4, and WL7, columnar contacts CC_WL1, CC_WL4, and CC_WL7 are provided. The upper surfaces of the contacts CC_WL1, CC_WL4, and CC_WL7 are in contact with and electrically connected to the corresponding one of the conductive layers 80_1, 80_4, and 80_7, respectively. In addition, on the upper surface of the conductive layer 23 of the word lines WL0, WL3, and WL6 of the remaining word lines WL used as the contact CC_WL not shown, Figure 7 In the cross section near the front side of the embodiment, contacts CC_WL0, CC_WL3, and CC_WL6 are provided. In addition, on the upper surface of the conductive layer 22 used as the selection gate line SGS and the conductive layer 23 used as the word lines WL2 and WL5, contacts CC_SGS, CC_WL2, and CC_WL5 are provided in a cross section closer to the front side of the cross section where contacts CC_WL0, CC_WL3, and CC_WL6 are provided.

[0120] A columnar contact CC_SGD is provided so as to be in contact with the upper surface of each of the three conductive layers 24 used as the selection gate lines SGDa, SGDb, and SGDc. Figure 7 In the cross-sectional view of FIG. 1 , the contact CC_SGD0 corresponding to the string assembly SU0 is shown among the four contacts CC_SGD. The remaining three contacts CC_SGD1 to CC_SGD3 not shown are arranged at Figure 7 In the cross section near the front side of . The upper surface of each contact CC_SGD is in contact with a corresponding one of the conductive layers 81 and is electrically connected.

[0121] The contact CC_SGD has a cross section with a diameter Δ1 along the lower surface of the selection gate line SGDb of the second layer from the bottom, has a cross section with a diameter Δ1+2Δ2 greater than the diameter Δ1 along the lower surface of the selection gate line SGDc of the third layer from the bottom (the uppermost layer), and has a diameter Δ3 greater than the diameter Δ1+2Δ2 along the upper surface of the selection gate line SGDc of the uppermost layer. The XY cross section of the contact CC_SGD on the lower surface of the selection gate line SGDb and the XY cross section of the contact CC_SGD on the lower surface of the selection gate line SGDc are similar to each other, and their centers coincide when viewed from above.

[0122] The slit SHE_Y is formed, for example, to extend in a plate shape along the YZ plane and divide the conductor layer 24 in the X direction. The slit SHE_Y has, for example, an upper end and a lower end at the same height as the slit SHE_X and is made of an insulator such as silicon oxide, similarly to the slit SHE_X.

[0123] The three layers of the conductor layer 24 are divided by the slit SHE_Y into a portion including the selection gate lines SGDa to SGDc and a portion including the selection gate line SGDX. In the portion including the selection gate line SGDX, the bottom conductor layer 24 is only δ1 longer than the second conductor layer 24 from the bottom along the X-axis, and the second conductor layer 24 from the bottom is only Δ2 longer than the top conductor layer 24 along the X-axis. In this way, the difference Δ2 in length along the X-axis between the second conductor layer 24 from the bottom and the top conductor layer 24 corresponds to the difference (2Δ2) between the diameter of the contact CC_SGD along the lower surface of the second conductor layer 24 from the bottom and the diameter of the contact CC_SGD along the lower surface of the top conductor layer 24. In addition, the difference δ1 may also be "0" (that is, the bottom conductor layer 24 and the second conductor layer 24 from the bottom may also be the same length along the X-axis).

[0124] Figure 8 The three layers of the selection gate line SGD in the first embodiment are shown. Figure 3 An example of a top view of region VIII enlarged and viewed from above. Figure 8 In FIG. 1 , the contact CC_SGD and the interlayer insulating layer are omitted, and the outer edge of the surface of the diameter Δ3 of the contact CC_SGD in contact with the upper surface of the uppermost conductive layer 24 is indicated by a single-dot chain line.

[0125] like Figure 8As shown, a through hole with a diameter of Δ1+2Δ2 is formed in the topmost conductive layer 24 used as the selection gate line SGDc. A through hole with a diameter of Δ1 is formed in the second conductive layer 24 from the bottom used as the selection gate line SGDb. The through hole with a diameter of Δ1+2Δ2 is similar in shape to the through hole with a diameter of Δ1, and in a plan view, the center of the through hole with a diameter of Δ1+2Δ2 coincides with the center of the through hole with a diameter of Δ1.

[0126] exist Figure 8 In the example, the through hole with a diameter of Δ1 and the through hole with a diameter of Δ1+2Δ2 are described as being circular, but the present invention is not limited thereto. For example, the through hole with a diameter of Δ1 and the through hole with a diameter of Δ1+2Δ2 may be in any shape such as a rectangle. Figure 8 In the figure, the outer edge of the surface of the contact CC_SGD in contact with the upper surface of the topmost conductive layer 24 can take any shape within the range including the through hole of diameter Δ1+2Δ2, but it does not necessarily need to be consistent with the shape of the through hole of diameter Δ1 and the through hole of diameter Δ1+2Δ2, and it may not be consistent with their centers.

[0127] 1.2 Method for manufacturing semiconductor storage device

[0128] Hereinafter, an example of a series of manufacturing steps of the semiconductor memory device according to the first embodiment, from the formation of the stacked structure corresponding to the word line WL to the formation of the contact CC_SGD corresponding to the select gate line SGD, will be described. Figure 9 to Figure 24 Each of the figures shows an example of a cross-sectional structure of a structure corresponding to a memory cell array in the manufacturing steps of the semiconductor memory device of the first embodiment. In addition, the cross-sectional view of the manufacturing steps referred to below includes a cross-sectional view perpendicular to the surface of the semiconductor substrate 20. In addition, the area shown in the cross-sectional view of each manufacturing step includes an area where contacts CC_WL1, CC_WL4, CC_WL7, CC_SGD0 and slit SHE_Y in the wiring area HA are formed, and a memory column MP in the cell area CA.

[0129] First, if Fig. 9 As shown, after the sacrificial material 52 corresponding to the selection gate line SGS and the sacrificial material 53 corresponding to the word line WL are stacked, a step structure is formed in the portion corresponding to the areas A to C of the wiring area HA.

[0130] Specifically, first, the insulating layer 50 and the conductive layer 21 are sequentially stacked on the semiconductor substrate 20. The insulating layer 51 and the sacrificial material 52 are stacked on the conductive layer 21, and the insulating layer 51 and the sacrificial material 53 are stacked alternately multiple times on the sacrificial material 52.

[0131] Then, a mask (not shown) is set on the upper surface of the sacrificial material 53, and a pattern is formed in the portion of the mask corresponding to the regions A to C by photolithography. After that, the following operations are repeated in sequence: anisotropic etching of the sacrificial materials 52 and 53 and the laminated structure of the insulator layer 51 based on the obtained pattern; and removing a portion of the laminated structure by thinning the mask pattern. Thus, the portion corresponding to the regions A to C in the laminated structure can be etched in a step-like manner along the X direction and the Y direction. The anisotropic etching in this step is, for example, RIE (Reactive Ion Etching).

[0132] Then, the step structure is embedded to the position of the uppermost sacrificial material 53 by the insulator layer 54, and the insulator layer 55 is stacked on the insulator layer 54 and the uppermost sacrificial material 53. The insulator layers 51, 54, and 55 include, for example, silicon oxide (SiO 2 The number of layers of the sacrificial materials 52 and 53 respectively corresponds to the number of stacked select gate lines SGS and word lines WL. The sacrificial materials 52 and 53 include, for example, silicon nitride (SiN).

[0133] Then, if Fig.10 As shown, a memory hole H0 corresponding to the lower pillar LP is formed. Specifically, first, a mask having an opening in a region corresponding to the memory hole H0 is formed by photolithography. Then, the memory hole H0 is formed by anisotropic etching using the formed mask.

[0134] The memory hole H0 formed in this step penetrates the insulating layer 51, the sacrificial materials 52 and 53, and the insulating layer 55, and reaches the conductive layer 21. The anisotropic etching in this step is, for example, RIE.

[0135] Then, if Fig.11 As shown, a layered structure, namely, a lower pillar LP, is formed in the memory hole H0.

[0136] Specifically, a blocking insulating film 37, an insulating film 36, and a tunnel insulating film 35 are sequentially formed on the side and bottom surfaces of the memory hole H0 and the upper surface of the insulating layer 55 to form a stacked film 32. Then, after removing the stacked film 32 at the bottom of the memory hole H0, a semiconductor layer 31 and a core component 30 are sequentially formed to fill the memory hole H0. Thereafter, the core component 30 from the upper end of the memory hole H0 to a specified depth is removed together with the portion remaining on the upper layer than the insulating layer 54.

[0137] Next, the semiconductor portion 33 is formed to fill the memory hole H0. Thereafter, the semiconductor portion 33, the semiconductor layer 31, and the build-up film 32 remaining on the upper layer than the insulating layer 54 are removed. Thus, the lower pillar LP is formed.

[0138] Then, if Fig.12 As shown, after forming an insulating layer 56 on the upper surface of the lower pillar LP and the insulating layer 55, sacrificial materials 57 and insulating layers 58 corresponding to the selection gate lines SGD are alternately stacked. An insulating layer 59 is formed on the upper layer of the uppermost sacrificial material 57. The insulating layers 56, 58, and 59 include silicon oxide, and the sacrificial material 57 includes silicon nitride.

[0139] Then, if Fig.13 As shown, the portion of the insulator layer 59 corresponding to the regions A to C and the uppermost sacrificial material 57 are removed. Specifically, a mask (not shown) is provided on the upper surface of the insulator layer 59, and the portion of the mask corresponding to the regions A to C is removed by photolithography. Thereafter, anisotropic etching is performed on the insulator layer 59 and the sacrificial material 57 based on the obtained mask. The position of the end of the sacrificial material 57 extending along the Y axis formed by this step corresponds to the position of the end of the lowermost conductive layer 24.

[0140] Then, if Figure 14 to Figure 16 As shown, the end of the three-layer sacrificial material 57 in the wiring area HA is formed in a stepped shape, and a hole is formed for allowing the contact CC_SGD to reach the bottommost conductor layer 24.

[0141] Specifically, if Fig.14 As shown, a mask pattern is formed by photolithography, and the mask pattern removes the Fig.13 The mask formed by the steps described in the above is formed to form a portion corresponding to an area within δ1 from the end of the sacrificial material 57 along the X axis, and a portion corresponding to an area of ​​a predetermined diameter Δ1 in contact with the contact CC_SGD on the upper surface of the bottom conductive layer 24. Thereafter, anisotropic etching is performed on the insulator layer 59 and the sacrificial material 57 based on the obtained mask pattern. As a result, the end of the sacrificial material 57 of the top layer is shortened by only δ1 along the X axis. In addition, a hole H1 including a through hole of diameter Δ1 is formed in the sacrificial material 57 of the top layer. The anisotropic etching in this step is, for example, RIE.

[0142] Then, if Fig.15As shown, by thinning the mask pattern on the insulator layer 59, the portion of the mask pattern corresponding to the area within Δ2 from the end of the uppermost sacrificial material 57 along the X-axis, and the portion corresponding to the area isotropically extending only by Δ2 from the outer edge of the hole H1 are removed. Thereafter, anisotropic etching is performed on the insulator layer 59 and the sacrificial material 57 based on the obtained mask pattern. As a result, the end of the sacrificial material 57 of the uppermost layer is shortened by only Δ2 along the X-axis, and the end of the sacrificial material 57 of the second layer from the bottom is shortened by only δ1 along the X-axis. In addition, a hole H2 is formed, which includes a through hole with a diameter of Δ1+2Δ2 formed in the sacrificial material 57 of the uppermost layer, and a through hole with a diameter of Δ1 formed in the sacrificial material 57 of the second layer from the bottom. The anisotropic etching in this step is, for example, RIE.

[0143] Then, if Fig.16 As shown, through Fig.14 and Fig.15 The sacrificial material 57 and the portions of the insulating layers 58 and 59 removed by the steps described above are embedded in the insulating layer 60 .

[0144] Then, if Fig.17 As shown, the SGD hole H3 corresponding to the upper pillar UP is formed. Specifically, first, a mask with an opening in a region corresponding to the SGD hole H3 is formed by photolithography. Then, the SGD hole H3 is formed by anisotropic etching using the formed mask.

[0145] The SGD hole H3 penetrates the insulating layers 59, 58, and 56 and the sacrificial material 57, and reaches the semiconductor portion 33 of the lower pillar LP. The anisotropic etching in this step is, for example, RIE.

[0146] Then, if Fig.18 As shown, a stacked structure is formed in the SGD hole H3. Specifically, first, a blocking insulating film 47, an insulating film 46, and a tunnel insulating film 45 are sequentially formed to form a stacked film 43, and then a semiconductor layer 42 is formed. Then, the semiconductor layer 42 and the stacked film 43 at the bottom of the SGD hole H3 are removed by anisotropic etching (for example, RIE) to expose the upper surface of the semiconductor portion 33.

[0147] Then, the semiconductor layer 41 is formed in the SGD hole H3 and is in contact with the semiconductor portion 33. Thus, the semiconductor layer 31 and the semiconductor layer 41 form a current path (channel path) for a cell current to flow through the semiconductor portion 33 in the memory pillar MP.

[0148] Then, the core component 40 is formed on the semiconductor layer 41 and in the SGD hole H3. After that, a portion of the core component 40 above the SGD hole H3 is removed, and the semiconductor portion 44 is embedded in the space. The stacked film 43, the semiconductor layer 42, the semiconductor layer 41, the core component 40, and the semiconductor portion 44 remaining above the insulator layer 59 are removed by, for example, CMP (Chemical Mechanical Polishing). Thus, an upper column UP is formed in the SGD hole H3.

[0149] Then, if Fig.19 As shown, the sacrificial materials 52, 53, and 57 are replaced by the conductive layers 22 to 24, respectively.

[0150] Specifically, first, a hole (not shown) corresponding to the slit SLT is formed. The hole formed in this step separates the insulator layer 51, the sacrificial materials 52 and 53, the insulator layers 55 and 56, the sacrificial material 57, and the insulator layers 58 and 59, respectively. Then, the surface of the conductor layer 21 exposed in the hole is oxidized to form an oxide protective film (not shown). Thereafter, the sacrificial materials 52, 53, and 57 are selectively removed, for example, by wet etching using hot phosphoric acid. The structure after removing the sacrificial materials 52, 53, and 57 maintains its three-dimensional structure through a plurality of memory pillars MP, etc.

[0151] Then, after the conductor is embedded into the space where the sacrificial materials 52, 53 and 56 are removed through the hole, an insulator layer corresponding to the slit SLT is formed in the hole. In this step, for example, CVD (Chemical Vapor Deposition) is used. The portion of the conductor formed inside the hole and on the upper surface of the insulator layer 59 is removed by etching back. Thus, the conductor formed in the adjacent wiring layer is separated to form a conductor layer 22, a plurality of conductor layers 23, and a plurality of conductor layers 24. The conductor layers 22, 23, and 24 formed in this step may also include a barrier metal. In this case, in the formation of the conductor after removing the sacrificial materials 52, 53 and 57, for example, after forming a film of titanium nitride (TiN) as a barrier metal, tungsten is formed.

[0152] Then, if Fig. 20 As shown in FIG. 1 , a hole H4 corresponding to the slits SHE_X and SHE_Y is formed. Fig. 20, the portion of the hole H4 corresponding to the slit SHE_Y is shown. Specifically, first, a mask with openings in the regions corresponding to the slits SHE_X and SHE_Y is formed by photolithography. Then, the hole H4 is formed by anisotropic etching (e.g., RIE) using the formed mask. The hole H4 formed in this step separates the insulator layers 59 and 58 and the conductor layer 24, and reaches the insulator layer 56.

[0153] Then, if Fig.21 As shown, an insulating layer 61 corresponding to the slits SHE_X and SHE_Y is formed on the insulating layers 59 and 60 to fill the holes H4. Then, the insulating layer 61 formed on the upper layer than the insulating layers 59 and 60 is removed by, for example, etching back. The insulating layer 61 includes, for example, silicon oxide.

[0154] Then, if Fig. 22 As shown, a conductive layer 62 is formed on the upper surface of the semiconductor portion 44 of the memory pillar MP, and a conductive layer 25 is formed on the upper surface of the conductive layer 62 , and an insulating layer 63 is formed so as to embed them over the entire surface.

[0155] Then, if Fig.23 As shown, a plurality of holes H5 corresponding to the contacts CC_SGD0 to CC_SGD3, and a plurality of holes H6 corresponding to the contacts CC_SGS and CC_WL0 to CC_WL7 are formed. Fig.23 , one hole H5 corresponding to the contact point CC_SGD0 and three holes H6 corresponding to the contact points CC_WL1, CC_WL4, and CC_WL7 are shown.

[0156] Specifically, first, a mask with openings in the regions corresponding to the holes H5 and H6 is formed by photolithography. Then, holes H5 and H6 are formed by anisotropic etching using the formed mask. In addition, the opening corresponding to the hole H6 is formed in a manner that includes a through hole of diameter Δ1+2Δ2 formed in the uppermost conductive layer 24.

[0157] The anisotropic etching in this step is, for example, RIE, and the conditions are selected such that the oxide and nitride are selectively removed while the conductive layers 22 to 24 are hardly etched. Thus, the hole H5 reaches the upper surface of the uppermost conductive layer 24, the second conductive layer 24, and the lowermost conductive layer 24. The hole H5 has a diameter Δ3 on the upper surface of the uppermost conductive layer 24, a diameter Δ1+2Δ2 on the upper surface of the second conductive layer 24 from the bottom, and a diameter Δ1 on the upper surface of the lowermost conductive layer 24. The hole H6 penetrates the insulator layers 63, 60, 56, and 55 to reach the uppermost conductive layer 23, and further penetrates the insulator layer 54 to reach the other conductive layers 23 and the conductive layer 22.

[0158] Then, if Fig.24 As shown in FIG. 6 , the conductive layers 64 and 65 are formed to fill the holes H5 and H6 , respectively. Thereafter, the conductive layers 64 and 65 remaining on the upper layer than the insulating layer 63 are removed.

[0159] Through the manufacturing steps of the semiconductor memory device of the first embodiment described above, the memory column MP, the source line SL connected to the memory column MP, the word line WL, the selection gate lines SGS and SGD, and the contacts CC_SGS, CC_WL0 to CC_WL7, and CC_SGD0 to CC_SGD3 are formed. In addition, the manufacturing steps described above are only examples, and other processes may be inserted between the manufacturing steps, and the order of the manufacturing steps may be changed within the range that does not cause problems.

[0160] 1.3 Effects of this Implementation

[0161] According to the configuration of the first embodiment, the selection gate line SGD and the contact CC_SGD can be well connected. More specifically, the contact CC_SGD is in contact with the plurality of conductive layers 24 that function as the selection gate line SGD on their respective upper surfaces, so that a sufficient contact area with any conductive layer 24 can be ensured. Therefore, an increase in resistance of the connection portion can be suppressed.

[0162] Furthermore, since all the plurality of conductor layers 24 can be electrically connected via one contact CC_SGD, there is no need to provide a stepped region for forming the contact CC_SGD for each of the plurality of conductor layers 24. Therefore, the length of the selection gate line SGD along the X axis can be shortened.

[0163] In addition, in order to form the contact CC_SGD as described above, the step of etching based on the mask pattern formed by thinning is appropriately repeated according to the number of layers of the selection gate line SGD. As a result, a through hole whose diameter gradually becomes smaller as it goes toward the lower layer is formed in the multi-layer sacrificial material 57, and a step shape whose step width corresponds to the diameter of the through hole is formed. In addition, the difference Δ2 in diameter between the through hole of the sacrificial material 57 of the second layer from the bottom and the through hole of the sacrificial material 57 of the top layer is consistent with the difference Δ2 in length along the X-axis between the sacrificial material 57 of the second layer from the bottom and the sacrificial material 57 of the top layer.

[0164] In addition, according to the configuration of the first embodiment, the slit SHE includes a slit SHE_Y extending along the Y axis in addition to the slit SHE_X extending along the X axis. Thus, the selection gate line SGD is divided into the selection gate lines SGD0 to SDG3 corresponding to the string components SU0 to SU3, respectively, and the selection gate line SGDX which does not correspond to any string component SU and is located at the end of the selection gate line SGD along the X axis. Therefore, the slit SHE_X can insulate and separate the selection gate line SGD in units of the string components SU without completely dividing the selection gate line SGD along the X axis (by dividing to the slit SHE_Y).

[0165] Regarding the effects of this structure, further use Fig.25 and Fig.26 Provide explanation. Fig.25 This is a comparative example for explaining the effect of the semiconductor memory device of the first embodiment. Figure 3 correspond, Fig.26 It is along Fig.25 A cross-sectional view of the line XXVI-XXVI. Fig.25 and Fig.26 In the comparative example, the plurality of slits SHE_X extend along the X axis longer than the plurality of conductive layers 24. Thus, the slits SHE_X separate the wiring layers corresponding to the selection gate line SGD into the selection gate lines SGD0 to SGD3 and insulate and separate them, without forming the selection gate line SGDX. As a result, there is no insulating layer corresponding to the slit SHE_Y that separates the three conductive layers 24 along the Y direction in the wiring area HA. ​​In addition, Fig.25 and Fig.26 In the comparative example, the contact CC_SGDp extends upward from the upper surface of the bottommost conductor layer 24 and contacts the side surfaces of other conductor layers 24 .

[0166] Depend on Fig.25 It can also be seen that when the slit SHE_Y is not formed, the slit SHE_X reaches the region OEA that does not include the three-layer conductor layer 24 in a plan view. Fig.26It can also be seen that in the region OEA, a stacked structure is formed of oxide or nitride up to the depth of the conductor layer 23 and no metal layer is included.

[0167] Under the etching conditions applied when forming the hole H4 corresponding to the slit SHE_X, etching progresses rapidly in the laminated structure formed of oxide and nitride, but etching progresses slowly in the metal layer. Therefore, when forming the hole H4, overetching may occur in the region OEA to the depth of the conductor layer 23. In this case, the conductor layer 23 may be etched and deformed, thereby generating unexpected leakage current, etc.

[0168] According to the first embodiment, by forming the slit SHE_Y, the slit SHE_X does not reach the area OEA. As a result, the layer structure etched when the hole H4 is formed is limited to the area including the three-layer conductor layer 24 in a plan view. Therefore, it is possible to avoid the etching of the hole H4 from progressing to the conductor layer 23. Therefore, it is possible to suppress the slit SHE_X and the conductor layer 23 from becoming deformed, and to suppress the generation of unexpected leakage current in the conductor layer 23.

[0169] 1.4 Variations

[0170] In addition, the first embodiment described above can be modified in various ways.

[0171] 1.4.1 Variation 1

[0172] In the first embodiment, a case where the contact CC_SGD is in contact with the upper surface of each of the plurality of conductor layers 24 is described, but the present invention is not limited thereto. For example, a through hole having a sufficient contact area with the side surface of each of the plurality of conductor layers 24 may be formed, and a contact may be formed on the upper surface of the through hole. In the following description, description of the same structure and manufacturing method as the first embodiment is omitted, and description of the structure and manufacturing method different from the first embodiment is mainly given.

[0173] Fig. 27 1 is a top view for explaining the plan layout of a memory cell array of a semiconductor memory device according to a first variation of the first embodiment, and is similar to the plan layout of the memory cell array of the semiconductor memory device according to the first variation of the first embodiment. Figure 3 correspond.

[0174] like Fig. 27 As shown, through holes CV_SGD0 to CV_SGD3 are provided in a manner of connecting to selection gate lines SGD0 to SGD3, respectively. Contact points CC'_SGD0 to CC'_SGD3 are provided on the upper surfaces of through holes CV_SGD0 to CV_SGD3, respectively. The diameter of through hole CV_SGD is larger than the diameter of contact point CC'_SGD.

[0175] Fig.28 It means that along the line XXVIII-XXVIII Fig. 27 An example of a cross-sectional structure obtained by cutting the memory cell array 10 described in the first embodiment is similar to Figure 7 Corresponding. Fig.28 As shown, the through hole CV_SGD is arranged on the upper surface of the bottom conductor layer 24, and the other conductor layers 24 (in Fig.28 In the example, the through hole CV_SGD extends along the Z axis in the second layer from the bottom and the top conductor layer 24. That is, the through hole CV_SGD is connected to the bottom conductor layer 24 on the top surface of the bottom conductor layer 24, and is connected to the other conductor layers 24 on the side surfaces of the other conductor layers 24.

[0176] As described above, since the diameter of the through hole CV_SGD is larger than the diameter of the contact CC'_SGD, a sufficient contact area with the conductor layer 24 in contact with the side surface can be ensured. This can suppress an increase in contact resistance between the selection gate line SGD and the contact CC'_SGD.

[0177] In addition, the plurality of conductor layers 24 are all electrically connected to the contact CC'_SGD through one through hole CV_SGD. Therefore, it is not necessary to form the plurality of conductor layers 24 in a stepped shape in order to form a plurality of contacts corresponding to the plurality of conductor layers 24, respectively. Thus, compared with the case where the contacts CC'_SGD are formed for the plurality of conductor layers 24, respectively, the area used to form the contacts CC'_SGD can be reduced. In addition, accordingly, the following configuration can be applied in the same manner as in the first embodiment: the plurality of conductor layers 24 are divided into portions corresponding to the selection gate lines SGD0 to SGD3 and portions corresponding to the selection gate line SGDX by the slits SHE_X and SHE_Y. Therefore, it is possible to suppress the shape abnormality of the conductor layer 23 caused by over-etching when the slit SHE_X is formed.

[0178] Furthermore, in the first variation, the through hole CV_SGD does not have a structure in contact with the upper surfaces of the plurality of conductor layers 24. Therefore, in the first variation, unlike the first embodiment, there is no need to repeatedly perform the step of etching the multilayer sacrificial material 57 using the mask pattern formed by thinning. Therefore, the ends of the plurality of conductor layers 24 along the -X direction do not have a step shape, but can have the same length and are aligned.

[0179] 1.4.2 Example 2

[0180] In addition, in the first variation, the case where the selection gate line SGD and the contact CC_SGD are shunted by the through hole CV_SGD is described, but it is not limited to this. In the following description, the description of the same structure and manufacturing method as the first variation of the first embodiment is omitted, and the description is mainly about the structure and manufacturing method different from the first variation of the first embodiment.

[0181] Fig.29 1 is a top view for explaining the plan layout of a memory cell array of a semiconductor memory device according to a second variation of the first embodiment, which is similar to the plan layout of the memory cell array of the first variation of the first embodiment. Fig. 27 correspond.

[0182] like Fig.29 As shown, the contact points CC"_SGD0~CC"_SGD3 are respectively set in a manner connected to the selection gate lines SGD0~SGD3.

[0183] Fig.30 It means that along the XXX-XXX line Fig.29 An example of a cross-sectional structure obtained by cutting the memory cell array 10 described in the first embodiment is similar to that in the first variation of the first embodiment. Fig.28 Corresponding. Fig.30 As shown, the contact CC"_SGD is arranged on the upper surface of the bottom conductor layer 24, and the other conductor layers 24 (in Fig.30 In the example, the contact CC"_SGD extends along the Z axis within the second layer from the bottom and the top conductor layer 24. That is, the contact CC"_SGD is in contact with the bottom conductor layer 24 on the upper surface of the bottom conductor layer 24, and is in contact with the other multiple conductor layers 24 on the side surfaces of the other multiple conductor layers 24. The diameter of the contact CC"_SGD is, for example, the same as the diameter of the contact CC_WL.

[0184] As described above, when there is a margin for the restriction of the contact resistance, the same effect as that of the first embodiment and the first variation of the first embodiment can be achieved by a configuration in which the side surface of the selection gate line SGD is directly in contact with the contact CC_SGD.

[0185] 2. Second Implementation Method

[0186] Next, a semiconductor memory device according to the second embodiment is described. In the second embodiment, a hole for forming a contact CC_SGD connected to the selection gate line SGD and a hole for forming a slit SHE are formed simultaneously, and this mainly differs from the second variation of the first embodiment in this respect. In the following description, descriptions of the same configuration and manufacturing method as those of the second variation of the first embodiment are omitted, and descriptions of the configuration and manufacturing method different from those of the second variation of the first embodiment are mainly given.

[0187] 2.1 Structure of semiconductor storage devices

[0188] Fig.31 1 is a cross-sectional view for explaining a wiring region of a memory cell array of a semiconductor memory device according to a second embodiment, which is different from the second variation of the first embodiment. Fig.30 correspond.

[0189] like Fig.31 As shown, the contact CC2_SGD extends along the Z axis in the plurality of conductive layers 24, and its lower end is located below the lower surface of the lowest conductive layer 24. The lower ends and upper ends of the slit SHE2_Y (and the slit SHE2_X not shown) and the contact CC2_SGD are located at substantially the same height along the Z direction. That is, the length L from the lower end to the upper end of the slits SHE2_X and SHE2_Y is substantially the same as the length L from the lower end to the upper end of the contact CC2_SGD.

[0190] 2.2 Method for manufacturing semiconductor storage device

[0191] Hereinafter, an example of a series of manufacturing steps of the semiconductor memory device according to the second embodiment, from the formation of the stacked structure corresponding to the word line WL to the formation of the contact CC_SGD corresponding to the select gate line SGD, will be described. Figure 32 to Figure 43 Each of the diagrams shows an example of a cross-sectional structure including a structure corresponding to a memory cell array in a manufacturing step of the semiconductor memory device according to the second embodiment.

[0192] First, by comparing with the first embodiment Figures 9 to 12 In the same steps as shown in the figure, an insulator layer 50 and a conductor layer 21 are sequentially formed on a semiconductor substrate 20. An insulator layer 51 and a sacrificial material 52 are stacked on the conductor layer 21, and an insulator layer 51 and a sacrificial material 53 are stacked alternately on the sacrificial material 52. Then, after forming a step structure in the wiring area HA of the stacked structure, a lower pillar LP is formed in the cell area. Subsequently, an insulator layer 56 is formed on the stacked structure, and further, a sacrificial material 57 and an insulator layer 58 corresponding to the selection gate line SGD are alternately stacked. An insulator layer 59 is formed on the upper layer of the uppermost sacrificial material 57.

[0193] Then, if Fig.33 and Fig.34 As shown, an SGD hole H3 corresponding to the upper post UP is formed, and a layered structure corresponding to the upper post UP is formed in the SGD hole H3.

[0194] Next, a hole (not shown) is formed corresponding to the slit SLT. Fig.35 As shown, the sacrificial materials 52, 53, and 56 are replaced with the conductive layers 22 to 24 through the holes. An insulating layer (not shown) is embedded in the holes used in the replacement step to form the slits SLT.

[0195] Then, if Fig.36 As shown, a conductive layer 62 is formed on the upper surface of the semiconductor portion 44 of the memory pillar MP, and a conductive layer 25 is formed on the upper surface of the conductive layer 62 , and an insulating layer 63 is formed so as to embed them over the entire surface.

[0196] Then, if Fig.37 As shown in FIG. 1 , a hole H11 corresponding to the slits SHE2_X and SHE2_Y and a hole H12 corresponding to the contact CC2_SGD are formed. Fig.37 , the portion of the hole H11 corresponding to the slit SHE2_Y is shown. Specifically, first, a mask with openings in the regions corresponding to the slits SHE2_X and SHE2_Y and the contact CC2_SGD is formed by photolithography. Then, the holes H11 and H12 are formed by anisotropic etching (for example, RIE) using the formed mask.

[0197] The holes H11 and H12 formed in this step separate the insulating layers 63, 59, and 58 and the conductive layer 24 and reach the insulating layer 56. The depths of the holes H11 and H12 are substantially equal to each other. Fig.31 The length L in is roughly the same.

[0198] Then, if Fig.38 As shown in FIG. 6 , insulating layers 72 and 73 are formed to fill the holes H11 and H12, respectively. Thereafter, the insulating layers 72 and 73 remaining above the insulating layer 63 are removed. The insulating layers 72 and 73 are made of, for example, silicon nitride.

[0199] Then, if Fig.39 As shown, the insulating layer 72 is selectively removed to form the hole H11 again. Specifically, for example, after a resist (not shown) is formed on the insulating layer 73 to protect the insulating layer 73, the insulating layer 72 is removed by wet etching or the like that selectively removes silicon nitride.

[0200] Then, if Fig.40As shown in FIG. 6 , an insulating layer 74 is formed to fill the hole H11 again. Thereafter, the insulating layer 74 remaining on the upper layer than the insulating layer 63 is removed. The insulating layer 74 includes, for example, silicon oxide.

[0201] Then, if Fig.41 As shown, a plurality of holes H13 are formed corresponding to the contacts CC_SGS and CC_WL0 to CC_WL7. Specifically, a mask with openings in regions corresponding to the holes H13 is first formed by photolithography. Then, the holes H13 are formed by anisotropic etching using the formed mask.

[0202] Then, if Fig.42 As shown, the insulating layer 73 is selectively removed by wet etching or the like for selectively removing silicon nitride, and the hole H12 is formed again.

[0203] Then, if Fig.43 As shown in FIG. 6 , the conductive layers 64A and 65 are formed to fill the holes H12 and H13 , respectively. Thereafter, the conductive layers 64A and 65 remaining on the upper layer than the insulating layer 63 are removed.

[0204] Through the manufacturing steps of the semiconductor memory device of the second embodiment described above, the slits SHE2_X and SHE2_Y whose lower and upper ends are substantially consistent with each other and the contacts CC2_SGD0 to CC2_SGD3 are formed. In addition, the manufacturing steps described above are only an example, and other processing may be inserted between the manufacturing steps, and the order of the manufacturing steps may be changed within the range that does not cause problems.

[0205] 2.3 Effects of this Implementation

[0206] According to the second embodiment, the contact CC2_SGD is in contact with the side surfaces of each of the plurality of conductor layers 24. Thus, it is not necessary to form a contact for each of the plurality of conductor layers 24, and accordingly, it is not necessary to form a contact step region for each of the plurality of conductor layers 24. Therefore, the stepped shape along the -X direction can be omitted for the plurality of conductor layers 24, thereby reducing the chip area.

[0207] In addition, the hole H13 corresponding to the contact CC_WL and the hole H12 corresponding to the contact CC2_SGD are formed in different steps. This can reduce the difference in etching depth of the holes formed in the same etching step.

[0208] In addition, when the holes H12 and H13 are formed by the same step, the deepest hole among the formed holes is the hole H13 that reaches the conductor layer 22, and the shallowest hole is the hole H12 that reaches the uppermost conductor layer 24. On the other hand, when the holes H12 and H13 are formed by different steps, the deepest hole among the formed holes is the hole H13 that reaches the lowermost conductor layer 22, and the shallowest hole is the hole H13 that reaches the uppermost conductor layer 23. Therefore, the difference in etching depth between the deepest hole and the shallowest hole can be reduced, and the risk of over-etching the conductor layer 24 corresponding to the shallower hole can be reduced, thereby suppressing the generation of unexpected leakage current.

[0209] In addition, the hole H12 formed in a different step from the hole H13 and the hole H11 corresponding to the slits SHE2_X and SHE2_Y are formed in the same step. This can suppress the increase in manufacturing steps. In addition, the contact CC2_SGD and the slits SHE2_X and SHE2_Y have a structure in which the lower ends and the upper ends are located at approximately the same height along the Z direction.

[0210] 3. Others

[0211] In addition, the first embodiment and the second embodiment described above can be modified in various ways.

[0212] For example, in the first and second embodiments, the memory column MP is described as being formed by the upper column UP and the lower column LP which are separately manufactured, but the present invention is not limited thereto. For example, the memory column MP may also be an integrally formed structure including a semiconductor layer extending along the Z axis in the conductive layer 22 to 24, and a charge accumulation layer arranged between the conductive layer 22 to 24 and the semiconductor layer.

[0213] In the first and second embodiments, for example, the stacked film 43 includes the tunnel insulating film 45, the insulating film 46, and the blocking insulating film 47, thereby configuring to adjust the threshold voltage of the selection transistor ST2, and this case is described as an example, but the present invention is not limited thereto. For example, the stacked film 43 may be configured not to include the tunnel insulating film 45 and the insulating film 46.

[0214] In addition, in the first embodiment and the second embodiment, the semiconductor memory device 1 has a structure in which the circuits such as the sense amplifier module 16 are provided under the memory cell array 10, and this case is used as an example for description, but the present invention is not limited to this. For example, the semiconductor memory device 1 may also have a structure in which the memory cell array 10 and the sense amplifier module 16 are formed on the semiconductor substrate 20. In addition, the semiconductor memory device 1 may also have a structure in which a chip provided with the sense amplifier module 16 and the like is bonded to a chip provided with the memory cell array 10.

[0215] In addition, in the first embodiment and the second embodiment, the structure in which the word line WL is adjacent to the selection gate line SGS and the word line WL is adjacent to the selection gate line SGD is described, but it is not limited to this. For example, a dummy word line may be provided between the word line WL of the uppermost layer and the selection gate line SGD. Similarly, a dummy word line may be provided between the word line WL of the lowermost layer and the selection gate line SGS. In addition, in the case of a structure in which a plurality of pillars are connected, the conductive layer near the connection portion may also be used as a dummy word line.

[0216] In the first and second embodiments, the case where the semiconductor layer 31 and the conductor layer 21 are electrically connected via the bottom of the memory pillar MP is exemplified, but the present invention is not limited thereto. The semiconductor layer 31 and the conductor layer 21 may be electrically connected via the side of the memory pillar MP. In this case, a structure is formed in which a portion of the laminated film 32 formed on the side of the memory pillar MP is removed, and the semiconductor layer 31 and the conductor layer 21 are in contact via the portion.

[0217] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

[0218] [Explanation of symbols]

[0219] 1 Semiconductor storage device

[0220] 2 Memory Controller

[0221] 10 Memory Cell Array

[0222] 11 Command Register

[0223] 12 Address register

[0224] 13 Sequencer

[0225] 14 Driver module

[0226] 15-line decoder module

[0227] 16 Sense Amplifier Module

[0228] 20 Semiconductor substrate

[0229] 21-25, 62, 64, 64A, 65, 80, 81 conductor layer

[0230] 30, 40 core components

[0231] 31, 41, 42 semiconductor layer

[0232] 32, 43 Laminated film

[0233] 33, 44 Semiconductor Division

[0234] 35, 45 Tunnel insulation film

[0235] 36, 46 Insulation film

[0236] 37, 47 Barrier insulation film

[0237] 50, 51, 54, 55, 56, 58, 59, 60, 61, 63, 71, 72, 73, 74 insulation layer

[0238] 52, 53, 57 Sacrificial materials

[0239] BLK Block

[0240] SU string assembly

[0241] MT memory cell transistor

[0242] ST1, ST2 selection transistor

[0243] BL bit line

[0244] WL Word Line

[0245] SGD Select gate line

Claims

1. A semiconductor storage device comprising: A plurality of first conductive layers are stacked in a first direction; a first semiconductor layer extending along the first direction within the plurality of first conductive layers; a first charge storage layer disposed between the plurality of first conductive layers and the first semiconductor layer; a plurality of second conductive layers stacked along the first direction on the uppermost layer among the plurality of first conductive layers; as well as The first insulating layer includes a first part and a second part, wherein the first part extends along a second direction intersecting the first direction, and divides the plurality of second conductive layers into a first region and a second region arranged along a third direction intersecting the first direction and the second direction, and the second part extends along the third direction, and divides the first region into a third region and a fourth region arranged along the second direction.

2. The semiconductor memory device according to claim 1, wherein The invention further includes a third conductive layer extending in the first direction in the third region or the fourth region of the plurality of second conductive layers and electrically connecting the plurality of second conductive layers to each other.

3. The semiconductor memory device according to claim 2, wherein The third conductive layer extends from the upper surface of the lowest layer among the plurality of second conductive layers along the first direction in one or more layers other than the lowest layer among the plurality of second conductive layers.

4. The semiconductor memory device according to claim 3, wherein The third conductor layer is in contact with the upper surfaces of the plurality of second conductors.

5. The semiconductor memory device according to claim 3, wherein The upper end of the third conductive layer is located above the upper surface of the uppermost layer among the plurality of second conductive layers, and The semiconductor memory device further includes a fourth conductive layer extending from an upper end of the third conductive layer in the first direction and having a smaller diameter than the third conductive layer.

6. The semiconductor memory device according to claim 1, wherein The first portion and the second portion of the first insulating layer are provided in a T-shape when viewed from the first direction.

7. The semiconductor memory device according to claim 3, wherein The third conductive layer extends along the first direction within the plurality of second conductive layers. The lower end of the third conductive layer is located on the same layer as the lower end of the first insulating layer. The upper end of the third conductive layer is located on the same layer as the upper end of the first insulating layer.

8. The semiconductor memory device according to claim 1, wherein The first semiconductor layer further extends along the first direction within the plurality of second conductive layers. The first charge storage layer is further provided between the plurality of second conductive layers and the first semiconductor layer.

9. The semiconductor memory device according to claim 1, further comprising: a second semiconductor layer extending along the first direction within the plurality of second conductive layers; and The second insulating layer is provided between the plurality of second conductive layers and the second semiconductor layer.

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