High-integration-level silicon-based semiconductor polycrystalline silicon film resistor module and manufacturing method thereof

Abstract

The invention relates to the field of semiconductor device manufacturing, and discloses a high-integration-level silicon-based semiconductor polycrystalline silicon film resistor module and a manufacturing method of the high-integration-level silicon-based semiconductor polycrystalline silicon film resistor module. The silicon oxide layer is positioned above the silicon substrate layer; the nanocrystalline polycrystalline silicon thin film layer is directly deposited on the silicon oxide layer; the self-aligned nano patterned structure belongs to one part of the nanocrystalline polycrystalline silicon thin film layer; the double-layer doped region is located in the nanocrystalline polycrystalline silicon thin film layer; the graphene base layer covers the surface of the polycrystalline silicon thin film; the metal composite electrode layer is deposited on the graphene base layer; and the silicon nitride protection layer covers the top of the whole module. The resistance value of the resistance module can be accurately controlled in the manufacturing process through the combination of shallow layer doping and deep layer doping and the self-alignment nanometer patterning technology, the high precision of the resistance is ensured, the high precision enables the resistance module to be kept stable when the temperature, the pressure and the like change, and drifting of the resistance value is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, in particular to a highly integrated silicon-based semiconductor polysilicon film resistor module and a manufacturing method thereof. Background Art

[0002] With the rapid development of modern electronic devices, the demand for integrated circuits (ICs) is increasing, and these circuits require higher integration, smaller size, and higher performance. As an important component of integrated circuits, polysilicon film resistors are widely used in various circuits, including analog circuits, digital circuits, and mixed signal circuits. However, with the increasing complexity of integrated circuits and the diversification of application environments, traditional polysilicon film resistors have gradually exposed some limitations in terms of accuracy, stability, size, temperature coefficient, and environmental adaptability, and cannot meet the high performance requirements of modern electronic devices.

[0003] The manufacturing process of traditional polysilicon film resistors usually includes depositing a polysilicon film on a silicon substrate and then performing a doping process to control the resistance value. The resistance value of traditional polysilicon film resistors often changes significantly when the temperature changes, resulting in a high temperature coefficient. This will cause unstable circuit performance in a working environment with large temperature changes, limiting the application range of polysilicon film resistors. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a highly integrated silicon-based semiconductor polysilicon film resistor module and a method for manufacturing the same, which solves the problem that the resistance value of traditional polysilicon film resistors often changes significantly when the temperature changes, causing unstable circuit performance.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: A highly integrated silicon-based semiconductor polysilicon film resistor module, comprising:

[0006] Silicon substrate layer: located at the bottom of the module, it is the base of the entire module;

[0007] Silicon oxide layer: located above the silicon substrate layer;

[0008] Nanocrystalline polysilicon thin film layer: deposited directly on top of the silicon oxide layer;

[0009] Self-aligned nanopatterned structure: a part of the nanocrystalline polysilicon thin film layer, with a specific pattern formed by photolithography and etching processes;

[0010] Double-layer doped region: located inside the nanocrystalline polysilicon thin film layer;

[0011] Graphene base layer: covers the surface of the polysilicon film at both ends of the self-aligned nano-patterned structure or at the position where electrodes need to be formed;

[0012] Metal composite electrode layer: deposited on top of the graphene base layer;

[0013] Silicon nitride protective layer: covers the top of the entire module, including the nanocrystalline polysilicon thin film layer and the metal composite electrode layer.

[0014] Preferably, the thickness of the silicon oxide layer is 5-10nm, the thickness of the nanocrystalline polysilicon thin film layer is 100-200nm, the thickness of the graphene base layer is 5-10nm, the thickness of the silicon nitride protective layer is 500nm, the shallow doping area in the double-layer doping area adopts low-energy ion implantation technology, the deep doping area adopts high-energy ion implantation technology, and is processed by a step annealing process combining rapid thermal annealing and laser annealing, the nanocrystalline polysilicon thin film layer is deposited by plasma enhanced chemical vapor deposition technology, and contains a small amount of carbon nanotube doping, and the doping concentration is about 1wt%, and the metal composite electrode layer is composed of two layers of titanium and aluminum, wherein the thickness of the titanium layer is 50-100nm, and the thickness of the aluminum layer is 200-300nm.

[0015] Preferably, a method for manufacturing a highly integrated silicon-based semiconductor polysilicon film resistor module comprises the following steps:

[0016] S1. Preparation and surface treatment of silicon substrate: Select a single crystal silicon substrate and perform standardized surface cleaning and treatment to make the substrate surface defect-free and clean. Then, grow a layer of silicon oxide film on the surface of the silicon substrate through a thermal oxidation process;

[0017] S2. Deposition of nanocrystalline polysilicon film: Deposit nanocrystalline polysilicon film on the substrate by plasma enhanced chemical vapor deposition technology. The nanocrystalline polysilicon film is doped with a small amount of carbon nanotubes to form the core functional layer of the resistor;

[0018] S3, self-aligned nanopatterning: using deep ultraviolet lithography and plasma etching technology to pattern the deposited nanocrystalline polysilicon film;

[0019] S4, double-layer doping and step annealing: shallow and deep doping of the polysilicon film is performed by ion implantation, and then the doped area is annealed by rapid thermal annealing and laser annealing technology;

[0020] S5. Formation of metal graphene composite electrode: depositing a graphene film on the contact area of ​​the resistor, and forming a titanium / aluminum composite metal electrode thereon, and then forming an electrode structure matching the resistor through photolithography and etching processes;

[0021] S6, packaging and protection: depositing a silicon nitride protection layer on the resistor module by low-pressure chemical vapor deposition, and then stacking and packaging multiple chips using three-dimensional integrated packaging technology;

[0022] S7. Testing and verification: Finally, the completed resistor module is subjected to comprehensive electrical performance and environmental reliability tests.

[0023] Preferably, the preparation and surface treatment of the silicon substrate comprises the following steps:

[0024] S101: Silicon substrate selection:

[0025] Use P-type or N-type single crystal silicon with a thickness of about 500 microns. The silicon wafer surface must be free of any defects and the surface roughness should be less than 1nm.

[0026] S102: Surface cleaning and treatment:

[0027] Use standard RCA cleaning steps SC-1 and SC-2 to remove organic and metal ion impurities from the surface:

[0028] SC-1: ammonia, hydrogen peroxide and water solution mixed in a ratio of 1:1:5, cleaned at 80°C for 10 minutes;

[0029] SC-2: a mixture of hydrochloric acid, hydrogen peroxide and water in a ratio of 1:1:6, cleaned at 80°C for 10 minutes;

[0030] Rinse with deionized water and blow dry in a dust-free environment;

[0031] S103: Growth of oxide layer:

[0032] A 5-10nm thick silicon oxide layer is grown on the surface of the silicon substrate through a thermal oxidation process. This oxide layer will serve as an isolation layer for the polysilicon film.

[0033] Preferably, the deposition of the nanocrystalline polysilicon thin film comprises the following steps:

[0034] S201: placing the silicon substrate into a plasma enhanced chemical vapor deposition system, and setting the operating temperature between 350-450°C;

[0035] S202: SiH2 is used as the silicon source gas, and H2 is introduced for hydrogen passivation. The nano-grain size is controlled within the range of 3-5 nm, and the film thickness is 100-200 nm.

[0036] S203: During the deposition process, a small amount of carbon nanotubes are doped, and the concentration is controlled at about 1 wt%.

[0037] Preferably, the self-aligned nanopatterning process comprises the following steps:

[0038] S301: using a deep ultraviolet lithography machine with a wavelength of 193 nm, patterning the nanocrystalline polysilicon through a self-aligned nanolithography mask, and controlling the thickness of the photoresist to be less than 200 nm;

[0039] S302: Under the protection of the photoresist mask, using a plasma etching process, anisotropically etching the polysilicon film to form a predetermined resistance pattern;

[0040] S303: After etching is completed, the photoresist is removed and O plasma cleaning is performed.

[0041] Preferably, the double-layer doping and step annealing process comprises the following steps:

[0042] S401: The first shallow doping layer:

[0043] Low energy 10-20keV phosphorus ion implantation is used, and the implantation dose is 1×101ions / cm 2 , to form a shallow uniformly doped region and control the resistance value of the surface layer;

[0044] S402: Second layer of deep doping:

[0045] High energy 100-200keV phosphorus ion implantation is used with an implantation dose of 5×101ions / cm 2 , forming a deep high conductivity region;

[0046] S403: Step annealing treatment:

[0047] The sample was placed in a rapid thermal annealing device with the temperature set to 700°C for 30 seconds to activate the shallow dopants;

[0048] Laser annealing is then carried out, with a laser wavelength of 1.06 μm infrared light and a scanning speed of 0.5 m / s. Uniform activation of deep dopants is achieved by scanning 3-5 times.

[0049] Preferably, the formation of the metal graphene composite electrode comprises the following steps:

[0050] S501: In the resistor contact area, a graphene film is deposited by chemical vapor deposition, and the graphene thickness is controlled at 5-10 nm. During the deposition process, methane is used as a carbon source gas, and the deposition temperature is controlled at about 900° C.-1100° C.;

[0051] S502: On the graphene layer, a 50-100 nm thick titanium layer is deposited by a physical vapor deposition method, and then a 200-300 nm thick aluminum layer is deposited to form a composite metal electrode;

[0052] The metal layer is patterned using photolithography and wet etching techniques to form an electrode pattern that matches the resistor structure.

[0053] Preferably, the packaging and protection comprises the following steps:

[0054] S601: depositing a 500nm thick silicon nitride layer on the entire module by low pressure chemical vapor deposition technology as a protective film;

[0055] S602: Using three-dimensional integrated packaging technology, multiple chips are stacked through wafer bonding process to form a three-dimensional structure; the packaging process includes wafer bonding, thermal compression bonding, cutting and testing.

[0056] Preferably, the testing and verification comprises the following steps:

[0057] S701: Use the probe station to test the resistance value, temperature coefficient and noise performance of the resistor module.

[0058] Pay special attention to the temperature stability test of resistors, and test the resistance change rate in the temperature range of -40℃ to 150℃;

[0059] S702: Conduct environmental reliability tests of high temperature and humidity, hot and cold cycles, and vibration to verify the stability and durability of the module in extreme environments.

[0060] The present invention provides a highly integrated silicon-based semiconductor polysilicon film resistor module and a manufacturing method thereof. It has the following beneficial effects:

[0061] 1. The present invention combines shallow and deep doping with self-aligned nano-patterning technology to enable the resistance value of the resistor module to be accurately controlled during the manufacturing process, ensuring the high precision of the resistor. This high precision allows the resistor module to remain stable when the temperature, pressure, etc. change, reducing the drift of the resistance value, and through optimized materials and doping processes, effectively reducing the temperature coefficient of the resistor, so that it remains stable at different operating temperatures. This is particularly important for precision equipment such as temperature sensors.

[0062] 2. The present invention adopts deep ultraviolet lithography and plasma etching technology, so that the module can realize nano-level graphic structure, further improve the density of integrated circuits, and effectively save circuit board space. In addition, the module adopts three-dimensional integrated packaging technology to stack and package multiple chips, further reducing the size of the module, making it suitable for use in high-density integrated circuits and meeting the miniaturization requirements of modern electronic devices.

[0063] 3. During the design and manufacturing process of the module of the present invention, the tolerance to high temperature and high humidity environments is improved by adding a protective layer (such as a silicon nitride layer) and optimizing the packaging technology, so that it can work stably for a long time in harsh working environments. By using special doping processes and material selections, the module can remain stable in high radiation environments, which is particularly important for special application fields such as aerospace.

[0064] 4. The present invention uses nanocrystalline polysilicon film and carbon nanotube doping technology to enable the module to achieve high precision while maintaining low power consumption characteristics, which is suitable for portable and low-power devices. The design of the graphene base layer and composite metal electrodes improves the thermal conductivity of the module, reduces the thermal effect during operation, and at the same time reduces electrical noise, thereby improving the overall performance of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 The present invention is a flow chart of a method for manufacturing a highly integrated silicon-based semiconductor polysilicon film resistor module. DETAILED DESCRIPTION

[0066] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] Please see attached Figure 1 The embodiment of the present invention provides a highly integrated silicon-based semiconductor polysilicon film resistor module, comprising:

[0068] Silicon substrate layer

[0069] Position: The bottom layer, which is the base of the entire module.

[0070] Description: High purity single crystal silicon ( <100> Crystal direction), provides mechanical support and basic platform, the layer is the carrier of all other layers, and all structures of the entire resistor module are built on this silicon substrate;

[0071] Silicon oxide (SiO) layer

[0072] Location: Located above the silicon substrate layer.

[0073] Description: A 5-10nm thick silicon oxide film serves as an insulating layer between the resistor structure and the silicon substrate. This oxide layer ensures that the polysilicon film is electrically isolated from the silicon substrate, preventing leakage current and reducing electrical interference.

[0074] Nanocrystalline polysilicon thin film layer

[0075] Location: Deposited directly on top of the silicon oxide layer.

[0076] Description: 100-200nm thick nanocrystalline polysilicon film, containing a small amount of carbon nanotubes (CNTs) as doping materials, which is the core functional layer of the resistor. The structure and doping of the polysilicon film determine the electrical properties of the resistor;

[0077] Self-aligned nanopatterned structures

[0078] Position: It is part of the nanocrystalline polysilicon thin film layer, but it is formed into a specific pattern through lithography and etching processes.

[0079] Description: The polysilicon film is etched into a precise resistor shape through deep ultraviolet lithography (DUV) and plasma etching technology. This patterned polysilicon structure determines the geometric size of the resistor, thus affecting its resistance value;

[0080] Double doped region

[0081] Location: Located inside the nanocrystalline polysilicon thin film layer.

[0082] Description: The shallow doping area is close to the surface of the polysilicon film, and the deep doping area is close to the bottom of the polysilicon film. Shallow doping controls the resistance value, and deep doping improves conductivity. After step annealing, the structure of the doping area is optimized to ensure the temperature stability of the resistor;

[0083] Graphene base layer

[0084] Position: at both ends of the self-aligned nano-patterned structure or at the position where electrodes need to be formed, covering the surface of the polysilicon film.

[0085] Description: 5-10nm thick graphene film, as the base layer of the metal electrode, this layer of graphene provides low contact resistance and excellent thermal conductivity, optimizing the interface between the electrode and the resistive material;

[0086] Metal composite electrode layer

[0087] Location: Deposited on top of the graphene base layer.

[0088] Description: It includes a layer of titanium (Ti) 50-100nm thick and a layer of aluminum (Al) 200-300nm thick to form composite metal electrodes, which are in close contact with the graphene base layer to ensure good current conduction and provide mechanical connection strength;

[0089] Silicon nitride (SiN) protective layer

[0090] Location: Covering the top of the entire module, including the nanocrystalline polysilicon thin film layer and the metal composite electrode layer.

[0091] Description: A 500nm thick silicon nitride film acts as a protective layer for the resistor module, preventing the intrusion of environmental pollutants such as moisture and chemicals, ensuring the reliability of the resistor module in various environments.

[0092] Three-dimensional integrated packaging structure

[0093] Location: Outside the silicon nitride protective layer, which is the outermost structure of the entire module.

[0094] Description: A three-dimensional package formed by stacking multiple resistor modules and other functional components, usually including wafer bonding and thermal compression bonding. The package integrates multiple circuit units together, reduces the module volume, and enhances the functionality and integration of the system.

[0095] Relationships between layers

[0096] Vertical relationship: Each layer of the structure is stacked on top of each other, starting from the silicon substrate layer at the bottom and stacking up layer by layer until the top silicon nitride protection layer and three-dimensional integrated packaging.

[0097] Electrical connection: The metal composite electrode directly contacts the double-layer doped region in the nanocrystalline polysilicon thin film layer through the graphene base layer to form a low-resistance ohmic contact, ensuring the precise conductive performance of the resistor.

[0098] Insulation and protection: The silicon oxide layer and silicon nitride layer play the role of bottom insulation and top protection respectively, ensuring the electrical isolation and environmental tolerance of the entire module.

[0099] The thickness of the silicon oxide layer is 5-10nm, the thickness of the nanocrystalline polysilicon film layer is 100-200nm, the thickness of the graphene base layer is 5-10nm, the thickness of the silicon nitride protective layer is 500nm, the shallow doping area in the double-layer doping area adopts low-energy ion implantation technology, the deep doping area adopts high-energy ion implantation technology, and is processed by a step annealing process combining rapid thermal annealing and laser annealing. The nanocrystalline polysilicon film layer is deposited by plasma enhanced chemical vapor deposition technology and contains a small amount of carbon nanotube doping with a doping concentration of about 1wt%. The metal composite electrode layer is composed of two layers of titanium and aluminum, wherein the thickness of the titanium layer is 50-100nm and the thickness of the aluminum layer is 200-300nm.

[0100] A method for manufacturing a highly integrated silicon-based semiconductor polysilicon film resistor module comprises the following steps:

[0101] S1. Preparation and surface treatment of silicon substrate: This step is to provide a high-quality substrate for the resistor module. By selecting a high-purity single-crystal silicon substrate and performing standardized surface cleaning and treatment, the substrate surface is ensured to be defect-free and clean. Subsequently, a layer of silicon oxide film is grown on the surface of the silicon substrate through a thermal oxidation process to provide electrical isolation for the subsequent deposition of polysilicon film;

[0102] S2, deposition of nanocrystalline polysilicon film: In this step, nanocrystalline polysilicon film is deposited on the substrate by plasma enhanced chemical vapor deposition (PECVD) technology. The nanocrystalline polysilicon film is doped with a small amount of carbon nanotubes to enhance the conductivity and temperature stability of the film, forming the core functional layer of the resistor;

[0103] S3, self-aligned nanopatterning: This step involves patterning the deposited nanocrystalline polysilicon film using deep ultraviolet lithography (DUV) technology and plasma etching process. This step is designed to form precise resistor patterns to ensure high resolution and consistency of the resistor structure;

[0104] S4, double-layer doping and step annealing: The polysilicon film is doped shallowly and deeply through ion implantation to form a stable resistor area. Subsequently, the doped area is annealed using rapid thermal annealing (RTA) and laser annealing technology to further optimize the electrical performance and temperature stability of the resistor;

[0105] S5, metal graphene composite electrode formation: This step includes depositing a graphene film on the contact area of ​​the resistor and forming a titanium / aluminum composite metal electrode thereon. The graphene base layer helps to reduce the contact resistance, and the titanium / aluminum composite electrode provides good conductivity and mechanical strength, and an electrode structure matching the resistor is formed through photolithography and etching processes;

[0106] S6, Packaging and protection: A silicon nitride protective layer is deposited on the resistor module through low-pressure chemical vapor deposition (LPCVD) to enhance the module's environmental tolerance and insulation performance. Then, multiple chips are stacked and packaged using three-dimensional integrated packaging technology to improve the module's integration and reliability;

[0107] S7. Testing and Verification: Finally, the completed resistor module is subjected to comprehensive electrical performance and environmental reliability tests to ensure the stability and durability of the module under different temperature and environmental conditions, and to verify whether it meets the design requirements and application standards.

[0108] The preparation and surface treatment of silicon substrates include the following steps:

[0109] S101: Silicon substrate selection:

[0110] Choose high purity P-type or N-type single crystal silicon ( <100> crystal direction), the thickness is controlled at about 500 microns.

[0111] The silicon wafer surface must be free of any defects, and wafers with a surface roughness of less than 1nm should be selected.

[0112] S102: Surface cleaning and treatment:

[0113] Use standard RCA cleaning steps (SC-1 and SC-2) to remove organic and metal ion impurities from the surface:

[0114] SC-1: Ammonia, hydrogen peroxide and water solution were mixed in a ratio of 1:1:5 and cleaned at 80°C for 10 minutes.

[0115] SC-2: Mix hydrochloric acid, hydrogen peroxide and water solution in a ratio of 1:1:6 and clean at 80°C for 10 minutes.

[0116] Rinse with deionized water and blow dry in a dust-free environment.

[0117] S103: Growth of oxide layer:

[0118] A 5-10nm thick silicon oxide (SiO) layer is grown on the surface of the silicon substrate through a thermal oxidation process. This oxide layer will serve as an isolation layer for the polysilicon film to ensure the stability of the resistor module.

[0119] The deposition of nanocrystalline polysilicon thin films includes the following steps:

[0120] S201: placing the silicon substrate into a plasma enhanced chemical vapor deposition (PECVD) system, with the operating temperature set between 350-450°C to ensure high-quality growth of nanocrystalline silicon;

[0121] S202: SiH2 is used as the silicon source gas, and H2 is introduced for hydrogen passivation. The nano-grain size is controlled within the range of 3-5 nm, and the film thickness is 100-200 nm.

[0122] S203: During the deposition process, a small amount of carbon nanotubes (CNTs) are doped, with the concentration controlled at about 1 wt %, and the distribution of the carbon nanotubes is precisely controlled to improve the conductivity and temperature stability of the resistor.

[0123] The self-aligned nanopatterning process includes the following steps:

[0124] S301: Use a deep ultraviolet lithography machine with a wavelength of 193nm to pattern the nanocrystalline polysilicon through a self-aligned nanolithography mask.

[0125] The thickness of the photoresist is controlled below 200nm to ensure the formation of high-resolution graphics.

[0126] S302: Under the protection of the photoresist mask, a highly selective plasma etching process (such as HBr / Cl mixed gas) is used to anisotropically etch the polysilicon film to form a predetermined resistor pattern.

[0127] S303: After etching is completed, the photoresist is removed and O plasma cleaning is performed to ensure that there is no residue on the edge of the pattern.

[0128] The double-layer doping and step annealing process includes the following steps:

[0129] S401: The first shallow doping layer:

[0130] Low energy (10-20keV) phosphorus ion (P) implantation is used with an implantation dose of 1×101ions / cm 2 , to form a shallow uniformly doped region and control the resistance value of the surface layer;

[0131] S402: Second layer of deep doping:

[0132] High energy (100-200keV) phosphorus ion implantation is used with an implantation dose of 5×101ions / cm 2 , forming a deep high conductivity area to ensure resistance stability at operating temperature;

[0133] S403: Step annealing treatment:

[0134] Step 1: Place the sample in a rapid thermal annealing (RTA) device at 700°C for 30 seconds to activate the shallow dopants.

[0135] Step 2: Laser annealing is then carried out. The laser wavelength is 1.06μm infrared light and the scanning speed is 0.5m / s. Multiple scans (3-5 times) are performed to complete the uniform activation of deep dopants and ensure the stability of the entire resistor structure.

[0136] The formation of the metal graphene composite electrode includes the following steps:

[0137] S501: In the resistive contact area, a layer of graphene film is deposited by chemical vapor deposition (CVD), and the thickness of the graphene is controlled to be 5-10nm to reduce the contact resistance.

[0138] During the deposition process, methane (CH) was used as the carbon source gas and the deposition temperature was controlled at about 900°C-1100°C.

[0139] S502: On the graphene layer, a 50-100 nm thick titanium (Ti) layer is deposited by a physical vapor deposition (PVD) method, and then a 200-300 nm thick aluminum (Al) layer is deposited to form a composite metal electrode.

[0140] The metal layer is patterned using photolithography and wet etching techniques to form an electrode pattern that matches the resistor structure.

[0141] Encapsulation and protection include the following steps:

[0142] S601: A 500nm thick silicon nitride (SiN) layer is deposited on the entire module by low-pressure chemical vapor deposition (LPCVD) technology as a protective film to improve the environmental tolerance and insulation performance of the module;

[0143] S602: Using 3D integrated packaging (3DPackaging) technology, multiple chips are stacked through wafer bonding process to form a three-dimensional structure, further improving the integration level.

[0144] The packaging process includes wafer bonding, thermocompression bonding, dicing and testing, and finally plastic or ceramic packaging to improve the mechanical strength and reliability of the module.

[0145] Testing and verification includes the following steps:

[0146] S701: Use a probe station to fully test the resistance value, temperature coefficient and noise performance of the resistor module to ensure that all parameters meet the design requirements.

[0147] Special attention is paid to the temperature stability test of resistors, and the resistance change rate is tested in the temperature range of -40℃ to 150℃ to ensure that the temperature coefficient meets expectations.

[0148] S702: Conduct environmental reliability tests such as high temperature and high humidity (HTHH), hot and cold cycles, and vibration to verify the stability and durability of the module in extreme environments.

[0149] The following is an introduction in conjunction with specific embodiments:

[0150] Example 1: Low temperature drift resistor module for high-precision temperature sensor

[0151] Process parameters:

[0152] Silicon substrate: Choose N-type single crystal silicon ( <100> crystal direction), thickness 500 μm.

[0153] Silicon oxide layer thickness: maintained at 8nm to ensure insulation performance.

[0154] Nanocrystalline polysilicon film thickness: 150nm, enhancing the stability and precision of resistors.

[0155] Shallow doping: phosphorus ions (P), energy 15keV, dose 1×101ions / cm 2 .

[0156] Deep doping: phosphorus ion (P), energy 150keV, dose 5×101ions / cm 2 .

[0157] RTA temperature: set to 700°C to activate the dopant.

[0158] Laser annealing: Use 1.06 μm infrared laser, scan speed 0.5 m / s, and perform multiple scans.

[0159] Final Features:

[0160] Resistance value: 10kΩ, suitable for high-precision temperature measurement.

[0161] Temperature coefficient: <50ppm / ℃, ensuring stability over a wide temperature range.

[0162] Application areas: high-precision temperature sensors, pressure sensors, etc.

[0163] Example 2: High temperature resistant resistor module for automotive electronics

[0164] Process parameters:

[0165] Silicon substrate: Choose P-type single crystal silicon ( <100> crystal direction), thickness 500 μm.

[0166] Silicon oxide layer thickness: 10nm, to increase insulation effect.

[0167] Nanocrystalline polysilicon film thickness: 200nm, improves the heat resistance of resistors.

[0168] Shallow doping: phosphorus ions (P), energy 10keV, dose 1×101ions / cm 2 .

[0169] Deep doping: phosphorus ion (P), energy 200keV, dose 5×101ions / cm 2 .

[0170] RTA temperature: set to 700°C to activate shallow dopants.

[0171] Laser annealing: 1.06μm infrared laser, scanning speed 0.5m / s.

[0172] Final Features:

[0173] Resistance value: 100Ω, suitable for low resistance applications in automotive electronics.

[0174] Temperature coefficient: <100ppm / ℃, can work in extreme temperature environment.

[0175] Application areas: automotive electronic control modules, sensors.

[0176] Example 3: Ultra-thin resistor module for portable medical devices

[0177] Process parameters:

[0178] Silicon substrate: Select high-purity P-type single crystal silicon with a thickness of 500 microns.

[0179] Silicon oxide layer thickness: 5nm, minimized thickness to achieve ultra-thin structure.

[0180] Nanocrystalline polysilicon film thickness: 100nm, reducing the overall thickness of the module.

[0181] Shallow doping: phosphorus ions (P), energy 20keV, dose 1×101ions / cm 2 .

[0182] Deep doping: phosphorus ion (P), energy 150keV, dose 5×101ions / cm 2 .

[0183] RTA temperature: set to 700°C.

[0184] Laser annealing: 1.06μm infrared laser, scanning speed 0.5m / s.

[0185] Final Features:

[0186] Resistance value: 5kΩ, suitable for low power applications.

[0187] Temperature coefficient: <80ppm / ℃.

[0188] Application areas: wearable devices, portable medical instruments.

[0189] Example 4: High stability resistor module for aerospace applications

[0190] Process parameters:

[0191] Silicon substrate: Select N-type single crystal silicon with a thickness of 500 microns.

[0192] Silicon oxide layer thickness: 10nm, ensuring electrical insulation.

[0193] Nanocrystalline polysilicon film thickness: 200nm, increasing durability and stability.

[0194] Shallow doping: phosphorus ions (P), energy 15keV, dose 1×101ions / cm2 .

[0195] Deep doping: phosphorus ion (P), energy 150keV, dose 5×101ions / cm 2 .

[0196] RTA temperature: set to 700°C.

[0197] Laser annealing: 1.06μm infrared laser, scanning speed 0.5m / s.

[0198] Final Features:

[0199] Resistance value: 50Ω, suitable for use in high radiation environments.

[0200] Temperature coefficient: <100ppm / ℃.

[0201] Application areas: satellites, space station equipment.

[0202] Example 5: Low-noise resistor module for high-density integrated circuits

[0203] Process parameters:

[0204] Silicon substrate: Select P-type single crystal silicon with a thickness of 500 microns.

[0205] Silicon oxide layer thickness: 8nm, optimized electrical isolation effect.

[0206] Nanocrystalline polysilicon film thickness: 100nm, reducing self-inductance and capacitance effects.

[0207] Shallow doping: phosphorus ions (P), energy 10keV, dose 1×101ions / cm 2 .

[0208] Deep doping: phosphorus ion (P), energy 150keV, dose 5×101ions / cm 2 .

[0209] RTA temperature: set to 700°C.

[0210] Laser annealing: 1.06μm infrared laser, scanning speed 0.5m / s.

[0211] Final Features:

[0212] Resistance value: 50Ω, suitable for applications in high frequency circuits.

[0213] Noise figure: Significantly lower than traditional resistor modules.

[0214] Application areas: radio frequency circuits, high-speed digital signal processing chips.

[0215] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A highly integrated silicon-based semiconductor polysilicon film resistor module, characterized in that: include: Silicon substrate layer: located at the bottom of the module, it is the base of the entire module; Silicon oxide layer: located above the silicon substrate layer; Nanocrystalline polysilicon thin film layer: deposited directly on top of the silicon oxide layer; Self-aligned nanopatterned structure: a part of the nanocrystalline polysilicon thin film layer, with a specific pattern formed by photolithography and etching processes; Double-layer doped region: located inside the nanocrystalline polysilicon thin film layer; Graphene base layer: covers the surface of the polysilicon film at both ends of the self-aligned nano-patterned structure or at the position where electrodes need to be formed; Metal composite electrode layer: deposited on top of the graphene base layer; Silicon nitride protective layer: covers the top of the entire module, including the nanocrystalline polysilicon thin film layer and the metal composite electrode layer.

2. A highly integrated silicon-based semiconductor polysilicon film resistor module according to claim 1, characterized in that: The thickness of the silicon oxide layer is 5-10nm, the thickness of the nanocrystalline polysilicon thin film layer is 100-200nm, the thickness of the graphene base layer is 5-10nm, the thickness of the silicon nitride protective layer is 500nm, the shallow doping area in the double-layer doping area adopts low-energy ion implantation technology, the deep doping area adopts high-energy ion implantation technology, and is processed by a step annealing process combining rapid thermal annealing and laser annealing, the nanocrystalline polysilicon thin film layer is deposited by plasma enhanced chemical vapor deposition technology, and contains a small amount of carbon nanotube doping, and the doping concentration is about 1wt%, and the metal composite electrode layer is composed of two layers of titanium and aluminum metal, wherein the thickness of the titanium layer is 50-100nm, and the thickness of the aluminum layer is 200-300nm.

3. A method for manufacturing a highly integrated silicon-based semiconductor polycrystalline silicon film resistor module, according to the highly integrated silicon-based semiconductor polycrystalline silicon film resistor module according to claim 1 or 2, characterized in that: The following steps are involved: S1. Preparation and surface treatment of silicon substrate: Select a single crystal silicon substrate and perform standardized surface cleaning and treatment to make the substrate surface defect-free and clean. Then, grow a layer of silicon oxide film on the surface of the silicon substrate through a thermal oxidation process; S2. Deposition of nanocrystalline polysilicon film: Deposit nanocrystalline polysilicon film on the substrate by plasma enhanced chemical vapor deposition technology. The nanocrystalline polysilicon film is doped with a small amount of carbon nanotubes to form the core functional layer of the resistor; S3, self-aligned nanopatterning: using deep ultraviolet lithography and plasma etching technology to pattern the deposited nanocrystalline polysilicon film; S4, double-layer doping and step annealing: shallow and deep doping of the polysilicon film is performed by ion implantation, and then the doped area is annealed by rapid thermal annealing and laser annealing technology; S5. Formation of metal graphene composite electrode: depositing a graphene film on the contact area of ​​the resistor, and forming a titanium / aluminum composite metal electrode thereon, and then forming an electrode structure matching the resistor through photolithography and etching processes; S6, packaging and protection: depositing a silicon nitride protection layer on the resistor module by low-pressure chemical vapor deposition, and then stacking and packaging multiple chips using three-dimensional integrated packaging technology; S7. Testing and verification: Finally, the completed resistor module is subjected to comprehensive electrical performance and environmental reliability tests.

4. The method for manufacturing a highly integrated silicon-based semiconductor polysilicon film resistor module according to claim 3, characterized in that: The preparation and surface treatment of the silicon substrate comprises the following steps: S101: Silicon substrate selection: Use P-type or N-type single crystal silicon with a thickness of about 500 microns. The silicon wafer surface must be free of any defects and the surface roughness should be less than 1nm. S102: Surface cleaning and treatment: Use standard RCA cleaning steps SC-1 and SC-2 to remove organic and metal ion impurities from the surface: SC-1: ammonia, hydrogen peroxide and water solution mixed in a ratio of 1:1:5, cleaned at 80°C for 10 minutes; SC-2: a mixture of hydrochloric acid, hydrogen peroxide and water in a ratio of 1:1:6, cleaned at 80°C for 10 minutes; Rinse with deionized water and blow dry in a dust-free environment; S103: Growth of oxide layer: A 5-10nm thick silicon oxide layer is grown on the surface of the silicon substrate through a thermal oxidation process. This oxide layer will serve as an isolation layer for the polysilicon film.

5. The method for manufacturing a highly integrated silicon-based semiconductor polysilicon film resistor module according to claim 3, characterized in that: The deposition of the nanocrystalline polysilicon film comprises the following steps: S201: placing the silicon substrate into a plasma enhanced chemical vapor deposition system, and setting the operating temperature between 350-450°C; S202: SiH2 is used as the silicon source gas, and H2 is introduced for hydrogen passivation. The nano-grain size is controlled within the range of 3-5 nm, and the film thickness is 100-200 nm. S203: During the deposition process, a small amount of carbon nanotubes are doped, and the concentration is controlled at about 1 wt%.

6. The method for manufacturing a highly integrated silicon-based semiconductor polysilicon film resistor module according to claim 3, characterized in that: The self-aligned nanopatterning process comprises the following steps: S301: using a deep ultraviolet lithography machine with a wavelength of 193 nm, patterning the nanocrystalline polysilicon through a self-aligned nanolithography mask, and controlling the thickness of the photoresist to be less than 200 nm; S302: Under the protection of the photoresist mask, using a plasma etching process, anisotropically etching the polysilicon film to form a predetermined resistance pattern; S303: After etching is completed, the photoresist is removed and O plasma cleaning is performed.

7. The method for manufacturing a highly integrated silicon-based semiconductor polysilicon film resistor module according to claim 3, characterized in that: The double-layer doping and step annealing process comprises the following steps: S401: The first shallow doping layer: Low energy 10-20keV phosphorus ion implantation is used, and the implantation dose is 1×101ions / cm 2 , to form a shallow uniformly doped region and control the resistance value of the surface layer; S402: Second layer of deep doping: High energy 100-200keV phosphorus ion implantation is used with an implantation dose of 5×101ions / cm 2 , forming a deep high conductivity region; S403: Step annealing treatment: The sample was placed in a rapid thermal annealing device with the temperature set to 700°C for 30 seconds to activate the shallow dopants; Laser annealing is then carried out, with a laser wavelength of 1.06 μm infrared light and a scanning speed of 0.5 m / s. Uniform activation of deep dopants is achieved by scanning 3-5 times.

8. The method for manufacturing a highly integrated silicon-based semiconductor polysilicon film resistor module according to claim 3, characterized in that: The metal graphene composite electrode is formed by the following steps: S501: depositing a graphene film in the resistive contact region by chemical vapor deposition, wherein the graphene thickness is controlled at 5-10 nm, and during the deposition process, methane is used as a carbon source gas, and the deposition temperature is controlled at 900° C.-1100° C.; S502: On the graphene layer, a 50-100 nm thick titanium layer is deposited by a physical vapor deposition method, and then a 200-300 nm thick aluminum layer is deposited to form a composite metal electrode; The metal layer is patterned using photolithography and wet etching techniques to form an electrode pattern that matches the resistor structure.

9. The method for manufacturing a highly integrated silicon-based semiconductor polysilicon film resistor module according to claim 3, characterized in that: The packaging and protection comprises the following steps: S601: depositing a 500nm thick silicon nitride layer on the entire module by low pressure chemical vapor deposition technology as a protective film; S602: Using three-dimensional integrated packaging technology, multiple chips are stacked through wafer bonding process to form a three-dimensional structure; the packaging process includes wafer bonding, thermal compression bonding, cutting and testing.

10. The method for manufacturing a highly integrated silicon-based semiconductor polysilicon film resistor module according to claim 3, characterized in that: The testing and verification includes the following steps: S701: Use the probe station to test the resistance value, temperature coefficient and noise performance of the resistor module. Pay special attention to the temperature stability test of resistors, and test the resistance change rate in the temperature range of -40℃ to 150℃; S702: Conduct environmental reliability tests of high temperature and humidity, hot and cold cycles, and vibration to verify the stability and durability of the module in extreme environments.

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