Bidirectional current response difference thin-film resistor and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor devices, and provides a bidirectional current response differential film resistor and a preparation method thereof. The oxide layer is arranged on the N-type silicon substrate; the first window is formed in the oxide layer; the P-type doped region is formed by injecting P-type ions into the first window; the film layer comprises a first resistor and a second resistor which are arranged at intervals and have different resistance values; the passivation layer is arranged on the oxide layer and the thin film layer; the second window is formed in the passivation layer and corresponds to the first window B; the N-type doped region is formed by injecting N-type ions into the second window; the third window is formed in the passivation layer; a first electrode, a second electrode, a first test PAD and a second test PAD are respectively formed on the front metal layer. According to the thin-film resistor provided by the invention, when forward current passes through a device, one resistor takes effect, when reverse current passes through the device, the other resistor takes effect, and when the current directions are different, the device presents different resistance values.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly relates to a thin film resistor with different bidirectional current responses and a preparation method thereof. Background Art

[0002] With the rapid development of technology, electronic devices are constantly moving towards miniaturization, integration, and precision, which puts forward higher requirements for resistor technology.

[0003] A thin film resistor is a common electronic component. A conductive metal or alloy thin film (usually with a thickness of nanometers) is formed on an insulating substrate (such as ceramics, glass) through processes such as vacuum deposition or sputtering, and then the resistance value is adjusted through photolithography or laser etching. Commonly used ones include nickel-chromium (NiCr), tantalum nitride (TaN), etc., with stable performance; a spiral conductive path is formed through patterned etching to precisely control the resistance value. It is widely used in precision instruments (such as medical equipment, test instruments), high-frequency circuits (radio frequency modules), aerospace electronics, etc.

[0004] For traditional thin film resistors, although the resistance values are the same under forward and reverse voltages, in some specific scenarios, their performance is difficult to meet the growing demands. For example, in circuits such as overvoltage protection, current limiting, and signal shaping, it is often necessary for the resistor to exhibit different resistance values according to the change in the voltage direction or magnitude to achieve more flexible circuit control. Conventional thin film resistors cannot provide this non-linear resistance characteristic, which to a certain extent limits the flexibility and innovation of circuit design. Summary of the Invention

[0005] Aiming at the defects in the prior art, the present invention provides a thin film resistor with different bidirectional current responses and a preparation method thereof to solve the problem that the current thin film resistor cannot provide non-linear resistance characteristics according to the change in the voltage direction or magnitude.

[0006] In a first aspect, a thin film resistor with different bidirectional current responses provided by the present invention includes: An N-type silicon substrate; An oxide layer disposed on the N-type silicon substrate; A first window opened on the oxide layer. The first window includes first window A, first window B, first window C, and first window D. First window A is located on one side of the N-type silicon substrate, and first window B, first window C, and first window D are located on the other side of the N-type silicon substrate; A P-type doped region disposed on the N-type silicon substrate and formed by injecting P-type ions through the first window; A thin film layer disposed on the oxide layer and between first window A and first window B; the thin film layer includes a first resistor and a second resistor which are arranged at intervals and have different resistance values; A passivation layer disposed on the oxide layer and the thin film layer; A second window is formed on the passivation layer and is provided corresponding to the first window B. An N-type doped region is formed on the N-type silicon substrate and is formed by implanting N-type ions through the second window. A third window is formed on the passivation layer. The third window includes a third window A, a third window B, and a third window C. The third window A and the third window B respectively correspond to the first window A and the first window D, and the third window C is formed outside the first window D. The front metal layer is formed between the first resistor and the second resistor to form a first electrode, is formed on the first window D and the third window C to form a second electrode, is formed on the first window A to form a first test PAD, and is formed on the second window to form a second test PAD. An oxidation insulating layer is formed at the bottom of the N-type silicon substrate.

[0007] As can be seen from the above technical solutions, for a thin film resistor with different two-way current response differences provided by the present invention, when a forward current flows through the device, the first resistor becomes effective; when a reverse current flows through the device, the second resistor becomes effective. When the current directions are different, the device presents different resistance values. At the same time, two test PADs are respectively formed on the front metal layer to facilitate the test of a single resistor.

[0008] Optionally, at least two of the first window D and the third window C are provided. When the current flowing directions are different, the first window D and the third window C respectively form paths with the second electrode. By providing at least two first window D and third window C, when there is a problem with one of the paths, the other path can still operate, improving the reliability of the product.

[0009] Optionally, the thickness of the oxide layer is 1 - 2 μm.

[0010] Optionally, the implantation dose of the P-type doped region is 1×10 16 ~5×10 18 cm -2 , and the implantation energy is 100 keV - 200 keV.

[0011] Optionally, the implantation dose of the N-type doped region is 1×10 15 ~5×10 17 cm -2 , and the implantation energy is 50 keV - 100 keV.

[0012] Optionally, the thin film layer includes one or more of the following low-temperature drift materials: nickel-chromium alloy, titanium-nickel-chromium alloy, nickel-chromium-aluminum alloy, nickel-phosphorus alloy, titanium nitride, tantalum nitride.

[0013] Optionally, the material of the passivation layer is SiO2 or Si3N4, and the thickness is 1 - 2 μm.

[0014] Optionally, the material of the front metal layer is Al - Si.

[0015] Optionally, the thickness of the oxidation insulation layer is 2 - 3 μm.

[0016] In a second aspect, a method for preparing a thin - film resistor with bidirectional current response difference provided by the present invention is used to prepare the thin - film resistor with bidirectional current response difference provided by the first aspect, and includes: S1. Form an oxide layer on an N - type silicon substrate; S2. Open a first window in the oxide layer to expose the N - type silicon substrate; S3. Inject P - type ions into the first window to form a P - type doped region; S4. Form a thin - film layer on the oxide layer, and the thin - film layer forms a first resistor and a second resistor that are spaced apart from each other and have different resistance values; S5. Form a passivation layer on the oxide layer and the thin - film layer; S6. Open a second window in the passivation layer; S7. Inject N - type ions into the second window to form an N - type doped region; S8. Open a third window in the passivation layer; S9. Sputter the front metal layer, the front metal layer contacts the N - type silicon substrate and the thin - film layer, and the edge of the front metal layer covers the passivation layer; Remove part of the region of the front metal layer to retain the spaced - apart first electrode, second electrode, first test PAD, and second test PAD; S10. Thinning the back surface, annealing the wafer, and forming an oxidation insulation layer on the back surface of the N - type silicon substrate.

[0017] Adopting the above - mentioned technical solution, the present application has the following beneficial effects: (1) For the resistor provided by the present invention, when a forward current passes through the device, one of the resistors becomes effective, and when a reverse current passes through the device, the other resistor becomes effective. With different current directions, the device presents different resistance values.

[0018] (2) The front metal layer of the present invention is provided with two test PADs. The first electrode forms a loop with the first / second test PAD. At this time, under forward and reverse currents, the resistance value changes linearly, which is convenient for checking the resistance value of a single resistor; Both the first electrode and the second electrode are arranged on the surface of the device, and the process flow is simple and the manufacturing cost is low.

[0019] (3) The passivation layer covers the thin - film layer, avoiding direct contact between the resistor body and water vapor, and increasing the reliability of the thin - film resistor.

[0020] (4) After thinning the back surface, an oxidation insulation layer is formed, effectively avoiding device failure caused by a back - side path. Description of the Drawings

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0022] Figure 1 Shows a schematic diagram of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 2 Shows a schematic diagram of the current flow direction of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 3 Shows another schematic diagram of the current flow direction of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 4 Shows a test schematic diagram of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 5 Shows an equivalent circuit diagram of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 6 Shows a schematic diagram of the product obtained in S1 of the preparation method of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 7 Shows a schematic diagram of the product obtained in S3 of the preparation method of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 8 Shows a schematic diagram of the product obtained in S4 of the preparation method of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 9 Shows a schematic diagram of the product obtained in S7 of the preparation method of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 10 Shows a schematic diagram of the product obtained in S8 of the preparation method of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 11 Shows a schematic diagram of the product obtained in S9 of the preparation method of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention; Figure 12 Shows a top view of a thin film resistor with bidirectional current response difference provided by an embodiment of the present invention.

[0023] Reference numerals: 1 - N - type silicon substrate; 2 - oxide layer; 3 - P - type doped region; 4 - thin film layer; 41 - first resistor; 42 - second resistor; 5 - passivation layer; 6 - N - type doped region; 7 - front - side metal layer; 71 - first electrode; 72 - second electrode; 73 - first test PAD; 74 - second test PAD; 8 - oxide insulating layer. Detailed implementation mode

[0024] The embodiments of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, so they are only used as examples and cannot be used to limit the protection scope of the present invention.

[0025] It should be noted that unless otherwise specified, the technical terms or scientific terms used in this application should have the ordinary meaning understood by those skilled in the art to which the present invention belongs.

[0026] In one embodiment, as Figure 1 shown, a thin - film resistor with different bidirectional current responses is provided, including: An N - type silicon substrate 1, the crystal orientation of the N - type silicon substrate 1 is <1 0 0>, and the resistivity is less than 10×10 -3 Ω·cm.

[0027] An oxide layer 2, disposed on the N - type silicon substrate 1, and the thickness of the oxide layer 2 is 1 - 2μm.

[0028] A first window, opened on the oxide layer 2, the first window includes first window A, first window B, first window C, and first window D. First window A is located on one side of the N - type silicon substrate 1, and first window B, first window C, and first window D are located on the other side of the N - type silicon substrate 1. First window B, first window C, and first window D are arranged sequentially from the central region to the outside.

[0029] A P - type doped region 3, disposed on the N - type silicon substrate 1, formed by implanting P - type ions through the first window. The P - type ions can be boron; the implantation dose of the P - type doped region 3 is 1×10 16 ~5×10 18 cm -2 , and the implantation energy is 100 keV - 200 keV. After ion implantation, the wafer is annealed to repair lattice damage and activate impurities to form the P - type doped region 3.

[0030] The thin film layer 4 is disposed on the oxide layer 2 and between the first window A and the first window B; the thin film layer 4 includes a first resistor 41 and a second resistor 42 which are spaced apart and have different resistances. The thickness of the thin film layer 4 is 50 nm to 2000 nm; wherein the first resistor 41 and the second resistor 42 have the same length, which is 500 μm to 3000 μm, and different widths to achieve different resistances. The width of the first resistor 41 is 100 μm to 1000 μm, the width of the second resistor 42 is 300 μm to 1500 μm, and the spacing between the first resistor 41 and the second resistor 42 is 600 μm to 4600 μm.

[0031] The passivation layer 5 is disposed on the oxide layer 2 and the thin film layer 4; the material of the passivation layer 5 is SiO2 or Si3N4, and the thickness is 1 to 2 μm.

[0032] The second window is opened on the passivation layer 5 and corresponds to the first window B; the width of the second window is 55 μm to 305 μm.

[0033] The N-type doped region 6 is disposed on the N-type silicon substrate 1 and is formed by implanting N-type ions through the second window. The N-type ions can be phosphorus or arsenic; the implantation dose of the N-type doped region 6 is 1×10 15 ~5×10 17 cm -2 , and the implantation energy is 50 keV to 100 keV.

[0034] The third window is opened on the passivation layer 5; the third window includes a third window A, a third window B, and a third window C. The third window A and the third window B respectively correspond to the first window A and the first window D, and the third window C is opened outside the first window D; the width of the third window A is 55 μm to 305 μm, and the widths of the third window A, the third window B, and the third window C are 15 μm to 55 μm.

[0035] The front metal layer 7 is disposed between the first resistor 41 and the second resistor 42 to form a first electrode, is disposed on the first window D and the third window C to form a second electrode 72, is disposed on the first window A to form a first test PAD 73, and is disposed on the second window to form a second test PAD 74; The oxide insulating layer 8 is disposed at the bottom of the N-type silicon substrate 1; the thickness of the oxide insulating layer 8 is 2 to 3 μm, and the oxide insulating layer 8 can prevent the backside path from causing device failure.

[0036] See Figure 2 , when a forward current flows through the device, the first resistor 41 becomes effective; see Figure 3 , when a reverse current flows through the device, the second resistor 42 becomes effective, and with different current directions, the device exhibits different resistances; see Figure 4, two test PADs 73 and 74 are also respectively formed on the same positive metal layer 7 for the test of a single resistor.

[0037] As Figure 4 shown, taking the first resistor 41 as an example, when the positive and negative power supplies are connected to the first electrode 71 and the first / second test PADs, the current will not pass through the substrate. At this time, no matter how the power supply polarity changes, the resistor to be tested shows a linear state. By setting the test PADs, it can be used to respectively detect whether the first resistor 41 / second resistor 42 is stable, ensuring the accuracy and reliability of the resistor.

[0038] Specifically, the first window A is located on the left side of the chip, the first window B, the first window C and the first window D are located on the right side of the chip, and the interval between the first window A and the first window B is 1000μm to 5000μm. The window widths of the first window A and the first window B are 10μm to 50μm; the window widths of the first window C and the first window D are 10μm to 30μm.

[0039] As Figure 2-3 shown, at least two of the first window D and the third window C are provided. When the current flow directions are different, the first window D and the third window C respectively form a path with the second electrode; by setting at least two of the first window D and the third window C, when there is a problem with one of the paths, the other path can still operate, improving the reliability of the product.

[0040] Optionally, the thin film layer 4 includes one or more of the following low-temperature drift materials: nickel-chromium alloy, titanium-nickel-chromium alloy, nickel-chromium-aluminum alloy, nickel-phosphorus alloy, titanium nitride, tantalum nitride.

[0041] Optionally, the material of the positive metal layer 7 is Al-Si.

[0042] In one embodiment, a preparation method of a thin film resistor with bidirectional current response difference is provided, including: S1. As Figure 6 shown, an oxide layer 2 is formed on the N-type silicon substrate 1. Specifically, the oxide layer 2 can be prepared on the N-type silicon substrate 1 by the dry oxidation method. The thickness of the oxide layer 2 is 1 to 2μm. By using the dry oxidation method to prepare the oxide layer 2, the oxide layer 2 has high density and few defects.

[0043] S2. First photolithography, a first window is opened on the oxide layer 2 to expose the N-type silicon substrate 1.

[0044] S3. Inject P-type ions into the first window to form a P-type doped region 3; the P-type ions can be boron, and the injection dose is 1×10 16 ~5×10 18 cm -2, the implanted energy is 100 keV to 200 keV; after ion implantation, the wafer is annealed to repair lattice damage and activate impurities, forming a P-type doped region 3, as Figure 7 shown.

[0045] S4. As Figure 8 shown, a thin film layer 4 is formed on the oxide layer 2 by reactive magnetron sputtering. The thin film layer 4 is an alloy-based thin film. Using the corresponding target, sputtering is carried out in a pure argon environment. The thin film layer 4 forms a first resistor 41 and a second resistor 42 that are spaced apart from each other and have different resistance values.

[0046] S5. A passivation layer 5 is formed on the thin film layer 4 and the oxide layer 2; the passivation layer 5 is grown by PE-CVD. The passivation layer 5 is SiO2 or Si3N4, and the temperature is 350 - 450 °C. The passivation layer 5 covers the thin film layer 4 to prevent the resistor body from contacting water vapor.

[0047] S6. A second window is opened on the passivation layer 5.

[0048] S7. N-type ions are implanted in the second window to form an N-type doped region 6; the N-type ions are phosphorus or arsenic, and the implantation dose is 1×10 15 ~5×10 17 cm -2 , the implantation energy is 50 keV to 100 keV. After ion implantation, the wafer is annealed to repair lattice damage and activate impurities, forming an N-type doped region 6, as Figure 9 shown.

[0049] S8. As Figure 10 shown, a third window is opened on the passivation layer 5 to facilitate subsequent contact between the front metal layer 7 and the silicon substrate. The third window includes a third window A, a third window B, and a third window C. The third window A and the third window B respectively correspond to the first window A and the first window D, and the third window C is opened outside the first window D. In this step, the passivation layer between the first resistor 41 and the second resistor 42 is also removed.

[0050] S9. Sputter the front metal layer 7. The front metal layer 7 contacts the N-type silicon substrate 1 and the thin film layer 4, and the edge of the front metal layer 7 covers the passivation layer 5. A fourth window is opened on the front metal layer 7 to remove a part of the front metal layer 7 so that the effective resistance region is exposed, and the spaced-apart first electrode, second electrode, first test PAD, and second test PAD are retained, as Figure 11 shown.

[0051] S10. Thinning the back side, annealing the wafer, and forming an oxide insulating layer 8 on the back side of the N-type silicon substrate 1, as Figure 1 shown. Its top view is as Figure 12 shown.

[0052] The technical solutions in the embodiments of the present application at least have the following technical effects: (1) When a forward current passes through the device, the first resistor 41 becomes effective. When a reverse current passes through the device, the second resistor 42 becomes effective. With different current directions, the device presents different resistance values.

[0053] (2) The passivation layer 5 covers the thin film layer 4, avoiding direct contact between the resistor body and water vapor, and increasing the reliability of the thin film resistor.

[0054] (3) The front metal layer 7 is provided with two test PADs. The first electrode 71 forms a loop with the first / second test PADs. At this time, under forward and reverse currents, the resistance value changes linearly, which is convenient for checking the resistance value of a single resistor; both the first electrode 71 and the second electrode 72 are arranged on the surface of the device, and the process flow is simple and the manufacturing cost is low.

[0055] (4) After the wafer is thinned, an annealing treatment is performed to grow an oxide insulating layer 8 on the back surface, effectively avoiding device failure caused by a back path.

[0056] The above embodiments are only used to introduce the technical solutions of the present application in detail. However, the description of the above embodiments is only for helping to understand the method of the embodiments of the present invention, and should not be construed as a limitation on the embodiments of the present invention. Any changes or substitutions that can be easily thought of by those skilled in the art should be covered within the protection scope of the embodiments of the present invention.

Claims

1. A two-way current response difference thin film resistor, characterized in that, Comprising: N-type silicon substrate; Oxide layer, disposed on the N-type silicon substrate; First window, opened on the oxide layer, the first window includes first window A, first window B, first window C and first window D, first window A is located on one side of the N-type silicon substrate, first window B, first window C and first window D are located on the other side of the N-type silicon substrate; P-type doped region, disposed on the N-type silicon substrate, formed by injecting P-type ions through the first window; Thin film layer, disposed on the oxide layer and between first window A and first window B; the thin film layer includes a first resistor and a second resistor which are spaced apart and have different resistances; Passivation layer, disposed on the oxide layer and the thin film layer; Second window, opened on the passivation layer, corresponding to first window B; N-type doped region, disposed on the N-type silicon substrate, formed by injecting N-type ions through the second window; Third window, opened on the passivation layer, the third window includes third window A, third window B and third window C, third window A and third window B respectively correspond to first window A, first window D, third window C is opened outside first window D; Front metal layer, disposed between the first resistor and the second resistor to form a first electrode, disposed on first window D and third window C to form a second electrode, disposed on first window A to form a first test PAD, disposed on the second window to form a second test PAD; Oxide insulating layer, disposed at the bottom of the N-type silicon substrate.

2. The dual-current response difference thin film resistor according to claim 1, wherein Both the first window D and the third window C are provided with at least two.

3. The bidirectional current response difference thin film resistor according to claim 2, characterized in that, The thickness of the oxide layer is 1 - 2 μm.

4. The dual-current response difference thin film resistor according to claim 1, characterized in that, The implantation dose of the P-type doping region is 1×10 16 ~5×10 18 cm -2 , the injection energy is 100keV ~ 200keV.

5. The dual-current response difference thin-film resistor according to claim 4, wherein The implantation dose of the N-type doped region is 1×10 15 ~ 5×10 17 cm -2 , and the implantation energy is 50 keV to 100 keV.

6. The bidirectional current response difference thin film resistor according to claim 1, characterized in that The thin film layer includes one or more of the following low-temperature drift materials: nickel-chromium alloy NiCr, titanium-nickel-chromium alloy TiNiCr, nickel-chromium-aluminum alloy NiCrAl, nickel-phosphorus alloy NiP, titanium nitride TiN, tantalum nitride TaN.

7. The bidirectional current response difference thin film resistor according to claim 1, wherein, The material of the passivation layer is SiO2 or Si3N4, and the thickness is 1 - 2 μm.

8. The bidirectional current response difference thin film resistor according to claim 1, characterized in that, The material of the front metal layer is Al-Si.

9. The dual-current response difference thin film resistor according to claim 1, wherein The thickness of the oxide insulating layer is 2 - 3 μm.

10. A preparation method of a thin film resistor with different bidirectional current responses, characterized in that, For preparing the dual-current response difference thin film resistor according to any one of claims 1 - 9, comprising: S1. Form an oxide layer on the N-type silicon substrate; S2. Open a first window on the oxide layer to expose the N-type silicon substrate; S3. Inject P-type ions through the first window to form a P-type doped region; S4. Form a thin film layer on the oxide layer, and the thin film layer forms a first resistor and a second resistor which are spaced apart and have different resistances; S5. Form a passivation layer on the oxide layer and the thin film layer; S6. Open a second window on the passivation layer; S7. Inject N-type ions through the second window to form an N-type doped region; S8. Open a third window on the passivation layer; S9. Sputter the front metal layer, the front metal layer contacts the N-type silicon substrate and the thin film layer, and the edge of the front metal layer covers the passivation layer; remove part of the region of the front metal layer to retain the spaced first electrode, second electrode, first test PAD and second test PAD; S10. Back thinning, annealing the wafer, and forming an oxide insulating layer on the back of the N-type silicon substrate.

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