Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a first substrate; a buffer layer, a channel layer and a barrier layer are sequentially formed on the first substrate, and the surfaces, facing one side of the first substrate, of the buffer layer, the channel layer and the barrier layer are nitrogen polar surfaces; forming a second substrate on the barrier layer, wherein the material of the second substrate is monocrystalline or polycrystalline diamond; separating the first substrate from the buffer layer; carrying out thinning treatment on the buffer layer; forming a source electrode and a drain electrode on the two sides of the channel layer respectively; and forming a grid electrode on one surface, far away from the channel layer, of the buffer layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] GaN RF devices have attracted widespread attention for their high integration, small size, weight and power consumption. They can replace traditional silicon-based and GaAs-based devices on a large scale and be used in radar, electronic countermeasures and communication systems. The improvement of the power density of GaN microwave power devices includes two prerequisites, namely 1) higher crystal quality and better heat dissipation characteristics; 2) lower trap effect to avoid current collapse at high frequency. Traditional HEMT (High Electron Mobility Transistor) devices use GaN buffer layers, which require C or Fe doping of GaN, thus introducing more deep energy level defects. Secondly, in order to ensure the high breakdown voltage and frequency characteristics of GaN HEMT, high-quality epitaxial film is an important guarantee. Due to the high lattice mismatch, HEMT in the field is currently mainly epitaxially grown on sapphire or silicon substrates. However, the thermal conductivity of sapphire and silicon is poor, which affects the heat dissipation characteristics of HEMT devices under high-power working conditions.

[0003] Therefore, the method of combining diamond substrate with GaN HEMT is used to achieve a synergistic improvement in the power density and efficiency of RF devices. However, the direct epitaxial HEMT structure on diamond will introduce a large number of threading dislocations and deteriorate device performance due to the lattice mismatch between nitride and diamond. At the same time, nitrogen polar epitaxy will introduce a large number of unintentionally doped oxygen impurities, making it impossible to prepare a high-resistance buffer layer. In addition, compared with metal polarity, the nitrogen polarity surface morphology is rough, which easily causes the device mobility to deteriorate. Summary of the invention

[0004] The present disclosure provides a method for preparing a semiconductor structure and a semiconductor structure, so as to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a method for preparing a semiconductor structure is provided, wherein the method comprises:

[0006] providing a first substrate;

[0007] forming a buffer layer, a channel layer and a barrier layer in sequence on the first substrate, wherein the surfaces of the buffer layer, the channel layer and the barrier layer facing the first substrate are nitrogen polar surfaces;

[0008] forming a second substrate on the barrier layer, wherein the material of the second substrate is single crystal or polycrystalline diamond;

[0009] separating the first substrate from the buffer layer;

[0010] Thinning the buffer layer;

[0011] forming a source electrode and a drain electrode on both sides of the channel layer respectively;

[0012] A gate is formed on a side of the buffer layer away from the channel layer.

[0013] In one embodiment, the buffer layer after thinning has a thickness ranging from 0 to 200 nm.

[0014] In one possible implementation, it also includes:

[0015] Before forming the second substrate, forming an intermediate layer on the barrier layer, wherein the material of the intermediate layer includes AlN;

[0016] The second substrate is located on the intermediate layer.

[0017] In one embodiment, forming a gate on a side of the buffer layer away from the channel layer includes:

[0018] The gate is directly formed on the surface of the buffer layer; or,

[0019] Etching the buffer layer to form a groove, wherein the groove extends to the inside of the buffer layer;

[0020] The gate is formed in the trench.

[0021] In one embodiment, the thickness of the channel layer is in the range of 20-80 nm;

[0022] The thickness of the barrier layer is in the range of 20-500 nm.

[0023] According to a second aspect of the present disclosure, a semiconductor structure is provided, wherein the semiconductor structure comprises:

[0024] A second substrate, wherein the material of the second substrate is single crystal or polycrystalline diamond;

[0025] A barrier layer, a channel layer and a buffer layer are sequentially disposed on the second substrate, wherein surfaces of the buffer layer, the channel layer and the barrier layer away from the second substrate are nitrogen polar surfaces;

[0026] A source electrode and a drain electrode respectively located at two sides of the channel layer;

[0027] A gate is located on a side of the buffer layer away from the channel layer.

[0028] In one embodiment, the buffer layer has a thickness ranging from 0 to 200 nm.

[0029] In one embodiment, the semiconductor structure further includes:

[0030] The intermediate layer is located between the second substrate and the barrier layer, and the material of the intermediate layer includes AlN.

[0031] In one embodiment, the gate located on a side of the buffer layer away from the channel layer includes:

[0032] The gate is directly located on the surface of the buffer layer; or,

[0033] A trench is formed in the buffer layer, and the gate is located in the trench.

[0034] In one embodiment, the thickness of the channel layer is in the range of 20-80 nm;

[0035] The thickness of the barrier layer is in the range of 20-500 nm.

[0036] The preparation method of the semiconductor structure and the semiconductor structure disclosed in the present invention first form a buffer layer, a channel layer and a barrier layer on a first substrate, the surfaces of the buffer layer, the channel layer and the barrier layer facing the first substrate are nitrogen polar surfaces, and the surfaces away from the first substrate are metal polar surfaces. The device structure is epitaxially grown based on the metal polar surface, and a high-quality epitaxial structure can be obtained, avoiding the problems of high oxygen impurities and poor surface morphology caused by direct epitaxial growth; then the first substrate and the buffer layer are peeled off and thinned, so as to obtain a uniform and flat nitrogen polar surface; in addition, a diamond substrate is deposited on the barrier layer, and diamond has good thermal conductivity, which can improve the thermal conductivity of the device.

[0037] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:

[0039] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0040] Figure 1 A flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0041] Figure 2a to Figure 2e A schematic diagram of a semiconductor structure during preparation provided by an embodiment of the present disclosure;

[0042] Figure 3 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0043] Figure 4 Structural schematic diagram 2 of the semiconductor structure provided for the embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0045] The present disclosure provides a method for preparing a semiconductor structure. Figure 1 ,like Figure 1 As shown, the method for preparing the semiconductor structure comprises the following steps:

[0046] Step 101: providing a first substrate;

[0047] Step 102: forming a buffer layer, a channel layer and a barrier layer in sequence on a first substrate, wherein surfaces of the buffer layer, the channel layer and the barrier layer facing the first substrate are nitrogen polar surfaces;

[0048] Step 103: forming a second substrate on the barrier layer, wherein the material of the second substrate is single crystal or polycrystalline diamond;

[0049] Step 104: separating the first substrate from the buffer layer;

[0050] Step 105: thinning the buffer layer;

[0051] Step 106: forming a source electrode and a drain electrode on both sides of the channel layer respectively;

[0052] Step 107: forming a gate on a side of the buffer layer away from the channel layer.

[0053] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure is further described in detail below in conjunction with specific embodiments. Figure 2a to Figure 2e A schematic diagram of a semiconductor structure during the preparation process provided in an embodiment of the present disclosure.

[0054] First, see Figure 2a , perform step 101 and provide a first substrate 10.

[0055] In one embodiment, the first substrate 10 includes at least one of sapphire or silicon.

[0056] Continue to see Figure 2a , perform step 102 to sequentially form a buffer layer 20, a channel layer 30 and a barrier layer 40 on the first substrate 10, wherein the surfaces of the buffer layer 20, the channel layer 30 and the barrier layer 40 facing the first substrate 10 are nitrogen polar surfaces.

[0057] In one embodiment, the material of the buffer layer 20 includes but is not limited to at least one of GaN or AlN doped with C or Fe; the thickness of the buffer layer 20 is in the range of 50 nm-4 μm.

[0058] The material of the channel layer 30 includes but is not limited to GaN or Al x Ga 1-x At least one of N, wherein 0≤x≤1; and the thickness of the channel layer 30 is in the range of 20-80 nm.

[0059] The material of the barrier layer 40 includes but is not limited to Al y Ga 1-y N or AlInN, wherein 0≤y≤1, and y>x; the thickness of the barrier layer 40 is in the range of 20-500 nm.

[0060] In the disclosed embodiment, the total thickness of the channel layer 30 and the barrier layer 40 is less than 1 μm, which achieves efficient conduction of heat energy and avoids the trap effect of the RF HEMT device under high-frequency operation.

[0061] The dotted lines within the channel layer 30 represent a two-dimensional electron gas (2DEG).

[0062] It can be understood that because the materials of the buffer layer 20, the channel layer 30 and the barrier layer 40 all include nitride, the buffer layer 20, the channel layer 30 and the barrier layer 40 all include a nitrogen polarity surface and a metal polarity surface, wherein the surface facing the first substrate 10 is a nitrogen polarity surface, and the surface away from the first substrate 10 is a metal polarity surface.

[0063] In the disclosed embodiments, the device structure is based on metal polar surface epitaxial growth, which can obtain a high-quality epitaxial structure and avoid the problems of excessive oxygen impurities and poor surface morphology caused by direct epitaxial growth.

[0064] In one embodiment, the method further includes: before forming the barrier layer 40, forming a transition layer (not shown in the figure) on the channel layer 30, the barrier layer 40 is located on the transition layer, wherein the material of the transition layer includes AlN. The transition layer can improve the mobility of 2DEG.

[0065] Next, see Figure 2b , executing step 103: forming a second substrate 50 on the barrier layer 40, wherein the material of the second substrate 50 is single crystal or polycrystalline diamond.

[0066] In the embodiment of the present disclosure, a diamond substrate is deposited on the barrier layer 40 . Diamond has good thermal conductivity and can improve the thermal conductivity of the device.

[0067] In actual operation, the second substrate 50 may be formed by using medium pressure plasma chemical vapor deposition (MPCVD), atmospheric pressure chemical vapor deposition (APCVD), or the like.

[0068] In one embodiment, the second substrate 50 has a thickness ranging from 10 μm to 100 μm.

[0069] In one embodiment, the method further includes: before forming the second substrate 50 , forming an intermediate layer (not shown in the figure) on the barrier layer 40 , wherein the material of the intermediate layer includes AlN; and the second substrate 50 is located on the intermediate layer.

[0070] In actual operation, the intermediate layer can be prepared by methods such as magnetron sputtering and metal organic vapor phase epitaxial deposition (MOCVD).

[0071] The function of the intermediate layer is to provide nucleation for diamond growth, improve the thermal conductivity of the chip and the diamond heat sink, and serve as a protective layer for the barrier layer 40 to prevent the decomposition of the nitride epitaxial layer by the hydrogen atmosphere during the diamond growth process.

[0072] In the disclosed embodiment, the first substrate is not removed first and then the second substrate is deposited on the removed surface of the first substrate, thus avoiding the problem of low yield caused by multiple transfers of the carrier wafer.

[0073] Next, see Figure 2c , perform step 104 to separate the first substrate 10 from the buffer layer 20 .

[0074] In actual operation, if the first substrate 10 is a sapphire substrate, the first substrate is separated from the buffer layer by laser lift-off, wherein the laser lift-off uses an excimer laser including 248nm or 193nm. When laser lift-off is used, Ga or Al metal particles will be generated at the interface after lift-off, and mechanical chemical polishing (CMP) will be performed later to make the surface flat.

[0075] If the first substrate 10 is a silicon substrate, it can be removed by etching with a KOH solution or mechanical chemical polishing.

[0076] Next, see Figure 2d, execute step 105 to thin the buffer layer 20.

[0077] In actual operation, the interface of the buffer layer 20 after stripping can be processed by mechanical chemical polishing to thin the buffer layer 20. The thinned surface is a nitrogen polar surface with a roughness of less than 1 nm.

[0078] In one embodiment, the thickness of the buffer layer 20 after thinning is in the range of 0-200 nm.

[0079] Figure 2d In the example, after thinning, the entire device was flipped over.

[0080] In the disclosed embodiment, a nitrogen-polar RF HEMT device is prepared by substrate stripping and thinning, so that the total thickness of the epitaxial layer of the device is low, and the trap effect can be effectively improved under high-frequency operation; at the same time, a uniform and flat nitrogen-polar surface can be obtained.

[0081] Next, see Figure 2e , perform step 106 to form a source 61 and a drain 62 on both sides of the channel layer 30 ; and perform step 107 to form a gate 70 on a side of the buffer layer 20 away from the channel layer 30 .

[0082] In actual operation, a first trench (not shown in the figure) can be etched on both sides of the buffer layer 20 and the channel layer 30. The first trench penetrates the buffer layer 20 and extends to the inside of the channel layer 30, and then a source 61 and a drain 62 are formed in the first trench.

[0083] As mentioned above, the thickness of the buffer layer 20 after thinning is in the range of 0-200 nm. Specifically, in some embodiments, when the thickness of the buffer layer 20 after thinning is 0, it means that the buffer layer 20 is completely removed, and the semiconductor structure finally formed is as follows: Figure 3 As shown, the gate 70 is formed on the channel layer 30 .

[0084] In other embodiments, when the thickness of the thinned buffer layer 20 is greater than 0, a gate 70 is formed on a side of the buffer layer 20 away from the channel layer 30, including: directly forming the gate 70 on the surface of the buffer layer 20; or, etching the buffer layer 20 to form a groove, the groove extending to the interior of the buffer layer 20; and forming the gate 70 in the groove.

[0085] Specifically, see Figure 2e , the gate 70 may be formed directly on the surface of the buffer layer 20; or see Figure 4 The gate 70 extends to the inside of the buffer layer 20, and the distance between the gate 70 and the 2DEG is less than 20 nm.

[0086] In one embodiment, a gate dielectric layer (not shown) is formed below the gate 70. The material of the gate dielectric layer includes Al2O3, HfO2, SiN x , SiO2, etc.

[0087] The present disclosure also provides a semiconductor structure, such as Figure 2e As shown, the semiconductor structure includes:

[0088] The second substrate 50 is made of single crystal or polycrystalline diamond.

[0089] In the embodiment of the present disclosure, a diamond substrate is deposited on the barrier layer 40 . Diamond has good thermal conductivity and can improve the thermal conductivity of the device.

[0090] In one embodiment, the second substrate 50 has a thickness ranging from 10 μm to 100 μm.

[0091] like Figure 2e As shown, the semiconductor structure further includes: a barrier layer 40, a channel layer 30 and a buffer layer 20 sequentially located on the second substrate 50, wherein the surfaces of the buffer layer 20, the channel layer 30 and the barrier layer 40 away from the second substrate 50 are nitrogen polar surfaces.

[0092] In one embodiment, the material of the buffer layer 20 includes but is not limited to at least one of GaN or AlN doped with C or Fe; the thickness of the buffer layer ranges from 0 to 200 nm.

[0093] The material of the channel layer 30 includes but is not limited to GaN or Al x Ga 1-x At least one of N, wherein 0≤x≤1; and the thickness of the channel layer 30 is in the range of 20-80 nm.

[0094] The material of the barrier layer 40 includes but is not limited to Al y Ga 1-y N or AlInN, wherein 0≤y≤1, and y>x; the thickness of the barrier layer 40 is in the range of 20-500 nm.

[0095] In the disclosed embodiment, the total thickness of the channel layer 30 and the barrier layer 40 is less than 1 μm, which achieves efficient conduction of heat energy and avoids the trap effect of the RF HEMT device under high-frequency operation.

[0096] The dotted lines within the channel layer 30 represent a two-dimensional electron gas (2DEG).

[0097] It can be understood that because the materials of the buffer layer 20, the channel layer 30 and the barrier layer 40 all include nitride, the buffer layer 20, the channel layer 30 and the barrier layer 40 all include a nitrogen polarity surface and a metal polarity surface, wherein the surface away from the second substrate 50 is a nitrogen polarity surface, and the surface facing the second substrate 50 is a metal polarity surface.

[0098] In the disclosed embodiments, the device structure is based on metal polar surface epitaxial growth, which can obtain a high-quality epitaxial structure and avoid the problems of excessive oxygen impurities and poor surface morphology caused by direct epitaxial growth.

[0099] In one embodiment, the semiconductor structure further includes: a transition layer (not shown in the figure) located between the channel layer 30 and the barrier layer 40, wherein the material of the transition layer includes AlN. The transition layer can improve the mobility of 2DEG.

[0100] In one embodiment, the semiconductor structure further includes: an intermediate layer (not shown in the figure) located between the second substrate 50 and the barrier layer 40 , and the material of the intermediate layer includes AlN.

[0101] The function of the intermediate layer is to provide nucleation for diamond growth, improve the thermal conductivity of the chip and the diamond heat sink, and serve as a protective layer for the barrier layer 40 to prevent the decomposition of the nitride epitaxial layer by the hydrogen atmosphere during the diamond growth process.

[0102] like Figure 2e As shown, the semiconductor structure further includes: a source 61 and a drain 62 respectively located on both sides of the channel layer 30 ; and a gate 70 located on a side of the buffer layer 20 away from the channel layer 30 .

[0103] In some embodiments, the semiconductor structure may not have a buffer layer 20, and the final semiconductor structure may be Figure 3 As shown, the gate 70 is located on the channel layer 30 .

[0104] In other embodiments, the gate 70 located on the side of the buffer layer 20 away from the channel layer 30 includes: the gate 70 is directly located on the surface of the buffer layer 20; or, a groove is formed in the buffer layer 20 (not shown in the figure), and the gate 70 is located in the groove.

[0105] Specifically, see Figure 2e , the gate 70 may be formed directly on the surface of the buffer layer 20; or see Figure 4 The gate 70 extends to the inside of the buffer layer 20, and the distance between the gate 70 and the 2DEG is less than 20 nm.

[0106] In one embodiment, a gate dielectric layer (not shown) is formed below the gate 70. The material of the gate dielectric layer includes Al2O3, HfO2, SiN x, SiO2, etc.

[0107] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0108] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0109] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: providing a first substrate; forming a buffer layer, a channel layer and a barrier layer in sequence on the first substrate, wherein the surfaces of the buffer layer, the channel layer and the barrier layer facing the first substrate are nitrogen polar surfaces; forming a second substrate on the barrier layer, wherein the material of the second substrate is single crystal or polycrystalline diamond; separating the first substrate from the buffer layer; Thinning the buffer layer; forming a source electrode and a drain electrode on both sides of the channel layer respectively; A gate is formed on a side of the buffer layer away from the channel layer.

2. The method according to claim 1, characterized in that The thickness of the buffer layer after thinning is in the range of 0-200 nm.

3. The method according to claim 1, characterized in that Also includes: Before forming the second substrate, forming an intermediate layer on the barrier layer, wherein the material of the intermediate layer includes AlN; The second substrate is located on the intermediate layer.

4. The method according to claim 1, characterized in that: The forming of a gate on a side of the buffer layer away from the channel layer comprises: The gate is directly formed on the surface of the buffer layer; or, Etching the buffer layer to form a groove, wherein the groove extends to the inside of the buffer layer; The gate is formed in the trench.

5. The method according to claim 1, characterized in that The thickness of the channel layer is in the range of 20-80 nm; The thickness of the barrier layer is in the range of 20-500 nm.

6. A semiconductor structure, characterized in that: The semiconductor structure comprises: A second substrate, wherein the material of the second substrate is single crystal or polycrystalline diamond; A barrier layer, a channel layer and a buffer layer are sequentially disposed on the second substrate, wherein surfaces of the buffer layer, the channel layer and the barrier layer away from the second substrate are nitrogen polar surfaces; A source electrode and a drain electrode respectively located at two sides of the channel layer; A gate is located on a side of the buffer layer away from the channel layer.

7. The semiconductor structure according to claim 6, characterized in that: The thickness of the buffer layer is in the range of 0-200 nm.

8. The semiconductor structure according to claim 6, characterized in that: The semiconductor structure further comprises: The intermediate layer is located between the second substrate and the barrier layer, and the material of the intermediate layer includes AlN.

9. The semiconductor structure according to claim 6, characterized in that: The gate located on a side of the buffer layer away from the channel layer includes: The gate is directly located on the surface of the buffer layer; or, A trench is formed in the buffer layer, and the gate is located in the trench.

10. The semiconductor structure according to claim 6, characterized in that: The thickness of the channel layer is in the range of 20-80 nm; The thickness of the barrier layer is in the range of 20-500 nm.

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