Semiconductor device, preparation method, power module, conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle, and relates to the technical field of semiconductors, and the semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; wherein the first surface comprises a first surface of a cellular area and a first surface of a terminal area, and the first surface of the terminal area is provided with a plurality of limiting grooves which are arranged at intervals; the semiconductor body further comprises a plurality of field limiting rings, and each field limiting ring is located on the side, close to the second surface, of the corresponding limiting groove. And in the direction from the first surface to the second surface, the distance between the two adjacent field limiting rings is gradually increased. According to the technical scheme provided by the invention, the terminal voltage withstanding characteristic of the semiconductor device is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. Background Art

[0002] As a representative of the third generation of semiconductor materials, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap, high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0003] In order to improve the reverse withstand voltage of semiconductor devices and reduce the electric field concentration effect, in high-voltage devices, junction termination technology is needed to modulate the electric field distribution in the internal withstand voltage region of the device. Figure 1 is a schematic cross-sectional structure diagram of a terminal structure of a power device provided in the related art, referring to Figure 1 The field limiting ring 100 is a commonly used edge terminal structure of a power device. The structure can be manufactured simultaneously with the main junction region of the device, so the manufacturing steps are simple and the cost is low. However, the field limiting ring 100 needs to be precisely designed in terms of ring spacing, ring width, and ring depth. A slight deviation may cause a significant drop in breakdown voltage. However, the ions in the field limiting ring 100 will diffuse during the high-temperature annealing process, causing adjacent field limiting rings 100 to be connected together, reducing the withstand voltage characteristics of the terminal structure. Summary of the invention

[0004] Embodiments of the present invention provide a semiconductor device, a manufacturing method, a power module, a conversion circuit and a vehicle to improve the terminal withstand voltage characteristics of the semiconductor device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0006] A semiconductor body comprises a first surface and a second surface arranged opposite to each other; wherein the first surface comprises a first surface of a cell region and a first surface of a terminal region, and the first surface of the terminal region is provided with a plurality of spaced-apart limiting grooves; the semiconductor body further comprises a plurality of field limiting rings, each of the field limiting rings being located on a side of a limiting groove close to the second surface; in a direction from the first surface to the second surface, the spacing between two adjacent field limiting rings gradually increases.

[0007] Optionally, the semiconductor body includes a cell portion and a terminal portion; the field limiting ring is located at the terminal portion; in a direction from the cell portion to the terminal portion, a plurality of the field limiting rings are arranged in sequence and spaced apart;

[0008] The maximum width of each field limiting ring is smaller than the width of the corresponding limiting groove.

[0009] Optionally, the plurality of field limiting rings include at least one first field limiting ring;

[0010] The first field limiting ring includes a first side wall, a second side wall, and a third side wall and a fourth side wall connecting the first side wall and the second side wall; wherein the third side wall is located at the bottom surface of the limiting groove, and the fourth side wall is arranged opposite to the third side wall; the area of ​​the fourth side wall is smaller than the area of ​​the third side wall.

[0011] Optionally, the multiple field limiting rings further include at least one second field limiting ring;

[0012] The second field limiting ring includes a fifth side wall, a sixth side wall and a seventh side wall connecting the fifth side wall and the sixth side wall; wherein the seventh side wall is located at the bottom surface of the limiting groove, and in the direction from the first surface to the second surface, the distance between the fifth side wall and the sixth side wall gradually decreases until it is zero;

[0013] The distance from the first field limiting ring to the cell portion is greater than the distance from the second field limiting ring to the cell portion.

[0014] Optionally, among the plurality of field limiting rings, the field limiting ring closest to the cell portion has the largest width, and the field limiting ring closest to the cell portion has the shortest distance to the second surface;

[0015] Among the plurality of limiting grooves, the limiting groove closest to the cell portion has the largest width, and different limiting grooves have the same depth.

[0016] Optionally, the semiconductor material of the field limiting ring and the material of the semiconductor body have different conductivity types;

[0017] And / or, the semiconductor material of the field limiting ring and the material of the semiconductor body include SiC.

[0018] Optionally, the limiting groove is provided with a filling material, and the filling material includes at least one of silicon oxide, silicon nitride and polyimide.

[0019] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0020] A semiconductor body is provided, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other; wherein the first surface comprises a first surface of a cell region and a first surface of a terminal region;

[0021] Forming a plurality of spaced limiting grooves on the first surface of the terminal area;

[0022] Forming a mask layer, wherein the mask layer is located on the bottom surface, the sidewalls and the first surface of the terminal region of the limiting groove; wherein the mask layer has a cavity at the location of the limiting groove, and the width of the cavity gradually increases in the direction from the first surface to the second surface;

[0023] Based on the mask layer, a field limiting ring is correspondingly formed at the bottom of each limiting groove; in the direction from the first surface to the second surface, the distance between two adjacent field limiting rings gradually increases.

[0024] Optionally, the forming of the mask layer includes:

[0025] Forming a first mask layer on the sidewalls of the limiting groove, the bottom surface of the limiting groove and the first surface of the terminal region by a low pressure chemical vapor deposition method;

[0026] A second mask layer is formed on the surface of the first mask layer by plasma enhanced chemical vapor deposition; wherein the first mask layer and the second mask layer are used to enclose a cavity at the position where the limiting groove is located.

[0027] Optionally, at least the cross-sectional shape of the cavity closest to the first surface of the cell region is a trapezoid, and the length of the side of the trapezoid close to the second surface is greater than the length of the side away from the second surface;

[0028] Based on the mask layer, a field limiting ring is correspondingly formed at the bottom of each limiting groove, including:

[0029] Based on the trapezoidal cavity of the mask layer, a first field limiting ring is formed at the bottom of the limiting groove; wherein, the multiple field limiting rings include at least one first field limiting ring, and the first field limiting ring includes a first side wall, a second side wall, and a third side wall and a fourth side wall connecting the first side wall and the second side wall; the third side wall is located at the bottom surface of the limiting groove, and the fourth side wall is arranged opposite to the third side wall; the area of ​​the four side walls is smaller than the area of ​​the third side wall.

[0030] Optionally, the cross-sectional shape of at least one cavity outside the cavity closest to the first surface of the cell region is a triangle;

[0031] Based on the mask layer, a field limiting ring is formed at the bottom of each limiting groove, and further comprising:

[0032] Based on the triangular cavity of the mask layer, a second field limiting ring is formed at the bottom of the limiting groove; the multiple field limiting rings also include at least one second field limiting ring, and the second field limiting ring includes a fifth side wall, a sixth side wall and a seventh side wall connecting the fifth side wall and the sixth side wall; the seventh side wall is located on the bottom surface of the limiting groove; in the direction from the first surface to the second surface, the distance between the fifth side wall and the sixth side wall gradually decreases until it is zero.

[0033] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device according to any one of the embodiments of the present invention, wherein the substrate is used for carrying the semiconductor device.

[0034] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0035] The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0036] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0037] The embodiment of the present invention provides a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle, wherein the semiconductor device comprises: a semiconductor body, comprising a first surface and a second surface arranged oppositely; wherein the first surface comprises a first surface of a cell region and a first surface of a terminal region, and the first surface of the terminal region comprises a plurality of spaced limiting grooves; the semiconductor body further comprises a plurality of field limiting rings, each of which is located on a side of a limiting groove close to the second surface; in the direction from the first surface to the second surface, the spacing between two adjacent field limiting rings gradually increases. The technical solution provided by the embodiment of the present invention forms a field limiting ring by ion implantation at the bottom of the limiting groove, which can increase the ion implantation depth, reduce the energy required for ion implantation, and avoid implantation damage to the semiconductor body caused by high-energy implantation. Based on the shape setting of the mask layer in the limiting groove, the width of the field limiting ring formed by ion implantation gradually decreases in the direction from the first surface to the second surface, that is, the spacing between two adjacent field limiting rings gradually increases, thereby avoiding the adjacent field limiting rings being connected together due to ion diffusion in the field limiting ring, improving the voltage dividing effect and pressure resistance of the terminal structure in the semiconductor device, and thus improving the pressure resistance of the semiconductor device.

[0038] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 It is a schematic cross-sectional structure diagram of a terminal structure of a power device provided in the related art;

[0041] Figure 2 is a top view of a semiconductor device provided by an embodiment of the present invention;

[0042] Figure 3 yes Figure 2 The structure shown is a schematic cross-sectional view along AA1;

[0043] Figure 4 is a schematic cross-sectional structure diagram of another semiconductor device provided by an embodiment of the present invention;

[0044] Figure 5 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0045] Figure 6 is a schematic cross-sectional structure diagram corresponding to step S10 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0046] Figure 7 is a schematic cross-sectional structure diagram corresponding to step S20 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0047] Figure 8~Figure 9 is a schematic cross-sectional structure diagram corresponding to step S30 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0048] Fig.10 It is a schematic cross-sectional structure diagram corresponding to step S40 in a method for preparing a semiconductor device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] An embodiment of the present invention provides a semiconductor device, Figure 2 is a top view of a semiconductor device provided by an embodiment of the present invention, Figure 3 yes Figure 2 The structure shown is a cross-sectional view along AA1, see Figure 2 and Figure 3 , semiconductor devices include:

[0052] The semiconductor body 1 comprises a first surface 11 and a second surface 12 arranged opposite to each other; wherein the first surface 11 comprises a first surface of a cell region and a first surface of a terminal region, and the first surface of the terminal region comprises a plurality of spaced limiting grooves 30; the semiconductor body 1 further comprises a plurality of field limiting rings 2, each of which is located on a side of a corresponding limiting groove 30 close to the second surface 12;

[0053] In the direction Y from the first surface 11 to the second surface 12 , the distance between two adjacent field limiting rings 2 gradually increases.

[0054] Specifically, the semiconductor body 1 can be formed by one epitaxy or multiple epitaxys. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer 20 or a stacked structure formed by multiple semiconductor epitaxial layers 20. The semiconductor body 1 can also include a substrate 10, that is, the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer 20 formed on one side of the substrate 10. Figure 3The semiconductor body 1 shown includes a substrate 10 and a semiconductor epitaxial layer 20 formed on one side of the substrate 10 .

[0055] The material of the substrate 10 may be the same as the material of the semiconductor epitaxial layer 20, or the material of the substrate 10 may be different from the material of the semiconductor epitaxial layer 20. In an embodiment of the present invention, the material of the semiconductor epitaxial layer 20 and the material of the substrate 10 may be SiC, and the semiconductor device may be a planar SiC power device with a terminal structure, a trench SiC power device, or other SiC devices. SiC has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap and have the advantages of high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0056] The semiconductor body 1 includes a cell portion 01 located in the central area and a terminal portion 02 located in the edge area, and the terminal portion 02 is arranged around the cell portion 01. The cell portion 01 of the semiconductor body 1 is used to prepare a SiC power device, and the terminal portion 02 of the semiconductor body 1 is used to prepare a terminal structure of the SiC power device. The semiconductor body 1 also includes a first surface 11 and a second surface 12 that are arranged opposite to each other. In the case where the semiconductor body 1 only includes a semiconductor epitaxial layer 20, the second surface 12 is a surface of the semiconductor body 1 on a side close to the substrate 10, and the first surface 11 is a surface of the semiconductor body 1 on a side away from the substrate 10. In the case where the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer 20, the second surface 12 is a surface of the substrate 10 on a side away from the semiconductor epitaxial layer 20, and the first surface 11 is a surface of the semiconductor epitaxial layer 20 that is farthest from the substrate 10 and is away from the substrate 10.

[0057] The first surface 11 includes a first surface of the cell region and a first surface of the terminal region. The first surface 11 located in the cell portion 01 is the first surface of the cell region, and the first surface 11 located in the terminal portion 02 is the first surface of the terminal region. The first surface of the terminal region is arranged around the first surface of the cell region. The terminal structure includes a plurality of field limiting rings 2, and the limiting grooves 30 are arranged one-to-one with the field limiting rings 2. Each field limiting ring 2 extends from the bottom surface of a corresponding limiting groove 30 to the second surface 12 of the semiconductor body 1. In the direction Y from the first surface 11 to the second surface 12, the distance between two adjacent field limiting rings 2 gradually increases.

[0058] The semiconductor device provided by the embodiment of the present invention forms a field limiting ring 2 by performing ion implantation at the bottom of the limiting groove 30, which can increase the ion implantation depth and reduce the energy required for ion implantation, thereby avoiding implantation damage to the semiconductor body 1 caused by high-energy implantation; in the process of preparing the semiconductor device, by adjusting the thickness of the mask layer at different positions in the limiting groove 30, the width of the field limiting ring 2 formed by the ion implantation gradually decreases in the direction Y from the first surface 11 to the second surface 12, thereby gradually increasing the distance between two adjacent field limiting rings 2, which can avoid the adjacent field limiting rings 2 being connected together due to ion diffusion in the field limiting ring 2, thereby improving the voltage dividing effect and voltage resistance of the terminal structure in the semiconductor device, and improving the voltage resistance of the semiconductor device.

[0059] Based on the above embodiments, Figure 3 Optionally, the conductivity type of the field limiting ring 2 is different from the conductivity type of the semiconductor body 1. The conductivity type of the semiconductor body 1 may be N-type, doped with N-type doping ions; the conductivity type of the field limiting ring 2 may be P-type, doped with P-type doping ions. Alternatively, the conductivity type of the semiconductor body 1 may be P-type, doped with P-type doping ions; the conductivity type of the field limiting ring 2 may be N-type, doped with N-type doping ions. The N-type doping ions may be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions may be Al (aluminum) ions or B (boron) ions. In an embodiment of the present invention, the conductivity type of the semiconductor body 1 is N-type, and the conductivity type of the field limiting ring 2 is P-type.

[0060] Furthermore, the material of the field limiting ring 2 and the material of the semiconductor body 1 are both SiC. The field limiting ring 2 can be formed by directly implanting doping ions of a different conductivity type from the semiconductor body 1 into the semiconductor body 1, thereby simplifying the preparation process of the semiconductor device.

[0061] Based on the above embodiments, Figure 3 Optionally, in the direction X from the cell portion 01 to the terminal portion 02 , a plurality of field limiting rings 2 are arranged in sequence at intervals.

[0062] Specifically, when the voltage applied to the main junction (located in cell section 01) gradually increases, the depletion region of the main junction gradually expands outward. Before the voltage increases to the avalanche voltage of the main junction, the depletion regions of the two junctions (main junction and field limiting ring 2) have already merged, which increases the radius of curvature of the junction and improves the breakdown voltage of the device. Field limiting ring 2 acts as a voltage divider to some extent and helps to significantly reduce the curvature of the main junction depletion region. The breakdown voltage increases with the increase in the number of field limiting rings 2, but it does not increase linearly. The effect of increasing the number of field limiting rings 2 to increase the breakdown voltage will gradually weaken. The more field limiting rings 2 there are, the larger the total area of ​​the device will be. Therefore, it is necessary to compromise the relationship between the number of rings and the size of the breakdown electric field.

[0063] Moreover, the distance between the main junction and the field limiting ring 2, the distance between the field limiting ring 2 and the field limiting ring 2, and the width of the field limiting ring 2 have a significant effect on the voltage division capability. If the spacing between the main junction and the field limiting ring 2 and the spacing between the field limiting ring 2 and the field limiting ring 2 are too small, the curvature radius of the main junction will increase only slightly, and the voltage division effect will not be obvious; if the spacing between the main junction and the field limiting ring 2 and the spacing between the field limiting ring 2 and the field limiting ring 2 are too large, the field limiting ring 2 and the depletion region of the main junction will not merge before the avalanche breakdown of the main junction, and the field limiting ring 2 will not play a role in voltage division. Therefore, it is necessary to select a suitable ring spacing and the spacing between the main junction and the field limiting ring 2 so that the electric field strength of the main junction and the field limiting ring 2 can reach the critical breakdown electric field at the same time, so as to obtain the highest breakdown voltage.

[0064] In addition, if the width of the field limiting ring 2 is too small, the voltage dividing effect of the field limiting ring 2 will be affected; if the width of the field limiting ring 2 is too large, the chip area will be wasted. In the embodiment of the present invention, the width of the field limiting ring 2 closest to the cell portion 01 is set to be the largest, and the widths of the other field limiting rings 2 are all smaller than the width of the field limiting ring 2 closest to the cell portion 01, which can ensure the voltage dividing effect of the field limiting ring 2 while reducing the waste of chip area.

[0065] Based on the above embodiments, Figure 3 Optionally, the maximum width L1 of each field limiting ring 2 is smaller than the width L2 of the corresponding limiting groove 30 .

[0066] Specifically, since the width of the field limiting ring 2 gradually decreases in the direction Y from the first surface 11 to the second surface 12, the maximum width L1 of the field limiting ring 2 is the width of the field limiting ring 2 at the bottom surface of the limiting groove 30, that is, the width of the field limiting ring 2 at the bottom surface of the limiting groove 30 is smaller than the width L2 of the limiting groove 30. By setting the maximum width L1 of each field limiting ring 2 to be smaller than the width L2 of the corresponding limiting groove 30, sufficient space can be provided for forming a mask layer with a certain thickness in the limiting groove 30 during the preparation of the semiconductor device, so that when the mask material is deposited in the limiting groove 30, a cavity is formed in the limiting groove 30 due to the wider width of the limiting groove 30. Based on the shape of the cavity, the thickness of the mask layer at different positions in the limiting groove 30 can be adjusted, so that the width of the field limiting ring 2 formed by ion implantation gradually decreases in the direction Y from the first surface 11 to the second surface 12, thereby gradually increasing the distance between two adjacent field limiting rings 2, which can avoid the adjacent field limiting rings 2 being connected together due to ion diffusion in the field limiting ring 2, thereby improving the pressure resistance of the terminal portion 02 in the semiconductor device.

[0067] Based on the above embodiments, Figure 3Optionally, the plurality of field limiting rings 2 include at least one first field limiting ring 21. The first field limiting ring 21 includes a first side wall a, a second side wall b, and a third side wall c and a fourth side wall d connecting the first side wall a and the second side wall b; wherein the third side wall c is located at the bottom surface of the limiting groove 30, and the fourth side wall d is arranged opposite to the third side wall c; and the area of ​​the fourth side wall d is smaller than the area of ​​the third side wall c.

[0068] The multiple field limiting rings 2 also include at least one second field limiting ring 22. The second field limiting ring 22 includes a fifth side wall e, a sixth side wall f, and a seventh side wall g connecting the fifth side wall e and the sixth side wall f; wherein the seventh side wall g is located at the bottom surface of the limiting groove 30, and in the direction Y from the first surface 11 to the second surface 12, the distance between the fifth side wall e and the sixth side wall b gradually decreases until it is zero. wherein the distance from the first field limiting ring 21 to the cell portion 01 is less than the distance from the second field limiting ring 22 to the cell portion 01.

[0069] For example, Figure 3 , five field limiting rings 2 are shown, including a first field limiting ring 21 and four second field limiting rings 22. The cross-sectional shape of the first field limiting ring 21 is an inverted trapezoid, and the cross-sectional shape of the second field limiting ring 22 is an inverted triangle. The maximum width L1 of the first field limiting ring 21 is greater than the maximum width L1 of the second field limiting ring 22, and the maximum widths L1 of the four second field limiting rings 22 are equal. In other embodiments of the present invention, all the field limiting rings 2 may be set as the first field limiting rings 21, or all the field limiting rings 2 may be set as the second field limiting rings 22, or multiple first field limiting rings 21 and multiple second field limiting rings 22 may be provided.

[0070] During the preparation of the first field limiting ring 21 and the second field limiting ring 22, the width L2 of the limiting groove 30 can be adjusted so that the width L2 of the limiting groove 30 corresponding to the first field limiting ring 21 (the limiting groove 30 located directly above the first field limiting ring 21) is greater than the width L2 of the limiting groove 30 corresponding to the second field limiting ring 22 (the limiting groove 30 located directly above the second field limiting ring 22). Figure 3In the semiconductor device shown, the width L2 of the limiting groove 30 (the limiting groove 30 corresponding to the first field limiting ring 21) closest to the cell portion 01 is the largest, and the widths L2 of the remaining limiting grooves 30 are equal. The step coverage of plasma enhanced chemical vapor deposition (PECVD) is poor, and a mask material can be deposited by plasma enhanced chemical vapor deposition to form a mask layer. In the process of depositing the mask material, due to the poor step coverage of PECVD, the thickness of the mask layer at the bottom of the limiting groove 30 is inconsistent with the thickness of the upper side wall of the limiting groove 30, and the thickness of the mask layer at the bottom of the limiting groove 30 is less than the thickness of the upper side wall of the limiting groove 30. When the mask material is deposited in the limiting groove 30, the width of the limiting groove 30 corresponding to the first field limiting ring 21 is larger, so that a topless regular trapezoidal cavity can be formed in the limiting groove 30; while the width of the limiting groove 30 corresponding to the second field limiting ring 22 is smaller, and the mask layer located on the upper side wall of the limiting groove 30 can be connected together to form a sealed regular triangular cavity; when ion implantation is performed to form the field limiting ring 2, based on the shape of the regular trapezoidal cavity, a first field limiting ring 21 with an inverted trapezoidal cross-sectional figure can be formed; based on the shape of the regular triangular cavity, a second field limiting ring 22 with an inverted triangular cross-sectional figure can be formed. Among them, the regular trapezoidal cavity refers to a trapezoidal cavity whose upper bottom (the side away from the second surface) length is greater than the lower bottom (the side close to the second surface) length. The regular trapezoidal cavity is axially symmetrical with the inverted trapezoidal first field limiting ring 21. The equilateral triangular cavity refers to a triangular cavity whose vertex is located on the side of the base of the triangle away from the second surface 12 . The equilateral triangular cavity is axially symmetrical with the inverted triangular second field limiting ring 22 .

[0071] Furthermore, the depths of different limiting grooves 30 are the same. Specifically, by setting the depths of different limiting grooves 30 to be the same, all limiting grooves 30 can be formed in the same process step, thereby reducing the difficulty of manufacturing semiconductor devices. Among them, since the cavity formed in the limiting groove 30 corresponding to the first field limiting ring 21 is not capped, the thickness of the first field limiting ring 21 is greater than the thickness of the second field limiting ring 22 in the direction from the first surface 11 to the second surface 12, that is, the field limiting ring 2 (first field limiting ring 21) closest to the cell portion 01 is the closest to the second surface 12. The distance from each field limiting ring to the second surface is greater than 0.

[0072] Based on the above embodiments, Figure 4 is a schematic cross-sectional view of another semiconductor device provided by an embodiment of the present invention, with reference to Figure 4Optionally, a filling material 40 is disposed in the limiting groove 30. Specifically, after forming the field limiting ring 2, the mask layer in the limiting groove 30 can be removed, and then the filling material 40 is disposed in the limiting groove 30 to achieve planarization of the device surface. The filling material 40 includes at least one of silicon oxide, silicon nitride and polyimide.

[0073] An embodiment of the present invention further provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device described in any of the above embodiments. Figure 5 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Figure 5 , the preparation of semiconductor devices includes:

[0074] S10, providing a semiconductor body, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other; wherein the first surface comprises a first surface of a cell region and a first surface of a terminal region.

[0075] Specifically, refer to Figure 6 The semiconductor body 1 can be formed by one epitaxy or multiple epitaxies. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer 20 or a stacked structure formed by multiple semiconductor epitaxial layers 20. The semiconductor body 1 can also include a substrate 10, that is, the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer 20 formed on one side of the substrate 10. The material of the substrate 10 can be the same as the material of the semiconductor epitaxial layer 20, or the material of the substrate 10 can be different from the material of the semiconductor epitaxial layer 20. The material of the semiconductor body 1 can be SiC.

[0076] The semiconductor body 1 includes a cell portion located in the central area and a terminal portion located in the edge area, and the terminal portion is arranged around the cell portion. The cell portion of the semiconductor body 1 is used to prepare a SiC power device, and the terminal portion of the semiconductor body 1 is used to prepare a terminal structure of the SiC power device. Among them, the first surface 11 includes a cell region first surface 11 and a terminal region first surface, the first surface 11 located in the cell portion is the cell region first surface 11, and the first surface 11 located in the terminal portion is the terminal region first surface.

[0077] S20, forming a plurality of spaced limiting grooves on the first surface of the terminal region.

[0078] Specifically, refer to Figure 7 , a plurality of spaced limiting grooves 30 can be formed on the first surface of the terminal region by dry etching. The depths of different limiting grooves 30 are set to be the same, and all limiting grooves 30 can be formed in the same process step, thereby reducing the difficulty of manufacturing the semiconductor device. Among the plurality of limiting grooves 30, the limiting groove 30 closest to the cell portion has the largest width.

[0079] S30, forming a mask layer, the mask layer being located on the bottom surface, sidewalls and first surface of the terminal region of the limiting groove; wherein the mask layer has a cavity at the position where the limiting groove is located, and the width of the cavity gradually increases in the direction from the first surface to the second surface.

[0080] The forming of the mask layer may specifically include: forming a first mask layer on the sidewall of the limiting groove 30, the bottom surface of the limiting groove 30 and the first surface 11 of the terminal region by low pressure chemical vapor deposition; forming a second mask layer on the surface of the first mask layer by plasma enhanced chemical vapor deposition; the first mask layer and the second mask layer are used to enclose a cavity at the position where the limiting groove 30 is located. The mask layer includes a first mask layer and a second mask layer.

[0081] Specifically, refer to Figure 8 A first mask layer 51 of a certain thickness is formed by low pressure chemical vapor deposition (LPCVD). The material of the first mask layer 51 may be SiO 2 Or SiN. Since LPCVD has good step coverage, a first mask layer 51 of a certain thickness will be formed along the sidewalls and bottom surface of the limiting groove 30 during the deposition process. Fig. 9 After forming the first mask layer 51, a certain thickness of SiO is deposited by plasma enhanced chemical vapor deposition (PECVD). 2 or SiN film to form the second mask layer 52. Since the step coverage of PECVD is poor, a cavity will be formed in the limiting groove 30 during the deposition process.

[0082] S40, based on the mask layer, forming a field limiting ring at the bottom of each limiting groove; in the direction from the first surface to the second surface, the distance between two adjacent field limiting rings gradually increases.

[0083] Specifically, refer to Fig.10 Based on the mask layer 50, a field limiting ring 2 is formed at the bottom of each limiting groove 30; wherein each field limiting ring 2 extends from the bottom surface of a corresponding limiting groove 30 to the second surface 12 of the semiconductor body 1; in the direction from the first surface 11 to the second surface 12, the distance between two adjacent field limiting rings 2 gradually increases.

[0084] The method for preparing a semiconductor power device provided by an embodiment of the present invention forms a limiting groove 30 first, and then performs ion implantation at the bottom of the limiting groove 30 to form a field limiting ring 2, thereby increasing the depth of ion implantation and reducing the energy required for ion implantation, thereby avoiding implantation damage to the semiconductor body 1 caused by high-energy implantation. In addition, before forming the field limiting ring 2, a mask layer 50 is formed on the bottom surface, sidewall and first surface 11 of the terminal region of the limiting groove 30, and the mask layer 50 has a cavity at the position where the limiting groove 30 is located. The shape of the cavity can be used to adjust the depth of ion implantation at different positions, so that the width of the formed field limiting ring 2 gradually decreases in the direction from the first surface 11 to the second surface 12, that is, the spacing between two adjacent field limiting rings 2 gradually increases, thereby avoiding the adjacent field limiting rings 2 being connected together due to ion diffusion in the field limiting ring 2, thereby improving the pressure resistance of the terminal portion 02 in the semiconductor device.

[0085] Optional, reference Fig.10 , at least the cross-sectional shape of the cavity closest to the first surface of the cell region is a trapezoid, and the length of the side of the trapezoid close to the second surface is greater than the length of the side away from the second surface. In step S40, based on the mask layer, a field limiting ring is formed at the bottom of each limiting groove, including:

[0086] Based on the trapezoidal cavity 61 of the mask layer, a first field limiting ring 21 is formed at the bottom of the limiting trench 30 .

[0087] Among them, the multiple field limiting rings 2 include at least one first field limiting ring 21, and the first field limiting ring 21 includes a first side wall, a second side wall, and a third side wall and a fourth side wall connecting the first side wall and the second side wall; the third side wall is located at the bottom surface of the limiting groove 30, and the fourth side wall is arranged opposite to the third side wall; the area of ​​the four side walls is smaller than the area of ​​the third side wall.

[0088] Optionally, the cross-sectional shape of at least one cavity outside the cavity closest to the first surface 11 of the cell region is triangular. In step S40, based on the mask layer, a field limiting ring 2 is formed at the bottom of each limiting groove 30, and further includes:

[0089] Based on the triangular cavity 62 , a second field limiting ring 22 is formed at the bottom of the limiting groove 30 .

[0090] Among them, the multiple field limiting rings 2 also include at least one second field limiting ring 22, and the second field limiting ring 22 includes a fifth side wall, a sixth side wall and a seventh side wall connecting the fifth side wall and the sixth side wall; the seventh side wall is located on the bottom surface of the limiting groove 30; in the direction from the first surface 11 to the second surface 12, the distance between the fifth side wall and the sixth side wall gradually decreases until it is zero.

[0091] Specifically, during the preparation of the first field limiting ring 21 and the second field limiting ring 22, the width of the limiting groove 30 can be adjusted so that the width of the limiting groove 30 corresponding to the first field limiting ring 21 (the limiting groove 30 located directly above the first field limiting ring 21) is greater than the width of the limiting groove 30 corresponding to the second field limiting ring 22 (the limiting groove 30 located directly above the second field limiting ring 22). Figure 3 In the semiconductor device shown, the limiting groove 30 (the limiting groove 30 corresponding to the first field limiting ring 21) closest to the cell portion 01 has the largest width, and the remaining limiting grooves 30 have the same width. A mask material of a certain thickness is deposited by plasma enhanced chemical vapor deposition (PECVD) to form a mask layer. Due to the poor step coverage of PECVD, during the deposition process, the thickness of the mask layer at the bottom of the groove is inconsistent with the thickness of the upper sidewall of the groove, and the thickness of the mask layer at the bottom of the groove is less than the thickness of the upper sidewall of the groove.

[0092] When the mask material is deposited in the limiting groove 30, the width of the limiting groove 30 corresponding to the first field limiting ring 21 is larger, so that a regular trapezoidal cavity 61 can be formed in the limiting groove 30; while the width of the limiting groove 30 corresponding to the second field limiting ring 22 is smaller, and the mask layer located on the upper side wall of the limiting groove 30 can be connected together to form a sealed regular triangular cavity 62; when ion implantation is performed to form the field limiting ring 2, based on the regular trapezoidal cavity 61, a first field limiting ring 21 with a cross-sectional shape of an inverted trapezoid is formed; based on the regular triangular cavity 62, a second field limiting ring 22 with a cross-sectional shape of an inverted triangle is formed.

[0093] The embodiment of the present invention further provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. The power module has the same technical effect and will not be described in detail here.

[0094] The embodiment of the present invention further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board. It has the same technical effect and is not repeated here.

[0095] The embodiment of the present invention further provides a vehicle, comprising a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. The same technical effects are achieved, which will not be described in detail here.

[0096] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; wherein the first surface comprises a first surface of a cell region and a first surface of a terminal region, and the first surface of the terminal region is provided with a plurality of spaced limiting grooves; the semiconductor body further comprises a plurality of field limiting rings, each of the field limiting rings being located on a side of a limiting groove close to the second surface; In the direction from the first surface to the second surface, the distance between two adjacent field limiting rings gradually increases.

2. The semiconductor device according to claim 1, wherein: The semiconductor body comprises a cell portion and a terminal portion; the field limiting ring is located at the terminal portion; in a direction from the cell portion to the terminal portion, a plurality of the field limiting rings are arranged in sequence and spaced apart; The maximum width of each field limiting ring is smaller than the width of the corresponding limiting groove.

3. The semiconductor device according to claim 2, characterized in that The plurality of field limiting rings include at least one first field limiting ring; The first field limiting ring includes a first side wall, a second side wall, and a third side wall and a fourth side wall connecting the first side wall and the second side wall; wherein the third side wall is located at the bottom surface of the limiting groove, and the fourth side wall is arranged opposite to the third side wall; the area of ​​the fourth side wall is smaller than the area of ​​the third side wall.

4. The semiconductor device according to claim 3, characterized in that The plurality of field limiting rings further include at least one second field limiting ring; The second field limiting ring includes a fifth side wall, a sixth side wall and a seventh side wall connecting the fifth side wall and the sixth side wall; wherein the seventh side wall is located at the bottom surface of the limiting groove, and in the direction from the first surface to the second surface, the distance between the fifth side wall and the sixth side wall gradually decreases until it is zero; The distance from the first field limiting ring to the cell portion is greater than the distance from the second field limiting ring to the cell portion.

5. The semiconductor device according to claim 2, wherein: Among the plurality of field limiting rings, the field limiting ring closest to the cell portion has the largest width, and / or the field limiting ring closest to the cell portion has the shortest distance to the second surface; Among the plurality of limiting grooves, the limiting groove closest to the cell portion has the largest width, and / or different limiting grooves have the same depth.

6. The semiconductor device according to claim 1, wherein: The semiconductor material of the field limiting ring is different from the conductivity type of the material of the semiconductor body; And / or, the semiconductor material of the field limiting ring and the material of the semiconductor body include SiC.

7. The semiconductor device according to claim 1, wherein: The limiting groove is provided with a filling material, and the filling material includes at least one of silicon oxide, silicon nitride and polyimide.

8. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other; wherein the first surface comprises a first surface of a cell region and a first surface of a terminal region; Forming a plurality of spaced limiting grooves on the first surface of the terminal area; Forming a mask layer, wherein the mask layer is located on the bottom surface, the sidewalls and the first surface of the terminal region of the limiting groove; wherein the mask layer has a cavity at the location of the limiting groove, and the width of the cavity gradually increases in the direction from the first surface to the second surface; Based on the mask layer, a field limiting ring is correspondingly formed at the bottom of each limiting groove; in the direction from the first surface to the second surface, the distance between two adjacent field limiting rings gradually increases.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The forming of the mask layer comprises: Forming a first mask layer on the sidewalls of the limiting groove, the bottom surface of the limiting groove and the first surface of the terminal region by a low pressure chemical vapor deposition method; A second mask layer is formed on the surface of the first mask layer by plasma enhanced chemical vapor deposition; wherein the first mask layer and the second mask layer are used to enclose a cavity at the position where the limiting groove is located.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: At least the cross-sectional shape of the cavity closest to the first surface of the cell region is a trapezoid, and the length of the side of the trapezoid close to the second surface is greater than the length of the side away from the second surface; Based on the mask layer, a field limiting ring is correspondingly formed at the bottom of each limiting groove, including: Based on the trapezoidal cavity of the mask layer, a first field limiting ring is formed at the bottom of the limiting groove; wherein, the multiple field limiting rings include at least one first field limiting ring, and the first field limiting ring includes a first side wall, a second side wall, and a third side wall and a fourth side wall connecting the first side wall and the second side wall; the third side wall is located at the bottom surface of the limiting groove, and the fourth side wall is arranged opposite to the third side wall; the area of ​​the four side walls is smaller than the area of ​​the third side wall.

11. The method for preparing a semiconductor device according to claim 10, characterized in that: The cross-sectional shape of at least one cavity outside the cavity closest to the first surface of the cell region is a triangle; Based on the mask layer, a field limiting ring is formed at the bottom of each limiting groove, and further comprising: Based on the triangular cavity of the mask layer, a second field limiting ring is formed at the bottom of the limiting groove; The multiple field limiting rings also include at least one second field limiting ring, the second field limiting ring includes a fifth side wall, a sixth side wall and a seventh side wall connecting the fifth side wall and the sixth side wall; the seventh side wall is located on the bottom surface of the limiting groove; in the direction from the first surface to the second surface, the distance between the fifth side wall and the sixth side wall gradually decreases until it is zero.

12. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 7, wherein the substrate is used for carrying the semiconductor device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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