Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The present invention discloses a semiconductor device, a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device includes: a semiconductor body; the semiconductor body further includes a well region, a first region, a first insulating layer and a second insulating layer. The first region is disposed on a first surface, the well region is disposed on a side of the first region away from the first surface, and the first insulating layer is disposed on a side of the well region away from the first surface; a gate trench is provided on the first surface; a gate located in the gate trench; an interlayer dielectric layer located on a side of the gate away from the semiconductor body, and a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface; a source electrode located on the first surface; and a drain electrode located on a second surface. The present invention can effectively improve the breakdown voltage capability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] The trench metal oxide semiconductor field effect transistor (MOSFET) semiconductor device has advantages such as large current density and small cell size. However, the high electric fields at the bottom and corners of the gate trench result in a very high electric field on the gate oxide layer, which in turn makes the gate oxide layer extremely prone to breakdown.

[0003] In order to better protect the gate oxide layer, one solution is for the trench MOSFET semiconductor device to adopt a double trench structure, that is, source double trenches are constructed on both sides of the gate trench to shield the electric field at the bottom of the gate trench. However, the double trench structure requires additional fabrication of source trenches, and the process is complex. Another solution is for the trench MOSFET semiconductor device to adopt an asymmetric gate trench structure, and the electric field at the bottom of the gate trench is weakened by embedding a P++ doped region or an N++ doped region at the bottom of the gate trench. However, the asymmetric structure sacrifices half of the conductive trenches, thereby reducing the on-state current. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle to solve the problem that the high electric fields at the bottom and corners of the gate trench in a trench MOSFET semiconductor device result in a very high electric field on the gate oxide layer, which in turn makes the gate oxide layer extremely prone to breakdown, without adopting a double trench structure and an asymmetric structure.

[0005] In a first aspect, the present invention provides a semiconductor device, which includes:

[0006] A semiconductor body of a first conductivity type; the semiconductor body includes a first surface and a second surface arranged opposite to each other. The semiconductor body further includes a well region of a second conductivity type, a first region of a first conductivity type, a first insulating layer, and a second insulating layer. The first region is disposed on the first surface, the well region is disposed on a side of the first region away from the first surface, and the first insulating layer is disposed on a side of the well region away from the first surface; a gate trench is provided on the first surface, the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench is in contact with the first insulating layer; the vertical projection of the gate trench on the first surface is within the vertical projection of the first insulating layer on the first surface; the second insulating layer is disposed on the sidewall of the gate trench;

[0007] A gate located within the gate trench and on the side of the second insulating layer away from the semiconductor body;

[0008] An interlayer dielectric layer located on the side of the gate away from the semiconductor body, and the vertical projection of the interlayer dielectric layer on the first surface covers the vertical projection of the gate on the first surface;

[0009] A source electrode located on the first surface;

[0010] A drain electrode located on the second surface.

[0011] Optionally, the semiconductor body further includes a third insulating layer;

[0012] The third insulating layer is disposed on the side of the first insulating layer away from the first surface, the third insulating layer is connected to the first insulating layer, and the vertical projection of the third insulating layer on the first surface is within the vertical projection of the first insulating layer on the first surface.

[0013] Optionally, the thickness of the first insulating layer is less than the thickness of the third insulating layer.

[0014] Optionally, the first insulating layer includes a silicon dioxide insulating layer, and the third insulating layer includes a silicon dioxide insulating layer.

[0015] Optionally, the source electrode is located on the first surface of the semiconductor body, the source electrode is connected to the first region, and the vertical projection of the source electrode on the first surface covers the vertical projection of the interlayer dielectric layer on the first surface.

[0016] Optionally, a source trench is provided on the first surface, and the source trench extends from the first surface into the semiconductor body; the semiconductor body further includes a fourth insulating layer located on the bottom surface and side walls of the source trench;

[0017] The source electrode is located on the first surface of the semiconductor body, the source electrode is connected to the first region, and the vertical projection of the source electrode on the first surface covers the vertical projection of the interlayer dielectric layer on the first surface.

[0018] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, the manufacturing method including:

[0019] Provide a semiconductor body of a first conductivity type; the semiconductor body includes a first surface and a second surface disposed opposite to each other, the semiconductor body further includes a well region of a second conductivity type, a first region of a first conductivity type, a first insulating layer and a second insulating layer, the first region is disposed on the first surface, the well region is disposed on a side of the first region away from the first surface, and the first insulating layer is disposed on a side of the well region away from the first surface; a gate trench is provided on the first surface, the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench contacts the first insulating layer; the vertical projection of the gate trench on the first surface is within the vertical projection of the first insulating layer on the first surface; the second insulating layer is disposed on the sidewall of the gate trench;

[0020] Form a gate within the gate trench and on a side of the second insulating layer away from the semiconductor body;

[0021] Form an interlayer dielectric layer on a side of the gate away from the semiconductor body; the vertical projection of the interlayer dielectric layer on the first surface covers the vertical projection of the gate on the first surface;

[0022] Form a source electrode on the first surface;

[0023] Form a drain electrode on the second surface.

[0024] Optionally, provide a semiconductor body of a first conductivity type, further including:

[0025] Form a third insulating layer on a side of the first insulating layer away from the first surface, the third insulating layer is connected to the first insulating layer, and the vertical projection of the third insulating layer on the first surface is within the vertical projection of the first insulating layer on the first surface.

[0026] Optionally, provide a semiconductor body of a first conductivity type, including:

[0027] Provide a substrate;

[0028] Form an epitaxial layer on one side of the substrate;

[0029] Form a first mask layer on a side of the epitaxial layer away from the substrate, and the first mask layer is provided with a first mask trench;

[0030] Form a first insulating layer within the epitaxial layer; the vertical projection of the first mask trench on the substrate coincides with the vertical projection of the first insulating layer on the substrate;

[0031] Remove the first mask layer;

[0032] Form a second mask layer on a side of the epitaxial layer away from the substrate, and the second mask layer is provided with a second mask trench;

[0033] A third insulating layer is formed on one side of the first insulating layer close to the substrate; the vertical projection of the second mask trench on the substrate coincides with the vertical projection of the third insulating layer on the substrate;

[0034] Remove the second mask layer;

[0035] Continue to epitaxially grow an epitaxial layer on the side of the epitaxial layer away from the substrate;

[0036] A well region and a first region are formed on the side of the epitaxial layer away from the substrate;

[0037] A gate trench is formed on the first surface, the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench contacts the first insulating layer;

[0038] A second insulating layer is formed on the sidewall of the gate trench.

[0039] Optionally, forming a first insulating layer in the epitaxial layer, removing the first mask layer, forming a second mask layer on the side of the epitaxial layer away from the substrate, forming a third insulating layer on the side of the first insulating layer close to the substrate, and removing the second mask layer, including:

[0040] Inject oxygen ions into the epitaxial layer to form a first oxygen ion region, and the vertical projection of the first oxygen ion region on the substrate coincides with the vertical projection of the first mask trench on the substrate;

[0041] Remove the first mask layer;

[0042] A second mask layer is formed on the side of the epitaxial layer away from the substrate, and the second mask layer is provided with a second mask trench;

[0043] Inject oxygen ions into the side of the first oxygen ion region close to the substrate to form a second oxygen ion region, and the vertical projection of the second oxygen ion region on the substrate coincides with the vertical projection of the second mask trench on the substrate;

[0044] Remove the second mask layer;

[0045] Perform a thermal oxidation treatment on the epitaxial layer to thermally oxidize the first oxygen ion region into a first insulating layer and the second oxygen ion region into a third insulating layer.

[0046] Optionally, forming a second insulating layer on the sidewall of the gate trench, including:

[0047] Form a second insulating layer on the first surface and the sidewall of the gate trench;

[0048] Form an interlayer dielectric layer on the side of the gate away from the semiconductor body, including:

[0049] Form an interlayer dielectric layer on the side of the gate away from the semiconductor body and the side of the second insulating layer on the first surface away from the first surface;

[0050] Remove a partial interlayer dielectric layer on the first surface and a partial second insulating layer on the first surface. The vertical projection of the interlayer dielectric layer on the first surface covers the vertical projection of the gate on the first surface.

[0051] Optionally, the semiconductor body further includes a fourth insulating layer; providing a semiconductor body of a first conductivity type and forming a source electrode on the first surface includes:

[0052] Form a source trench on the first surface; the source trench extends from the first surface into the semiconductor body;

[0053] Form a fourth insulating layer on the bottom and sidewalls of the source trench;

[0054] Form a source electrode on the first surface. The source electrode is connected to the first region, and the vertical projection of the source electrode on the first surface covers the vertical projection of the interlayer dielectric layer on the first surface.

[0055] In a third aspect, the present invention provides a power module, which includes a substrate and at least one semiconductor device provided as described in the first aspect above. The substrate is used to carry the semiconductor device.

[0056] In a fourth aspect, the present invention provides a power conversion circuit. Among them, the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0057] The power conversion circuit includes a circuit board and at least one semiconductor device provided as described in the first aspect above. The semiconductor device is electrically connected to the circuit board.

[0058] In a fifth aspect, the present invention provides a vehicle, which includes a load and a power conversion circuit provided as described in the fourth aspect above. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0059] In the technical solution of the embodiment of the present invention, a first insulating layer is provided in the epitaxial layer below the bottom of the gate trench or the semiconductor layer formed by other processes. The first insulating layer can effectively improve the breakdown voltage capability of the semiconductor device, and solve the problem that the high electric field at the bottom and the corner of the gate trench of the trench MOSFET semiconductor device causes a very high electric field on the second insulating layer, thereby causing the second insulating layer to be easily broken down. The semiconductor device provided by the technical solution of the embodiment of the present invention may include a single trench MOSFET semiconductor device, that is, the source structure is a planar source structure, and there is no need to provide a source trench. By providing the first insulating layer, the breakdown voltage capability of the semiconductor device can be effectively improved, and the manufacturing process of the semiconductor device is effectively simplified. Moreover, there is no need to adopt an asymmetric gate trench structure, effectively avoiding the problem that the asymmetric structure sacrifices half of the conductive trench, resulting in a reduction in the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the strong electric field at the bottom and the corner of the gate trench causes a very high electric field on the gate oxide layer, thereby causing the gate oxide layer to be easily broken down, and effectively improves the reliability of the semiconductor device.

[0060] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0062] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0063] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0064] Figure 3 is a schematic structural diagram of yet another semiconductor device provided by an embodiment of the present invention;

[0065] Figure 4 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0066] Figures 5 - 10 is a structural diagram corresponding to each step in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0067] Figure 11It is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0068] Figures 12 - 21 It is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0069] Figure 22 It is a flowchart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0070] Figures 23 - 27 It is a structural diagram corresponding to some steps in yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0071] Figure 28 It is a flowchart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0072] Figures 29 - 31 It is a structural diagram corresponding to some steps in yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0073] Figure 32 It is a flowchart of yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0074] Figures 33 - 35 It is a structural diagram corresponding to some steps in yet another method for manufacturing a semiconductor device provided by an embodiment of the present invention. Detailed implementation manners

[0075] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0076] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0077] To solve the problem that the high electric fields at the bottom and corners of the gate trenches of trench MOSFET semiconductor devices lead to a very high electric field on the gate oxide layer, which in turn causes the gate oxide layer to be extremely prone to breakdown and improve the reliability of trench MOSFET semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0078] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, Figure 2 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, Figure 3 is still another schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, as Figures 1 - 3 shown, the semiconductor device includes: a semiconductor body 1 of a first conductivity type; the semiconductor body 1 includes a first surface 101 and a second surface 102 arranged opposite to each other, and the semiconductor body 1 further includes a well region 14 of a second conductivity type, a first region 13 of a first conductivity type, a first insulating layer 16, and a second insulating layer 18. The first region 13 is disposed on the first surface 101, the well region 14 is disposed on a side of the first region 13 away from the first surface 101, and the first insulating layer 16 is disposed on a side of the well region 14 away from the first surface 101. A gate trench is provided on the first surface 101, and the gate trench extends from the first surface 101 into the semiconductor body 1, and the bottom of the gate trench is in contact with the first insulating layer 16. The vertical projection of the gate trench on the first surface 101 is within the vertical projection of the first insulating layer 16 on the first surface 101; the second insulating layer 18 is disposed on the sidewall of the gate trench. A gate 2 located within the gate trench and on a side of the second insulating layer 18 away from the semiconductor body 1. An interlayer dielectric layer 3 on a side of the gate 2 away from the semiconductor body 1, and the vertical projection of the interlayer dielectric layer 3 on the first surface 101 covers the vertical projection of the gate 2 on the first surface 101. A source 4 located on the first surface 101. A drain 5 located on the second surface 102.

[0079] The semiconductor device of the embodiment of the present invention includes Figure 1 the single trench type MOSFET semiconductor device shown in Figure 2 and Figure 3 the double trench type MOSFET semiconductor device shown in

[0080] Optionally, as Figures 1 - 3 shown, the semiconductor body 1 may further include a second region 15, and the doping concentration of the second region 15 is greater than that of the well region 14, and a good ohmic contact can be formed with the source 4.

[0081] It should be noted that the MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. Exemplarily, for an N-channel MOSFET semiconductor device, the first conduction type is N-type and the second conduction type is P-type. The semiconductor body 1 is an N-type semiconductor body, the well region 14 is a P-type well region, the first region 13 is an N++ doped region, and the second region 15 is a P++ doped region. For a P-channel MOSFET semiconductor device, the first conduction type is P-type and the second conduction type is N-type. The semiconductor body 1 is a P-type semiconductor body, the well region 14 is an N-type well region, the first region 13 is a P++ doped region, and the second region 15 is an N++ doped region.

[0082] Exemplarily, as Figures 1 - 3 shown, the semiconductor body 1 may further include a substrate 11 and an epitaxial layer 12. For an N-channel MOSFET semiconductor device, the substrate 11 includes an N+ substrate and the epitaxial layer 12 includes an N-epitaxial layer. For a P-channel MOSFET semiconductor device, the substrate 11 includes a P+ substrate and the epitaxial layer 12 includes a P-epitaxial layer. In some embodiments of the present invention, the semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may further include a substrate 11 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 12 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 11, and the epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0083] As Figures 1 - 3 shown, a first insulating layer 16 may be provided in the epitaxial layer 12. When the semiconductor body 1 includes a substrate 11 and a semiconductor layer formed by other processes, the first insulating layer 16 may also be provided in the semiconductor layer formed by other processes. The first insulating layer 16 is provided at a position below the bottom of the gate trench. The gate trench extends from the first surface 101 into the epitaxial layer 12 of the semiconductor body 1, and the bottom of the gate trench is in contact with the first insulating layer 16. The width of the first insulating layer 16 near the gate trench is relatively wide. The first insulating layer 16 can effectively improve the breakdown voltage capability of the semiconductor device, and solve the problem that the high electric field at the bottom and the corner of the gate trench of the trench-type MOSFET semiconductor device causes a very high electric field on the second insulating layer 18, thereby causing the second insulating layer 18 to be easily broken down. The vertical projection of the first insulating layer 16 on the first surface 101 covers the vertical projection of the gate trench on the first surface 101. Such a setting can further ensure that the first insulating layer 16 can effectively improve the breakdown voltage capability of the semiconductor device, solve the problem that the high electric field at the bottom and the corner of the gate trench of the trench-type MOSFET semiconductor device causes a very high electric field on the second insulating layer 18, thereby causing the second insulating layer 18 to be easily broken down, and effectively improve the reliability of the semiconductor device.

[0084] The semiconductor body 1 may further include a second insulating layer 18 located on the sidewalls of the gate trench, and the gate 2 is located on the side of the second insulating layer 18 away from the semiconductor body 1. The gate 2 may contact the first insulating layer 16 through the bottom of the gate trench. The second insulating layer 18 is the gate oxide layer. The second insulating layer 18 may be located on the sidewalls of the gate trench, or may be located on the sidewalls of the gate trench and extend to the first surface 101. The vertical projection of the second insulating layer 18 on the first surface 101 may coincide with the vertical projection of the interlayer dielectric layer 3 on the first surface 101. The gate 2 is located within the gate trench and on the side of the second insulating layer 18 away from the semiconductor body 1. The gate 2 may contact the first insulating layer 16 through the bottom of the gate trench.

[0085] In the technical solution of the embodiment of the present invention, a first insulating layer 16 is provided in the epitaxial layer 12 below the bottom of the gate trench or in a semiconductor layer formed by other processes. The first insulating layer 16 can effectively improve the breakdown voltage of the semiconductor device, and solve the problem that the high electric field at the bottom and the corners of the gate trench of the trench MOSFET semiconductor device causes a very high electric field on the second insulating layer 18, which in turn causes the second insulating layer 18 to be extremely easily broken down. The semiconductor device provided by the technical solution of the embodiment of the present invention may include a single-trench MOSFET semiconductor device, that is, the source structure is a planar source structure, and there is no need to provide a source trench. By providing the first insulating layer 16, the breakdown voltage of the semiconductor device can be effectively improved, and the manufacturing process of the semiconductor device is effectively simplified. Moreover, there is no need to adopt an asymmetric gate trench structure, effectively avoiding the problem that the asymmetric structure sacrifices half of the conductive trench, resulting in a reduction in the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the strong electric field at the bottom and the corners of the gate trench causes a very high electric field on the gate oxide layer, which in turn causes the gate oxide layer to be extremely easily broken down, and effectively improves the reliability of the semiconductor device.

[0086] Optionally, on the basis of the above embodiments, continue to refer to Figures 1 - 3 , for the single-trench MOSFET semiconductor device and the double-trench MOSFET semiconductor device, the semiconductor body 1 further includes a third insulating layer 17. The third insulating layer 17 is disposed on the side of the first insulating layer 16 away from the first surface 101. The third insulating layer 17 is connected to the first insulating layer 16, and the vertical projection of the third insulating layer 17 on the first surface 101 is within the vertical projection of the first insulating layer 16 on the first surface 101.

[0087] Specifically, a third insulating layer 17 may be further provided in the epitaxial layer 12. When the semiconductor body 1 includes a substrate 11 and a semiconductor layer formed by other processes, the third insulating layer 17 may also be provided in the semiconductor layer formed by other processes. The third insulating layer 17 is provided on a side of the first insulating layer 16 away from the first surface 101, and the combined shape of the first insulating layer 16 and the third insulating layer 17 may be an inverted convex shape. The width of the third insulating layer 17 away from the gate trench is narrower than the width of the first insulating layer 16. The third insulating layer 17 can also effectively improve the breakdown voltage capability of the semiconductor device, and further solve the problem that the high electric field at the bottom and the corners of the gate trench of the trench MOSFET semiconductor device causes a very high electric field on the second insulating layer 18, thereby causing the second insulating layer 18 to be extremely easily broken down. The narrow width of the third insulating layer 17 can also effectively ensure the current path.

[0088] Optionally, based on the above embodiments, continue to refer to Figures 1 - 3 , for a single-trench MOSFET semiconductor device and a double-trench MOSFET semiconductor device, the thickness of the first insulating layer 16 is less than the thickness of the third insulating layer 17.

[0089] Specifically, the thickness range of the first insulating layer 16 may be set to 0 - 0.3 um, and the thickness range of the third insulating layer 17 may be set to 0 - 0.7 um. The thicknesses of the first insulating layer 16 and the third insulating layer 17 can be arbitrarily set according to specific needs, while effectively improving the breakdown voltage capability of the semiconductor device and ensuring the reliable operation of the semiconductor device. In some embodiments of the present invention, the semiconductor body 1 may only include the first insulating layer 16. In some other embodiments of the present invention, the semiconductor body 1 may also only include the third insulating layer 17. When the semiconductor body 1 only includes the third insulating layer 17, the third insulating layer 17 may be provided at a position below the bottom of the gate trench, so that the bottom of the gate trench can be in contact with the third insulating layer 17.

[0090] Optionally, based on the above embodiments, continue to refer to Figures 1 - 3 , for a single-trench MOSFET semiconductor device and a double-trench MOSFET semiconductor device, the first insulating layer 16 includes a silicon dioxide insulating layer, and the third insulating layer 17 includes a silicon dioxide insulating layer.

[0091] Specifically, the materials of the first insulating layer 16 and the third insulating layer 17 can both be silicon dioxide. The combined shape of the two silicon dioxide insulating layers can be an inverted convex shape. The width of the silicon dioxide insulating layer close to the gate trench is relatively wide, which can effectively improve the breakdown voltage capability of the semiconductor device and solve the problem that the high electric field at the bottom and corners of the gate trench of the trench MOSFET semiconductor device causes a very high electric field on the second insulating layer 18, thereby making the second insulating layer 18 extremely vulnerable to breakdown. The width of the silicon dioxide insulating layer far from the gate trench is relatively narrow compared to the width of the silicon dioxide insulating layer close to the gate trench. The silicon dioxide insulating layer far from the gate trench can also effectively improve the breakdown voltage capability of the semiconductor device and further solve the problem that the high electric field at the bottom and corners of the gate trench of the trench MOSFET semiconductor device causes a very high electric field on the second insulating layer 18, thereby making the second insulating layer 18 extremely vulnerable to breakdown. The narrow width of the third insulating layer 17 can also effectively ensure the current path.

[0092] Optionally, based on the above embodiments, continue to refer to Figure 1 , for a single-trench MOSFET semiconductor device, the source 4 is located on the first surface 101 of the semiconductor body 1. The source 4 is connected to the first region 13, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the interlayer dielectric layer 3 on the first surface 101.

[0093] Specifically, the semiconductor body 1 of the single-trench MOSFET semiconductor device does not need to be provided with a source trench, and the source 4 is located on the first surface 101 of the semiconductor body 1. The source 4 can be a metal electrode, and the source 4 is electrically connected to the first region 13. The manufacturing process of the single-trench MOSFET semiconductor device is simple, which can effectively simplify the manufacturing process of the MOSFET semiconductor device, thereby effectively reducing the time cost.

[0094] Optionally, based on the above embodiments, continue to refer to Figures 2 - 3 , for a double-trench MOSFET semiconductor device, a source trench 10 is provided on the first surface 101. The source trench 10 extends from the first surface 101 into the semiconductor body 1. The semiconductor body 1 further includes a fourth insulating layer 19, and the fourth insulating layer 19 is located on the bottom surface and side walls of the source trench 10. The source 4 is located on the first surface 101 of the semiconductor body 1. The source 4 is connected to the first region 13, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the interlayer dielectric layer 3 on the first surface 101.

[0095] Specifically, for the double-trench MOSFET semiconductor device, a source trench 10 needs to be provided on the first surface 101 of the semiconductor body 1. The source trench 10 can be located inside the second region 15. The fourth insulating layer 19 is provided on the bottom surface and side walls of the source trench 10. As Figure 2As shown, the source trench 10 may not be filled with a source trench structure. As Figure 3 shown, the source trench may be filled with a source trench structure 6. Exemplarily, the material of the source trench structure 6 may be metal, polysilicon, or the like. The setting of the source trench can further effectively alleviate the problem that the electric fields at the bottom and the trench corners of the gate trench are relatively strong, resulting in a very high electric field on the second insulating layer 18, and further leading to the easy breakdown of the second insulating layer 18, thereby further improving the reliability of the semiconductor device.

[0096] Figure 4 FIG. is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, Figures 5 - 10 and FIG. is a structural diagram corresponding to each step in the method for manufacturing a semiconductor device according to an embodiment of the present invention. As Figure 4 shown, the manufacturing method includes:

[0097] S100: Provide a semiconductor body of a first conductivity type; the semiconductor body includes a first surface and a second surface arranged opposite to each other, and the semiconductor body further includes a well region of a second conductivity type, a first region of a first conductivity type, a first insulating layer, and a second insulating layer. The first region is arranged on the first surface, the well region is arranged on a side of the first region away from the first surface, and the first insulating layer is arranged on a side of the well region away from the first surface; a gate trench is arranged on the first surface, the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench is in contact with the first insulating layer; the vertical projection of the gate trench on the first surface is within the vertical projection of the first insulating layer on the first surface; the second insulating layer is arranged on the sidewall of the gate trench.

[0098] Specifically, as Figure 5 shown, first, a semiconductor body 1 is provided. The semiconductor body 1 may further include a substrate 11 and an epitaxial layer 12. In some embodiments of the present invention, the semiconductor body 1 may also only include the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may further include a substrate 11 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 12 is a semiconductor layer formed on the basis of the substrate 11 through a single epitaxial process, and the epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0099] The semiconductor body 1 may further include a well region 14, a first region 13, and a second region 15. The well region 14, the first region 13, and the second region 15 are formed on a side of the epitaxial layer 12 away from the substrate 11 through processes such as doping, and then the doped impurities are activated through an annealing process. A gate trench 20 is formed on the first surface 101 through processes such as photolithography and etching. The gate trench 20 may penetrate through the well region 14 and the first region 13 and extend into the epitaxial layer 12.

[0100] The MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. Exemplarily, for an N-channel MOSFET semiconductor device, the first conduction type is N-type and the second conduction type is P-type. The semiconductor body 1 is an N-type semiconductor body, the well region 14 is a P-type well region, the first region 13 is an N++ doped region, the second region 15 is a P++ doped region, the substrate 11 includes an N+ substrate, and the epitaxial layer 12 includes an N-epitaxial layer. For a P-channel MOSFET semiconductor device, the first conduction type is P-type and the second conduction type is N-type. The semiconductor body 1 is a P-type semiconductor body, the well region 14 is an N-type well region, the first region 13 is a P++ doped region, the second region 15 is an N++ doped region, the substrate 11 includes a P+ substrate, and the epitaxial layer 12 includes a P-epitaxial layer.

[0101] A first insulating layer 16 may be disposed in the epitaxial layer 12. When the semiconductor body 1 includes a substrate 11 and a semiconductor layer formed by other processes, the first insulating layer 16 may also be disposed in the semiconductor layer formed by other processes. The first insulating layer 16 is disposed at a position below the bottom of the gate trench 20. The gate trench 20 extends from the first surface 101 into the epitaxial layer 12 of the semiconductor body 1, and the bottom of the gate trench 20 is in contact with the first insulating layer 16. The width of the first insulating layer 16 near the gate trench 20 is relatively wide. The first insulating layer 16 can effectively improve the breakdown voltage of the semiconductor device, and solve the problem that the high electric field at the bottom and the corner of the gate trench 20 of the trench MOSFET semiconductor device causes a very high electric field on the second insulating layer 18, which in turn causes the second insulating layer 18 to be extremely easily broken down. The vertical projection of the first insulating layer 16 on the first surface 101 covers the vertical projection of the gate trench 20 on the first surface 101. Such a setting can further ensure that the first insulating layer 16 can effectively improve the breakdown voltage of the semiconductor device, solve the problem that the high electric field at the bottom and the corner of the gate trench 20 of the trench MOSFET semiconductor device causes a very high electric field on the second insulating layer 18, which in turn causes the second insulating layer 18 to be extremely easily broken down, and effectively improve the reliability of the semiconductor device.

[0102] The semiconductor body 1 may further include a second insulating layer 18. The second insulating layer 18 is located on the sidewall of the gate trench 20, and the second insulating layer 18 is the gate oxide layer. The second insulating layer 18 may be located on the sidewall of the gate trench 20, or may be located on the sidewall of the gate trench 20 and extend to the first surface 101.

[0103] A third insulating layer 17 may also be provided in the epitaxial layer 12. When the semiconductor body 1 includes a substrate 11 and a semiconductor layer formed by other processes, the third insulating layer 17 may also be provided in the semiconductor layer formed by other processes. The third insulating layer 17 is provided on a side of the first insulating layer 16 away from the first surface 101, and the combined shape of the first insulating layer 16 and the third insulating layer 17 may be an inverted convex shape. The width of the third insulating layer 17 away from the gate trench 20 is narrower than the width of the first insulating layer 16. The third insulating layer 17 can also effectively improve the breakdown voltage of the semiconductor device, further solving the problem that the high electric field at the bottom and the groove corners of the gate trench 20 of the trench MOSFET semiconductor device causes a very high electric field on the second insulating layer 18, thereby causing the second insulating layer 18 to be easily broken down. The narrow width of the third insulating layer 17 can also effectively ensure the current channel.

[0104] S110: Form a gate in the gate trench and on a side of the second insulating layer away from the semiconductor body.

[0105] Specifically, as Figure 6 shown, a gate 2 is formed in the gate trench and on a side of the second insulating layer 18 away from the semiconductor body 1. Exemplarily, the second insulating layer 18 may include a silicon dioxide insulating layer, and the gate 2 may include a polysilicon gate.

[0106] S120: Form an interlayer dielectric layer on a side of the gate away from the semiconductor body; the vertical projection of the interlayer dielectric layer on the first surface covers the vertical projection of the gate on the first surface.

[0107] Specifically, as Figure 7 shown, an interlayer dielectric layer 3 is formed on a side of the gate 2 away from the semiconductor body 1. The vertical projection of the interlayer dielectric layer 3 on the first surface 101 may coincide with the vertical projection of the second insulating layer 18 on the first surface 101, and the vertical projection of the interlayer dielectric layer 3 on the first surface 101 should cover the vertical projection of the gate 2 on the first surface 101, thereby effectively insulating the source electrode and the gate 2.

[0108] S130: Form a source electrode on the first surface.

[0109] Specifically, as Figure 8 shown, for a single trench MOSFET semiconductor device, the semiconductor body 1 does not need to be provided with a source trench. Exemplarily, a metal is deposited on the first surface 101 to form a source electrode 4. The source electrode 4 is electrically connected to the first region 13, and the vertical projection of the source electrode 4 on the first surface 101 covers the vertical projection of the interlayer dielectric layer 3 on the first surface 101.

[0110] As Figure 9 and Figure 10As shown, for a double-groove MOSFET semiconductor device, a source trench 10 needs to be formed on the first surface 101 of the semiconductor body 1, and the source trench 10 can be located inside the second region 15. A fourth insulating layer 19 is provided on the bottom and sidewalls of the source trench 10. As Figure 9 shown, the source trench 10 may not be filled with a source trench structure. As Figure 10 shown, the source trench may be filled with a source trench structure 6. Exemplarily, the material of the source trench structure 6 may be metal, polysilicon, etc. The setting of the source trench can further effectively alleviate the problem that the electric field at the bottom and corners of the gate trench is strong, resulting in a very high electric field on the second insulating layer 18, and further leading to the easy breakdown of the second insulating layer 18, thereby further improving the reliability of the semiconductor device.

[0111] S140: Form a drain on the second surface.

[0112] Specifically, as Figures 1 - 3 shown, for a single-groove MOSFET semiconductor device and a double-groove MOSFET semiconductor device, a drain 5 is formed on the second surface 102. Exemplarily, the drain 5 is formed by depositing metal on the second surface 102.

[0113] In the technical solution of the embodiment of the present invention, a first insulating layer 16 is provided in the epitaxial layer 12 below the bottom of the gate trench or a semiconductor layer formed by other processes. The first insulating layer 16 can effectively improve the breakdown voltage of the semiconductor device, and solve the problem that the high electric field at the bottom and corners of the gate trench of the trench MOSFET semiconductor device leads to a very high electric field on the second insulating layer 18, and further leads to the easy breakdown of the second insulating layer 18. The semiconductor device provided by the technical solution of the embodiment of the present invention may include a single-groove MOSFET semiconductor device, that is, the source structure is a planar source structure, and there is no need to provide a source trench. By providing the first insulating layer 16, the breakdown voltage of the semiconductor device can be effectively improved, and the manufacturing process of the semiconductor device is effectively simplified. And there is no need to adopt an asymmetric gate trench structure, effectively avoiding the problem that the asymmetric structure sacrifices half of the conductive trench, resulting in a reduction in the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the strong electric field at the bottom and corners of the gate trench leads to a very high electric field on the gate oxide layer, and further leads to the easy breakdown of the gate oxide layer, and effectively improves the reliability of the semiconductor device.

[0114] Optionally, on the basis of the above embodiments, Figure 11 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figures 12 - 21 is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 11 shown, the manufacturing method includes:

[0115] S200: Provide a substrate.

[0116] Specifically, as Figure 12 shown, first, provide a substrate 11. The semiconductor material of the substrate 11 can be silicon carbide or gallium nitride. The MOSFET semiconductor device can include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. For the N-channel MOSFET semiconductor device, the substrate 11 is an N+ silicon carbide substrate or an N+ gallium nitride substrate. For the P-channel MOSFET semiconductor device, the substrate 11 is a P+ silicon carbide substrate or a P+ gallium nitride substrate.

[0117] S210: Form an epitaxial layer on one side of the substrate.

[0118] Specifically, as Figure 13 shown, epitaxially grow an epitaxial layer 12 on one side of the substrate 11. The epitaxial layer 12 can be a semiconductor layer formed on the substrate 11 through a single epitaxial process. The epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE). For the N-channel MOSFET semiconductor device, the epitaxial layer 12 includes an N-epitaxial layer. For the P-channel MOSFET semiconductor device, the epitaxial layer 12 includes a P-epitaxial layer.

[0119] S220: Form a first mask layer on the side of the epitaxial layer away from the substrate. The first mask layer is provided with a first mask trench.

[0120] Specifically, as Figure 14 shown, form a first mask layer 7 on the side of the epitaxial layer 12 away from the substrate 11. The first mask layer 7 is provided with a first mask trench 71. Exemplarily, the first mask layer 7 can include a mask plate.

[0121] S230: Form a first insulating layer in the epitaxial layer; the vertical projection of the first mask trench on the substrate coincides with the vertical projection of the first insulating layer on the substrate.

[0122] Specifically, as Figure 15 shown, form a first insulating layer 16 in the epitaxial layer 12 at the corresponding position of the first mask trench 71. Exemplarily, the semiconductor materials of the substrate 11 and the epitaxial layer 12 are silicon carbide, and the material of the first insulating layer 16 is silicon dioxide. Certain-depth oxygen ions can be implanted into the epitaxial layer 12 from the first mask trench 71 using a high-energy ion implanter. The implantation energy can be controlled according to specific requirements to make the oxygen ions implanted to an appropriate depth. Then, perform high-temperature thermal oxidation treatment to make the implanted oxygen ions react with silicon carbide to generate silicon dioxide, thereby forming the first insulating layer 16.

[0123] S240: Remove the first mask layer.

[0124] Specifically, as Figure 16 shown, after forming the first insulating layer 16, the first mask layer is removed.

[0125] S250: Form a second mask layer on the side of the epitaxial layer away from the substrate. The second mask layer is provided with second mask grooves.

[0126] Specifically, as Figure 17 shown, a second mask layer 8 is formed on the side of the epitaxial layer 12 away from the substrate 11. The second mask layer 8 is provided with second mask grooves 81. Exemplarily, the second mask layer 8 may include a mask plate. The width of the second mask grooves 81 may be less than the width of the first mask grooves.

[0127] S260: Form a third insulating layer on the side of the first insulating layer close to the substrate; the vertical projection of the second mask grooves on the substrate coincides with the vertical projection of the third insulating layer on the substrate.

[0128] Specifically, as Figure 18 shown, a third insulating layer 17 is formed in the epitaxial layer 12 on the side of the first insulating layer 16 close to the substrate 11 corresponding to the position of the second mask grooves 81. Exemplarily, the semiconductor materials of the substrate 11 and the epitaxial layer 12 are silicon carbide, and the material of the third insulating layer 17 is silicon dioxide. Oxygen ions can be injected into the epitaxial layer 12 to a certain depth from the second mask grooves 81 by using a high-energy ion implanter. The implantation energy can be controlled according to specific requirements so that the oxygen ions are implanted to an appropriate depth. Then, high-temperature thermal oxidation treatment is carried out to make the implanted oxygen ions react with silicon carbide to generate silicon dioxide, thereby forming the third insulating layer 17.

[0129] S270: Remove the second mask layer.

[0130] Specifically, as Figure 19 shown, after forming the third insulating layer 17, the second mask layer is removed.

[0131] S280: Continue to epitaxially grow an epitaxial layer on the side of the epitaxial layer away from the substrate.

[0132] Specifically, as Figure 20 shown, an epitaxial layer 12 is continuously epitaxially grown on the side of the epitaxial layer 12 away from the substrate 11.

[0133] S290: Form a well region and a first region on the side of the epitaxial layer away from the substrate.

[0134] Specifically, as Figure 21As shown, on the side of the epitaxial layer 12 away from the substrate 11, a well region 14, a first region 13, and a second region 15 are formed by processes such as doping, and then the doped impurities are activated by an annealing process. For an N-channel MOSFET semiconductor device, the well region 14 is a P-type well region, the first region 13 is an N++ doped region, and the second region 15 is a P++ doped region; for a P-channel MOSFET semiconductor device, the well region 14 is an N-type well region, the first region 13 is a P++ doped region, and the second region 15 is an N++ doped region.

[0135] S291: Form a gate trench on the first surface, the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench contacts the first insulating layer.

[0136] Specifically, as Figure 5 shown, a gate trench 20 is formed on the first surface 101 by processes such as photolithography and etching. The gate trench 20 can penetrate the well region 14 and the first region 13 and extend into the epitaxial layer 12. The bottom of the gate trench 20 contacts the first insulating layer 16.

[0137] S292: Form a second insulating layer on the sidewalls of the gate trench.

[0138] Specifically, as Figure 5 shown, a second insulating layer 18 is formed on the sidewalls of the gate trench 20 and part of the first surface 101.

[0139] S293: Form a gate in the gate trench and on the side of the second insulating layer away from the semiconductor body.

[0140] S294: Form an interlayer dielectric layer on the side of the gate away from the semiconductor body; the vertical projection of the interlayer dielectric layer on the first surface covers the vertical projection of the gate on the first surface.

[0141] S295: Form a source on the first surface.

[0142] S296: Form a drain on the second surface.

[0143] Optionally, on the basis of the above embodiments, Figure 22 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figures 23 - 27 is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 22 shown, the manufacturing method includes:

[0144] S300: Provide a substrate.

[0145] S310: Form an epitaxial layer on one side of the substrate.

[0146] S320: Form a first mask layer on the side of the epitaxial layer away from the substrate, and the first mask layer is provided with a first mask trench.

[0147] S330: Inject oxygen ions into the epitaxial layer to form a first oxygen ion region, and the vertical projection of the first oxygen ion region on the substrate coincides with the vertical projection of the first mask trench on the substrate.

[0148] Specifically, as Figure 23 shown, oxygen ions with a certain depth can be injected into the epitaxial layer 12 from the first mask trench 71 by using a high-energy ion implanter, so as to form a first oxygen ion region 161. The injection energy can be controlled according to specific requirements to make the oxygen ions be injected to an appropriate depth.

[0149] S340: Remove the first mask layer.

[0150] Specifically, as Figure 24 shown, after the first oxygen ion region 161 is formed, the first mask layer is removed.

[0151] S350: Form a second mask layer on the side of the epitaxial layer away from the substrate, and the second mask layer is provided with a second mask trench.

[0152] Specifically, as Figure 25 shown, a second mask layer 8 is formed on the side of the epitaxial layer 12 away from the substrate 11, and the second mask layer 8 is provided with a second mask trench 81. Exemplarily, the second mask layer 8 may include a mask plate. The width of the second mask trench 81 may be smaller than the width of the first mask trench.

[0153] S360: Inject oxygen ions on the side of the first oxygen ion region close to the substrate to form a second oxygen ion region, and the vertical projection of the second oxygen ion region on the substrate coincides with the vertical projection of the second mask trench on the substrate.

[0154] Specifically, as Figure 26 shown, oxygen ions with a certain depth are injected into the epitaxial layer 12 on the side of the first oxygen ion region 161 close to the substrate 11 corresponding to the second mask trench 81 by using a high-energy ion implanter, so as to form a second oxygen ion region 171. The injection energy can be controlled according to specific requirements to make the oxygen ions be injected to an appropriate depth. Exemplarily, the combined pattern of the first oxygen ion region 161 and the second oxygen ion region 171 may be an inverted convex shape, that is, the width of the first oxygen ion region 161 may be greater than the width of the second oxygen ion region 171. When forming the first oxygen ion region 161 and the second oxygen ion region 171, the first mask layer and the second mask layer 8 need to be formed respectively, and two ion implantations are performed. When forming the first oxygen ion region 161, the ion implantation width is large and the depth is small, and when forming the second oxygen ion region 171, the ion implantation width is small and the depth is large.

[0155] S370: Remove the second mask layer.

[0156] Specifically, as Figure 27 shown, after forming the second oxygen ion region 171, remove the second mask layer.

[0157] S380: Perform thermal oxidation on the epitaxial layer to thermally oxidize the first oxygen ion region into a first insulating layer and the second oxygen ion region into a third insulating layer.

[0158] Specifically, as Figure 19 shown, after ion implanting to form the first oxygen ion region and the second oxygen ion region in the epitaxial layer 12, perform high-temperature thermal oxidation on the epitaxial layer 12 to thermally oxidize the first oxygen ion region into a first insulating layer 16 and the second oxygen ion region into a third insulating layer 17. Exemplarily, the semiconductor materials of the substrate 11 and the epitaxial layer 12 are silicon carbide, and the materials of the first insulating layer 16 and the third insulating layer 17 are silicon dioxide. When performing high-temperature thermal oxidation, the oxygen ions in the first oxygen ion region and the second oxygen ion region react with silicon carbide to generate silicon dioxide, thereby forming the first insulating layer 16 and the third insulating layer 17.

[0159] S390: Continue to epitaxially grow an epitaxial layer on the side of the epitaxial layer away from the substrate.

[0160] S391: Form a well region and a first region on the side of the epitaxial layer away from the substrate.

[0161] S392: Form a gate trench on the first surface, the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench contacts the first insulating layer.

[0162] S393: Form a second insulating layer on the sidewalls of the gate trench.

[0163] S394: Form a gate in the gate trench and on the side of the second insulating layer away from the semiconductor body.

[0164] S395: Form an interlayer dielectric layer on the side of the gate away from the semiconductor body; the vertical projection of the interlayer dielectric layer on the first surface covers the vertical projection of the gate on the first surface.

[0165] S396: Form a source electrode on the first surface.

[0166] S397: Form a drain electrode on the second surface.

[0167] The manufacturing method of the semiconductor device provided by the embodiment of the present invention injects oxygen ions with a certain depth through a high-energy ion implanter, and then performs high-temperature annealing to make the oxygen ions react with silicon carbide to generate a buried silicon dioxide layer, thereby forming a first insulating layer 16 and a third insulating layer 17. At this time, the side of the epitaxial layer 12 away from the substrate 11 still maintains the lattice of silicon carbide, so the epitaxial layer 12 can continue to grow epitaxially.

[0168] Optionally, based on the above embodiments, Figure 28 is a flowchart of another manufacturing method of the semiconductor device provided by the embodiment of the present invention, Figures 29 - 31 is a structural diagram corresponding to some steps in another manufacturing method of the semiconductor device provided by the embodiment of the present invention. As Figure 28 shown, the manufacturing method includes:

[0169] S400: Provide a substrate.

[0170] S410: Form an epitaxial layer on one side of the substrate.

[0171] S420: Form a first mask layer on the side of the epitaxial layer away from the substrate. The first mask layer is provided with a first mask trench.

[0172] S430: Form a first insulating layer in the epitaxial layer; the vertical projection of the first mask trench on the substrate coincides with the vertical projection of the first insulating layer on the substrate.

[0173] S440: Remove the first mask layer.

[0174] S450: Form a second mask layer on the side of the epitaxial layer away from the substrate. The second mask layer is provided with a second mask trench.

[0175] S460: Form a third insulating layer on the side of the first insulating layer close to the substrate; the vertical projection of the second mask trench on the substrate coincides with the vertical projection of the third insulating layer on the substrate.

[0176] S470: Remove the second mask layer.

[0177] S480: Continue to grow the epitaxial layer on the side of the epitaxial layer away from the substrate.

[0178] S490: Form a well region and a first region on the side of the epitaxial layer away from the substrate.

[0179] S491: Form a gate trench on the first surface. The gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench contacts the first insulating layer.

[0180] S492: Form a second insulating layer on the first surface and the sidewalls of the gate trench.

[0181] Specifically, asFigure 29 As shown, a second insulating layer 18 is formed on the sidewall and the first surface 101 of the gate trench 20 through thermal oxidation treatment. Exemplarily, the second insulating layer 18 may include a silicon dioxide insulating layer.

[0182] S493: A gate is formed in the gate trench and on the side of the second insulating layer away from the semiconductor body.

[0183] Specifically, as Figure 30 shown, a gate 2 is formed in the gate trench and on the side of the second insulating layer 18 away from the semiconductor body 1. Exemplarily, the gate 2 may include a polysilicon gate. First, doped polysilicon may be deposited over the entire surface on the side of the second insulating layer 18 away from the first surface 101 in the gate trench and on the first surface 101, and then etched back over the entire surface to form the gate 2 in the gate trench. Since the bottom of the gate trench is in direct contact with the first insulating layer 16, the second insulating layer 18 will not be formed at the bottom of the gate trench during thermal oxidation to form the second insulating layer 18.

[0184] S494: An interlayer dielectric layer is formed on the side of the gate away from the semiconductor body and on the side of the second insulating layer on the first surface away from the first surface.

[0185] Specifically, as Figure 31 shown, an interlayer dielectric layer 3 is formed on the side of the gate 2 away from the semiconductor body 1 and on the side of the second insulating layer 18 on the first surface 101 away from the first surface 101.

[0186] S495: Remove a part of the interlayer dielectric layer on the first surface and a part of the second insulating layer on the first surface, and the vertical projection of the interlayer dielectric layer on the first surface covers the vertical projection of the gate on the first surface.

[0187] Specifically, as Figure 7 shown, a part of the interlayer dielectric layer 3 on the first surface 101 and a part of the second insulating layer 18 on the first surface 101 are removed. The width of the interlayer dielectric layer 3 should be greater than the width of the gate trench, and the first region 13 needs to be exposed.

[0188] S496: A source is formed on the first surface.

[0189] S497: A drain is formed on the second surface.

[0190] Optionally, on the basis of the above embodiments, Figure 32 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figures 33 - 35 is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 32 shown, the manufacturing method includes:

[0191] S500: Provide a semiconductor body of a first conductivity type; the semiconductor body includes a first surface and a second surface disposed opposite to each other, the semiconductor body further includes a well region of a second conductivity type, a first region of a first conductivity type, a first insulating layer and a second insulating layer, the first region is disposed on the first surface, the well region is disposed on a side of the first region away from the first surface, and the first insulating layer is disposed on a side of the well region away from the first surface; a gate trench is formed on the first surface, the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench contacts the first insulating layer; the vertical projection of the gate trench on the first surface is within the vertical projection of the first insulating layer on the first surface; the second insulating layer is disposed on the sidewall of the gate trench.

[0192] S510: Form a gate within the gate trench and on a side of the second insulating layer away from the semiconductor body.

[0193] S520: Form an interlayer dielectric layer on a side of the gate away from the semiconductor body; the vertical projection of the interlayer dielectric layer on the first surface covers the vertical projection of the gate on the first surface.

[0194] S530: Form a source trench on the first surface; the source trench extends from the first surface into the semiconductor body.

[0195] Specifically, as Figure 33 shown, for a double-trench MOSFET semiconductor device, the source structure is a trench-type source structure, and a source trench 10 is formed on the first surface 101 through an etching process, and the source trench 10 is located inside the second region 15.

[0196] S540: Form a fourth insulating layer on the bottom and sidewall of the source trench.

[0197] Specifically, as Figure 34 shown, a fourth insulating layer 19 is formed on the bottom and sidewall of the source trench 10. Exemplarily, a silicon dioxide insulating layer is formed on the bottom and sidewall of the source trench 10 through a thermal oxidation process to form the fourth insulating layer 19.

[0198] S550: Form a source on the first surface, the source is connected to the first region, and the vertical projection of the source on the first surface covers the vertical projection of the interlayer dielectric layer on the first surface.

[0199] Specifically, as Figure 35 shown, metal is deposited on the first surface 101 to form a source 4. The source 4 is electrically connected to the first region 13, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the interlayer dielectric layer 3 on the first surface 101.

[0200] S560: Form a drain on the second surface.

[0201] An embodiment of the present invention provides a power module. The power module includes a substrate and at least one semiconductor device provided in any of the above embodiments of the present invention. The substrate is used to carry at least one semiconductor device provided in any of the above embodiments of the present invention.

[0202] The power module provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0203] An embodiment of the present invention provides a power conversion circuit. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction.

[0204] The power conversion circuit includes a circuit board and at least one semiconductor device provided in any of the above embodiments of the present invention. The semiconductor device is electrically connected to the circuit board.

[0205] The power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0206] An embodiment of the present invention provides a vehicle. The vehicle includes a load and the power conversion circuit provided in any of the above embodiments of the present invention. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0207] The vehicle provided in any of the above embodiments of the present invention includes the power conversion circuit provided in any of the above embodiments of the present invention. The power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention. Therefore, the vehicle provided in any of the above embodiments of the present invention has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0208] It should be understood that the various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0209] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a semiconductor body of a first conductivity type; the semiconductor body includes a first surface and a second surface disposed opposite to each other, and the semiconductor body further includes a well region of a second conductivity type, a first region of a first conductivity type, a first insulating layer, and a third insulating layer. The first region is disposed on the first surface, the well region is disposed on a side of the first region away from the first surface, the first insulating layer is disposed on a side of the well region away from the first surface, the third insulating layer is located on a side of the first insulating layer away from the first surface, the third insulating layer is connected to the first insulating layer, and a vertical projection of the third insulating layer on the first surface is within a vertical projection of the first insulating layer on the first surface; Forming a gate trench on the first surface, the gate trench extending from the first surface into the semiconductor body, and a bottom of the gate trench contacting the first insulating layer; A vertical projection of the gate trench on the first surface is within a vertical projection of the first insulating layer on the first surface; Forming a second insulating layer on a sidewall of the gate trench; Forming a gate within the gate trench and on a side of the second insulating layer away from the semiconductor body; Forming an interlayer dielectric layer on a side of the gate away from the semiconductor body; A vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface; Forming a source on the first surface; Forming a drain on the second surface; The semiconductor body includes a substrate and an epitaxial layer on one side of the substrate. Oxygen ions are implanted into the epitaxial layer to form a first oxygen ion region, and oxygen ions are implanted on a side of the first oxygen ion region close to the substrate to form a second oxygen ion region. The epitaxial layer is subjected to a thermal oxidation treatment to thermally oxidize the first oxygen ion region into the first insulating layer and thermally oxidize the second oxygen ion region into the third insulating layer.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Providing a semiconductor body of a first conductivity type, comprising: Providing a substrate; Forming an epitaxial layer on one side of the substrate; Forming a first mask layer on a side of the epitaxial layer away from the substrate, the first mask layer being provided with a first mask trench; Forming the first insulating layer within the epitaxial layer; a vertical projection of the first mask trench on the substrate coincides with a vertical projection of the first insulating layer on the substrate; Removing the first mask layer; Forming a second mask layer on a side of the epitaxial layer away from the substrate, the second mask layer being provided with a second mask trench; Forming the third insulating layer on a side of the first insulating layer close to the substrate; a vertical projection of the second mask trench on the substrate coincides with a vertical projection of the third insulating layer on the substrate; Removing the second mask layer; Continuing to epitaxially grow the epitaxial layer on a side of the epitaxial layer away from the substrate; Forming a well region and a first region on a side of the epitaxial layer away from the substrate.

3. The method for manufacturing a semiconductor device according to claim 2, wherein, Forming the first insulating layer within the epitaxial layer, removing the first mask layer, forming a second mask layer on a side of the epitaxial layer away from the substrate, forming the third insulating layer on a side of the first insulating layer close to the substrate, and removing the second mask layer, includes: Injecting oxygen ions into the epitaxial layer to form a first oxygen ion region, a vertical projection of the first oxygen ion region on the substrate coinciding with a vertical projection of the first mask trench on the substrate; Removing the first mask layer; Forming a second mask layer on a side of the epitaxial layer away from the substrate, the second mask layer being provided with a second mask trench; Injecting oxygen ions into a side of the first oxygen ion region close to the substrate to form a second oxygen ion region, a vertical projection of the second oxygen ion region on the substrate coinciding with a vertical projection of the second mask trench on the substrate; Removing the second mask layer; Performing a thermal oxidation process on the epitaxial layer to thermally oxidize the first oxygen ion region into the first insulating layer and the second oxygen ion region into the third insulating layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein, Forming the second insulating layer on sidewalls of the gate trench, includes: Forming the second insulating layer on the first surface and on sidewalls of the gate trench; Forming an interlayer dielectric layer on a side of the gate away from the semiconductor body, includes: Forming the interlayer dielectric layer on a side of the gate away from the semiconductor body and on a side of the second insulating layer on the first surface away from the first surface; Removing a part of the interlayer dielectric layer on the first surface and a part of the second insulating layer on the first surface, a vertical projection of the interlayer dielectric layer on the first surface covering a vertical projection of the gate on the first surface.

5. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a fourth insulating layer; providing a semiconductor body of a first conductivity type and forming a source electrode on the first surface, includes: Forming a source trench on the first surface; the source trench extending from the first surface into the semiconductor body; Forming the fourth insulating layer on a bottom and sidewalls of the source trench; Forming a source electrode on the first surface, the source electrode being connected to the first region, and a vertical projection of the source electrode on the first surface covering a vertical projection of the interlayer dielectric layer on the first surface.

6. A semiconductor device, characterized in that, The semiconductor device is made by the method for manufacturing a semiconductor device according to any one of claims 1 - 5; the semiconductor device includes: A semiconductor body of a first conductivity type; the semiconductor body includes a first surface and a second surface disposed opposite to each other, and the semiconductor body further includes a well region of a second conductivity type, a first region of a first conductivity type, a first insulating layer, and a second insulating layer. The first region is disposed on the first surface, the well region is disposed on a side of the first region away from the first surface, and the first insulating layer is disposed on a side of the well region away from the first surface; a gate trench is provided on the first surface, the gate trench extends from the first surface into the semiconductor body, and a bottom of the gate trench contacts the first insulating layer; a vertical projection of the gate trench on the first surface is within a vertical projection of the first insulating layer on the first surface; the second insulating layer is disposed on a sidewall of the gate trench; A gate located within the gate trench and on a side of the second insulating layer away from the semiconductor body; An interlayer dielectric layer located on a side of the gate away from the semiconductor body, and a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface; A source electrode located on the first surface; A drain electrode located on the second surface.

7. The semiconductor device according to claim 6, wherein The semiconductor body further includes a third insulating layer; The third insulating layer is disposed on a side of the first insulating layer away from the first surface, the third insulating layer is connected to the first insulating layer, and a vertical projection of the third insulating layer on the first surface is within a vertical projection of the first insulating layer on the first surface.

8. The semiconductor device according to claim 7, wherein, The thickness of the first insulating layer is less than the thickness of the third insulating layer.

9. The semiconductor device according to claim 7 or 8, characterized in that, The first insulating layer includes a silicon dioxide insulating layer, and the third insulating layer includes a silicon dioxide insulating layer.

10. The semiconductor device according to claim 6, wherein, The source electrode is located on the first surface of the semiconductor body, the source electrode is connected to the first region, and a vertical projection of the source electrode on the first surface covers a vertical projection of the interlayer dielectric layer on the first surface.

11. The semiconductor device according to claim 6, wherein, A source trench is provided on the first surface, the source trench extends from the first surface into the semiconductor body; the semiconductor body further includes a fourth insulating layer, and the fourth insulating layer is located on a bottom surface and a sidewall of the source trench; The source electrode is located on the first surface of the semiconductor body, the source electrode is connected to the first region, and a vertical projection of the source electrode on the first surface covers a vertical projection of the interlayer dielectric layer on the first surface.

12. A power module, characterized in that, Including a substrate and at least one semiconductor device according to any one of claims 6-11, and the substrate is used to carry the semiconductor device.

13. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 6-11, and the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that, Comprising a load and a power conversion circuit as described in claim 13, the power conversion circuit being configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted current to the load.

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